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| CS4392 24-Bit, 192 kHz Stereo DAC with Volume Control Features l Complete Stereo DAC System: Interpolation, Description The CS4392 is a complete stereo digital-to-analog system including digital interpolation, fifth-order delta-sigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing and analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, and a high tolerance to clock jitter. The CS4392 accepts PCM data at sample rates from 4 kHz to 192 kHz, DSD audio data, has selectable digital filters, and consumes very little power. These features are ideal for DVD, SACD players, A/V receivers, CD and set-top box systems. The CS4392 is pin and register compatible with the CS4391, making easy performance upgrades possible. ORDERING INFORMATION CS4392-KS -10 to 70 C CS4392-KZ -10 to 70 C CDB4392 20-pin SOIC 20-pin TSSOP Evaluation Board D/A, Output Analog Filtering l 114 dB Dynamic Range l 100 dB THD+N l Up to 192kHz Sample Rates l Direct Stream Digital Mode l Low Clock Jitter Sensitivity l Single +5 V Power Supply l Selectable Digital Filters - Fast and Slow roll-off l Volume Control with Soft Ramp - 1 dB Step Size - Zero Crossing Click-Free Transitions l Direct Interface with 5 V to 1.8 V Logic l ATAPI mixing functions l Pin compatible with the CS4391 I M1 (SDA/CDIN) M3 M2 (SCL/CCLK) M0 (AD0/CS) AMUTEC BMUTEC CMOUT FILT+ MODE SELECT (CONTROL PORT) RST EXTERNAL MUTE CONTROL REFERENCE VOLUME CONTROL SCLK SERIAL PORT LRCK VOLUME CONTROL MIXER INTERPOLATION FILTER DAC ANALOG FILTER AOUTA+ AOUTA- AOUTB+ INTERPOLATOR FILTER DAC ANALOG FILTER AOUTB- SDATA MCLK Advance Product Information P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright (c) Cirrus Logic, Inc. 2000 (All Rights Reserved) OCT `00 DS459PP1 1 CS4392 TABLE OF CONTENTS 1. CHARACTERISTICS/SPECIFICATIONS ................................................................................. 5 ANALOG CHARACTERISTICS ................................................................................................ 5 POWER AND THERMAL CHARACTERISTICS....................................................................... 7 DIGITAL CHARACTERISTICS ................................................................................................. 8 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 8 RECOMMENDED OPERATING CONDITIONS ....................................................................... 8 SWITCHING CHARACTERISTICS - PCM MODES ................................................................. 9 SWITCHING CHARACTERISTICS - DSD.............................................................................. 10 SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE....................... 11 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE.................................... 12 2. TYPICAL CONNECTION DIAGRAMS ................................................................................... 13 3. REGISTER QUICK REFERENCE .......................................................................................... 15 4. REGISTER DESCRIPTION .................................................................................................... 16 4.1 Mode Control 1 - Address 01h ......................................................................................... 16 4.1.1 Auto-Mute (Bit 7) ................................................................................................. 16 4.1.2 Digital Interface Formats (Bits 6:4) ...................................................................... 16 4.1.3 De-Emphasis Control (Bits 3:2) ........................................................................... 17 4.1.4 Functional Mode (Bits 1:0) .................................................................................. 17 4.2 Volume and Mixing Control (Address 02h) ...................................................................... 18 4.2.1 Channel A Volume = Channel B Volume (Bit 7) ................................................. 18 4.2.2 Soft Ramp or Zero Cross Enable (Bits 6:5) ......................................................... 18 4.2.3 ATAPI Channel Mixing and Muting (Bits 4:0) ...................................................... 18 4.3 Channel A Volume Control - Address 03h ....................................................................... 20 4.4 Channel B Volume Control - Address 04h ........................................................................ 20 4.4.1 Mute (Bit 7) .......................................................................................................... 20 4.4.2 Volume Control (Bits 6:0) .................................................................................... 20 4.5 Mode Control 2 - Address 05h ......................................................................................... 20 4.5.1 Invert Signal Polarity (Bits 7:6) ............................................................................ 20 4.5.2 Control Port Enable (Bit 5) .................................................................................. 21 4.5.3 Power Down (Bit 4) ............................................................................................. 21 4.5.4 AMUTEC = BMUTEC (Bit 3) ............................................................................... 21 4.5.5 Freeze (Bit 2) ...................................................................................................... 21 4.5.6 Master Clock Divide (Bit 1) .................................................................................. 21 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm I2C is a registered trademark of Philips Semiconductors. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. 2 DS459PP1 CS4392 4.6 Mode Control 3 - Address 06h ......................................................................................... 21 4.6.1 Interpolation Filter Select (Bit 4) .......................................................................... 21 4.6.2 Soft Volume Ramp-up after Reset (Bit 3) ........................................................... 22 4.6.3 Soft Ramp-down before Reset (Bit 2) ................................................................. 22 4.7 Chip ID - Register 07h ..................................................................................................... 22 5. PIN DESCRIPTION - PCM DATA MODE ............................................................................... 23 6. PIN DESCRIPTION - DSD MODE .......................................................................................... 27 7. APPLICATIONS ..................................................................................................................... 31 7.1 Recommended Power-up Sequence for Hardware Mode ............................................... 31 7.2 Recommended Power-up Sequence and Access to Control Port Mode ......................... 31 7.3 Analog Output and Filtering ............................................................................................. 31 7.4 Interpolation Filter ............................................................................................................ 31 8. CONTROL PORT INTERFACE .............................................................................................. 33 8.1 SPI Mode ......................................................................................................................... 33 8.2 Two-Wire Mode ............................................................................................................... 33 9. PARAMETER DEFINITIONS .................................................................................................. 35 Total Harmonic Distortion + Noise (THD+N) ................................................................... 35 Dynamic Range ............................................................................................................... 35 Interchannel Isolation ...................................................................................................... 35 Interchannel Gain Mismatch ........................................................................................... 35 Gain Error........................................................................................................................ 35 Gain Drift ......................................................................................................................... 35 10. REFERENCES ...................................................................................................................... 35 11. PACKAGE DIMENSIONS ................................................................................................. 36 DS459PP1 3 CS4392 LIST OF TABLES Table 1. Digital Interface Formats - PCM Modes .......................................................................... 16 Table 2. Digital Interface Formats - DSD Mode ............................................................................ 17 Table 3. De-Emphasis Mode Selection ........................................................................................ 17 Table 4. Functional Mode Selection .............................................................................................. 17 Table 5. Soft Cross or Zero Cross Mode Selection...................................................................... 18 Table 6. ATAPI Decode................................................................................................................. 19 Table 7. Digital Volume Control Example Settings........................................................................ 20 Table 8. Common Clock Frequencies ........................................................................................... 24 Table 9. Single Speed (4 to 50 kHz) Digital Interface Format, Stand-Alone Mode Options.......... 25 Table 10. Single Speed Only (4 to 50 kHz) De-Emphasis, Stand-Alone Mode Options ............... 25 Table 11. Double Speed (50 to 100 kHz) Digital Interface Format, Stand-Alone Mode Options .. 25 Table 12. Quad Speed (100 to 200 kHz) Digital Interface Format, Stand-Alone Mode Options ... 25 Table 13. Direct Stream Digital (DSD), Stand-Alone Mode Options ............................................. 28 Table 14. Memory Address Pointer (MAP).................................................................................... 34 LIST OF FIGURES Figure 1. Serial Mode Input Timing ................................................................................................. 9 Figure 2. Direct Stream Digital - Serial Audio Input Timing........................................................... 10 Figure 3. Two-Wire Mode Control Port Timing.............................................................................. 11 Figure 4. SPI Control Port Timing ................................................................................................. 12 Figure 5. Typical Connection Diagram - PCM Mode..................................................................... 13 Figure 6. Typical Connection Diagram - DSD Mode ..................................................................... 14 Figure 7. De-Emphasis Curve ....................................................................................................... 17 Figure 8. ATAPI Block Diagram .................................................................................................... 19 Figure 9. Format 0, Left Justified up to 24-Bit Data....................................................................... 29 Figure 10. Format 1, I2S up to 24-Bit Data ................................................................................... 29 Figure 11. Format 2, Right Justified 16-Bit Data ........................................................................... 29 Figure 12. Format 3, Right Justified 24-Bit Data ........................................................................... 29 Figure 13. Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only).............. 30 Figure 14. Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)............... 30 Figure 15. CS4392 Output Filter ................................................................................................... 32 Figure 16. Control Port Timing, SPI mode .................................................................................... 34 Figure 17. Control Port Timing, Two-Wire Mode........................................................................... 34 4 DS459PP1 CS4392 1. CHARACTERISTICS/SPECIFICATIONS ANALOG CHARACTERISTICS (TA = 25 C; Logic "1" = VL = VA; Logic "0" = AGND; Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; SCLK = 3.072 MHz, Sample Rate = 48, 96, or 192 kHz, 24-bit data, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Test load RL = 3 k, CL = 10 pF) VA = 5 V Parameter Dynamic Performance - Single Speed Mode (48kHz) Dynamic Range (Note 1) Total Harmonic Distortion + Noise (Note 1) Symbol unweighted A-Weighted 0 dB THD+N -20 dB -60 dB (1 kHz) unweighted A-Weighted 0 dB THD+N -20 dB -60 dB (1 kHz) unweighted A-Weighted 0 dB THD+N -20 dB -60 dB (1 kHz) Parameter Symbol Min TBD 3 Min TBD TBD TBD TBD TBD TBD Typ 1.0xVA 0.5xVA 0.1 100 Typ 111 114 -100 -91 -51 114 100 111 114 -100 -91 -51 114 100 111 114 -100 -91 -51 114 100 Max TBD 100 Max TBD TBD TBD TBD TBD TBD Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Units Vpp VDC dB ppm/C k pF Idle Channel Noise / Signal-to-Noise Ratio Interchannel Isolation Dynamic Performance - Double Speed Mode (96kHz) Dynamic Range (Note 1) Total Harmonic Distortion + Noise (Note 1) Idle Channel Noise / Signal-to-Noise Ratio Interchannel Isolation Dynamic Performance - Quad Speed Mode (192kHz) Dynamic Range (Note 1) Total Harmonic Distortion + Noise (Note 1) Idle Channel Noise / Signal-to-Noise Ratio Interchannel Isolation Analog Output Full Scale Differential Output Voltage Common Mode Voltage Interchannel Gain Mismatch Gain Drift AC-Load Resistance Load Capacitance CMOUT RL CL DS459PP1 5 CS4392 ANALOG CHARACTERISTICS (continued) Fast Roll-Off Slow Roll-Off Parameter Symbol Min Typ Max Min Typ Max Unit Combined Digital and On-chip Analog Filter Response - Single Speed Mode (Note2) Passband (Note 3) to -0.01 dB corner 0 .4535 0 0.4166 Fs to -3 dB corner 0 .4998 0 0.4998 Fs Frequency Response 10 Hz to 20 kHz -0.01 +0.01 -0.01 +0.01 dB StopBand .5465 .5834 Fs StopBand Attenuation (Note 5) 90 64 dB Group Delay tgd TBD TBD s Passband Group Delay Deviation 0 - 20 kHz TBD TBD s De-emphasis Error Fs = 32 kHz 0.23 0.23 dB (Relative to 1kHz) Fs = 44.1 kHz 0.14 0.14 dB Fs = 48 kHz 0.09 0.09 dB Combined Digital and On-chip Analog Filter Response - Double Speed Mode - 96kHz (Note 2) Passband (Note 4) to -0.01 dB corner 0 .4166 0 .2083 Fs to -3 dB corner 0 .4998 0 .4998 Fs Frequency Response 10 Hz to 20 kHz -0.01 0.01 -0.01 0.01 dB StopBand .5834 .7917 Fs StopBand Attenuation (Note 5) 80 70 dB Group Delay tgd TBD TBD s Passband Group Delay Deviation 0 - 20 kHz TBD TBD s Combined Digital and On-chip Analog Filter Response - Quad Speed Mode - 192kHz (Note 2) Passband (Note 4) to -0.01 dB corner 0 .1046 0 .1042 Fs to -3 dB corner 0 .4897 0 .4813 Fs Frequency Response 10 Hz to 20 kHz -0.01 0.01 -0.01 0.01 dB StopBand .6355 .8683 Fs StopBand Attenuation (Note 5) 75 75 dB Group Delay tgd TBD TBD s Passband Group Delay Deviation 0 - 20 kHz TBD TBD s Combined Digital and On-chip Analog Filter Response - DSD Mode (Note 2) Passband (Note 4) to -3 dB corner TBD TBD TBD TBD Fs Frequency Response 10 Hz to 20 kHz TBD TBD TBD TBD dB Notes: 1. Triangular PDF dithered data. 2. Filter response is not tested but is guaranteed by design. 3. Valid with the recommended capacitor values on FILT+ and CMOUT as shown in Figure 5. Increasing the capacitance will also increase the PSRR. 4. Response is clock dependent and will scale with Fs. 5. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. 6 DS459PP1 CS4392 POWER AND THERMAL CHARACTERISTICS Parameters Power Supplies Power Supply CurrentNormal Operation Power Supply CurrentPower Down Mode (Note 6) Power Supply CurrentNormal Operation Power Supply CurrentPower Down Mode (Note 6) Total Power DissipationNormal Operation Package Thermal Resistance Power Supply Rejection Ratio (Note 7) Notes: 6. GND = 0 V ( All voltages with respect to ground. All measurements taken with all zeros input and open outputs, unless otherwise specified.) Base-rate Mode Symbol VA=5V VL=3V VA=5V VL=3V VA=5V VL=5V VA=5V VL=5V All Supplies=5V VA=5V, VL=1.8V 1 kHz 60 Hz IA ID_L IA ID_L IA ID_L IA ID_L Min -Typ TBD TBD TBD TBD 25 TBD 60 TBD 125 TBD TBD 60 40 Max Units mA A A A mA A A A mW mW C/Watt dB dB JA PSRR GND = 0 V ( All voltages with respect to ground. All measurements taken with all zeros input and open outputs, unless otherwise specified.) Power Down Mode is defined as RST = LO with all clocks and data lines held static. 7. Valid with the recommended capacitor values on FILT+ as shown in Figure 5. Increasing the capacitance will also increase the PSRR. NOTE: Care should be taken when selecting capacitor type, as any leakage current in excess of 1.0 A will cause degradation in analog performance. DS459PP1 7 CS4392 DIGITAL CHARACTERISTICS (TA = 25 C) Parameters High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance Maximum MUTEC Drive Current Symbol VIH VIL Iin Min 70% Typ 8 3 Max 20% 10 Units VL VL A pF mA ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to ground.) Parameters DC Power Supply Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature Symbol VA VL Iin VIND TA Tstg Min -0.3 -0.3 -0.3 -55 -65 Max 6.0 VA 10 VL+0.4 125 150 Units V V mA V C C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.) Parameters DC Power Supply Symbol VA VL Min 4.75 1.8 Typ 5.0 Max 5.5 VA Units V V 8 DS459PP1 CS4392 SWITCHING CHARACTERISTICS - PCM MODES Inputs: Logic 0 = 0 V, Logic 1 = VL, CL = 20 pF) Parameters Input Sample Rate LRCK Duty Cycle MCLK Duty Cycle SCLK Frequency SCLK Frequency SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time Note 8 tslrd tslrs tsdlrs tsdh Symbol Fs Min 4 45 40 20 20 20 20 Typ 50 50 Max 200 55 60 MCLK/2 MCLK/4 Units kHz % % Hz Hz ns ns ns ns (TA = -10 to 70 C; VL = 5.5 to 1.8 Volts; Notes: 8. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled. LRCK t slrd t slrs SCLK t sdlrs SDATA t sdh Figure 1. Serial Mode Input Timing DS459PP1 9 CS4392 SWITCHING CHARACTERISTICS - DSD (TA= -10 to 70 C; Logic 0 = AGND = DGND; Logic 1 = VL = 5.5 to 1.8 Volts; CL = 20 pF) Parameter MCLK Duty Cycle DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Period DSD_L or DSD_R valid to DSD_SCLK rising setup time DSD_SCLK rising to DSD_L or DSD_R hold time tsclkl tsclkh tsclkw tsdlrs tsdh Symbol Min 40 TBD TBD TBD TBD TBD Typ 50 Max 60 Unit % ns ns ns ns ns t sclkh t sclkl DSD_SCLK t sdlrs DSD_L, DSD_R t sdh Figure 2. Direct Stream Digital - Serial Audio Input Timing 10 DS459PP1 CS4392 SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE (TA = 25 C; VL = 5.5 to 1.8 Volts; Inputs: logic 0 = AGND, logic 1 = VL, CL = 30 pF) Parameter Symbol fscl tirs tbuf thdst tlow thigh tsust (Note 10) thdd tsud tr tf tsusp Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 Max 100 1 300 Unit KHz ns s s s s s s ns s ns s Two-Wire Mode SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Notes: 9. The Two-Wire mode is compatible with the I2C protocol. 10. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. RST t irs Stop SDA t buf SCL Repeated Start Start Stop t hdst t high t hdst tf t susp t low t hdd t sud t sust tr Figure 3. Two-Wire Mode Control Port Timing DS459PP1 11 CS4392 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (TA = 25 C; VL = 5.5 to 1.8 Volts; Inputs: logic 0 = AGND, logic 1 = VL, CL = 30 pF) Parameter Symbol fsclk tsrs (Note 11) tspi tcsh tcss tscl tsch tdsu (Note 12) (Note 13) (Note 13) tdh tr2 tf2 Min 500 500 1.0 20 66 66 40 15 Max 6 100 100 Unit MHz ns ns s ns ns ns ns ns ns ns SPI Mode CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN Notes: 11. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 12. Data must be held for sufficient time to bridge the transition time of CCLK. 13. For FSCK < 1 MHz RST t srs CS t spi t css CCLK t r2 CDIN t scl t sch t csh t f2 t dsu t dh Figure 4. SPI Control Port Timing 12 DS459PP1 CS4392 2. TYPICAL CONNECTION DIAGRAMS 0.1 f + 1.0 f +5V Analog 10 17 VA M0 (AD0/CS) M1 (SDA/ CDIN ) Mode Select (Control Port) * 9 8 7 M2 (SCL/CCLK) M3 FILT+ 11 0.1 f + 1.0 f CS4392 Logic Power +5V to 1.8V 2 0.1 f VL AOUTA- 19 AMUTEC 20 5 LRCK AOUTA+ 18 Analog Conditioning & Mute Audio Data Processor * 4 3 SCLK SDATA RST AOUTB- 14 BMUTEC 13 AOUTB+ 15 CMOUT 12 AGND 16 + 1.0 f Analog Conditioning & Mute 1 6 MCLK External Clock Figure 5. Typical Connection Diagram - PCM Mode * A high logic level for all digital inputs should not exceed VL. DS459PP1 13 CS4392 0.1 f + 1.0 f +5V Analog 17 VA 10 M0 (AD0/CS) M1 (SDA/ CDIN) Mode Select (Control Port) 9 8 FILT+ 11 0.1 f + 1.0 f M2 (SCL/CCLK) CS4392 Logic Power +5V to 1.8V 2 0.1 f 5 AOUTAVL DSD_MODE 19 AMUTEC 20 AOUTA+ 18 7 Audio Data Processor * 4 3 Analog Conditioning & Mute DSD_CLK DSD_B AOUTB- 14 DSD_A RST MCLK BMUTEC 13 AOUTB+ 15 CMOUT 12 AGND 16 1 6 Analog Conditioning & Mute + 1.0 f External Clock Figure 6. Typical Connection Diagram - DSD Mode * A high logic level for all digital inputs should not exceed VL. 14 DS459PP1 CS4392 3. REGISTER QUICK REFERENCE This table shows the register names and their associated default values. Addr 01h 02h Function Mode Control 1 Volume and MIxing Control Channel A Volume Control Channel B Volume Control Mode Control 2 7 AMUTE 1 A=B 0 6 DIF2 0 Soft 1 VOL6 0 VOL6 0 5 DIF1 0 Zero Cross 0 VOL5 0 VOL5 0 CPEN 0 Reserved 0 PART1 0 4 DIF0 0 ATAPI4 0 VOL4 0 VOL4 0 PDN 1 Filt_rolloff 0 PART0 0 3 DEM1 0 ATAPI3 1 VOL3 0 VOL3 0 MUTEC A = B 0 rst_rmp_up 0 REV3 - 2 DEM0 0 ATAPI2 0 VOL2 0 VOL2 0 FREEZE 0 0 REV2 - 1 FM1 0 ATAPI1 0 VOL1 0 VOL1 0 MCLK Divide 0 0 REV1 - 0 FM0 0 ATAPI0 1 VOL0 0 VOL0 0 Reserved 0 0 REV0 - 03h MUTE 0 04h MUTE 0 05h INVERT_A INVERT_B 0 0 Reserved 0 PART2 0 06h 07h Mode Control 3 Reserved 0 Chip ID PART3 1 rst_rmp_dwn Reserved Reserved DS459PP1 15 CS4392 4. 4.1 REGISTER DESCRIPTION Mode Control 1 - Address 01h 6 DIF2 5 DIF1 4 DIF0 3 DEM1 2 DEM0 1 FM1 0 FM0 ** All registers are read/write in Two-Wire mode and write only in SPI mode, unless otherwise noted** 7 AMUTE 4.1.1 Auto-Mute (Bit 7) Function: The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. (However, Auto-Mute detection and muting can become dependent on either channel if the Mute A = B function is enabled.) The common mode on the output will be retained and the Mute Control pin for that channel will go active during the mute period. The muting function is effected, similar to volume control changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. 4.1.2 Digital Interface Formats (Bits 6:4) Function: PCM Mode - The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Table 1 and Figures 9-14. DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIFO 0 1 0 1 0 1 0 1 DESCRIPTION Left Justified, up to 24-bit data (default) I2S, up to 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data Right Justified, 20-bit Data Right Justified, 18-bit Data Reserved Reserved Format 0 1 2 3 4 5 Figure 9 10 11 12 13 14 Table 1. Digital Interface Formats - PCM Modes 16 DS459PP1 CS4392 DSD Mode - The relationship between the oversampling ratio of the DSD audio data and the required Master clock to DSD data rate is defined by the Digital interface Format pins. Note that the Functional Mode registers must be set to DSD Mode. See Table 2 for register options. DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIFO 0 1 0 1 0 1 0 1 DESCRIPTION 64x oversampled DSD data with a 4x MCLK to DSD data rate (default) 64x oversampled DSD data with a 6x MCLK to DSD data rate 64x oversampled DSD data with a 8x MCLK to DSD data rate 64x oversampled DSD data with a 12x MCLK to DSD data rate 128x oversampled DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate Table 2. Digital Interface Formats - DSD Mode 4.1.3 De-Emphasis Control (Bits 3:2) Function: Implementation of the standard 15 s/50 s digital de-emphasis filter response, Figure 7, requires reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates. NOTE: De-emphasis is available only in Single-Speed Mode. See Table 3 below. Gain dB DEM1 0 0 1 1 DEMO 0 1 0 1 DESCRIPTION Disabled (default) 44.1 kHz de-emphasis 48 kHz de-emphasis 32 kHz de-emphasis T1=50 s 0dB T2 = 15 s -10dB Table 3. De-Emphasis Mode Selection F1 3.183 kHz F2 Frequency 10.61 kHz Figure 7. De-Emphasis Curve 4.1.4 Functional Mode (Bits 1:0) Function: Selects the required range of input sample rates or DSD Mode. See Table 4 FM1 0 0 1 1 FM0 0 1 0 1 MODE Single-Speed Mode: 4 to 50 kHz sample rates (default) Double-Speed Mode: 50 to 100 kHz sample rates Quad-Speed Mode: 100 to 200 kHz sample rates Direct Stream Digital Mode Table 4. Functional Mode Selection DS459PP1 17 CS4392 4.2 Volume and Mixing Control (Address 02h) 7 A=B 6 Soft 5 Zero Cross 4 ATAPI4 3 ATAPI3 2 ATAPI2 1 ATAPI1 0 ATAPI0 4.2.1 Channel A Volume = Channel B Volume (Bit 7) Function: The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are determined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function is enabled. 4.2.2 Soft Ramp or Zero Cross Enable (Bits 6:5) Function: Soft Ramp Enable Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1dB per 8 left/right clock periods. Zero Cross Enable Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp and Zero Cross Enable Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 5 SOFT 0 0 1 1 ZERO 0 1 0 1 Mode Changes to affect immediately Zero Cross enabled Soft Ramp enabled (default) Soft Ramp and Zero Cross enabled Table 5. Soft Cross or Zero Cross Mode Selection 4.2.3 ATAPI Channel Mixing and Muting (Bits 4:0) Function: The CS4392 implements the channel mixing functions of the ATAPI CD-ROM specification. See Table 6 on page 19 18 DS459PP1 CS4392 ATAPI4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ATAPI3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ATAPI2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ATAPI1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ATAPI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 AOUTA MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL [(aL+bR)/2] [(aL+bR)/2] [(bL+aR)/2] [(aL+bR)/2] AOUTB MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL [(bL+aR)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(aL+bR)/2] Table 6. ATAPI Decode Left Channel Audio Data A Channel Volume Control MUTE AoutA Right Channel Audio Data B Channel Volume Control MUTE AoutB Figure 8. ATAPI Block Diagram DS459PP1 19 CS4392 4.3 Channel A Volume Control - Address 03h See 4.4 Channel B Volume Control - Address 04h 4.4 CHANNEL B VOLUME CONTROL - ADDRESS 04H 7 MUTE 6 VOL6 5 VOL5 4 VOL4 3 VOL3 2 VOL2 1 VOL1 0 VOL0 4.4.1 Mute (Bit 7) Function: The Digital-to-Analog converter output will mute when enabled. The common mode voltage on the output will be retained. The muting function is effected, similiar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. The MUTEC pin for that channel will go active during the mute period if the Mute function is enabled. Both the AMUTEC and BMUTEC will go active if either MUTE register is enabled and the MUTEC A = B bit (register 5) is enabled. 4.4.2 Volume Control (Bits 6:0) Function: The digital volume control allows the user to attenuate the signal in 1 dB increments from 0 to -127 dB. Volume settings are decoded as shown in Table 7. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Volume and Mixing Control register (see section 4.2.2). Binary Code 0000000 0010100 0101000 0111100 1011010 Decimal Value 0 20 40 60 90 Volume Setting 0 dB -20 dB -40 dB -60 dB -90 dB Table 7. Digital Volume Control Example Settings 4.5 Mode Control 2 - Address 05h 6 INVERT_B 5 CPEN 4 PDN 3 MUTEC A = B 2 FREEZE 1 MCLK Divide 0 Reserved 7 INVERT_A 4.5.1 Invert Signal Polarity (Bits 7:6) Function: When set to 1, this bit inverts the signal polarity for the appropriate channel. This is useful if a board layout error has occurred, or an other situations where a 180 degree phase shift is desirable. Default is 0. 20 DS459PP1 CS4392 4.5.2 Control Port Enable (Bit 5) Function: This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean powerup, the user should write 30h to register 5 within 10 ms following the release of Reset. 4.5.3 Power Down (Bit 4) Function: The device will enter a low-power state whenever this function is activated (set to 1). The power-down bit defaults to `enabled' (1) on power-up and must be disabled before normal operation will begin. The contents of the control registers are retained when the device is in power-down. 4.5.4 AMUTEC = BMUTEC (Bit 3) Function: When this function is enabled, the individual controls for AMUTEC and BMUTEC are internally connected through a AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC pins will go active only when the requirements for both AMUTEC and BMUTEC are valid. 4.5.5 Freeze (Bit 2) Function: This function allows modifications to the control port registers without the changes taking effect until Freeze is disabled. To make multiple changes in the Control port registers take effect simultaneously, set the Freeze Bit, make all register changes, then Disable the Freeze bit. 4.5.6 Master Clock Divide (Bit 1) Function: This function allows the user to select an internal divide by 2 of the Master Clock. This selection is required to access the higher Master Clock rates as shown in 8. 4.6 Mode Control 3 - Address 06h B6 Reserved B5 Reserved B4 Filt_rolloff B3 rst_rmp_up B2 rst_rmp_dwn B1 Reserved B0 Reserved B7 Reserved 4.6.1 Interpolation Filter Select (Bit 4) Function: This Function allows the user to select whether the Interpolation Filter has a fast (set to 0 - default) or slow (set to 1) roll off. The - 3dB corner is approximately the same for both filters, but the slope of the roll of is greater for the `fast' roll off filter. DS459PP1 21 CS4392 4.6.2 Soft Volume Ramp-up after Reset Function: This function allows the user to control whether a soft ramp up in volume is applied when reset is released either by the reset pin or internal to the chip. The modes are as follows: 0 - An instantaneous change is made from max attenuation to the control port volume setting on release of reset (default setting). 1 - Volume is ramped up using the soft-ramp settings in Bits 6:5 of register 02h (see 4.2.2) from max attenuation to the control port volume setting on release of reset. (Bit 3) 4.6.3 Soft Ramp-down before Reset (Bit 2) Function: This function allows the user to control if a soft ramp-down in volume is applied before a known reset condition. The modes are as follows: 0 - An instantaneous change is made from the control port volume setting to max attenuation when chip resets (default setting). 1 - Volume is ramped down using the soft-ramp settings in Bits 6:5 of register 02h (see 4.2.2) from the control port volume setting to max attenuation when chip resets. 4.7 Chip ID - Register 07h B7 PART3 B6 PART2 B5 PART1 B4 PART0 B3 REV3 B2 REV2 B1 REV1 B0 REV0 Function: This register is Read-Only. Bits 7 through 4 are the part number ID which is 1000b (8h) and the remaining Bits (3 through 0) are for the chip revision. 22 DS459PP1 CS4392 5. PIN DESCRIPTION - PCM DATA MODE Reset RST Logic Voltage VL Serial Data SDATA Serial Clock SCLK Left/Right Clock LRCK Master Clock MCLK See Description M3 See Description (SCL/CCLK) M2 See Description (SDA/CDIN) M1 See Description (AD0/CS) M0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 AMUTEC AOUTAAOUTA+ VA AGND AOUTB+ AOUTBBMUTEC CMOUT FILT+ Channel A Mute Control Differential Output Differential Output Analog Power Analog Ground Differential Output Differential Output Channel B Mute Control Common Mode Voltage Positive Voltage Reference RST 1 Reset (Input) - Hardware Mode: The device enters a low power mode and the inter- nal state machine is reset to the default setting when low (0). When high (1), the device becomes operational. Control Port Mode: The device enters a low power mode and all internal registers are reset to the default settings, including the control port, when low. When high, the control port becomes operational and the PDN bit must be cleared before normal operation will occur. The control port can not be accessed when reset is low. The Control Port Enable Bit must also be enabled after a device reset. RST is required to remain low until the power supplies and clocks are applied and stable. VL 2 Interface Power (Input) - Digital interface power supply. Typically 1.8 to 5.0 VDC. The voltage on this pin determines the logic level high threshold for the digital inputs. The voltage on VL is the maximum allowable input level for all digital inputs. Serial Audio Data (Input) - Two's complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial clock and the channel is determined by the Left/Right clock. Serial Clock (Input) - Clocks the individual bits of the serial data into the SDATA pin. Left / Right Clock (Input) - The Left / Right clock determines which channel is currently being input on the serial audio data input, SDATA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in Left/Right sample pairs will be simultaneously output from the digital-to-analog converter whereas Right/Left pairs will exhibit a one sample period difference. PCM Data Mode Pin Descriptions SDATA 3 SCLK LRCK 4 5 DS459PP1 23 CS4392 MCLK 6 Master Clock (Input) - the master clock frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in Single Speed Mode; either 128x, 192x 256x, 384x or 512x the input sample rate in Double Speed Mode; or 64x, 96x 128x, 192x or 256 x the input sample rate in Quad Speed Mode. Table 8 illustrates the standard audio sample rates and the required master clock frequencies. MCLK (MHz) Control port only modes 786x 24.5760 33.8688 36.8640 384x 24.5760 33.8688 36.8640 192x 33.8688 36.8640 1024x* 32.7680 45.1584 49.1520 512x* 32.7680 45.1584 49.1520 256x* 45.1584 49.1520 Mode (sample-rate range) MCLK Ratio Single Speed (4 to 50 kHz) MCLK Ratio Double Speed (50 to 100 kHz) Sample Rate (kHz) 32 44.1 48 64 88.2 96 256x 8.1920 11.2896 12.2880 128x 8.1920 11.2896 12.2880 64x 11.2896 12.2880 MCLK Ratio 176.4 Quad Speed (100 to 200 kHz) 192 384x 12.2880 16.9344 18.4320 192x 12.2880 16.9344 18.4320 96x 16.9344 18.4320 512x 16.3840 22.5792 24.5760 256x 16.3840 22.5792 24.5760 128x 22.5792 24.5760 Table 8. Common Clock Frequencies 14. *Note: these modes are only available in control port mode. M3 (Control Port Mode) SDA/CDIN (Control Port Mode) SCL/CCLK (Control Port Mode) AD0 / CS (Control Port Mode) 7 8 9 10 Mode Select (Inputs) - The Mode Select Pin, M3, is not used in PCM Control Port mode and should be terminated to ground. Serial Control Data I/O (Input/Output) - In Two-Wire mode, SDA is a data I/O line. CDIN is the input data line for the control port interface in SPI mode. Serial Control Interface Clock (Input) - Clocks the serial control data into or from SDA/CDIN. Address Bit / Chip Select (Input) - In Two-Wire mode, AD0 is a chip address bit. CS is used to enable the control port interface in SPI mode. The device will enter the SPI mode at anytime a high to low transition is detected on this pin. Once the device has entered the SPI mode, it will remain in SPI mode until either the part is reset or undergoes a power-down cycle. PCM Data Mode Pin Descriptions 24 DS459PP1 CS4392 M3, M2, M1 and M0 7, 8, 9, Mode Select (Inputs) - The Mode Select Pins, M0-M3, select the operational mode (Stand-alone Mode) and 10 of the device while in stand-alone mode. M3 0 0 0 0 M1 (DIF1) 0 0 1 1 M0 (DIF0) 0 1 0 1 DESCRIPTION Left Justified, up to 24-bit data I2S, up to 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data FORMAT 0 1 2 3 FIGURE 9 10 11 12 Table 9. Single Speed (4 to 50 kHz) Digital Interface Format, Stand-Alone Mode Options M3 0 0 M2 (DEM) 0 1 DESCRIPTION No De-Emphasis De-Emphasis Enabled FIGURE 7 7 Table 10. Single Speed Only (4 to 50 kHz) De-Emphasis, Stand-Alone Mode Options M3 1 1 1 1 M2 0 0 0 0 M1 0 0 1 1 M0 0 1 0 1 DESCRIPTION Left Justified up to 24-bit data I2S up to 24-bit data Right Justified 16-bit data Right Justified 24-bit data FORMAT 0 1 2 3 FIGURE 9 10 11 12 Table 11. Double Speed (50 to 100 kHz) Digital Interface Format, Stand-Alone Mode Options M3 1 1 1 1 M2 1 1 1 1 M1 0 0 1 1 M0 0 1 0 1 DESCRIPTION Left Justified up to 24-bit data I2S up to 24-bit data Right Justified 16-bit data Right Justified 24-bit data FORMAT 0 1 2 3 FIGURE 9 10 11 12 Table 12. Quad Speed (100 to 200 kHz) Digital Interface Format, Stand-Alone Mode Options FILT+ 11 Positive Voltage Reference (Output) - Positive reference for internal sampling circuits. External capacitors are required from FILT+ to analog ground, as shown in Figure 5. The recommended values will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 Hz. FILT+ is not intended to supply external current. FILT+ has a typical source impedance of 250 k and any current drawn from this pin will alter device performance. Common Mode Voltage (Output) - Filter connection for internal common mode reference voltage, typically 50% of VA. Capacitors must be connected from CMOUT to analog ground, as shown in Figure 5. CMOUT is not intended to supply external current. CMOUT has a typical source impedance of 250 k and any current drawn from this pin will alter device performance. PCM Data Mode Pin Descriptions CMOUT 12 DS459PP1 25 CS4392 AMUTEC and BMUTEC 13 and Channel A and Channel B Mute Control (Output) - The Mute Control pins go high 20 during power-up initialization, reset, muting, when master clock to left/right clock fre- quency ratio is incorrect, or power-down. These pins are intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single supply system. Use of Mute Control is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. AOUTB+, AOUTBand AOUTA+, AOUTA AGND 14, 15, Differential Analog Audio Output (Output) - The fullscale differential output level is 18, and specified in the Analog Characteristics specification table. 19 16 17 Analog Ground (Input) Analog ground reference. Should be connected to analog ground. Analog Power (Input) - Analog power supply. Typically 5 VDC. PCM Data Mode Pin Descriptions VA 26 DS459PP1 CS4392 6. PIN DESCRIPTION - DSD MODE Reset RST Logic Voltage VL Channel A Data DSD_A Channel B Data DSD_B DSD Mode Select DSD_MODE Master Clock MCLK DSD Serial Clock DSD_SCLK Refer to PCM Mode (SCL/CCLK) M2 Refer to PCM Mode (SDA/CDIN) M1 Refer to PCM Mode (AD0/CS) M0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 AMUTEC AOUTAAOUTA+ VA AGND AOUTB+ AOUTBBMUTEC CMOUT FILT+ Refer to PCM Mode Refer to PCM Mode Refer to PCM Mode Refer to PCM Mode Refer to PCM Mode Refer to PCM Mode Refer to PCM Mode Refer to PCM Mode Refer to PCM Mode Refer to PCM Mode RST 1 Reset (Input) - Hardware Mode: The device enters a low power mode and the internal state machine is reset to the default setting when low (0). When high (1), the device becomes operational. Control Port Mode: The device enters a low power mode and all internal registers are reset to the default settings, including the control port, when low. When high, the control port becomes operational and the PDN bit must be cleared before normal operation will occur. The control port can not be accessed when reset is low. The Control Port Enable Bit must also be enabled after a device reset. RST is required to remain low until the power supplies and clocks are applied and stable. VL 2 Interface Power (Input) - Digital interface power supply. Typically 1.8 to 5.0 VDC. The voltage on this pin determines the logic level high threshold for the digital inputs. The voltage on VL is the maximum allowable input level for all digital inputs. DSD_A and DSD_B 3 and 4 DSD Audio Data (Inputs) - Direct Stream Digital audio data is clocked into DSD_A and DSD_B via the DSD serial clock. 5 DSD_Mode DSD Mode (Input) - This pin must be set to a logic `1' and M0-M2 must be properly set to access the DSD Mode in Stand-Alone Mode. Refer to Table 13.In Control Port Mode, this pin must be set to a logic `1' and the Control Registers must be properly set to access the DSD Mode. Refer to register descriptions in Section 4. 6 MCLK Master Clock (Input) - The master clock frequency must be either 4x, 6x, 8x or 12x the DSD data rate for 64x oversampled DSD data or 2x, 3x, 4x or 6x the DSD data rate for 128x oversampled DSD data. 7 DSD_SCLK DSD Serial Clock (Input) - Clocks the individual bits of the DSD audio data into the DSD_A and DSD_B pins. DSD Mode Pin Descriptions DS459PP1 27 CS4392 8, 9, Mode Select (Inputs) - The Mode Select Pins, M0-M2, select the operational mode of M2, M1 and M0 (Stand-alone Mode) and 10 the device while in stand-alone mode. DSD_Mode 1 1 1 1 1 1 1 1 M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 DESCRIPTION 64x oversampled DSD data with a 4x MCLK to DSD data rate 64x oversampled DSD data with a 6x MCLK to DSD data rate 64x oversampled DSD data with a 8x MCLK to DSD data rate 64x oversampled DSD data with a 12x MCLK to DSD data rate 128x oversampled DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate Table 13. Direct Stream Digital (DSD), Stand-Alone Mode Options SDA/CDIN (Control Port Mode) SCL/CCLK (Control Port Mode) AD0 / CS (Control Port Mode) 8 9 10 Serial Control Data I/O (Input/Output) - In Two-Wire mode, SDA is a data I/O line. CDIN is the input data line for the control port interface in SPI mode. Serial Control Interface Clock (Input) - Clocks the serial control data into or from SDA/CDIN. Address Bit / Chip Select (Input) - In Two-Wire mode, AD0 is a chip address bit. CS is used to enable the control port interface in SPI mode. The device will enter the SPI mode at anytime a high to low transition is detected on this pin. Once the device has entered the SPI mode, it will remain in SPI mode until either the part is reset or undergoes a power-down cycle. Positive Voltage Reference (Output) - Positive reference for internal sampling circuits. External capacitors are required from FILT+ to analog ground, as shown in Figure 6. The recommended values will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 Hz. FILT+ is not intended to supply external current. FILT+ has a typical source impedance of 250 k and any current drawn from this pin will alter device performance. Common Mode Voltage (Output) - Filter connection for internal common mode reference voltage, typically 50% of VA. Capacitors must be connected from CMOUT to analog ground, as shown in Figure 6. CMOUT is not intended to supply external current. CMOUT has a typical source impedance of 250 k and any current drawn from this pin will alter device performance. FILT+ 11 CMOUT 12 AMUTEC and BMUTEC 13 and Channel A and Channel B Mute Control (Output) - The Mute Control pins go high dur20 ing power-up initialization, reset, muting, when master clock to left/right clock fre- quency ratio is incorrect, or power-down. These pins are intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single supply system. Use of Mute Control is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. AOUTB+, AOUTBand AOUTA+, AOUTA AGND 14, 15, Differential Analog Audio Output (Output) - The fullscale differential output level is 18, and specified in the Analog Characteristics specification table. 19 16 17 Analog Ground (Input) Analog ground reference. Should be connected to analog ground. Analog Power (Input) - Analog power supply. Typically 5 VDC. DSD Mode Pin Descriptions VA 28 DS459PP1 CS4392 LRCK SCLK Left Channel Right Channel SDATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 9. Format 0, Left Justified up to 24-Bit Data LRCK SCLK Left Channel Right Channel SDATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 10. Format 1, I2S up to 24-Bit Data LRCK Left Channel Right Channel SCLK SDATA 15 14 13 12 11 10 9 8 7 6 5 43210 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 clocks Figure 11. Format 2, Right Justified 16-Bit Data LRCK Left Channel Right Channel SCLK SDATA 0 23 22 21 20 19 18 76543210 23 22 21 20 19 18 76543210 32 clocks Figure 12. Format 3, Right Justified 24-Bit Data DS459PP1 29 CS4392 LRCK Left Channel Right Channel SCLK SDATA 10 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 13. Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only) 32 clocks LRCK Right Channel Left Channel SCLK SDATA 10 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 14. Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only) 32 clocks 30 DS459PP1 CS4392 7. APPLICATIONS 7.1 Recommended Power-up Sequence for Hardware Mode 7.3 Analog Output and Filtering 1) Hold RST low until the power supplies, master, and left/right clocks are stable. 2) Bring RST high. 7.2 Recommended Power-up Sequence and Access to Control Port Mode 1) Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control port is reset to its default settings and CMOUT will remain low. 2) Bring RST high. The device will remain in a low power state with CMOUT low and the control port is accessible. 3) Write 30h to register 05h within 10 ms following the release of RST. 4) The desired register settings can be loaded while keeping the PDN bit set to 1. 5) Set the PDN bit to 0 which will initiate the power-up sequence which requires approximately 10 S. The application note "Design Notes for a 2-Pole Filter with Differential Input" discusses the second-order Butterworth filter and differential to single-ended converter which was implemented on the CS4392 evaluation board, CDB4392, as seen in Figure 15. The CS4392 filter is a linear phase design and does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry. 7.4 Interpolation Filter To accommodate the increasingly complex requirements of digital audio systems, the CS4392 incorporates selectable interpolation filters for each mode of operation. A "fast" and a "slow" roll-off filter is available in each of Single, Double, and Quad Speed modes. These filters have been designed to accommodate a variety of musical tastes and styles. Bit 5 of the Mode Control 3 register (06h) is used to select which filter is used. When the part is used without the control port, the "fast" roll-off filter is selected. DS459PP1 31 CS4392 3.32k 2700 pF 680 pF Aout - 3.01k 10 uF 1.58k 1 + 3 10 uF 47k C10 2 560 Analog_Ou Aout + 3.01k 10 uF 1.58k 2700 pF R17 3.32k 680 pF Figure 15. CS4392 Output Filter 32 DS459PP1 CS4392 8. CONTROL PORT INTERFACE The control port is used to load all the internal settings of the CS4392. The operation of the control port may be completely asynchronous to the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port has 2 modes: SPI and Two-Wire, with the CS4392 operating as a slave device in both modes. If Two-Wire operation is desired, AD0/CS should be tied to VA or AGND. If the CS4392 ever detects a high to low transition on AD0/CS after power-up, SPI mode will be selected. The control port registers are write-only in SPI mode. Upon release of the /RST pin, the CS4392 will wait approximately 100 ms before it begins its powerup sequence. The part defaults to Stand-Alone Mode, in which all operational modes are controlled as described in tables 9 through 12. The control port is active at all times, and if bit 5 of register 05h is set, the part enters Control-Port Mode and all operational modes are controlled by the control port registers. This bit can be set at any time, but to avoid unpredictable output noises, bit 5 and bit 4 of register 05h should be set before the end of the 100 ms power-up wait period. All registers can then be set as desired before releasing bit 4 of register 05h to begin the power-up sequence. If system requirements do not allow writing to the control port immediately following the release of /RST, the SDATA line should be held at logic "0" until the proper serial mode can be selected. must be 0010000. The eighth bit is a read/write indicator (R/W), which must be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next 8 bits are the data which will be placed into the register designated by the MAP. See Table 14 on page 34. The CS4392 has MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will auto increment after each byte is written, allowing block reads or writes of successive registers. 8.2 Two-Wire Mode In Two-Wire mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 3. There is no CS pin. Pin AD0 forms the partial chip address and should be tied to VA or AGND as required. The upper 6 bits of the 7bit address field must be 001000. To communicate with the CS4392 the LSB of the chip address field, which is the first byte sent to the CS4392, should match the setting of the AD0 pin. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If the operation is a write, the next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then followed by the data to be written. If the operation is a read, then the contents of the register pointed to by the MAP will be output after the chip address. The CS4392 has MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will auto increment after each byte is written, allowing block reads or writes of successive registers. Two-Wire mode is compatible with I2C. For more information on I2C, please see "The I2C-Bus Specification: Version 2.0", listed in the References section. 33 8.1 SPI Mode In SPI mode, CS is the CS4392 chip select signal, CCLK is the control port bit clock, CDIN is the input data line from the microcontroller and the chip address is 0010000. All signals are inputs and data is clocked in on the rising edge of CCLK. Figure 16 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address, and DS459PP1 CS4392 7 INCR 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 Reserved 0 2 MAP2 0 1 MAP1 0 0 MAP0 0 INCR (Auto MAP Increment Enable) Default = `0'. 0 - Disabled 1 - Enabled MAP0-2 (Memory Address Pointer) Default = `000'. Table 14. Memory Address Pointer (MAP) CS CCLK CHIP ADDRESS CDIN 0010000 R/W MAP MSB DATA LSB byte 1 MAP = Memory Address Pointer byte n Figure 16. Control Port Timing, SPI mode Note 1 SDA 001000 ADDR AD0 R/W ACK DATA 1-8 ACK DATA 1-8 ACK SCL Start Stop Note: If operation is a write, this byte contains the Memory Address Pointer, MAP. Figure 17. Control Port Timing, Two-Wire Mode 34 DS459PP1 CS4392 9. PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. 10. REFERENCES 1. "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2. CDB4392 Evaluation Board Datasheet 3. "The I2C-Bus Specification: Version 2.0" Philips Semiconductors, December 1998. http://www.semiconductors.philips.com DS459PP1 35 CS4392 11. PACKAGE DIMENSIONS 20L TSSOP (4.4 mm BODY) PACKAGE DRAWING N D E1 A2 A1 L E A e b SIDE VIEW END VIEW SEATING PLANE 123 TOP VIEW INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.03346 0.00748 0.252 0.248 0.169 -0.020 0 NOM -0.004 0.0354 0.0096 0.256 0.2519 0.1732 -0.024 4 MAX 0.043 0.006 0.037 0.012 0.259 0.256 0.177 0.026 0.028 8 MIN -0.05 0.85 0.19 6.40 6.30 4.30 -0.50 0 MILLIMETERS NOM --0.90 0.245 6.50 6.40 4.40 -0.60 4 MAX 1.10 0.15 0.95 0.30 6.60 6.50 4.50 0.65 0.70 8 NOTE 2,3 1 1 JEDEC #: MO-153 Controlling Dimension is Millimeters. Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips 36 DS459PP1 CS4392 . 20L SOIC (300 MIL BODY) PACKAGE DRAWING E H 1b c D L A SEATING PLANE e A1 DIM A A1 b C D E e H L MIN 0.093 0.004 0.013 0.009 0.496 0.291 0.040 0.394 0.016 0 INCHES NOM 0.098 0.008 0.017 0.011 0.504 0.295 0.050 0.407 0.025 4 MAX 0.104 0.012 0.020 0.013 0.512 0.299 0.060 0.419 0.050 8 MIN 2.35 0.10 0.33 0.23 12.60 7.40 1.02 10.00 0.40 0 MILLIMETERS NOM 2.50 0.20 0.43 0.28 12.80 7.50 1.27 10.34 0.64 4 MAX 2.65 0.30 0.51 0.32 13.00 7.60 1.52 10.65 1.27 8 JEDEC #: MS-013 Controlling Dimension is Millimeters DS459PP1 37 |
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