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* 8 AVR(R) * RISC
- 130 - - 32 8 - - 16 MHz 16 MIPS - - 8K Flash : 10,000 - Boot Boot - 512 EEPROM : 100,000 - 1K SRAM - - 8 / , - 16 / - RTC - PWM - TQFP MLF 8 ADC 8 10 ADC - PDIP 6 ADC 8 10 ADC - - USART - / SPI - - - - RC - / - 5 : ADC Standby I/O - 23 I/O - 28 PDIP ,32 TQFP ,32 MLF - 2.7 - 5.5V (ATmega8L) - 4.5 - 5.5V (ATmega8) - 0 - 8 MHz (ATmega8L) - 0 - 16 MHz (ATmega8) 4 Mhz , 3V, 25C - : 3.6 mA - : 1.0 mA - : 0.5 A
*
*
8KB Flash 8 ATmega8 ATmega8L
*
* * * *
2486N-AVR-07/04
PDIP
(RESET) PC6 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (XCK/T0) PD4 VCC GND (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7 (T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP1) PB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) PC1 (ADC1) PC0 (ADC0) GND AREF AVCC PB5 (SCK) PB4 (MISO) PB3 (MOSI/OC2) PB2 (SS/OC1B) PB1 (OC1A)
TQFP Top View
PD2 (INT0) PD1 (TXD) PD0 (RXD) PC6 (RESET) PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) 32 31 30 29 28 27 26 25
(INT1) PD3 (XCK/T0) PD4 GND VCC GND VCC (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22 21 20 19 18 17
PC1 (ADC1) PC0 (ADC0) ADC7 GND AREF ADC6 AVCC PB5 (SCK)
32 31 30 29 28 27 26 25
PD2 (INT0) PD1 (TXD) PD0 (RXD) PC6 (RESET) PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2)
(T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP1) PB0 (OC1A) PB1 (SS/OC1B) PB2 (MOSI/OC2) PB3 (MISO) PB4
MLF Top View
(INT1) PD3 (XCK/T0) PD4 GND VCC GND VCC (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22 21 20 19 18 17
PC1 (ADC1) PC0 (ADC0) ADC7 GND AREF ADC6 AVCC PB5 (SCK)
2
ATmega8(L)
2486N-AVR-07/04
(T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP1) PB0 (OC1A) PB1 (SS/OC1B) PB2 (MOSI/OC2) PB3 (MISO) PB4
NOTE: The large center pad underneath the MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the PCB to ensure good mechanical stability. If the center pad is left unconneted, the package might loosen from the PCB.
ATmega8(L)
ATmega8AVR RISC8CMOS ATmega8 1 MIPS/MHz Figure 1.
XTAL1 RESET PC0 - PC6 VCC XTAL2 PB0 - PB7
PORTC DRIVERS/BUFFERS
PORTB DRIVERS/BUFFERS
GND
PORTC DIGITAL INTERFACE
PORTB DIGITAL INTERFACE
MUX & ADC AGND AREF PROGRAM COUNTER
ADC INTERFACE
TWI
STACK POINTER
TIMERS/ COUNTERS
OSCILLATOR
PROGRAM FLASH
SRAM
INTERNAL OSCILLATOR
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS X
WATCHDOG TIMER
OSCILLATOR
INSTRUCTION DECODER
Y Z
MCU CTRL. & TIMING
CONTROL LINES
ALU
INTERRUPT UNIT
AVR CPU
STATUS REGISTER
EEPROM
PROGRAMMING LOGIC
SPI
USART
+ -
COMP. INTERFACE
PORTD DIGITAL INTERFACE
PORTD DRIVERS/BUFFERS
PD0 - PD7
3
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AVR 32 (ALU) CISC 10 ATmega8 :8K Flash( RWW) 512 EEPROM1K SRAM32 I/O 32 / (T/C), / USART 10 6 (8 TQFP MLF )ADC SPI CPU SRAM T/C SPI ADC CPU ADC I/O ADC Standby Atmel ISP Flash ISP AVR Flash(Application Flash Memory) FlashFlash(Boot Flash Memory) RWW 8 RISC CPU Flash ATmega8 ATmega8 C /
AVR
4
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
VCC GND B(PB7..PB0) XTAL1/XTAL2/TOSC1/TOSC2 B 8 I/O B PB6 PB7 RC ASSR AS2 PB7..6 T/C2 TOSC2..1 B P 55" B " P 22" " C(PC5..PC0) C 7 I/O C RSTDISBL PC6 I/O PC6 C RSTDISBL PC6 P 35Table 15 C D(PD7..PD0) D 8 I/O D D RESET P 35Table 15
PC6/RESET
5
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AVCC
AVCC A/D C (3..0) ADC (7..6) ADC VCC ADC VCC C (5..4) VCC A/D TQFPMLFADC7..6A/D 10ADC C C
AREF ADC7..6(TQFP MLF )
6
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
AVR CPU

AVR CPU Figure 2. AVR MCU
Data Bus 8-bit
Flash Program Memory
Program Counter
Status and Control
Instruction Register
32 x 8 General Purpose Registrers
Interrupt Unit SPI Unit Watchdog Timer
Indirect Addressing
Instruction Decoder
Direct Addressing
ALU
Control Lines
Analog Comparator
i/O Module1
Data SRAM
i/O Module 2
i/O Module n EEPROM
I/O Lines
AVR Harvard CPU ( ) Flash 32 8 ALU ALU 6 3 16 16 X Y Z ALU ALU
7
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/ 16 16 32 (Boot ) / SPM (PC) SRAM SRAM SP I/O SRAM 5 AVR AVR I/O I/O 64 CPU SPI I/O 0x20 - 0x5F
8
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
ALU
AVR ALU 32 ALU ALU 3 / ALU AVR SREG
Bit / 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG
* Bit 7 - I: I I I RETI I I SEI CLI * Bit 6 - T: BLD BST T BST T BLD T * Bit 5 - H: H BCD * Bit 4 - S: , S = N
V
S N 2 V * Bit 3 - V:2 2 * Bit 2 - N: * Bit 1 - Z: * Bit 0 - C:
AVR RISC / * * * * 8 8 8 8 8 16 16 16
Figure 3 CPU 32
9
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Figure 3. AVR CPU
7 R0 R1 R2 ... R13 R14 R15 R16 R17 ... R26 R27 R28 R29 R30 R31 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X X Y Y Z Z 0x0D 0x0E 0x0F 0x10 0x11 0 Addr. 0x00 0x01 0x02
Figure 3 32 SRAM X Y Z
10
ATmega8(L)
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ATmega8(L)
XYZ R26..R31 Figure 4 Figure 4. X Y Z
15 X 7 R27 (0x1B) XH 0 7 R26 (0x1A) XL 0 0
15 Y 7 R29 (0x1D)
YH 0 7 R28 (0x1C)
YL
0 0
15 Z 7 R31 (0x1F)
ZH 0 7 R30 (0x1E)
ZL 0
0

/ AVR SRAM 0x60 PUSH POP RET RETI AVRI/O8 AVR SPL SPH
Bit 15 SP15 SP7 7 / R/W R/W 0 0 14 SP14 SP6 6 R/W R/W 0 0 13 SP13 SP5 5 R/W R/W 0 0 12 SP12 SP4 4 R/W R/W 0 0 11 SP11 SP3 3 R/W R/W 0 0 10 SP10 SP2 2 R/W R/W 0 0 9 SP9 SP1 1 R/W R/W 0 0 8 SP8 SP0 0 R/W R/W 0 0 SPH SPL
AVR CPU clkCPU Figure 5 Harvard 1 MIPS/MHz / /
11
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Figure 5.
T1 T2 T3 T4
clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch
Figure 6 ALU Figure 6. ALU
T1 T2 T3 T4
clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back
AVR I PC BLB02 BLB12 P 209" " P 43" " RESET INT0 - 0 (GICR) IVSEL Flash P 43"" BOOTRST Flash P 196" (RWW, Read-While-Write) " I I RETI I "1" "0" I
12
ATmega8(L)
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ATmega8(L)
AVR CLI CLI CLI EEPROM EEPROM
in cli r16, SREG ; ; EEPROM ; SREG (I ) ; SREG
sbi EECR, EEMWE sbi EECR, EEWE out SREG, r16
C
char cSREG; cSREG = SREG; /* */ _CLI(); EECR |= (1< SEI
sei ; sleep ; ; : MCU
C
_SEI(); /* */ _SLEEP(); /* */ /* : MCU */
AVR 4 4 4 PC 3 MCU MCU 4 4 PC( ) SREG I
13
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AVR ATmega8
ATmega8 AVR ATmega8 EEPROM
Flash ATmega88KFlash AVR 1632 Flash4K x 16 Flash
(Boot) Flash 10,000 ATmega8 (PC) 12 4K P 196" (RWW, Read-While-Write) " P 209" " SPI Flash ( LPM ) P 11" " Figure 7.
$000
Application Flash Section
Boot Flash Section $FFF
14
ATmega8(L)
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ATmega8(L)
SRAM
Figure 8 ATmega8 SRAM 1120 I/O SRAM 96 I/O 1024 SRAM 5 R26 R31 Y Z 63 X Y Z ATmega8 32 64 I/O 1024 SRAM P 9" " Figure 8.
Register File R0 R1 R2 ... R29 R30 R31 I/O Registers $00 $01 $02 ... $3D $3E $3F Data Address Space $0000 $0001 $0002 ... $001D $001E $001F $0020 $0021 $0022 ... $005D $005E $005F Internal SRAM $0060 $0061 ... $045E $045F
15
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SRAM clkCPU Figure 9 Figure 9. SRAM
T1 T2 T3
clkCPU Address Data WR Data RD
Compute Address Address Valid
Memory Vccess Instruction
Next Instruction
EEPROM
ATmega8 512 EEPROM EEPROM 100,000 EEPROM P 209" " SPI EEPROM
EEPROM /
EEPROM I/O EEPROM Table 1 EEPROM / VCC / CPU P 20 " EEPROM " EEPROM EEPROM EEPROM EEPROM CPU 4 EEPROM CPU 2
16
ATmega8(L)
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Read
Write
ATmega8(L)
EEPROM EEARH EEARL
Bit 15 - EEAR7 7 / R R/W 0 X 14 - EEAR6 6 R R/W 0 X 13 - EEAR5 5 R R/W 0 X 12 - EEAR4 4 R R/W 0 X 11 - EEAR3 3 R R/W 0 X 10 - EEAR2 2 R R/W 0 X 9 - EEAR1 1 R R/W 0 X 8 EEAR8 EEAR0 0 R/W R/W X X EEARH EEARL
* Bits 15..9 - Res: * Bits 8..0 - EEAR8..0: EEPROM EEPROM- EEARHEEARL512EEPROM EEPROM 0 511EEAR EEPROM EEPROM EEDR
Bit / 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 EEDR
* Bits 7..0 - EEDR7..0: EEPROM EEPROM EEDR EEAR EEDR EEAR EEPROM EECR
Bit / 7
-
6
-
5
-
4
-
3
EERIE
2
EEMWE
1
EEWE
0
EERE EECR
R 0
R 0
R 0
R 0
R/W 0
R/W 0
R/W X
R/W 0
* Bits 7..4 - Res: * Bit 3 - EERIE: EEPROM SREG I "1" EERIE EEPROM EERIE EEWE EEPROM * Bit 2 - EEMWE: EEPROM EEMWEEEWEEEPROM EEMWE"1" 4 EEWE EEPROM EEMWE "0" EEWE EEMWE 4 EEPROM EEWE * Bit 1 - EEWE: EEPROM EEWE EEPROM EEPROM EEWE EEPROM EEMWE EEPROM ( 3 4 ) 1. EEWE 2. SPMCSR SPMEN 3. EEPROM EEAR( )
17
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4. EEPROM EEDR( ) 5. EECR EEMWE "1" EEWE 6. EEMWE 4 EEWE CPU Flash EEPROM EEPROM Flash (2) CPU Flash CPU Flash (2) P 196" (RWW, Read-While-Write) " 5 6 EEPROM EEPROM EEPROM EEAR EEDR EEPROM I EEWE EEWE CPU * Bit 0 - EERE: EEPROM EEREEEPROM EEPROM EERE EEAR EEPROM EEPROM CPU 4 EEPROM EEWE EEPROM EEAR EEPROM Table 1 CPU EEPROM Table 1. EEPROM
EEPROM (CPU) Note: RC (1) 8448 1. 1 MHz CKSEL 8.5 ms
18
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
C EEPROM Boot Loader Boot Loader EEPROM SPM
EEPROM_write: ; sbic EECR,EEWE rjmp EEPROM_write ; (r18:r17) out out out sbi sbi ret EEARH, r18 EEARL, r17 EEDR,r16 EECR,EEMWE EECR,EEWE
; (r16) ; EEMWE ; EEWE
C
void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* */ while(EECR & (1<19
2486N-AVR-07/04
C EEPROM
EEPROM_read: ; sbic EECR,EEWE rjmp EEPROM_read ; (r18:r17) out out sbi in ret EEARH, r18 EEARL, r17 EECR,EERE r16,EEDR
; EERE ;
C
unsigned char EEPROM_read(unsigned int uiAddress) { /* */ while(EECR & (1< EEPROM EEPROM
EEPROM EEPROM EEPROM CPU EEPROM EEPROM ( ) EEPROM EEPROM EEPROM CPU EEPROM AVR RESET BOD BOD
I/O
ATmega8 I/O P 271"" ATmega8I/OI/O I/OIN OUT 32 I/O 0x00 - 0x1F I/O SBI CBI SBIS SBIC IN OUT 0x00 - 0x3F SRAM LD ST I/O 0x20
20
ATmega8(L)
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ATmega8(L)
"0" I/O "1" AVR CBI SBI CBI SBI 0x00 0x1F I/O
21
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Figure 10AVR P 30" " Figure 10 Figure 10.
Asynchronous Timer/Counter General I/O Modules ADC CPU Core RAM Flash and EEPROM
clkADC clkI/O clkASY clkCPU clkFLASH
AVR Clock Control Unit
Reset Logic
Watchdog Timer
Source Clock Clock Multiplexer
Watchdog Clock Watchdog Oscillator
Timer/Counter Oscillator
External RC Oscillator
External Clock
Crystal Oscillator
Low-Frequency Crystal Oscillator
Calibrated RC Oscillator
CPU clkCPU I/O clkI/O
CPUAVR CPU I/O I/O / SPI USART I/O I/O USI clkI/O Flash Flash CPU
Flash clkFLASH
22
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
clkASY / 32 kHz / / CPU XTAL ADC ADCCPUI/O ADC ATmega8Flash AVR Table 2. (1)
/ RC RC Note: 1. "1" "0" CKSEL3..0 1111 - 1010 1001 1000 - 0101 0100 - 0001 0000
ADC clkADC
CPU CPU MCU WDT Table 3 "ATmega8 " CKSEL = "0001" SUT = "10" (1 MHz RC ) Table 3.
(VCC = 5.0V) 4.1 ms 65 ms (VCC = 3.0V) 4.3 ms 69 ms 4K (4,096) 64K (65,536)
23
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XTAL1 XTAL2 Figure 11 CKOPT CKOPT XTAL2 CKOPT CKOPT 8 MHz CKOPT 16 MHz C1 C2 Table 4 Figure 11.
C2 C1
XTAL2 XTAL1 GND
CKSEL3..1 Table 4 Table 4.
CKOPT 1 1 1 0 Note: CKSEL3..1 101(1) 110 111 101, 110, 111 (MHz) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 1.0 C1 C2 (pF) - 12 - 22 12 - 22 12 - 22
1.
Table 5 CKSEL0 SUT1..0
24
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Table 5.
CKSEL0 0 0 0 0 1 1 1 1 Notes: SUT1..0 00 01 10 11 00 01 10 11 258 CK(1) 258 CK(1) 1K CK(2) 1K CK(2) 1K CK(2) 16K CK 16K CK 16K CK (VCC = 5.0V) 4.1 ms 65 ms - 4.1 ms 65 ms - 4.1 ms 65 ms BOD BOD
1. 2.
32.768 kHz CKSEL "1001" Figure 11 CKOPT XTAL1 XTAL2 36 pF SUT Table 6 Table 6.
SUT1..0 00 01 10 11 Note: 1K CK
(1)
(VCC = 5.0V) 4.1 ms 65 ms 65 ms
BOD
1K CK(1) 32K CK
1.
RC
Figure 12 Figure 12 RC f = 1/(3RC) C 22 pF CKOPT XTAL1 GND 36 pF
25
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Figure 12. RC
VCC NC
R
XTAL2 XTAL1
C GND
CKSEL3..0 Table 7 Table 7. RC
CKSEL3..0 0101 0110 0111 1000 (MHz) 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 12.0
SUT Table 8 Table 8. RC
SUT1..0 00 01 10 11 Note: 18 CK 18 CK 18 CK 6 CK(1) (VCC = 5.0V) - 4.1 ms 65 ms 4.1 ms BOD BOD
1.
26
ATmega8(L)
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ATmega8(L)
RC
RC 1.0 2.0 4.0 8.0 MHz 5V 25C Table 9 CKSEL (CKOPT) OSCCAL RC 5V 25C 1.0 MHz 3% www.atmel.com/avr 1% P 211" " Table 9. RC
CKSEL3..0 0001(1) 0010 0011 0100 Note: 1. (MHz) 1.0 2.0 4.0 8.0
SUT Table 10 PB6 (XTAL1/TOSC1) PB7(XTAL2/TOSC2) I/O Table 10. RC
SUT1..0 00 01 10
(1)
6 CK 6 CK 6 CK
(VCC = 5.0V) - 4.1 ms 65 ms
BOD
11 Note: 1.
27
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OSCCAL
Bit /
7 CAL7 R/W
6 CAL6 R/W
5 CAL5 R/W
4 CAL4 R/W
3 CAL3 R/W
2 CAL2 R/W
1 CAL1 R/W
0 CAL0 R/W OSCCAL
* Bits 7..0 - CAL7..0: 1 MHz ( 0x00) OSCCAL RC Flash EEPROM OSCCAL OSCCAL 0xFF EEPROM Flash EEPROM Flash 10% 1.0 2.0 4.08.0 MHz Table 11 Table 11. RC
OSCCAL 0x00 0x7F 0xFF (%) 50 75 100 (%) 100 150 200
28
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
XTAL1 Figure 13 CKSEL"0000" CKOPT XTAL1 GND 36 pF Figure 13.
EXTERNAL CLOCK SIGNAL
SUT Table 12 Table 12.
SUT1..0 00 01 10 11 6 CK 6 CK 6 CK (VCC = 5.0V) - 4.1 ms 65 ms BOD
MCU 2% MCU
/
/ (TOSC1 TOSC2) AVR 32.768 kHz TOSC1
29
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MCU AVR MCUCR SE SLEEP ( ADC Standby ) MCUCR SM2SM1 SM0 Table 13 MCU 4 MCU SLEEP SRAM MCU TOSC XTAL AVR MCU Standby ATmega8 P 22Figure 10 ATmega8
MCU MCUCR
MCU
Bit / 7 SE R/W 0 6 SM2 R/W 0 5 SM1 R/W 0 4 SM0 R/W 0 3 ISC11 R/W 0 2 ISC10 R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR
* Bit 7 - SE: MCU SLEEP SE SLEEP SEMCU SE * Bits 6..4 - SM2..0: 2 1 0 Table 13 Table 13.
SM2 0 0 0 0 1 1 1 Note: SM1 0 0 1 1 0 0 1 SM0 0 1 0 1 0 1 0 ADC Standby(1)
1. Standby
30
ATmega8(L)
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ATmega8(L)
SM2..0 000 SLEEP MCU CPU SPI USART ADC / clkCPU clkFLASH USART MCU MCU ACSR ACD ADC
ADC
SM2..0 001 SLEEP MCU CPU ADC / 2 clkI/O clkCPU clkFLASH ADC ADC AD ADC BOD / 2 SPM/EEPROM INT0 INT1 INT2 MCU ADC
SM2..0 010 SLEEP MCU BOD INT0 INT1 INT2 MCU MCU P 62" " CKSEL P 23" "
SM2..0 011 SLEEP MCU / 2 ASSR AS2 / 2 / 2 MCU TIMSK SREG I AS2 0 MCU clkASY
Standby
SM2..0 110 SLEEP MCU Standby 6
Table 14.
INT1 TWI INT0 X(2) X(2) X X(3) X X
2
ADC
clkCPU clkFLASH clkIO clkADC clkASY X X X X X
X X
SPM/ EEPROM ADC X X X X
I/O X
X X
31
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Table 14.
INT1 TWI INT0 X(3) X(2) X X(2) X(3) X(3) X X X X(2)
2
Standby (1) Notes:
clkCPU clkFLASH clkIO clkADC clkASY
SPM/ EEPROM ADC
I/O
1. 2. ASSR AS2 3. INT1 INT0
AVR ADC ADC P 183" " ADC P 180" "
(ADC)
32
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
BOD BOD BODEN BOD P 37" " BOD BOD ADC P 39" " P 40" " I/O clkI/O ADC clkADC P 52" " VCC/2
33
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AVR I/O JMP Boot -- -- Figure 14 Table 15 I/O MCU SUT CKSEL P 23" " ATmega8 4 * * * * VPOT MCU RESET MCU VBOT MCU
Figure 14.
DATA BUS
MCU Control and Status Register (MCUCSR) PORF BORF EXTRF WDRF BODEN BODLEVEL Brown-Out Reset Circuit Pull-up Resistor
SPIKE FILTER
Watchdog Oscillator
Clock Generator
CK
Delay Counters TIMEOUT
CKSEL[3:0] SUT[1:0]
34
ATmega8(L)
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ATmega8(L)
Table 15.
( )(1) ( ) RESET RESET (2) BODLEVEL = 1 BODLEVEL = 0 BODLEVEL = 1 BODLEVEL = 0 2.4 3.7 2.6 4.0 2 2 130 0.1 1.4 1.3 2.3 2.3 0.9 1.5 2.9 4.5 V V VCC s V s s mV
VPOT
VRST tRST VBOT tBOD VHYST Notes:
1. VPOT 2. VBOT VCC = VBOT VCC ATmega8LBODLEVEL=1 ATmega8BODLEVEL=0 BODLEVEL=1 ATmega8
(POR) Table 15 VCC POR POR POR CC V VCC RESET Figure 15. MCU RESET VCC
VCC VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
35
2486N-AVR-07/04
Figure 16. MCU RESET
VCC VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
36
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
RESET ( Table 15) VRST( ) tTOUT MCU Figure 17.
CC
ATmega8 BOD(Brown-out Detection) VCC BODLEVEL2.7V (BODLEVEL ) 4.0V (BODLEVEL ) BOD VBOT+ = VBOT + VHYST/2 VBOT- = VBOT - VHYST/2 BOD BODEN BOD(BODEN) VCC (VBOT- Figure 18) BOD VCC (VBOT+ Figure 18) tTOUT MCU VCC Table 15 tBOD BOD Figure 18.
VCC VBOTVBOT+
RESET
TIME-OUT
tTOUT
INTERNAL RESET
37
2486N-AVR-07/04
1 CK tTOUT Figure 19.
CC
CK
MCU MCUCSR
MCU MCU
Bit / 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 WDRF R/W 2 BORF R/W 1 EXTRF R/W 0 PORF R/W MCUCSR
* Bit 7..4 - Res: "0" * Bit 3 - WDRF: "0" * Bit 2 - BORF: "0" * Bit 1 - EXTRF: "0" * Bit 0 - PORF: "0"
38
ATmega8(L)
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ATmega8(L)
ATmega8 ADC ADC 2.56V Table 16 1. BOD ( BODEN ) 2. (ACSR ACBG ) 3. ADC BOD ACBG ADC Table 16.
VBG tBG IBG 1.15 1.23 40 10 1.40 70 V s A
39
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1 MHz VCC = 5V VCC P 41Table 17 WDR 8 ATmega8 P 38 Figure 20.
WATCHDOG OSCILLATOR
WDTCR
Bit /
7 - R 0
6 - R 0
5 - R 0
4 WDCE R/W 0
3 WDE R/W 0
2 WDP2 R/W 0
1 WDP1 R/W 0
0 WDP0 R/W 0 WDTCR
* Bits 7..5 - Res: * Bit 4 - WDCE: WDE WDCE 4 WDE 1 2 WDCE
40
ATmega8(L)
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ATmega8(L)
* Bit 3 - WDE: WDE"1" WDCE"1"WDE 1. WDCE WDE "1" WDE "1" 2. 4 WDE "0" * Bits 2..0 - WDP2, WDP1, WDP0: 2, 1, 0 WDP2 WDP1 WDP0 Table 17 Table 17.
WDP2 0 0 0 0 1 1 1 1 WDP1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 WDT 16K (16,384) 32K (32,768) 64K (65,536) 128K (131,072) 256K (262,144) 512K (524,288) 1,024K (1,048,576) 2,048K (2,097,152) VCC = 3.0V 17.1 ms 34.3 ms 68.5 ms 0.14 s 0.27 s 0.55 s 1.1 s 2.2 s VCC = 5.0V 16.3 ms 32.5 ms 65 ms 0.13 s 0.26 s 0.52 s 1.0 s 2.1 s
C WDT ( )
41
2486N-AVR-07/04

WDT_off: ; WDT wdr ; WDCE WDE in ori r16, WDTCR r16, (1<out WDTCR, r16 ; WDT ldi ret r16, (0<C
void WDT_off(void) { /* WDT */ _WDR() /* WDCE WDE */ WDTCR |= (1< 1(WDTON )
WDE ( ) 1. WDCE WDE "1" WDE "1" 2. 4 WDE WDP WDCE "0"
2(WDTON )
WDE "1" 1. WDCEWDE"1" WDE "1" 4 WDCE "0" WDP WDE
42
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
ATmega8
Table 18.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Notes: (2) 0x000
(1)
ATmega8 AVR P 12" "
RESET INT0 INT1 TIMER2 COMP TIMER2 OVF TIMER1 CAPT TIMER1 COMPA TIMER1 COMPB TIMER1 OVF TIMER0 OVF SPI, STC USART, RXC USART, UDRE USART, TXC ADC EE_RDY ANA_COMP TWI SPM_RDY
0 1 / 2 / 2 / 1 / 1 A / 1 B / 1 / 0 SPI USART, Rx USART USART, Tx ADC EEPROM
0x001 0x002 0x003 0x004 0x005 0x006 0x007 0x008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 0x012
1. BOOTRST MCUBoot Loader P 196" (RWW, Read-While-Write) " 2. GICRIVSEL Boot Boot
Table 19BOOTRST/IVSEL Boot Table 19.
BOOTRST(1) 1 1 0 0 IVSEL 0 1 0 1 0x000 0x000 Boot Boot 0x001 Boot + 0x001 0x001 Boot + 0x001
43
2486N-AVR-07/04
Note:
1. Boot P 207Table 82 BOOTRST "0" "1"

ATmega8
0x000 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0x008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 0x012 0x013 0x014 ; 0x015 RESET: 0x016 0x017 0x018 0x019 0x020 ... ...
rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp ldi out ldi out sei
RESET EXT_INT0 EXT_INT1 TIM2_COMP TIM2_OVF TIM1_CAPT TIM1_COMPA TIM1_COMPB TIM1_OVF TIM0_OVF SPI_STC USART_RXC USART_UDRE USART_TXC ADC EE_RDY ANA_COMP TWSI EXT_INT2 TIM0_COMP SPM_RDY
; ; IRQ0 ; IRQ1 ; Timer2 ; Timer2 ; Timer1 ; Timer1 A ; Timer1 B ; Timer1 ; Timer0 ; SPI ; USART RX ; UDR ; USART TX ; ADC ; EEPROM ; ; ; IRQ2 ; Timer0 ; SPM
r16,high(RAMEND) ; SPH,r16 SPL,r16 ; ; RAM r16,low(RAMEND)
xxx ...
44
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
BOOTRST Boot 2K GICR IVSEL

$000 ; $001 $002 $003 $004 $005 $006 ; .org $c01 $c01 $c02 ... $c12
rjmp RESET:ldi out ldi out sei
RESET
;
r16,high(RAMEND); SPH,r16 r16,low(RAMEND) SPL,r16 ; xxx ; RAM

rjmp rjmp ... rjmp
EXT_INT0 EXT_INT1 ... ; SPM_RDY
; IRQ0 ; IRQ1 ; SPM
BOOTRST Boot 2K BOOTRST Boot 2K

.org 0x001 0x001 0x002 ... 0x014 ; .org $c00 $c00 ; $c01 $c02 $c03 $c04 $c05 $c06 rjmp RESET ; ... . rjmp rjmp .. rjmp SPM_RDY EXT_INT0 EXT_INT1 ; IRQ0 ; IRQ1 ; ; SPM
RESET:ldi out ldi out sei
r16,high(RAMEND); SPH,r16 SPL,r16 ; xxx ; RAM r16,low(RAMEND)

45
2486N-AVR-07/04
BOOTRST Boot 2K GICR IVSEL

; .org $c00 $c00 $c01 $c02 ... $c12 $c13 $c14 $c15 $c16 $c17 $c18 rjmp rjmp rjmp ... rjmp RESET: ldi out ldi out sei xxx RESET EXT_INT0 EXT_INT1 ... ; SPM_RDY SPH,r16 SPL,r16 ; ; SPM ; RAM r16,high(RAMEND); r16,low(RAMEND) ; Reset ; IRQ0 ; IRQ1
Boot GICR
Bit /
7 INT1 R/W 0
6 INT0 R/W 0
5 - R 0
4 - R 0
3 - R 0
2 - R 0
1 IVSEL R/W 0
0 IVCE R/W 0 GICR
* Bit 1 - IVSEL: IVSEL "0" Flash IVSEL "1" Boot Boot BOOTSZ P 196" (RWW, Read-While-Write) " IVSEL 1. IVCE 2. 4 IVSEL IVCE "0" IVCE IVSEL IVSEL IVCE 4 I Boot Boot BLB02 Boot BLB12 Boot Boot P 196" (RWW, Read-
While-Write) "
46
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
* Bit 0 - IVCE: IVSEL IVCE IVCE IVSEL 4 IVCE IVCE
Move_interrupts: ; ldi out ldi out ret r16, (1<; boot Flash
C
void Move_interrupts(void) { /* */ GICR = (1<47
2486N-AVR-07/04
I/O
I/O AVR I/O - - SBI CBI ( / ) ( / ) LED VCC Figure 21 P 226" " Figure 21. I/O
Rpu
Pxn
Logic Cpin
See Figure "General Digital I/O" for Details
"x" "n" PORTB3 B 3 PORTxn I/O P 61"I/O " I/O - PORTx - DDRx - PINx / PINx "1" "0" "1" SFIOR PUD I/O P 48" I/O " P 53" " I/O
I/O
I/O Figure 22 I/O
48
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 22. I/O(1)
PUD
Q
D
DDxn Q CLR
RESET
WDx
RDx
Pxn
Q
D
PORTxn Q CLR
WPx RESET SLEEP RRx
SYNCHRONIZER
D Q D Q
RPx
PINxn L Q Q
clk I/O
PUD: SLEEP: clkI/O:
PULLUP DISABLE SLEEP CONTROL I/O CLOCK
WDx: RDx: WPx: RRx: RPx:
WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN
Note:
1. WPx, WDx, RRx, RPx RDx clkI/O, SLEEP PUD
DDxn PORTxn PINxn P 61"I/O " DDxn DDRx PORTxn PORTx PINxn PINx DDxn DDxn "1" Pxn PORTxn "1" PORTxn PORTxn "1" ("1") ("0") ( ) ({DDxn, PORTxn} = 0b00) ({DDxn, PORTxn} = 0b11) ({DDxn, PORTxn} = 0b01) ({DDxn, PORTxn} = 0b10) SFIOR PUD ({DDxn, PORTxn} = 0b00) ({DDxn, PORTxn} = 0b11)
2486N-AVR-07/04
DATA BUS
49
Table 20 Table 20.
DDxn 0 0 0 1 1 PORTxn 0 1 1 0 1 PUD (SFIOR) X 0 1 X X I/O No Yes No No No (Hi-Z) (Hi-Z) ( ) ( )
DDxn PINxn Figure 22 PINxn Figure 23 tpd,max tpd,min Figure 23.
SYSTEM CLK INSTRUCTIONS SYNC LATCH PINxn r17
0x00 t pd, max t pd, min 0xFF XXX XXX in r17, PINx
SYNC LATCH PINxn tpd,max tpd,min 1/2 ~ 11/2 Figure 24 out in nop out SYNC LATCH tpd
50
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 24.
SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17
0x00 t pd 0xFF out PORTx, r16 nop 0xFF
in r17, PINx
51
2486N-AVR-07/04
B 0 1 2 3 4 7 6 7 nop (1)
... ; ; ldi ldi out out nop ; in ... r16,PINB r16,(1<; nop
C (1)
unsigned char i; ... /* */ /* */ PORTB = (1<Note:
1. 0 1 6 7 2 3 0 1
Figure 22 ( ) SLEEP MCU Standby VCC/2 SLEEP SLEEP SLEEP P 53" " ("1") " " "1" "0" "0" "1"
( )
52
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
VCC GND
I/O Figure 25 Figure 22 AVR Figure 25. (1)
PUOExn PUOVxn
1 0
PUD
DDOExn DDOVxn
1 0
QD DDxn Q CLR
PVOExn PVOVxn
WDx RESET RDx
1 Pxn 0
Q D PORTxn
DIEOExn DIEOVxn
1 0
Q CLR
WPx RESET RRx
SLEEP SYNCHRONIZER
D
SET
RPx
Q
D
Q
PINxn L
CLR
Q
CLR
Q
clk I/O
DIxn
AIOxn
PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP:
Pxn PULL-UP OVERRIDE ENABLE Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn PORT VALUE OVERRIDE ENABLE Pxn PORT VALUE OVERRIDE VALUE Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP CONTROL
PUD: WDx: RDx: RRx: WPx: RPx: clkI/O: DIxn: AIOxn:
PULLUP DISABLE WRITE DDRx READ DDRx READ PORTx REGISTER WRITE PORTx READ PORTx PIN I/O CLOCK DIGITAL INPUT PIN n ON PORTx ANALOG INPUT/OUTPUT PIN n ON PORTx
Note:
1. WPx, WDx, RRx, RPxRDx I/O, SLEEP clk PUD
Table 21 Figure 25
DATA BUS
53
2486N-AVR-07/04
Table 21.
PUOE PUOV {DDxn, PORTxn, PUD} = 0b010 PUOE DDxnPORTxn PUD PUOV / / DDOV DDxn DDOE DDOV / / DDxn PVOV PVOE PORTxn PVOE PVOV PORTxn DIEOV DIEOE MCU ( ) DIEOE DIEOV / / MCU ( ) /
PUOV
DDOE DDOV PVOE
PVOV DIEOE
DIEOV
DI
AIO
/

54
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
I/O SFIOR
Bit / 7 R 0 6 R 0 5 R 0 4 R 0 3 ACME R/W 0 2 PUD R/W 0 1 PSR2 R/W 0 0 PSR10 R/W 0 SFIOR
* Bit 2 - PUD: DDxn PORTxn ({DDxn, PORTxn} = 0b01) I/O P 49" " B B Table 22 Table 22. B
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 XTAL2 ( 2) TOSC2 ( 2) XTAL1 ( 1 ) TOSC1 ( 1) SCK (SPI ) MISO (SPI / ) MOSI (SPI / ) OC2 (T/C2 ) SS (SPI ) OC1B (T/C1 B ) OC1A (T/C1 A ) ICP1 (T/C1 )
* XTAL2/TOSC2 - B, Bit 7 XTAL2 2 I/O TOSC2 2 RC ASSR AS2 "1" T/C2 PB7 I/O PB7 DDB7 PORTB7 PINB7 "0" * XTAL1/TOSC1 - B, Bit 6 XTAL1 1 ( RC ) I/O TOSC1 1 RC ASSR AS2 "1" T/C2 PB6 I/O PB6 DDB6 PORTB6 PINB6 "0" * SCK - B, Bit 5
55
2486N-AVR-07/04
SCKSPI DDB5 DDB5 PORTB5 * MISO - B, Bit 4 MISOSPI DDB4 DDB4 PORTB4 * MOSI/OC2 - B, Bit 3 MOSISPI DDB3 DDB3 PORTB3 OC2PB3 T/C2 PB3 OC2 PWM * SS/OC1B - B, Bit 2 SS DDB2 SPI DDB2 PORTB2 OC1B PB2 T/C1 PB2 OC1B PWM * OC1A - B, Bit 1 OC1A PB1 T/C1 A PB1 OC1A PWM * ICP1 - B, Bit 0 ICP1 - PB0 T/C1 Table 23 Table 24 B P 53Figure 25 SPI MSTR INPUT SPI SLAVE OUTPUT MISO MOSISPI MSTR OUTPUT SPI SLAVE INPUT Table 23. PB7..PB4
PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PB7/XTAL2/ TOSC2(1)(2) EXT * (INTRC + AS2) 0 EXT * (INTRC + AS2) 0 0 0 EXT * (INTRC + AS2) 0 - PB6/XTAL1/ TOSC1(1) INTRC + AS2 0 INTRC + AS2 0 0 0 INTRC + AS2 0 - / PB5/SCK SPE * MSTR PORTB5 * PUD SPE * MSTR 0 SPE * MSTR SCK 0 0 SCK - PB4/MISO SPE * MSTR PORTB4 * PUD SPE * MSTR 0 SPE * MSTR SPI 0 0 SPI -
56
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Notes: 1. INTRC RC ( CKSEL ) 2. EXT RC ( CKSEL )
Table 24. PB3..PB0
PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PB3/MOSI/OC2 SPE * MSTR PORTB3 * PUD SPE * MSTR 0 SPE * MSTR + OC2 SPI + OC2 0 0 SPI - PB2/SS/OC1B SPE * MSTR PORTB2 * PUD SPE * MSTR 0 OC1B OC1B 0 0 SPI SS - PB1/OC1A 0 0 0 0 OC1A OC1A 0 0 - - PB0/ICP1 0 0 0 0 0 0 0 0 ICP1 -
C
C Table 25 Table 25. C
PC6 PC5 PC4 PC3 PC2 PC1 PC0 RESET ( ) ADC5 (ADC 5) SCL ( ) ADC4 (ADC 4) SDA ( / ) ADC3 (ADC 3) ADC2 (ADC 2) ADC1 (ADC 1) ADC0 (ADC 0)
* RESET - C, Bit 6 RESET RSTDISBL I/O RSTDISBL I/O PC6 DDC6 PORTC6 PINC6 "0" * SCL/ADC5 - C, Bit 5 SCL TWCR TWEN 1 PC5 I/O 50 ns PC5 ADC 5 ADC 5 * SDA/ADC4 - C, Bit 4 57
2486N-AVR-07/04
SDA TWCR TWEN 1 PC1 I/O 50 ns PC4 ADC 4 ADC 4 * ADC3 - C, Bit 3 PC3 ADC 3 ADC 3 * ADC2 - C, Bit 2 PC2 ADC 2 ADC 2 * ADC1 - C, Bit 1 PC1 ADC 1 ADC 1 * ADC0 - C, Bit 0 PC0 ADC 0 ADC 0 Table 26 Table 27 C P 53Figure 25 Table 26. PC6..PC4
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PC6/RESET RSTDISBL 1 RSTDISBL 0 0 0 RSTDISBL 0 - PC5/SCL/ADC5 TWEN PORTC5 * PUD TWEN SCL_OUT TWEN 0 0 0 - ADC5 / SCL PC4/SDA/ADC4 TWEN PORTC4 * PUD TWEN SDA_OUT TWEN 0 0 0 - ADC4 / SDA
Table 27. PC3..PC0 (1)
PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PC3/ADC3 0 0 0 0 0 0 0 0 - ADC3 PC2/ADC2 0 0 0 0 0 0 0 0 - ADC2 PC1/ADC1 0 0 0 0 0 0 0 0 - ADC1 PC0/ADC0 0 0 0 0 0 0 0 0 - ADC0
58
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Note: 1. PC4 PC5 AIO TWI
D
D Table 28 Table 28. D
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 AIN1 ( ) AIN0 ( ) T1 (T/C1 ) XCK (USART / ) T0 (T/C0 ) INT1 ( 1 ) INT0 ( 0 ) TXD (USART ) RXD (USART )
* AIN1 - D, Bit 7 AIN1 * AIN0 - D, Bit 6 AIN0 * T1 - D, Bit 5 T1 T/C1 * XCK/T0 - D, Bit 4 XCK USART T0 T/C0 * INT1 - D, Bit 3 INT1 1PD3 * INT0 - D, Bit 2 INT0 0PD2 * TXD - D, Bit 1 TXDUSART USART DDD1 * RXD - D, Bit 0 RXDUSART USART DDD0 PORTD0 Table 29 Table 30 D P 53Figure 25
59
2486N-AVR-07/04
Table 29. PD7..PD4
PUOE PUO OOE OO PVOE PVO DIEOE DIEO DI AIO PD7/AIN1 0 0 0 0 0 0 0 0 - AIN1 PD6/AIN0 0 0 0 0 0 0 0 0 - AIN0 PD5/T1 0 0 0 0 0 0 0 0 T1 - PD4/XCK/T0 0 0 0 0 UMSEL XCK 0 0 XCK / T0 -
Table 30. PD3..PD0
PUOE PUO OOE OO PVOE PVO DIEOE DIEO DI AIO PD3/INT1 0 0 0 0 0 0 INT1 1 INT1 - PD2/INT0 0 0 0 0 0 0 INT0 1 INT0 - PD1/TXD TXEN 0 TXEN 1 TXEN TXD 0 0 - - PD0/RXD RXEN PORTD0 * PUD RXEN 0 0 0 0 0 RXD -
60
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
I/O
B PORTB
Bit / 7
PORTB7
6
PORTB6
5
PORTB5
4
PORTB4
3
PORTB3
2
PORTB2
1
PORTB1
0
PORTB0 PORTB
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
B DDRB
Bit /
7 DDB7 R/W 0
6 DDB6 R/W 0
5 DDB5 R/W 0
4 DDB4 R/W 0
3 DDB3 R/W 0
2 DDB2 R/W 0
1 DDB1 R/W 0
0 DDB0 R/W 0 DDRB
B PINB
Bit /
7 PINB7 R N/A
6 PINB6 R N/A
5 PINB5 R N/A
4 PINB4 R N/A
3 PINB3 R N/A
2 PINB2 R N/A
1 PINB1 R N/A
0 PINB0 R N/A PINB
C PORTC
Bit /
7
-
6
PORTC6
5
PORTC5
4
PORTC4
3
PORTC3
2
PORTC2
1
PORTC1
0
PORTC0 PORTC
R 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
C DDRC
Bit /
7 - R 0
6 DDC6 R/W 0
5 DDC5 R/W 0
4 DDC4 R/W 0
3 DDC3 R/W 0
2 DDC2 R/W 0
1 DDC1 R/W 0
0 DDC0 R/W 0 DDRC
C PINC
Bit /
7 - R 0
6 PINC6 R N/A
5 PINC5 R N/A
4 PINC4 R N/A
3 PINC3 R N/A
2 PINC2 R N/A
1 PINC1 R N/A
0 PINC0 R N/A PINC
D PORTD
Bit /
7
PORTD7
6
PORTD6
5
PORTD5
4
PORTD4
3
PORTD3
2
PORTD2
1
PORTD1
0
PORTD0 PORTD
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
D DDRD
Bit /
7 DDD7 R/W 0
6 DDD6 R/W 0
5 DDD5 R/W 0
4 DDD4 R/W 0
3 DDD3 R/W 0
2 DDD2 R/W 0
1 DDD1 R/W 0
0 DDD0 R/W 0 DDRD
D PIND
Bit /
7 PIND7 R N/A
6 PIND6 R N/A
5 PIND5 R N/A
4 PIND4 R N/A
3 PIND3 R N/A
2 PIND2 R N/A
1 PIND1 R N/A
0 PIND0 R N/A PIND
61
2486N-AVR-07/04
INT0 INT1 INT0..1 MCU MCUCR ( INT0/INT1) INT0 INT1 I/O P 22" " INT0/INT1 ( ) I/O MCU MCU 5.0V 25C 1 s P 226" " MCU SUT P 22" " MCU MCU
MCU MCUCR
MCU MCU
Bit / 7 SE R/W 0 6 SM2 R/W 0 5 SM1 R/W 0 4 SM0 R/W 0 3 ISC11 R/W 0 2 ISC10 R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR
* Bit 3, 2 - ISC11, ISC10: 1 Bit1 Bit 0 SREG I 1 INT1 Table 31 MCU INT1 Table 31. 1
ISC11 0 0 1 1 ISC10 0 1 0 1 INT1 INT1 INT1 INT1
62
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
* Bit 1, 0 - ISC01, ISC00: 0 Bit 1 Bit 0 SREG I Table 32 0 INT0 MCU INT0 Table 32. 0
ISC01 0 0 1 1 ISC00 0 1 0 1 INT0 INT0 INT0 INT0
GICR
Bit /
7 INT1 R/W 0
6 INT0 R/W 0
5 - R 0
4 - R 0
3 - R 0
2 - R 0
1 IVSEL R/W 0
0 IVCE R/W 0 GICR
* Bit 7 - INT1: 1 INT1 '1' SREG I MCU- MCUCR1 1/0 (ISC11ISC10) INT1 INT1 * Bit 6 - INT0: 0 INT0 '1' SREG I MCU- MCUCR0 1/0 (ISC01ISC00) INT0 INT0
63
2486N-AVR-07/04
GIFR
Bit /
7 INTF1 R/W 0
6 INTF0 R/W 0
5 - R 0
4 - R 0
3 - R 0
2 - R 0
1 - R 0
0 - R 0 GIFR
* Bit 7 - INTF1: 1 INT1 INTF1 SREG I GICR INT1 "1" MCU "1" * Bit 6 - INTF0: 0 INT0 INTF0 SREG I GICR INT0 "1" MCU "1" INT0
64
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
8 / 0
T/C0 8 / * * * * 10 Figure 268/ P 2"" CPU I/O I/O P 68"8 / " Figure 26. 8 T/C
TCCRn TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector Tn
DATA BUS
count
Timer/Counter TCNTn
( From Prescaler )
= 0xFF
T/C(TCNT0) (OCR0) 8 ( Int.Req. ) TIFR TIMSK TIFR TIMSK T/C T0 ( )T/C T/C clkT0
"n" T/C 0 TCNT0 T/C0 Table 33 Table 33. BOTTOM MAX 0x00 BOTTOM 0xFF ( 255) MAX
T/C
T/C T/C TCCR0 CS02:0 P 70"T/C0 T/C1 " 8 T/C Figure 27
65
2486N-AVR-07/04
Figure 27.
DATA BUS
TOVn (Int. Req.)
Clock Select TCNTn count Control Logic Edge Detector Tn
clkTn
max
( From Prescaler )
( ) count clkTn max TCNT0 1 T/C clkT0 TCNT0
clkT0 clkT0 CS02:0 (CS02:0 = 0) clkT0 CPU TCNT0 CPU ( )
( ) 8 (MAX = 0xFF) 0x00 TCNT0 "0" T/C (TOV0) TOV0 TOV0
66
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
T/C
T/C clkT0 Figure 28 T/C MAX Figure 28. T/C
clkI/O clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 29 Figure 29. T/C fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
67
2486N-AVR-07/04
8 /
T/C TCCR0
Bit / 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 CS02 R/W 0 1 CS01 R/W 0 0 CS00 R/W 0 TCCR0
* Bit 2:0 - CS02:0: T/C Table 34.
CS02 0 0 0 0 1 1 1 1 CS01 0 0 1 1 0 0 1 1 CS00 0 1 0 1 0 1 0 1 T/C clkI/O/1 ( ) clkI/O/8 ( ) clkI/O/64 ( ) clkI/O/256 ( ) clkI/O/1024 ( ) T0 T0
T/C0 T0 T/C TCNT0
Bit / 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 TCNT0 R/W 0
TCNT0[7:0]
T/C 8 T/C TIMSK
Bit / 7
OCIE2
6
TOIE2
5
TICIE1
4
OCIE1A
3
OCIE1B
2
TOIE1
1
-
0
TOIE0 TIMSK
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
* Bit 0 - TOIE0: T/C0 TOIE0 I "1" T/C0 T/C0 TIFR TOV0
68
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
T/C TIFR
Bit / 7 OCF2 R/W 0 6 TOV2 R/W 0 5 ICF1 R/W 0 4 OCF1A R/W 0 3 OCF1B R/W 0 2 TOV1 R/W 0 1 - R/W 0 0 TOV0 R/W 0 TIFR
* Bit 0 - TOV0:T/C0 T/C0 TOV0 TOV0 1 SREG I TOIE0(T/C0 ) TOV0
69
2486N-AVR-07/04
T/C0 T/C1
T/C1 T/C0 T/C1 T/C0 CSn2:0 = 1 T/C T/C fCLK_I/O 4 fCLK_I/O/8 fCLK_I/O/64 fCLK_I/O/256 fCLK_I/O/1024 T/C T/C1 T/C0 T/C (6 > CSn2:0 > 1) 1 N+1 N (8 64 256 1024) T/C T/C T/C
T1/T0 T/C clkT1/clkT0 T1/T0 ( ) Figure 30 T1/T0 clkI/O CSn2:0 = 7 clkT1 CSn2:0 = 6 clkT0 Figure 30. T1/T0
Tn
DQ LE
D
Q
DQ
Tn_sync (To Clock Select Logic)
clk I/O
Synchronization Edge Detector
T1/T0 2.5 3.5 T1/T0 T/C 50% (fExtClk < fclk_I/O/2) (Nyquist ) ( ) fclk_I/O/2.5
70
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 31. T/C0 T/C1 (1)
clk I/O
Clear
PSR10
T0
Synchronization
T1
Synchronization
clkT1
clkT0
Note:
1. (T1/T0) Figure 30
IO SFIOR
Bit /
7 - R 0
6 - R 0
5 - R 0
4 - R 0
3 ACME R/W 0
2 PUD R/W 0
1 PSR2 R/W 0
0 PSR10 R/W 0 SFIOR
* Bit 0 - PSR10:T/C1 T/C0 T/C1 T/C0 T/C1 T/C0 0
71
2486N-AVR-07/04
16 / 1
16 T/C ( ) * 16 ( 16 PWM) * 2 * * * * ( ) * PWM * PWM * * * 4 (TOV1OCF1A OCF1B ICF1) "n" T/C "x" TCNT1 T/C1 16 T/C Figure 32 P 2" " CPU I/O I/O I/O I/O I/O P 89"16 / " Figure 32. 16 T/C (1)
Count Clear Direction Control Logic TOVn (Int. Req.) clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn
=
=0
OCFnA (Int. Req.)
=
OCRnA Fixed TOP Values
Waveform Generation
OCnA
DATA BUS
OCFnB (Int.Req.) Waveform Generation OCnB
=
OCRnB ICFn (Int.Req.) Edge Detector
( From Analog Comparator Ouput )
ICRn
Noise Canceler ICPn
TCCRnA
TCCRnB
Note:
1. P 2" " P 55Table 22 P 59Table 28 T/C1
72
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
/ TCNT1 OCR1A/B ICR1 16 16 P 74" 16 " T/C TCCR1A/B 8 CPU ( Int.Req.) TIFR TIMSK TIFR TIMSK T/CT1 T/C( ) T/C clkT1 OCR1A/B T/C PWM OC1A/B P 79 " " OCF1A/B ICP1 ( P 180 " " ) ( ) T/C ( ) TOP T/C OCR1A ICR1 PWM OCR1A TOP OCR1A PWM OCR1A TOP TOP ICR1 OCR1A PWM Table 35. BOTTOM MAX TOP
0x0000 BOTTOM 0xFFFF ( 65535) MAX TOP TOP 0x00FF 0x01FF 0x03FF OCR1A ICR1
16T/C16AVRT/C * * * * * * * * 16 T/C I/O 16 T/C PWM10 WGM10 PWM11 WGM11 CTC1 WGM12 TCCR1A FOC1A FOC1B TCCR1B WGM13
16 T/C
16 T/C
73
2486N-AVR-07/04
16
TCNT1 OCR1A/B ICR1 AVR CPU 8 16 16 1688 16 16 16 CPU 16 8 8 16 16 CPU 16 16 OCR1A/B 16 16 16 OCR1A/B ICR1 "C" 16 (1)
... ; TCNT1 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; TCNT1 r17:r16 in in ... r16,TCNT1L r17,TCNT1H
C (1)
unsigned int i; ... /* TCNT1 0x01FF */ TCNT1 = 0x1FF; /* TCNT1 i */ i = TCNT1; ...
Note:
1.
TCNT1 r17:r16 16 16 16 16 16
74
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
TCNT1 OCR1A/B ICR1 (1)
TIM16_ReadTCNT1: ; in cli ; TCNT1 r17:r16 in in r16,TCNT1L r17,TCNT1H r18,SREG ;
; out SREG,r18 ret
C (1)
unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* */ sreg = SREG; /* */ _CLI(); /* TCNT1 i */ i = TCNT1; /* */ SREG = sreg; return i; }
Note:
1.
TCNT1 r17:r16
75
2486N-AVR-07/04
TCNT1 OCR1A/B ICR1 (1)
TIM16_WriteTCNT1: ; in cli ; TCNT1 r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; out SREG,r18 ret r18,SREG ;
C (1)
void TIM16_WriteTCNT1 ( unsigned int i ) { unsigned char sreg; unsigned int i; /* */ sreg = SREG; /* */ _CLI(); /* TCNT1 i */ TCNT1 = i; /* */ SREG = sreg; }
Note:
1.
r17:r16 TCNT1 16
76
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
T/C
T/C T/C B(TCCR1B) (CS12:0) P 70"T/C0 T/C1 " 16 T/C 16 Figure 33 Figure 33.
DATA BUS
(8-bit) TOVn (Int. Req.)
TEMP (8-bit) Clock Select count TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) clear direction Control Logic clkTn Edge Detector Tn
( From Prescaler ) TOP BOTTOM
( ) Count Direction Clear clkT1 TOP BOTTOM TCNT1 1 1 TCNT1 / TCNT1 TCNT1 (0)
16 8 I/O TCNT1H 8 TCNT1L 8 CPU TCNT1H CPU TCNT1H (TEMP) TCNT1L TCNT1HTCNT1L TCNT1H CPU 8 16 TCNT1 clkT1 1 1 clkT1 CS12:0 CS12:0= 0 CPU TCNT1 clkT1 CPU TCCR1A TCCR1B WGM13:0 ( ) OC1x P 82" " WGM13:0 TOV1 TOV1 CPU
T/C ICP1
77
2486N-AVR-07/04
Figure 34 "n" / Figure 34.
DATA BUS
(8-bit)
TEMP (8-bit)
ICRnH (8-bit) WRITE
ICRnL (8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
ICRn (16-bit Register)
TCNTn (16-bit Counter)
ACO* Analog Comparator ICPn
ACIC*
ICNC
ICES
Noise Canceler
Edge Detector
ICFn (Int. Req.)
ICP1 ( ) ACO 16 TCNT1 ICR1 ICF1 ICIE1 = 1 ICF1 I/O "1" ICR1 ICR1L ICR1H TEMP CPU ICR1H TEMP ICR1 ICR1 TOP ICR1 WGM13:0 ICR1 ICR1H I/O ICR1L P 74" 16 " 16 ICP1T/C1 ACSR ACIC ICP1 ACO T1 (P 70Figure 30 ), 4 ICR1 TOP T/C ICP1 4 4
78
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
TCCR1B ICNC1 ICR1 4 ICR1 ICR1 ICR1 TOP ICR1 ICF1 ( I/O "1") ICF1
16 TCNT1 OCR1x OCF1x OCIE1x = 1 OCF1x OCF1x I/O "1" WGM13:0 COM1x1:0 TOP BOTTOM (P 82 " " ) A T/C TOP ( ) TOP Figure 35 "n" (n = 1 T/C1) "x" (A/B) Figure 35.
DATA BUS (8-bit)
TEMP (8-bit)
OCRnxH Buf. (8-bit)
OCRnxL Buf. (8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
OCRnx Buffer (16-bit Register)
TCNTn (16-bit Counter)
OCRnxH (8-bit)
OCRnxL (8-bit)
OCRnx (16-bit Register)
= (16-bit Comparator )
OCFnx (Int.Req.) TOP BOTTOM
Waveform Generator
OCnx
WGMn3:0
COMnx1:0
79
2486N-AVR-07/04
T/C 12 PWM OCR1x (CTC) OCR1x TOP BOTTOM PWM OCR1x CPU OCR1x CPU OCR1x OCR1x( ) (T/C TCNT1 ICR1 ) OCR1x TEMP 16 OCR1x TEMP OCR1xH CPU I/O TEMP OCR1xL TEMP OCR1x OCR1x P 74" 16 " 16 PWM FOC1x "1" OCF1x / OC1x (COMx1:0 OC1x ) CPUTCNT1 OCR1x TCNT1 TCNT1 TCNT1 T/C TCNT1OCR1x PWM TOP TCNT1 TOP 0xFFFF TCNT1BOTTOM OC1x OC1x FOC1x OC1x COM1x1:0 COM1x1:0
TCNT1
80
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
COM1x1:0 COM1x1:0 OC1x COM1x1:0 OC1x Figure 36 COM1x1:0 I/O I/O I/O COM1x1:0 I/O (DDR PORT) OC1x OC1x OC1x OC1x "0" Figure 36.
COMnx1 COMnx0 FOCnx
Waveform Generator
D
Q
1 OCnx Pin
OCnx D
DATABUS
0
Q
PORT D Q
DDR
clk I/O
COM1x1:0 OC1x I/O OC1x (DDR) OC1x DDR_OC1x Table 36Table 37 Table 38 OC1x COM1x1:0 P 89 "16 / " COM1x1:0
81
2486N-AVR-07/04
COM1x1:0 CTC PWM COM1x1:0 = 0 OC1x PWM P 89Table 36 PWM P 90Table 37 PWM to P 90Table 38 COM1x1:0 PWM FOC1x
- T/C - (WGM13:0) (COM1x1:0) COM1x1:0 PWM PWM COM1x1:0 P 81 " " P 87" / "
(WGM13:0 = 0) (TOP = 0xFFFF) 0x0000 TCNT1T/CTOV1 TOV117 TOV1 CPU
CTC( )
CTC (WGM13:0 = 4 12) OCR1A ICR1 TCNT1 OCR1A(WGM13:0 = 4) ICR1 (WGM13:0 = 12) OCR1A ICR1 TOP CTCFigure 37 TCNT1TCNT1OCR1A ICR1 TCNT1 Figure 37. CTC
OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TCNTn
OCnA (Toggle) Period
1 2 3 4
(COMnA1:0 = 1)
82
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
OCF1A ICF1 TOP TOP CTC TOP BOTTOM OCR1A ICR1 TCNT1 0xFFFF 0x0000 OCR1A ICR1 PWM OCR1A TOP (WGM13:0 = 15) OCR1A CTC OC1A COM1A1:0 = 1 OC1A (DDR_OC1A = 1) fOC1A = fclk_I/O/2 (OCR1A = 0x0000) f clk_I/O f OCnA = ---------------------------------------------------2 N ( 1 + OCRnA ) N (1 8 64 256 1024) TOV1 MAX 0x0000 PWM PWM (WGM13:0 = 5 6 7 14 15) PWM PWM PWM BOTTOM TOP BOTTOM OC1x TCNT1 OCR1x TOP OCR1x PWM PWM PWM DAC ( ) PWM PWM 89 10 ICR1 OCR1A 2 (ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A MAX) PWM log ( TOP + 1 ) R FPWM = ----------------------------------log ( 2 ) PWM 0x00FF 0x01FF 0x03FF (WGM13:0 = 5 6 7)ICR1 (WGM13:0 = 14) OCR1A (WGM13:0 = 15) Figure 38 OCR1A ICR1 TOP PWM TCNT1 PWM PWM TCNT1 OCR1x TCNT1 OC1x Figure 38. PWM
OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
8
83
2486N-AVR-07/04
TOP T/C TOV1 TOP OCR1A ICR1 OC1A ICF1 TOV1 TOP TOPTOP TCNT1OCR1x TOP OCR1x "0" TOP ICR1 OCR1A ICR1 ICR1 ICR1 TCNT1 0xFFFF 0x0000 OCR1A OCR1A OCR1A TCNT1 TOP OCR1A TCNT1 TOV1 TOP ICR1 TOP OCR1A OC1A PWM PWM ( TOP ) OCR1A PWM OC1x PWM COM1x1:0 2 PWM 3 PWM ( P 90Table 37 ) OC1x DDR_OC1x PWM OC1x OCR1x TCNT1 ( ) ( TOP BOTTOM) ( ) PWM f clk_I/O f OCnxPWM = ----------------------------------N ( 1 + TOP ) N (1 8 64 256 1024) OCR1x PWM OCR1x BOTTOM(0x0000) TOP+1OCR1xTOP COM1x1:0 OC1A (COM1A1:0 = 1) 50% OCR1A TOP (WGM13:0 = 15) OCR1A 0(0x0000) fOC1A = fclk_I/O/2 CTC OC1A PWM PWM PWM (WGM13:0 = 1 2 3 11) 10 PWM BOTTOM TOP TOP BOTTOM TOP TCNT1 OCR1x OC1x BOTTOM TCNT1 OCR1x OC1x PWM PWM 8 9 10 ICR1 OCR1A 2 (ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A MAX) PWM log ( TOP + 1 ) R PCPWM = ----------------------------------log ( 2 ) PWM 0x00FF 0x01FF 0x03FF (WGM13:0 = 12 3) ICR1 (WGM13:0 = 10) OCR1A (WGM13:0 = 11)
84
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
TCNT1 TOP Figure 39 OCR1A ICR1 TOP PWM TCNT1 PWM PWM TCNT1 OCR1x TCNT1 OC1x Figure 39. PWM
OCRnx / TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
BOTTOM T/C TOV1 TOP OCR1A ICR1 OCR1x OC1A ICF1 TOPTOP TCNT1OCR1x TOP OCR1x "0" Figure 39 T/C TOP OCR1x OCR1x / TOP PWM TOP TOP T/C TOP TOP PWM OC1x PWM COM1x1:0 2 PWM COM1x1:0 3 PWM ( P 90Table 38 ) OC1x DDR_OC1x OCR1x TCNT1 OC1x PWM PWM f clk_I/O f OCnxPCPWM = ---------------------------2 N TOP N (1 8 64 256 1024) OCR1x PWM PWM OCR1x BOTTOM OCR1x TOP PWM
85
2486N-AVR-07/04
OCR1A TOP (WGM13:0 = 11) COM1A1:0 = 1 OC1A 50% PWM PWM (WGM13:0 = 8 9) - PWM - PWM PWM BOTTOM TOP TOP BOTTOM TOP TCNT1 OCR1x OC1xBOTTOMTCNT1OCR1x OC1x PWM PWM OCR1x Figure 39 Figure 40 PWM PWM ICR1 OCR1A 2 (ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A MAX) PWM log ( TOP + 1 ) R PFCPWM = ----------------------------------log ( 2 ) PWM ICR1 (WGM13:0 = 8) OCR1A (WGM13:0 = 9) TCNT1 TOP Figure 40 OCR1A ICR1 TOP PWM TCNT1 PWM PWM TCNT1 OCR1x TCNT1 OC1x Figure 40. PWM
OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
OCRnx / TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
OCR1x T/C TOV1 TOP OCR1A ICR1 TCNT1 TOP OC1A CF1 TOP BOTTOM TOPTOP TCNT1OCR1x
86
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 40 PWM OCR1x BOTTOM TOP ICR1 TOP OCR1A OC1A PWM PWM ( TOP ) OCR1A PWM OC1x PWM COM1x1:0 2 PWM 3 PWM ( P 90Table 38 ) OC1x PWM OC1x OCR1x TCNT1 ( ) TCNT1 ( ) PWM f clk_I/O f OCnxPFCPWM = ---------------------------2 N TOP N (1 8 64 256 1024) OCR1x PWM PWM OCR1x BOTTOM OCR1x TOP PWM OCR1A TOP (WGM13:0 = 9) COM1A1:0 = 1OC1A 50%
/
/ clkT1 OCR1x OCR1x ( ) Figure 41 OCF1x Figure 41. T/C OCF1x
clkI/O clkTn
(clkI/O /1)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 42
87
2486N-AVR-07/04
Figure 42. T/C OCF1x fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 43 TOP PWM OCR1x BOTTOM TOP BOTTOM BOTTOM+1 TOP-1 BOTTOM TOV1 Figure 43. T/C
clkI/O clkTn
(clkI/O /1)
TCNTn
(CTC and FPWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM) and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
Figure 44
88
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 44. T/C fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
(CTC and FPWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM) and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
16 /
T/C1 A TCCR1A
Bit / 7
COM1A1
6
COM1A0
5
COM1B1
4
COM1B0
3
FOC1A
2
FOC1B
1
WGM11
0
WGM10 TCCR1A
R/W 0
R/W 0
R/W 0
R/W 0
W 0
W 0
R/W 0
R/W 0
* Bit 7:6 - COM1A1:0: A * Bit 5:4 - COM1B1:0: B COM1A1:0 COM1B1:0 OC1A OC1B COM1A1:0(COM1B1:0) "1"OC1A(OC1B) I/O OC1A(OC1B) OC1A(OC1B) COM1x1:0 WGM13:0 Table 36 WGM13:0 CTC ( PWM) COM1x1:0 Table 36. PWM
COM1A1/ COM1B1 0 0 1 1 COM1A0/ COM1B0 0 1 0 1 OC1A/OC1B OC1A/OC1B OC1A/OC1B( ) OC1A/OC1B ( )
89
2486N-AVR-07/04
Table 37 WGM13:0 PWM COM1x1:0 Table 37. PWM(1)
COM1A1/ COM1B1 0 0 COM1A0/ COM1B0 0 1 OC1A/OC1B WGM13:0 = 15: OC1A OC1B WGM13:0 OC1A/OC1B OC1A/OC1B OC1A/OC1B TOP OC1A/OC1B OC1A/OC1B TOP
1 1 Note:
0 1
1. OCR1A/OCR1B TOP COM1A1/COM1B1 OC1A/OC1B / P 83 " PWM "
Table 38WGM13:0PWMPWMCOM1x1:0 Table 38. PWM (1)
COM1A1/ COM1B1 0 0 COM1A0/ COM1B0 0 1 OC1A/OC1B WGM13:0 = 9 14: OC1A OC1B WGM13:0 OC1A/OC1B OC1A/OC1B OC1A/OC1B OC1A/OC1B OC1A/OC1B
1 1 Note:
0 1
1. OCR1A/OCR1B TOP COM1A1/COM1B1 P 84 " PWM "
* Bit 3 - FOC1A: A * Bit 2 - FOC1B: B FOC1A/FOC1BWGM13:0PWM PWM TCCR1A FOC1A/FOC1B 1 COM1x1:0 OC1A/OC1B FOC1A/FOC1B COM1x1:0 CTC OCR1A TOP FOC1A/FOC1B FOC1A/FOC1B 0 * Bit 1:0 - WGM11:0: TCCR1B WGM13:2 ---- Table 39 T/C ( ) (CTC) (PWM) P 82 " "
90
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Table 39.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note: WGM13 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WGM12 (CTC1) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WGM11 (PWM11) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WGM10 (PWM10) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 / (1) 8 PWM 9 PWM 10 PWM CTC 8 PWM 9 PWM 10 PWM PWM PWM PWM PWM CTC PWM PWM TOP 0xFFFF 0x00FF 0x01FF 0x03FF OCR1A 0x00FF 0x01FF 0x03FF ICR1 OCR1A ICR1 OCR1A ICR1 - ICR1 OCR1A OCR1x TOP TOP TOP TOP TOP TOP BOTTOM BOTTOM TOP TOP - TOP TOP TOV1 MAX BOTTOM BOTTOM BOTTOM MAX TOP TOP TOP BOTTOM BOTTOM BOTTOM BOTTOM MAX - TOP TOP
1. CTC1 PWM11:0 WGM12:0
91
2486N-AVR-07/04
T/C1 B TCCR1B
Bit /
7
ICNC1
6
ICES1
5
-
4
WGM13
3
WGM12
2
CS12
1
CS11
0
CS10 TCCR1B
R/W 0
R/W 0
R 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
* Bit 7 - ICNC1: ICNC1 ICP1 ICP1 4 4 4 * Bit 6 - ICES1: ICP1 ICES "0" ICES1 "1" ICES1 ICR1 ICF1 ICR1 TOP ( TCCR1A TCCR1B WGM13:0 ) ICP1 * Bit 5 - TCCR1B "0" * Bit 4:3 - WGM13:2: TCCR1A * Bit 2:0 - CS12:0: 3 T/C Figure 41 Figure 42 Table 40.
CS12 0 0 0 0 1 1 1 1 CS11 0 0 1 1 0 0 1 1 CS10 0 1 0 1 0 1 0 1 (T/C ) clkI/O/1 ( ) clkI/O/8 ( ) clkI/O/64 ( ) clkI/O/256 ( ) clkI/O/1024 ( ) T1 T1
T1 T/C1 T/C1 TCNT1H TCNT1L
Bit 7 6 5 4 3 2 1 0 TCNT1H TCNT1L R/W 0 R/W 0 R/W 0
TCNT1[15:8] TCNT1[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
TCNT1HTCNT1LT/C1TCNT1 / 16 CPU 92
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
8 TEMPTEMP 16 P 74 " 16 " TCNT1TCNT1OCR1x TCNT1 1A OCR1AH OCR1AL
Bit 7 6 5 4 3 2 1 0 OCR1AH OCR1AL R/W 0 R/W 0 R/W 0
OCR1A[15:8] OCR1A[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
1B OCR1BH OCR1BL
Bit
7
6
5
4
3
2
1
0 OCR1BH OCR1BL
OCR1B[15:8] OCR1B[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
16 TCNT1 OC1x 16 CPU 8 TEMPTEMP 16 P 74 " 16 "
93
2486N-AVR-07/04
1 ICR1H ICR1L
Bit
7
6
5
4 ICR1[7:0]
3
2
1
0 ICR1H ICR1L
ICR1[15:8] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
ICP1(T/C1) TCNT1 ICR1 ICR1 TOP 16 CPU 8 TEMP TEMP 16 P 74 " 16 " T/C1 TIMSK(1)
Bit / 7
OCIE2
6
TOIE2
5
TICIE1
4
OCIE1A
3
OCIE1B
2
TOIE1
1 - R 0
0
TOIE0 TIMSK
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
Note:
1. T/C T1
* Bit 5 - TICIE1: T/C1 "1" I "1" T/C1 TIFR ICF1 CPU T/C1 ( P 43 " " ) * Bit 4 - OCIE1A:T/C1 A "1" I "1" T/C1 A TIFR OCF1A CPU T/C1 A ( P 43 " " ) * Bit 3 - OCIE1B:T/C1 B "1" I "1" T/C1 B TIFR OCF1B CPU T/C1 B ( P 43 " " ) * Bit 2 - TOIE1:T/C1 "1" I "1" T/C1 TIFR TOV1 CPU T/C1 ( P 43 " " ) T/C TIFR(1)
Bit / 7 OCF2 R/W 0 6 TOV2 R/W 0 5 ICF1 R/W 0 4 OCF1A R/W 0 3 OCF1B R/W 0 2 TOV1 R/W 0 1 - R 0 0 TOV0 R/W 0 TIFR
Note:
1. T/C T1
* Bit 5 - ICF1: T/C1 ICP1 ICF1 ICR1 TOP TOP ICF1 ICF1 "1" * Bit 4 - OCF1A: T/C1 A TCNT1 OCR1A "1"
94
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
(FOC1A) OCF1A A OCF1A "1" * Bit 3 - OCF1B: T/C1 B TCNT1 OCR1B "1" (FOC1B) OCF1B B OCF1B "1" * Bit 2 - TOV1: T/C1 T/C1 CTC T/C1 TOV1 TOV1 P 91Table 39 TOV1 "1"
95
2486N-AVR-07/04
8 PWM / 2
T/C2 8 / * * ( ) * , (PWM) * * 10 * (TOV2 OCF2) * 32 kHz I/O Figure 458T/C P 2"" CPUI/O I/O I/O I/O P 108"8 T/C " Figure 45. 8 T/C
TCCRn
count clear direction Control Logic
TOVn (Int. Req.) clkTn TOSC1
BOTTOM
TOP Prescaler
T/C Oscillator TOSC2
Timer/Counter TCNTn
=0
= 0xFF
OCn (Int. Req.) clkI/O
=
Waveform Generation
OCn
OCRn
DATA BUS
Synchronized Status Flags
clkI/O Synchronization Unit clkASY
Status Flags ASSRn asynchronous Mode Select (ASn)
/ TCNT2 OCR2 8 ( Int.Req.) TIFR TIMSK TIFR TIMSK
96
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
T/CTOSC1/2 ASSR T/C ( ) T/C clkT2 OCR2 TCNT2 PWM OC2 P 99 " " OCF2 "n" / 2 (TCNT2T/C2) Table 41 Table 41. BOTTOM MAX TOP 0x00 BOTTOM 0xFF ( 255) MAX TOPTOP 0xFF (MAX) OCR2
T/C
T/C clkT2 MCU clkI/O ASSR AS2 TOSC1 TOSC2 P 110" ASSR" P 113" / "
97
2486N-AVR-07/04
8T/CFigure 46 Figure 46.
DATA BUS
TOVn (Int. Req.)
TOSC1 count TCNTn clear direction Control Logic clk Tn Prescaler T/C Oscillator TOSC2
BOTTOM
TOP
clkI/O
( ) count direction clear clkT2 top bottom TCNT2 1 1 TCNT2 ( ) T/C TCNT2 TCNT2 (0)
clkT2 clkT2 CS22:0 (CS22:0 = 0) clkT2 CPU TCNT2 CPU ( ) T/C (TCCR2) WGM21 WGM20 OC2 P 102" " T/CTOV2WGM21:0 TOV2CPU
98
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
8 TCNT2 OCR2 TCNT2 OCR2 OCF2 OCIE2 = 1 OCF2 "1" WGM21:0 COM21:0 max bottom ( P 102 " " ) Figure 47 Figure 47.
DATA BUS
OCRn
TCNTn
= (8-bit Comparator )
OCFn (Int. Req.)
TOP BOTTOM FOCn
Waveform Generator
OCxy
WGMn1:0
COMn1:0
PWM OCR2 OCR2 top bottom PWM OCR2 CPU OCR2 CPU OCR2
99
2486N-AVR-07/04
PWM FOC2 "1" OCF2 / OC2 (COM21:0 OC2 ) CPU TCNT2 OCR2 TCNT2 TCNT2 TCNT2 T/C TCNT2 OCR2 TCNT2 BOTTOM OC2 OC2 FOC2 OC2 COM21:0 COM21:0
TCNT2
100
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
COM21:0 COM21:0 (OC2) COM21:0 OC2 Figure 48 COM21:0 I/O I/O I/O COM21:0 I/O (DDR PORT) OC2 OC2 OC2 Figure 48.
COMn1 COMn0 FOCn
Waveform Generator
D
Q
1 OCn Pin
OCn D Q
0
DATABUS
PORT D Q
DDR
clk I/O
COM21:0 OC2 I/O OC2 (DDR) OC2 DDR_OC2 OC2 COM21:0 P 108 "8 T/C "
101
2486N-AVR-07/04
COM21:0 CTC PWM COM21:0 = 0 OC2 PWM P 108Table 43 PWM P 109Table 44 PWM P 109Table 45 COM21:0 PWM FOC2
- T/C - (WGM21:0) (COM21:0) COM21:0 PWM PWM COM21:0 (P 101 " " ) P 106"T/C "
(WGM21:0 = 0) 8 (TOP = 0xFF) 0x00 TCNT0 T/C TOV2 TOV2 9 TOV2 CPU
102
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
CTC( ) CTC (WGM21:0 = 2) OCR2 TCNT2 OCR2 OCR2 TOP CTCFigure 49 TCNT2TCNT2OCR2 TCNT2 Figure 49. CTC
OCn Interrupt Flag Set
TCNTn
OCn (Toggle) Period
1 2 3 4
(COMn1:0 = 1)
OCF2 TOP TOP CTC TOP BOTTOM OCR2 TCNT2 0xFF 0x00 OCR2 CTC OC2 COM21:0 = 1 OC2 fOC2 = fclk_I/O/2 (OCR2 = 0x00) f clk_I/O f OCn = -----------------------------------------------2 N ( 1 + OCRn ) N (1 8 32 64 128 256 1024) TOV2 MAX 0x00
103
2486N-AVR-07/04
PWM
PWM (WGM21:0 = 3) PWM PWM PWM BOTTOMMAX BOTTOM OC2 TCNT2 OCR2 BOTTOM OC2 PWM PWM PWM DAC ( ) PWM MAX Figure 50 TCNT0 PWM PWM TCNT2 OCR2 TCNT2 Figure 50. PWM
OCRn Interrupt Flag Set
OCRn Update and TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
Period
1
2
3
4
5
6
7
MAX T/C TOV2 PWM OC2 PWM COM21:0 2 PWM 3 PWM ( P 109Table 44 ) OC2 PWM OC2 OCR2 TCNT2 ( ) ( MAX BOTTOM) ( ) PWM f clk_I/O f OCnPWM = -----------------N 256 N (1 8 32 64 128 256 1024) OCR2PWM OCR2ABOTTOM MAX+1 OCR2 MAX COM21:0
104
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
OC2 (COM21:0 = 1) 50% OCR2 0 foc2 = fclk_I/O/2 CTC OC2 PWM PWM PWM (WGM21:0 = 1) PWM BOTTOM MAX MAX BOTTOM MAX TCNT2 OCR2 OC2 BOTTOM TCNT2 OCR2 OC2 PWM PWM 8 MAX TCNT2 MAX Figure 51 TCNT2 PWM PWM TCNT2 OCR2 TCNT2 Figure 51. PWM
OCn Interrupt Flag Set
OCRn Update
TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
Period
1
2
3
BOTTOM T/C TOV2 PWM OC2 PWM COM21:0 2PWM COM21:03PWM (P 109Table 45 ) OC2 OCR2 TCNT2 OC2 PWM PWM f clk_I/O f OCnPCPWM = -----------------N 510 N (1 8 32 64 128 256 1024) OCR2 PWM PWM OCR2 BOTTOM OCR2 MAX PWM
105
2486N-AVR-07/04
Figure 51 2 OCn BOTTOM * Figure 51 OCR2A MAX OCR2A MAX OCn BOTTOM T/C MAX OCn OCn OCR2A OCn
*
T/C
T/C clkT2 clkI/O T/C Figure 52 T/C PWM MAX Figure 52. T/C
clkI/O clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 53 Figure 53. T/C fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 54 ( CTC )OCF2
106
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 54. T/C OCF2 fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRn - 1
OCRn
OCRn + 1
OCRn + 2
OCRn
OCRn Value
OCFn
Figure 55 CTC OCF2 TCNT2 Figure 55. T/C CTC fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn (CTC) OCRn
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCFn
107
2486N-AVR-07/04
8 T/C
T/C TCCR2
Bit / 7
FOC2
6
WGM20
5
COM21
4
COM20
3
WGM21
2
CS22
1
CS21
0
CS20 TCCR2
W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
* Bit 7 - FOC2: FOC2 WGM PWM PWM TCCR2 1 OC2 COM21:0 FOC2 COM21:0 FOC2 OCR2 TOP CTC FOC2 0 * Bit 6,3 - WGM21:0: TOP T/C (CTC) PWM Table 42 and P 102" " Table 42.
0 1 2 3 Note: WGM21 (CTC2) 0 0 1 1 WGM20 (PWM2) 0 1 0 1 T/C PWM CTC PWM TOP 0xFF 0xFF OCR2 0xFF OCR2 TOP TOP TOV2 MAX BOTTOM MAX MAX
1. CTC2 PWM2 WGM21:0
* Bit 5:4 - COM21:0: OC0 COM01:0 OC0 1 OC0 COM01:0 WGM01:0 Table 43 WGM01:0 CTC COM01:0 Table 43. PWM
COM21 0 0 1 1 COM20 0 1 0 1 OC2 OC2 OC2 OC2
Table 44 WGM21:0 PWM COM21:0
108
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Table 44. PWM (1)
COM21 0 0 1 1 Note: COM20 0 1 0 1 OC2 OC2 TOP OC0 OC2 TOP OC0
1. OCR2 TOP COM21 TOP P 104" PWM "
Table 45 WGM21:0 PWM COM21:0 Table 45. PWM (1)
COM21 0 0 1 1 Note: COM20 0 1 0 1 OC2 OC2 OC2 OC2 OC2
1. OCR2 TOP COM21 TOP P 105" PWM "
109
2486N-AVR-07/04
* Bit 2:0 - CS22:0: T/C Table 46 Table 46.
CS22 0 0 0 0 1 1 1 1 CS21 0 0 1 1 0 0 1 1 CS20 0 1 0 1 0 1 0 1 T/C
clkT2S/( ) clkT2S/8 ( ) clkT2S/32 ( ) clkT2S/64 ( ) clkT2S/128 ( )
clkT2S/256 ( ) clkT2S/1024 ( )
/ TCNT2
Bit /
7 R/W 0
6 R/W 0
5 R/W 0
4 R/W 0
3 R/W 0
2 R/W 0
1 R/W 0
0 TCNT2 R/W 0
TCNT2[7:0]
T/C 8 TCNT2 TCNT2 TCNT2 OCR2 OCR2
Bit / 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 OCR2 R/W 0
OCR2[7:0]
8 TCNT2 OC2
/
ASSR
Bit / 7
-
6
-
5
-
4
-
3
AS2
2
TCN2UB
1
OCR2UB
0
TCR2UB ASSR
R 0
R 0
R 0
R 0
R/W 0
R 0
R 0
R 0
* Bit 3 - AS2: T/C2 AS2"0"T/C2I/OclkI/OAS2"1"T/C2TOSC1 AS2 TCNT2 OCR2 TCCR2 * Bit 2 - TCN2UB:T/C2 T/C2 TCNT2TCN2UB TCNT2 TCN2UB TCN2UB 0 TCNT2 * Bit 1 - OCR2UB: 2 T/C2 OCR2OCR2UB OCR2 OCR2UB OCR2UB 0 OCR2 110
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
* Bit 0 - TCR2UB:T/C2 T/C2 TCCR2TCR2UB TCCR2 TCR2UB TCR2UB 0 TCCR2 TCNT2 OCR2 TCCR2 TCNT2 OCR2 TCCR2 / 2 T/C2 * TCNT2OCR2 TCCR2 1. OCIE2 TOIE2 T/C2 2. AS2 3. TCNT2 OCR2 TCCR2 4. TCN2UB OCR2UB TCR2UB 5. T/C2 6. * * 32.768 kHz TOSC1 T/C2 4 TCNT2 OCR2 TCCR2 TOSC1 3 TCNT2 OCR2 ASSR T/C2 MCU Standby TCNT2 OCR2ATCCR2A MCUT/C2 T/C2 MCU OCR2 TCNT2 (OCR2UB 0)MCU MCU T/C2Standby TOSC1 TOSC1 1. TCCR2 TCNT2 OCR2 2. ASSR 3. Standby * T/C2 32.768 kHz Standby 1 /Standby 1 T/C2 T/C2 Standby MCU 4 SLEEP TCNT2 TCNT2 TOSC TCNT2 I/O TOSC1 I/O 111
2486N-AVR-07/04
*
*
*
*
TCNT2 TOSC1 TOSC1 TCNT2 1. OCR2 TCCR2 2. 3. TCNT2 * 3
112
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
/ TIMSK
Bit / 7
OCIE2
6
TOIE2
5
TICIE1
4
OCIE1A
3
OCIE1B
2
TOIE1
1
-
0
TOIE0 TIMSK
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R 0
R/W 0
* Bit 7 - OCIE2:T/C2 OCIE2 I "1" T/C2 A T/C2 TIFR OCF2 * Bit 6 - TOIE2: T/C2 TOIE2 I "1" T/C2 T/C2 TIFR TOV2 / TIFR
Bit /
7 OCF2 R/W 0
6 TOV2 R/W 0
5 ICF1 R/W 0
4 OCF1A R/W 0
3 OCF1B R/W 0
2 TOV1 R/W 0
1 - R 0
0 TOV0 R/W 0 TIFR
* Bit 7 - OCF2: 2 T/C2 OCR2( 2) OCF2 1 SREG IOCIE2 OCF2 * Bit 6 - TOV2: T/C2 T/C2 TOV2 TOV2 1 SREG I TOIE2 TOV2 PWM T/C2 0x00 TOV2
/
Figure 56. T/C2
clkI/O TOSC1
clkT2S Clear
10-BIT T/C PRESCALER
clkT2S/32
clkT2S/64
AS2
PSR2
0
CS20 CS21 CS22
TIMER/COUNTER2 CLOCK SOURCE clkT2
clkT2S/1024
clkT2S/8
clkT2S/128
clkT2S/256
113
2486N-AVR-07/04
T/C2 clkT2S clkT2S clkI/O ASSR AS2 T/C2 TOSC1 T/C2 RTC TOSC1 TOSC2 C ( 32.768 kHz ) TOSC1 T/C2 clkT2S/8 clkT2S/32 clkT2S/64 clkT2S/128 clkT2S/256 clkT2S/1024 clkT2S 0 () SFIORPSR2 IO SFIOR
Bit / 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 ACME R/W 0 2 PUD R/W 0 1 PSR2 R/W 0 0 PSR10 R/W 0 SFIOR
* Bit 1 - PSR2: T/C2 1 T/C2 0 CPU T/C2 0 T/C2 1
114
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
SPI
SPI ATmega8 AVR ATmega8 SPI * 3 * * LSB MSB * 7 * * * * (CK/2) Figure 57. SPI (1)
DIVIDER /2/4/8/16/32/64/128
SPI2X
Note:
1. SPI P 2" " P 55Table 22
SPI Figure 58 SS SCK MOSI MOSI MISO MISO SS SPI SPI SS SPI SPI 8 SPI SPIF SPCR SPI SPIE SPDR SS
SPI2X
115
2486N-AVR-07/04
SS SPI MISO SPI SPDR SCK SPDR SS SPIF SPCRSPISPIE SPDR Figure 58. SPI -
MSB MASTER LSB MISO MOSI MISO MOSI SHIFT ENABLE SPI CLOCK GENERATOR SCK SS VCC SCK SS MSB SLAVE LSB 8 BIT SHIFT REGISTER 8 BIT SHIFT REGISTER
SPI SPI SPI SPI SCK SPI fosc/4 SPI MOSI MISO SCK SS Table 47 P 53" " Table 47. SPI (1)
MOSI MISO SCK SS Note: SPI SPI
1. P 55" B " SPI
SPI DDR_SPIDD_MOSI DD_MISODD_SCK
116
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
MOSI PB5 DD_MOSI DDB5 DDR_SPI DDRB (1)
SPI_MasterInit: ; MOSI SCK ldi out ldi out ret SPI_MasterTransmit: ; (r16) out SPDR,r16 Wait_Transmit: ; sbis SPSR,SPIF rjmp Wait_Transmit ret r17,(1<; SPI fck/16
C (1)
void SPI_MasterInit(void) { /* MOSI SCK */ DDR_SPI = (1<Note:
1.
117
2486N-AVR-07/04
SPI (1)
SPI_SlaveInit: ; MISO ldi out ldi out ret SPI_SlaveReceive: ; sbis SPSR,SPIF rjmp SPI_SlaveReceive ; in ret r16,SPDR r17,(1<; SPI
C (1)
void SPI_SlaveInit(void) { /* MISO */ DDR_SPI = (1<Note:
1.
118
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
SS
SPI SS SS SPI MISO ( ) SS SPI SS / SS SPI SPI (MSTR SPCR ) SS SS I/O SPI SS SS SPI SS SPI SPI 1. SPCR MSTR SPI MOSI SCK 2. SPSR SPIF SPI SPI SS MSTR "1" SPI SPI SPCR
Bit / 7 SPIE R/W 0 6 SPE R/W 0 5 DORD R/W 0 4 MSTR R/W 0 3 CPOL R/W 0 2 CPHA R/W 0 1 SPR1 R/W 0 0 SPR0 R/W 0 SPCR
* Bit 7 - SPIE: SPI SPSR SPIF SREG SPI * Bit 6 - SPE: SPI SPE SPI SPI SPE * Bit 5 - DORD: DORD LSB MSB * Bit 4 - MSTR: / MSTR MSTR "1" SS MSTR SPSR SPIF MSTR * Bit 3 - CPOL: CPOL SCK SCK Figure 59 Figure 60 CPOL Table 48. CPOL
CPOL 0 1
* Bit 2 - CPHA:
119
2486N-AVR-07/04
CPHA SCK SCK Figure 59 Figure 60 Table 49. CPHA
CPHA 0 1
* Bits 1, 0 - SPR1, SPR0: SPI 1 0 SCK SPR1 SPR0 SCK fosc Table 50. SCK
SPI2X 0 0 0 0 1 1 1 1 SPR1 0 0 1 1 0 0 1 1 SPR0 0 1 0 1 0 1 0 1 SCK
fosc/4 fosc/16 fosc/64 fosc/128 fosc/2 fosc/8 fosc/32 fosc/64
120
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
SPI SPSR
Bit / 7 SPIF R 0 6 WCOL R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 SPI2X R/W 0 SPSR
* Bit 7 - SPIF: SPI SPIF SPCR SPIE SPI SPI SS SPIF SPIF SPSR SPDRSPIF * Bit 6 - WCOL: SPI SPDR WCOL WCOL SPSR SPDR * Bit 5..1 - Res: * Bit 0 - SPI2X: SPI SPI ( Table 50) SCK CPU fosc /4 ATmega8SPIEEPROM SPI SPI SPDR
Bit / 7 MSB R/W X R/W X R/W X R/W X R/W X R/W X R/W X 6 5 4 3 2 1 0 LSB R/W X SPDR
SPI / SPI
121
2486N-AVR-07/04
SCK 4 CPHA CPOL SPI Figure 59 Figure 60 SCK Table 48 Table 49 Table 51. CPOL CPHA
CPOL = 0, CPHA = 0 CPOL = 0, CPHA = 1 CPOL = 1, CPHA = 0 CPOL = 1, CPHA = 1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) SPI 0 1 2 3
Figure 59. CPHA = 0 SPI
SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS
MSB first (DORD = 0) LSB first (DORD = 1)
MSB LSB
Bit 6 Bit 1
Bit 5 Bit 2
Bit 4 Bit 3
Bit 3 Bit 4
Bit 2 Bit 5
Bit 1 Bit 6
LSB MSB
Figure 60. CPHA = 1 SPI
SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS
MSB first (DORD = 0) LSB first (DORD = 1)
MSB LSB
Bit 6 Bit 1
Bit 5 Bit 2
Bit 4 Bit 3
Bit 3 Bit 4
Bit 2 Bit 5
Bit 1 Bit 6
LSB MSB
122
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
USART
(USART) * ( ) * * * * 5, 6, 7, 8, 9 1 2 * * * * * , * * Figure 61 USART CPU I/O I/O Figure 61. USART (1)
Clock Generator
UBRR[H:L] OSC
BAUD RATE GENERATOR
SYNC LOGIC
PIN CONTROL
XCK
Transmitter
UDR (Transmit) PARITY GENERATOR TRANSMIT SHIFT REGISTER PIN CONTROL TxD TX CONTROL
DATABUS
Receiver
CLOCK RECOVERY RX CONTROL
RECEIVE SHIFT REGISTER
DATA RECOVERY
PIN CONTROL
RxD
UDR (Receive)
PARITY CHECKER
UCSRA
UCSRB
UCSRC
Note:
1. P 2" " P 60Table 30 P 60Table 29 USART
USART 123
2486N-AVR-07/04
XCK ( ) USART UDR AVR USART AVR UART USART AVR UART * * * * * * USART FIFO FE DOR 9 RXB8 UDR ( Figure 61) USART (DOR) CHR9 UCSZ2 OR DOR
*
* *
USART 4 USART UMSEL C (UCSRC) ( ) UCSRA U2X (UMSEL = 1) XCK (DDR_XCK)()() XCK Figure 62
124
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 62.
UBRR fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 U2X
0 1 0
OSC DDR_XCK Sync Register Edge Detector
1
txclk
xcki XCK Pin xcko
0 1
UMSEL
DDR_XCK
UCPOL
1 0
rxclk
txclk rxclk xcki xcko fosc ( ) ( ) XCK ( ) XCK ( ) XTAL ( )
Figure 62 USART UBRR UBRRL UBRR fosc/(UBRR+1) 2 8 16 2 816 UMSEL U2X DDR_XCK Table 52(/)UBRR Table 52.
(U2X = 0) (U2X = 1) Equation for Calculating Baud Rate(1) Equation for Calculating UBRR Value
f OSC BAUD = --------------------------------------16 ( UBRR + 1 ) f OSC BAUD = -----------------------------------8 ( UBRR + 1 ) f OSC BAUD = -----------------------------------2 ( UBRR + 1 )
f OSC UBRR = ----------------------- - 1 16BAUD f OSC UBRR = -------------------- - 1 8BAUD f OSC UBRR = -------------------- - 1 2BAUD
Note:
1. (bps)
125
2486N-AVR-07/04
BAUD ( bps) fOSC UBRR UBRRH UBRRL (0-4095) Table 60 UBRR (U2X) UCSRA U2X "0" 16 8 Figure 62 XCK CPU XCK f OSC f XCK < -----------4 fosc
126
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
(UMSEL = 1)XCK ( ) ( ) TxD XCK RxD Figure 63. XCK
UCPOL = 1 XCK RxD / TxD Sample UCPOL = 0 XCK RxD / TxD Sample
UCRSC UCPOL XCK Figure 63 UCPOL=0 XCK XCK UCPOL=1 XCK XCK
( ) USART 30 * * * * 1 5 6 7 8 9 1 2
9 Figure 64 Figure 64.
FRAME
(IDLE)
St
0
1
2
3
4
[5]
[6]
[7]
[8]
[P]
Sp1 [Sp2]
(St / IDLE)
St (n) P Sp IDLE
(0 8) (RxD TxD)
UCSRB UCSRC UCSZ2:0 UPM1:0 USBS
127
2486N-AVR-07/04
USART UCSZ2:0 UPM1:0 USBS (FE) "0" P even = d n - 1 ... d 3 d 2 d 1 d 0 0 P odd = d n - 1 ... d 3 d 2 d 1 d 0 1 Peven Podd dn n
USART
USART USART ( ) USART TXC RXC ( UDR )TXC USART ( ) r17:r16 UCSRC UBRRH UCSRC I/O URSEL (MSB)
128
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
(1)
USART_Init: ; out out ldi out ldi out ret UBRRH, r17 UBRRL, r16 r16, (1<;
; : 8 , 2
C (1)
void USART_Init( unsigned int baud ) { /* */ UBRRH = (unsigned char)(baud>>8); UBRRL = (unsigned char)baud; /* */ UCSRB = (1<Note:
1.
I/O
129
2486N-AVR-07/04
USART UCSRB TXEN USART TxD
I/O USART XCK CPU UDR ( ) UDRE 8 UDR USART R16 (1)
USART_Transmit: ; sbis UCSRA,UDRE rjmp USART_Transmit ; out ret UDR,r16
5 8
C (1)
void USART_Transmit( unsigned char data ) { /* */ while ( !( UCSRA & (1<Note:
1.
UDRE
130
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
9 9 (UCSZ = 7) 9 UCSRB TXB8 8UDR 9 R17:R16 (1)
USART_Transmit: ; sbis UCSRA,UDRE rjmp USART_Transmit ; 9 r17 TXB8 cbi sbi out ret UCSRB,TXB8 UCSRB,TXB8 UDR,r16 sbrc r17,0 ; 8
C (1)
void USART_Transmit( unsigned int data ) { /* */ while ( !( UCSRA & (1<Note:
1. UCSRB UCSRB TXB8
9 USART USART UDRE TXC UDRE "1" UCSRA "0" UCSRB UDRIE "1" UDRE ( ) USART UDR UDRE UDR UDRE TXC TXC "1" TXC RS-485
131
2486N-AVR-07/04
UCSRB TXCIE "1" TXC USART TXC TXC (UPM1 = 1) TXEN TxD I/O
132
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
USART UCSRB (RXEN) USART RxD
USART XCK
5 8
XCK UDR RXC 8 UDR 0 USART (1)
USART_Receive: ; sbis UCSRA, RXC rjmp USART_Receive ; in ret r16, UDR
C (1)
unsigned char USART_Receive( void ) { /* */ while ( !(UCSRA & (1<Note:
1.
RXC
133
2486N-AVR-07/04
9
9 (UCSZ=7) UDR 8 UCSRB RXB8 9 FE DOR UPE UCSRA UDR UDR FIFO FIFO TXB8 FE DOR UPE USART 9 (1)
USART_Receive: ; sbis UCSRA, RXC rjmp USART_Receive ; 9 in in in r18, UCSRA r17, UCSRB r16, UDR
; -1 andi r18,(1<USART_ReceiveNoError: ; 9 lsr ret r17 andi r17, 0x01
C (1)
unsigned int USART_Receive( void ) { unsigned char status, resh, resl; /* */ while ( !(UCSRA & (1<> 1) & 0x01; return ((resh << 8) | resl); }
Note:
1.
I/O 134 USART
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
(RXC) 1 0( ) (RXEN = 0) RXC UCSRB (RXCIE) RXC ( ) USART UDR RXC USART (FE) (DOR) (UPE) UCSRA UDR UCSRA (UDR) "0" (FE) ( 1) FE 0 FE 1 UCSRC USBS FE UCSRA 0 (DOR) ( ) DOR UDR UDR UCSRA 0 DOR (PE) UPE UCSRA 0 P 128" " P 136" "
135
2486N-AVR-07/04
UPM1 ( ) UPM0 (UPE) (UPM1 = 1) UPE (UDR)
(RXEN ) RxD FIFO FIFO UDR RXC (1)
USART_Flush: sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush
C (1)
void USART_Flush( void ) { unsigned char dummy; while ( UCSRA & (1<Note:
1.
USART RxD Figure 65 16 8 (U2X = 1) RxD ( ) 0 Figure 65.
RxD IDLE START BIT 0
Sample
(U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
Sample
(U2X = 1) 0 1 2 3 4 5 6 7 8 1 2
RxD ( ) ( ) 1 0 136
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
8 9 10( ) 4 5 6( ) ( ) 16 8 Figure 66 Figure 66.
RxD BIT n
Sample
(U2X = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
Sample
(U2X = 1) 1 2 3 4 5 6 7 8 1
2 3 1 2 3 0RxD Figure 67 Figure 67.
RxD STOP 1
(A) (B) (C)
Sample
(U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1
Sample
(U2X = 1) 1 2 3 4 5 6 0/1
0 FE Figure 67 A B C ( Table 53)
137
2486N-AVR-07/04
( D + 1 )S R slow = --------------------------------------------S - 1 + D S + SF D S SF SM
( D + 2 )S R fast = ------------------------------------( D + 1 )S + S M
(D = 5 10 ) S = 16 S = 8 SF = 8 SF = 4 SM = 9 SM = 5
Rslow Rfast Table 53 Table 54 Table 53. (U2X = 0)
D # ( + ) 5 6 7 8 9 10 Rslow % 93,20 94,12 94,81 95,36 95,81 96,17 Rfast % 106,67 105,79 105,11 104,58 104,14 103,78 (%) +6.67/-6.8 +5.79/-5.88 +5.11/-5.19 +4.58/-4.54 +4.14/-4.19 +3.78/-3.83 (%) 3.0 2.0 2.0 2.0 1.5 1.5
Table 54. (U2X = 1)
D # + 5 6 7 8 9 10 Rslow (%) 94,12 94,92 95,52 96,00 96,39 96,70 Rfast (%) 105,66 104,92 104,35 103,90 103,53 103,23 (%) +5.66/-5.88 +4.92/-5.08 +4.35/-4.48 +3.90/-4.00 +3.53/-3.61 +3.23/-3.30 (%) 2.5 2.0 1.5 1.5 1.5 1.0
(XTAL) 2% UBRR
138
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
UCSRA (MPCM) USART CPU MPCM 5 8 9 9 (RXB8) ( 9 ) 1 MPCM 9 (UCSZ = 7) (TXB8 = 1) 9 (TXB8) 1 (TXB = 0) 9 1. (UCSRA MPCM ) 2. UCSRA RXC 3. UDR UCSRA MPCM MPCM 1 4. MPCM 1 5. MPCM 2 5 8 n n+1 5 8 (USBS = 1) - - (SBI CBI) MPCM MPCM TXC I/O SBI CBI
139
2486N-AVR-07/04
UBRRH/ UCSRC
UBRRH UCSRC I/O
USART (URSEL) URSEL 0 UBRRH URSEL 1 UCSRC (1)
... ; UBRRH 2 ldi r16,0x02 out UBRRH,r16 ... ; USBS UCSZ1 1 0 ldi r16,(1<C (1)
... /* UBRRH 2*/ UBRRH = 0x02; ... /* USBS UCSZ1 1 0*/ UCSRC = (1<Note:
1.
I/O
140
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
UBRRH UCSRC UBRRH I/O UCSRC UCSRC ( ) UCSRC (1)
USART_ReadUCSRC: ; UCSRC in in ret r16,UBRRH r16,UCSRC
C (1)
unsigned char USART_ReadUCSRC( void ) { unsigned char ucsrc; /* UCSRC */ ucsrc = UBRRH; ucsrc = UCSRC; return ucsrc; }
Note:
1.
r16 UCSRC UBRRH
USART
USART I/O UDR
Bit 7 6 5 4
RXB[7:0] TXB[7:0]
3
2
1
0 UDR ( ) UDR ( )
/
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
USART USART I/O USART UDR UDR (TXB) UDR (RXB) 567 0 UCSRA UDRE UDRE UDR USART TxD FIFO FIFO - - (SBI CBI) (SBIC SBIS) FIFO
141
2486N-AVR-07/04
USART A UCSRA
Bit /
7 RXC R 0
6 TXC R/W 0
5 UDRE R 1
4 FE R 0
3 DOR R 0
2 PE R 0
1 U2X R/W 0
0 MPCM R/W 0 UCSRA
* Bit 7 - RXC: USART RXC RXC RXC ( RXCIE ) * Bit 6 - TXC: USART (UDR) TXC TXC 1 TXC ( TXCIE ) * Bit 5 - UDRE: USART UDRE(UDR) UDRE1 UDRE ( UDRIE ) UDRE * Bit 4 - FE: 0 FE (UDR) 1 FE 0 UCSRA 0 * Bit 3 - DOR: DOR ( ) (UDR) UCSRA 0 * Bit 2 - PE: (UPM1 = 1) UPE (UDR) UCSRA 0 * Bit 1 - U2X: 1 16 8 * Bit 0 - MPCM: MPCM USART MPCM P 139" " USART B UCSRB
Bit /
7 RXCIE R/W 0
6 TXCIE R/W 0
5 UDRIE R/W 0
4 RXEN R/W 0
3 TXEN R/W 0
2 UCSZ2 R/W 0
1 RXB8 R 0
0 TXB8 R/W 0 UCSRB
* Bit 7 - RXCIE: RXC RXCIE 1 SREG UCSRA RXC 1 USART
142
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
* Bit 6 - TXCIE: TXC TXCIE 1 SREG UCSRA TXC 1 USART * Bit 5 - UDRIE: USART UDRE UDRIE 1 SREG UCSRA UDRE 1 USART * Bit 4 - RXEN: USART RxD USART FE DOR PE * Bit 3 - TXEN: USART TxD USART TXEN TxD I/O * Bit 2 - UCSZ2: UCSZ2UCSRCUCSZ1:0( ) * Bit 1 - RXB8: 8 9 RXB8 9 UDR RXB8 * Bit 0 - TXB8: 8 9 TXB8 9 UDR USART C UCSRC
Bit /
7 URSEL R/W 1
6 UMSEL R/W 0
5 UPM1 R/W 0
4 UPM0 R/W 0
3 USBS R/W 0
2 UCSZ1 R/W 1
1 UCSZ0 R/W 1
0 UCPOL R/W 0 UCSRC
UBRRH/ UCSRC "
UCSRC UBRRH I/O P 140"
* Bit 7 - URSEL: UCSRC UBRRH UCSRC 1 UCSRC URSEL 1 * Bit 6 - UMSEL: USART Table 55. UMSEL
UMSEL 0 1
143
2486N-AVR-07/04
* Bit 5:4 - UPM1:0: UPM0 UCSRA PE Table 56. UPM
UPM1 0 0 1 1 UPM0 0 1 0 1
* Bit 3 - USBS: Table 57. USBS
USBS 0 1 1 2
* Bit 2:1 - UCSZ1:0: UCSZ1:0UCSRB UCSZ2( ) Table 58. UCSZ
UCSZ2 0 0 0 0 1 1 1 1 UCSZ1 0 0 1 1 0 0 1 1 UCSZ0 0 1 0 1 0 1 0 1 5 6 7 8 9
* Bit 0 - UCPOL: UCPOL XCK Table 59. UCPOL
UCPOL 0 1 (TxD ) XCK XCK (RxD ) XCK XCK
144
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
USART UBRRL UBRRH
Bit
15 URSEL 7
14 - 6 R R/W 0 0
13 - 5 R R/W 0 0
12 -
11
10
9
8 UBRRH UBRRL 0 R/W R/W 0 0
UBRR[11:8] 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0
UBRR[7:0] 4 R R/W 0 0 / R/W R/W 0 0
UBRRH/ UCSRC "
UCSRC UBRRH I/O P 140"
* Bit 15 - URSEL: UCSRC UBRRH UBRRH 0 UBRRH URSEL 0 * Bit 14:12 - UBRRH * Bit 11:0 - UBRR11:0: USART 12 USART UBRRH USART 4 UBRRL 8 UBRRL
145
2486N-AVR-07/04
Table 60 UBRR 0.5% ( P 137" " )
BaudRate Closest Match Error[%] = ------------------------------------------------------- - 1 * 100% BaudRate
Table 60. UBRR
fosc = 1.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 1.
(1)
fosc = 1.8432 MHz U2X = 0 UBRR 47 23 11 7 5 3 2 1 1 0 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -25.0% 0.0% - - U2X = 1 UBRR 95 47 23 15 11 7 5 3 2 1 0 - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% - 0.2% 0.2% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - UBRR 51 25 12 8 6 3 2 1 1 0 - -
fosc = 2.0000 MHz U2X = 0 0.2% 0.2% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - 125 kbps U2X = 1 UBRR 103 51 25 16 12 8 6 3 2 1 - 0 0.2% 0.2% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% - 0.0% 250 kbps
U2X = 0 UBRR 25 12 6 3 2 1 1 0 - - - - 0.2% 0.2% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - - -
U2X = 1 UBRR 51 25 12 8 6 3 2 1 1 0 - - 125 kbps
62.5 kbps UBRR = 0, = 0.0%
115.2 kbps
230.4 kbps
146
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Table 61. UBRR
fosc = 3.6864 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1.
(1)
fosc = 4.0000 MHz U2X = 0 UBRR 103 51 25 16 12 8 6 3 2 1 0 0 - - 250 kbps 0.2% 0.2% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% 8.5% 0.0% - - U2X = 1 UBRR 207 103 51 34 25 16 12 8 6 3 1 1 0 - 0.2% 0.2% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 0.0% 0.0% - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% - UBRR 191 95 47 31 23 15 11 7 5 3 1 1 0 -
fosc = 7.3728 MHz U2X = 0 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% - U2X = 1 UBRR 383 191 95 63 47 31 23 15 11 7 3 3 1 0 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -7.8%
U2X = 0 UBRR 95 47 23 15 11 7 5 3 2 1 0 0 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - -
U2X = 1 UBRR 191 95 47 31 23 15 11 7 5 3 1 1 0 -
230.4 kbps UBRR = 0, = 0.0%
460.8 kbps
0.5 Mbps
460.8 kbps
921.6 kbps
147
2486N-AVR-07/04
Table 62. UBRR
fosc = 8.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1.
(1)
fosc = 11.0592 MHz U2X = 0 UBRR 287 143 71 47 35 23 17 11 8 5 2 2 - - 691.2 kbps 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - - U2X = 1 UBRR 575 287 143 95 71 47 35 23 17 11 5 5 2 - 1.3824 Mbps 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% - -0.1% 0.2% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% 8.5% 0.0% 0.0% 0.0% UBRR 383 191 95 63 47 31 23 15 11 7 3 3 1 0
fosc = 14.7456 MHz U2X = 0 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -7.8% U2X = 1 UBRR 767 383 191 127 95 63 47 31 23 15 7 6 3 1 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 5.3% -7.8% -7.8%
U2X = 0 UBRR 207 103 51 34 25 16 12 8 6 3 1 1 0 - 0.5 Mbps UBRR = 0, = 0.0% 0.2% 0.2% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 0.0% 0.0% -
U2X = 1 UBRR 416 207 103 68 51 34 25 16 12 8 3 3 1 0 1 Mbps
921.6 kbps
1.8432 Mbps
148
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Table 63. UBRR
fosc = 16.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1.
(1)
fosc = 18.4320 MHz U2X = 0 UBRR 479 239 119 79 59 39 29 19 14 9 4 4 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - - U2X = 1 UBRR 959 479 239 159 119 79 59 39 29 19 9 8 4 - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 2.4% -7.8% - 0.0% -0.1% 0.2% -0.1% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% -3.5% 0.0% 0.0% 0.0% UBRR 520 259 129 86 64 42 32 21 15 10 4 4 - -
fosc = 20.0000 MHz U2X = 0 0.0% 0.2% 0.2% -0.2% 0.2% 0.9% -1.4% -1.4% 1.7% -1.4% 8.5% 0.0% - - U2X = 1 UBRR 1041 520 259 173 129 86 64 42 32 21 10 9 4 - 0.0% 0.0% 0.2% -0.2% 0.2% -0.2% 0.2% 0.9% -1.4% -1.4% -1.4% 0.0% 0.0% -
U2X = 0 UBRR 416 207 103 68 51 34 25 16 12 8 3 3 1 0 -0.1% 0.2% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% 8.5% 0.0% 0.0% 0.0% 1 Mbps UBRR = 0, = 0.0%
U2X = 1 UBRR 832 416 207 138 103 68 51 34 25 16 8 7 3 1
2 Mbps
1.152 Mbps
2.304 Mbps
1.25 Mbps
2.5 Mbps
149
2486N-AVR-07/04
TWI
* * * * * * * * * *
7 128 400 kHz AVR
TWI TWI 128 SCL SDA TWI Figure 68. TWI
VCC
Device 1
Device 2
Device 3
........
Device n
R1
R2
SDA
SCL
TWI
Table 64. TWI
SCL
150
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 68 TWI TWI "0" TWI TWI TWI AVR 400 pF 7 TWI P 229" " 100 kHz 400 kHz
( ) TWI Figure 69.
SDA
SCL Data Stable Data Stable
Data Change
START/STOP START STOP START STOP START STOP START REPEATED START REPEATED START STOP START START REPEATED START START START STOP SCL SDA Figure 70. START REPEATED START STOP
SDA
SCL
START
STOP
START
REPEATED START
STOP
151
2486N-AVR-07/04
TWI 9 7 1 READ/WRITE 1 READ/WRITE 1 SCL (ACK) SDA ACK SDA STOP REPEATED START SLA+R SLA+W READ WRITE MSB 0000 000 ACK SDA Write ACK SDA Read 1111 xxx Figure 71.
Addr MSB SDA Addr LSB R/W ACK
SCL 1 START 2 7 8 9
152
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
TWI 9 8 1 START STOP 9 SCL SDA SDA NACK NACK MSB Figure 72.
Data MSB Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master 1 SLA+R/W 2 7 Data Byte 8 9 STOP, REPEATED START or Next Data Byte Data LSB ACK

START SLA+R/W STOP START STOP SCL SCL SCL SCL SCL SCL SCL TWI Figure 73 SLA+R/W STOP
Figure 73.
Addr MSB SDA
Addr LSB
R/W
ACK
Data MSB
Data LSB
ACK
SCL 1 START 2 7 SLA+R/W 8 9 1 2 Data Byte 7 8 9 STOP
153
2486N-AVR-07/04
TWI
*
*
SCL
SCL / SCL / Figure 74. SCL
TA low
TA high
SCL from Master A
SCL from Master B
SCL Bus Line TBlow Masters Start Counting Low Period TBhigh Masters Start Counting High Period
SDA SDA SDA SDA
154
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 75.
START SDA from Master A Master A Loses Arbitration, SDAA SDA
SDA from Master B
SDA Line
Synchronized SCL Line
* * * REPEATED START STOP REPEATED START STOP
SLA+R/W
155
2486N-AVR-07/04
TWI
TWI Figure 76 AVR Figure 76. TWI
SCL
Slew-rate Control Spike Filter
SDA
Slew-rate Control Spike Filter
Bus Interface Unit
START / STOP Control Spike Suppression
Bit Rate Generator
Prescaler
Arbitration detection
Address/Data Shift Register (TWDR)
Ack
Bit Rate Register (TWBR)
Address Match Unit
Address Register (TWAR)
Control Unit
Status Register (TWSR) Control Register (TWCR)
Address Comparator
State Machine and Status control
SCL SDA
SCL SDAMCU TWI TWI 50 ns SCL SDA I/O
156
ATmega8(L)
2486N-AVR-07/04
TWI Unit
ATmega8(L)
TWI SCL TWI TWSR TWBR TWI CPU TWI SCL 16 SCL TWI SCL CPU Clock frequency SCL frequency = -----------------------------------------------------------TWPS 16 + 2(TWBR) 4 * * TWBR = TWI TWPS = TWI
TWI TWBR 10 SDA SCL TWI Start + SLA + R/W ( )
Note:
TWDRSTART/STOP TWDR 8 TWDR (N)ACK (N)ACK TWI TWCR (N)ACK TWCR START/STOP TWI START REPEATED START STOP MCU START/STOP TWI START/STOP TWI MCU TWI TWI
TWAR 7 TWAR TWI TWGCE "1" TWI TWCR MCU MCU TWI TWI TWCR TWI TWI TWINT TWI TWSR TWSR TWINT "1" SCL TWI TWINT * * * * * * * * TWI START/REPEATED START TWI SLA+R/W TWI TWI TWI ( ) TWI TWI STOP REPEATED START START STOP
157
2486N-AVR-07/04
TWI
TWI TWBR
Bit / 7 TWBR7 R/W 0 6 TWBR6 R/W 0 5 TWBR5 R/W 0 4 TWBR4 R/W 0 3 TWBR3 R/W 0 2 TWBR2 R/W 0 1 TWBR1 R/W 0 0 TWBR0 R/W 0 TWBR
* Bits 7..0 - TWI TWBR SCL P 157" " TWI TWCR
Bit / 7 TWINT R/W 0 6 TWEA R/W 0 5 TWSTA R/W 0 4 TWSTO R/W 0 3 TWWC R 0 2 TWEN R/W 0 1 - R 0 0 TWIE R/W 0 TWCR
TWCR TWI TWI START STOP TWDR TWDR TWDR * Bit 7 - TWINT: TWI TWI TWINT SREG I TWCR TWIE MCU TWI TWINT SCL TWINT "1" "0" TWI TWINT TWAR TWSR TWDR * Bit 6 - TWEA: TWI TWEA TWEA ACK 1. 2. TWAR TWGCE 3. / TWEA * Bit 5 - TWSTA: TWI START CPU TWSTA TWI START STOP START START TWSTA * Bit 4 - TWSTO: TWI STOP TWSTOTWI STOP TWSTO TWSTO STOP TWI SCL SDA * Bit 3 - TWWC:TWI TWINT TWDR TWWC TWINT TWDR
158
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
* Bit 2 - TWEN: TWI TWEN TWITWI TWEN"1" TWII/O SCL SDA TWI TWI * Bit 1 - Res: "0" * Bit 0 - TWIE: TWI SREG I TWIE TWINT "1" TWI
159
2486N-AVR-07/04
TWI TWSR
Bit / 7 TWS7 R 1 6 TWS6 R 1 5 TWS5 R 1 4 TWS4 R 1 3 TWS3 R 1 2 - R 0 1 TWPS1 R/W 0 0 TWPS0 R/W 0 TWSR
* Bits 7..3 - TWS: TWI 5 TWI TWSR 5 2 "0" * Bit 2 - Res: "0" * Bits 1..0 - TWPS: TWI / Table 65. TWI
TWPS1 0 0 1 1 TWPS0 0 1 0 1 1 4 16 64
P 157" " TWPS1..0 TWI TWDR
Bit / 7 TWD7 R/W 1 6 TWD6 R/W 1 5 TWD5 R/W 1 4 TWD4 R/W 1 3 TWD3 R/W 1 2 TWD2 R/W 1 1 TWD1 R/W 1 0 TWD0 R/W 1 TWDR
TWDR TWDR TWI (TWINT ) TWINT TWDR TWDR MCU TWI TWDR ACK TWI CPU ACK * Bits 7..0 - TWD: TWI TWI( ) TWAR
Bit /
7
TWA6
6
TWA5
5
TWA4
4
TWA3
3
TWA2
2
TWA1
1
TWA0
0
TWGCE TWAR
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 1
R/W 0
TWAR 7 TWI TWAR
160
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
TWAR LSB (0x00) * Bits 7..1 - TWA: TWI * Bit 0 - TWGCE: TWI MCU TWI
TWI
AVR TWI START TWI TWI TWI TWCR TWI TWIESREGTWINT TWIE TWINT TWI TWINT "1" TWI TWI TWSR TWI TWCR TWCR TWDR TWI TWI Figure 77 TWI
Figure 77. TWI
Application Action
1. Application writes to TWCR to initiate transmission of START
3. Check TWSR to see if START was sent. Application loads SLA+W into TWDR, and loads appropriate control signals into TWCR, makin sure that TWINT is written to one, and TWSTA is written to zero.
5. Check TWSR to see if SLA+W was sent and ACK received. Application loads data into TWDR, and loads appropriate control signals into TWCR, making sure that TWINT is written to one
7. Check TWSR to see if data was sent and ACK received. Application loads appropriate control signals to send STOP into TWCR, making sure that TWINT is written to one
TWI bus
START
SLA+W
A
Data
A
STOP
2. TWINT set. Status code indicates START condition sent
4. TWINT set. Status code indicates SLA+W sent, ACK received
TWI Hardware Action
6. TWINT set. Status code indicates data sent, ACK received
Indicates TWINT set
1. TWI START TWCR TWI START TWINT TWINT "1" TWCR TWINT TWI TWINT TWI START 2. START TWCR TWINTTWCR START 3. TWSR START TWSR SLA+W TWDR TWDR TWDRSLA+W TWCRTWISLA+W TWINT TWINT
161
2486N-AVR-07/04
"1" TWCR TWINT TWI TWINT TWI 4. TWCR TWINT TWDR 5. TWSRACK TWSR TWDR TWCR TWI TWDR TWINT TWCR TWINT TWI TWINT TWI 6. TWCR TWINT TWSR 7. TWSR ACK TWSR TWCR TWI STOP TWINT TWINT "1" TWCR TWINT TWI TWINT TWI STOP TWINT STOP TWI * * * TWI TWINT TWINT SCL TWINT TWI TWI TWDR TWI TWCR TWCR TWINT TWINT "1" TWI TWCR
C
162
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
1 ldi r16, (1<C TWCR = (1< START
TWINT TWINT START
if ((TWSR & 0xF8) != START) ERROR();
TWI START SLA_W TWDR TWINT
TWDR = SLA_W; TWCR = (1<out TWCR, r16 wait2: in r16,TWCR sbrs r16,TWINT
while (!(TWCR & (1< TWINT TWINT SLA+W ACK/NACK TWI MT_SLA_ACK TWDR TWINT
5
rjmp wait2 in r16,TWSR andi r16, 0xF8 cpi r16, MT_SLA_ACK brne ERROR ldi r16, DATA out ldi TWDR, r16 r16, (1<if ((TWSR & 0xF8) != MT_SLA_ACK) ERROR();
TWDR = DATA; TWCR = (1<6
out TWCR, r16 wait3: in r16,TWCR sbrs r16,TWINT
while (!(TWCR & (1< TWINT TWINT DATA ACK/NACK TWI MT_DATA_ACK STOP
7
rjmp wait3 in r16,TWSR andi r16, 0xF8 cpi r16, MT_DATA_ACK brne ERROR ldi r16, (1<if ((TWSR & 0xF8) != MT_DATA_ACK) ERROR();
TWCR = (1<163
2486N-AVR-07/04
TWI 4 (MT) (MR) (ST) (SR) TWI MT TWI EEPROM MR EEPROM TWI SR S START RsREPEATED START R (SDA ) W (SDA ) A (SDA ) A (SDA ) Data8 P STOP SLA Figure 79 Figure 85 TWINT TWSR 0 / TWI TWI TWINT TWINT TWSR Table 66 Table 69. 0
164
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 78 START MT MR SLA+W MT SLA+R MR "0" Figure 78.
VCC
Device 1
MASTER TRANSMITTER
Device 2
SLAVE RECEIVER
Device 3
........
Device n
R1
R2
SDA
SCL
TWCR START
TWCR TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
TWEN TWSTA"1"START TWINT "1" TWINT TWI START TWINT TWSR 0x08 ( Table 66) MT SLA+W TWDR SLA+W TWINT TWI TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
SLA+W TWINT TWSR 0x18 0x20 0x38 Table 66 SLA+W TWDR TWDR TWINT TWCR TWWC TWDR TWINT TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
STOP REPEATED START STOP TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 1 TWWC X TWEN 1 - 0 TWIE X
REPEATED START TWCR
TWCR TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
165
2486N-AVR-07/04
REPEATED START ( 0x10) STOP REPEATED START Table 66.
(TWSR) "0"
0x08
TWCR 2 2 START START / TWDR SLA+W SLA+W SLA+R STA
0
STO
0
TWIN T
1
TWE A
X
2 SLA+W ACK NOT ACK SLA+W ACK NOT ACK SLA+R
0x10
0 0
0 0
1 1
X X
0x18
SLA+W ACK
( ) TWDR TWDR TWDR
0 1 0 1
0 0 1 1
1 1 1 1
X X X X
ACK NOT ACK START STOP TWSTO STOP START TWSTO ACK NOT ACK START STOP TWSTO STOP START TWSTO
0x20
SLA+W NOT ACK
( ) TWDR TWDR TWDR
0 1 0 1
0 0 1 1
1 1 1 1
X X X X
0x28
ACK
( ) TWDR TWDR TWDR
0 1 0 1
0 0 1 1
1 1 1 1
X X X X
ACK NOT ACK START STOP TWSTO STOP START TWSTO ACK NOT ACK START STOP TWSTO STOP START TWSTO
0x30
NOT ACK
( ) TWDR TWDR TWDR
0 1 0 1
0 0 1 1
1 1 1 1
X X X X
0x38
SLA+W
TWDR TWDR
0 1
0 0
1 1
X X
2 START
166
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 79.
MT
Successfull transmission to a slave receiver
S
SLA
W
A
DATA
A
P
$08
Next transfer started with a repeated start condition
$18
$28
RS
SLA
W
$10
Not acknowledge received after the slave address
A
P
R
$20
MR
Not acknowledge received after a data byte
A
P
$30
Arbitration lost in slave address or data byte
A or A
Other master continues
A or A
Other master continues
$38
Arbitration lost and addressed as slave
$38
Other master continues
A
$68
$78
$B0
To corresponding states in slave mode
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-Wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
167
2486N-AVR-07/04
Figure 80 START MT MR SLA+W MT SLA+R MR "0" Figure 80.
VCC
Device 1
MASTER RECEIVER
Device 2
SLAVE TRANSMITTER
Device 3
........
Device n
R1
R2
SDA
SCL
TWCR START
TWCR TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
TWEN TWSTA"1"START TWINT "1" TWINT TWI START TWINT TWSR 0x08 ( Table 66) MR SLA+R TWDR SLA+R TWINT TWI TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
SLA+R TWINT TWSR 0x380x40 0x48 Table 67 TWDR TWINT MR NACK STOP REPEATED START STOP TWCR
TWCR TWINT 1 TWEA X TWSTA 0 TWSTO 1 TWWC X TWEN 1 - 0 TWIE X
REPEATED START TWCR
TWCR TWINT 1 TWEA X TWSTA 1 TWSTO 0 TWWC X TWEN 1 - 0 TWIE X
REPEATED START ( 0x10) STOP REPEATED START Table 67.
(TWSR) "0" TWCR 2 2 / TWDR STA STO TWIN T TWE A 2
168
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Table 67.
0x08
START START
SLA+R SLA+R SLA+W
0
0
1
X
SLA+R ACK NOT ACK SLA+R ACK NOT ACK SLA+W
0x10
0 0
0 0
1 1
X X
0x38
SLA+R NOT ACK SLA+R ACK SLA+R NOT ACK
TWDR TWDR
0 1
0 0 0 0 0 1 1
1 1 1 1 1 1 1
X X 0 1
2 START NOT ACK ACK
0x40
TWDR TWDR
0 0
0x48
TWDR TWDR TWDR
1 0 1
X X X
START STOP TWSTO STOP START TWSTO
0x50
ACK NOT ACK

0 0
0 0 0 1 1
1 1 1 1 1
0 1
NOT ACK ACK
0x58

1 0 1
X X X
START STOP TWSTO STOP START TWSTO
169
2486N-AVR-07/04
Figure 81.
MR
Successfull reception from a slave receiver
S
SLA
R
A
DATA
A
DATA
A
P
$08
Next transfer started with a repeated start condition
$40
$50
$58
RS
SLA
R
$10
Not acknowledge received after the slave address
A
P
W
$48
MT
Arbitration lost in slave address or data byte
A or A
Other master continues
A
Other master continues
$38
Arbitration lost and addressed as slave
$38
Other master continues
A
$68
$78
$B0
To corresponding states in slave mode
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-Wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
Figure 82 "0" Figure 82.
VCC
Device 1
SLAVE RECEIVER
Device 2
MASTER TRANSMITTER
Device 3
........
Device n
R1
R2
SDA
SCL
TWAR TWCR
TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
170
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
7 TWI LSB TWI 0x00
TWCR TWINT 0 TWEA 1 TWSTA 0 TWSTO 0 TWWC 0 TWEN 1 - 0 TWIE X
TWENTWI TWEA() ACK TWSTA TWSTO TWAR TWCR TWI ( TWAR TWGCE ) 0 ( ) TWINT TWSR Table 68 TWI ( 0x68 0x78) CPU TWEA TWI SDA " " TWEA TWI TWEA TWEA TWI TWI / CPU TWISCL TWCINT AVRTWI AVR SCL MCU TWDR
171
2486N-AVR-07/04
Table 68.
(TWSR) "0"
0x60
TWCR 22 SLA+W ACK SLA+R/W SLA+W ACK ACK SLA+R/W ACK SLA+W ACK SLA+W NOT ACK / TWDR TWDR TWDR STA
X X
STO
0 0 0 0
TWIN T
1 1 1 1
TWE A
0 1
2 NOT ACK ACK
0x68
TWDR TWDR TWDR TWDR
X X
0 1
NOT ACK ACK
0x70
X X
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
0 1
NOT ACK ACK
0x78
TWDR TWDR TWDR TWDR
X X X X 0 0 1
0 1
NOT ACK ACK
0x80
0 1 0 1 0
NOT ACK ACK SLA GCA SLA TWGCE = "1" GCA SLA GCA START SLA TWGCE = "1" GCA START
0x88
1 0 1 1
172
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Table 68.
0x90
ACK NOT ACK
r
X X 0 0 1
0 0 0 0 0
1 1 1 1 1
0 1
NOT ACK ACK
0x98
0 1 0
SLA GCA SLA TWGCE = "1" GCA SLA GCA START SLA TWGCE = "1" GCA START
1 0 1 1
0xA0
STOP START
0 0 1
0 0 0
1 1 1
0 1 0
SLA GCA SLA TWGCE = "1" GCA SLA GCA START SLA TWGCE = "1" GCA START
1
0
1
1
173
2486N-AVR-07/04
Figure 83.
Reception of the own slave address and one or more data bytes. All are acknowledged
S
SLA
W
A
DATA
A
DATA
A
P or S
$60
Last data byte received is not acknowledged
$80
$80
$A0
A
P or S
$88
Arbitration lost as master and addressed as slave
A
$68
Reception of the general call address and one or more data bytes
General Call
A
DATA
A
DATA
A
P or S
$70
Last data byte received is not acknowledged
$90
$90
$A0
A
P or S
$98
Arbitration lost as master and addressed as slave by general call
A
$78
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-Wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
174
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 84 "0" Figure 84.
VCC
Device 1
SLAVE TRANSMITTER
Device 2
MASTER RECEIVER
Device 3
........
Device n
R1
R2
SDA
SCL
TWAR TWCR
TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
7 TWI LSB TWI 0x00
TWCR TWINT 0 TWEA 1 TWSTA 0 TWSTO 0 TWWC 0 TWEN 1 - 0 TWIE X
TWENTWI TWEA() ACK TWSTA TWSTO TWAR TWCR TWI ( TWAR TWGCE ) "1" ( ) TWI TWSR Table 69 TWI ( 0xB0) CPU TWEA TWI 0xC0 0xC8 "1" ( ACK) 0xC8 TWEA TWI TWEA TWEA TWI TWI / CPU TWISCL TWCINT AVR AVR SCL MCU TWDR
175
2486N-AVR-07/04
Table 69.
(TWSR) "0"
0xA8
TWCR 22 SLA+R ACK / TWDR STA
X X
STO
0 0
TWIN T
1 1
TWE A
0 1
2 NOT ACK ACK
0xB0
SLA+R/W SLA+R ACK TWDR ACK

X X
0 0
1 1
0 1
NOT ACK ACK
0xB8
X X
0 0
1 1
0 1
NOT ACK ACK
0xC0
TWDR NOT ACK
TWDR TWDR
0 0 1
0 0 0
1 1 1
0 1 0
SLA GCA SLA TWGCE = "1" GCA SLA GCA START SLA TWGCE = "1" GCA START
TWDR
1 0 1 1
TWDR
0xC8
TWDR (TWAE = "0"); ACK
TWDR TWDR
0 0 1
0 0 0
1 1 1
0 1 0
SLA GCA SLA TWGCE = "1" GCA SLA GCA START SLA TWGCE = "1" GCA START
TWDR
1 0 1 1
TWDR
176
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 85.
Reception of the own slave address and one or more data bytes
S
SLA
R
A
DATA
A
DATA
A
P or S
$A8
Arbitration lost as master and addressed as slave
$B8
$C0
A
$B0
Last data byte transmitted. Switched to not addressed slave (TWEA = '0')
A
All 1's
P or S
$C8
From master to slave
DATA
A
Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-Wire Serial Bus. The prescaler bits are zero or masked to zero
From slave to master
n
TWI Table 70 0xF8 TWINT "0" TWI 0x00 START STOP ACKSTARTSTOP TWINT TWSTO "1" TWINT TWI TWSTO (TWCR ) SDA SCL STOP
Table 70.
(TWSR) "0"
0xF8
TWCR 2 2 TWINT = "0" START STOP / TWDR TWDR TWDR
0
STA
STO
TWIN T
TWE A
2
No TWCR action
0x00
1
1
X
STOP TWSTO
177
2486N-AVR-07/04
TWI
TWI EEPROM 1. 2. EEPROM 3. 4. MT MR EEPROM REPEATED START REPEATED START Figure 86. TWI EEPROM
Master Transmitter Master Receiver
S
SLA+W
A
ADDRESS
A
Rs
SLA+R
A
DATA
A
P
S = START Transmitted from master to slave
Rs = REPEATED START Transmitted from slave to master
P = STOP
TWI Figure 87.
VCC
Device 1
MASTER TRANSMITTER
Device 2
MASTER TRANSMITTER
Device 3
SLAVE RECEIVER
........
Device n
R1
R2
SDA
SCL
* * READ/WRITE SDA "0" START
178
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
* SLA SDA "0" SLA SR ST SLA READ/WRITE START
Figure 88 TWI Figure 88.
START SLA Data STOP
Arbitration lost in SLA
Arbitration lost in Data
Own Address / General Call received
No
38
TWI bus will be released and not addressed slave mode will be entered A START condition will be transmitted when the bus becomes free
Yes Write 68/78
Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned
Direction
Read B0
Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received
179
2486N-AVR-07/04
AIN0 AIN1 AIN0 AIN1 ACO / 1 Figure 89 Figure 89. (2)
BANDGAP REFERENCE ACBG
ACME ADEN ADC MULTIPLEXER OUTPUT (1)
Notes:
1. P 182Table 72 2. P 2" " P 59Table 28
IO SFIOR
Bit / 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 ACME R/W 0 2 PUD R/W 0 1 PSR2 R/W 0 0 PSR10 R/W 0 SFIOR
* Bit 3 - ACME: "1" ADC (ADCSRA ADEN "0") ADC "0" AIN1 P 181" "
180
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
ACSR
Bit /
7 ACD R/W 0
6 ACBG R/W 0
5 ACO R N/A
4 ACI R/W 0
3 ACIE R/W 0
2 ACIC R/W 0
1 ACIS1 R/W 0
0 ACIS0 R/W 0 ACSR
* Bit 7 - ACD: ACD ACD ACSR ACIE ACD * Bit 6 - ACBG: ACBG AIN0 P 39 " " * Bit 5 - ACO: ACO 1-2 * Bit 4 - ACI: ACIS1 ACIS0 ACI ACIE SREG I ACI ACI "1" * Bit 3 - ACIE: ACIE "1" I * Bit 2 - ACIC: ACIC T/C1 T/C1 ACIC "0" T/C1 TIMSK TICIE1 * Bits 1,0 - ACIS1, ACIS0: Table 71 Table 71. ACIS1/ACIS0
ACIS1 0 0 1 1 ACIS0 0 1 0 1
ACIS1/ACIS0 ACSR
ADC7..0 ADC ADC (SFIOR ACME) ADC (ADCSRA ADEN 0)
181
2486N-AVR-07/04
ADMUX MUX2..0 Table 72 ACME ADEN AIN1 Table 72. (1)
ACME 0 1 1 1 1 1 1 1 1 1 Note: ADEN x 1 0 0 0 0 0 0 0 0 MUX2..0 xxx xxx 000 001 010 011 100 101 110 111 AIN1 AIN1 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7
1. TQFP MLF ADC7..6
182
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
* * * * * * * * * * * * *
10 0.5 LSB 2 LSB 13 - 260 s 15 kSPS 6 2 (TQFP MLF ) ADC 0 - VCC ADC 2.56V ADC ADC
.ATmega8 10 ADC ADC 8 C 8 0V (GND) ADC ADC ADC Figure 90 ADC AVCC AVCC VCC 0.3V P 188"ADC " 2.56V AVCC AREF
183
2486N-AVR-07/04
Figure 90.
ADC CONVERSION COMPLETE IRQ
8-BIT DATA BUS
ADIF ADIE
15 ADC DATA REGISTER (ADCH/ADCL)
ADPS0 ADC[9:0]
0
ADC MULTIPLEXER SELECT (ADMUX)
ADLAR REFS1 MUX2 MUX1 REFS0 MUX3 MUX0
ADC CTRL. & STATUS REGISTER (ADCSRA)
ADPS2 ADPS1
ADSC
ADEN
ADFR
MUX DECODER PRESCALER
CHANNEL SELECTION
ADIF
CONVERSION LOGIC
AVCC
INTERNAL 2.56V REFERENCE AREF
10-BIT DAC
SAMPLE & HOLD COMPARATOR +
GND
BANDGAP REFERENCE
ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0
INPUT MUX
ADC MULTIPLEXER OUTPUT
ADC 10 GND AREF 1 LSB ADMUX REFSn AVCC 2.56V AREF AREF ADMUX MUX ADC GND ADC ADCSRA ADEN ADC ADEN ADEN ADC ADC ADC10 ADCADCHADCL ADMUX ADLAR 8 ADCH ADCL ADCH ADCL ADC ADCL
184
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
ADCH ADC ADCH ADC ADCH ADCL ADC ADCHADCLADC
ADC ADSC "1" ADC ADC ADC ADC ADC ADCSRA ADSC 1 ADC ADC ADIF
ADC
Figure 91. ADC
ADEN START CK Reset 7-BIT ADC PRESCALER
ADPS0 ADPS1 ADPS2
ADC CLOCK SOURCE
50 kHz 200 kHz 10 200 kHz ADC 100 kHz CPU ADC ADCSRA ADPS ADCSRA ADEN ADC ADEN 1 ADEN ADCSRAADSC ADC 13 ADC ADC (ADCSRA ADEN ) 25 ADC ADC 1.5 ADC ADC 13.5 ADC ADC ADC ADIF ADSC ( ) ADSC ADC ADSC Table 73
CK/128
CK/16
CK/32
CK/64
CK/2
CK/4
CK/8
185
2486N-AVR-07/04
Figure 92. ADC ( )
First Conversion Next Conversion
Cycle Number
1
2
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
ADC Clock ADEN ADSC ADIF ADCH ADCL MSB of Result LSB of Result
MUX and REFS Update
Sample & Hold
Conversion Complete
MUX and REFS Update
Figure 93. ADC
One Conversion Next Conversion
Cycle Number ADC Clock ADSC ADIF ADCH ADCL
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
3
MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete
MUX and REFS Update
Figure 94. ADC
One Conversion 11 12 13 Next Conversion 1 2 3 4
Cycle Number ADC Clock ADSC ADIF ADCH ADCL
MSB of Result LSB of Result
Conversion Complete
Sample &Hold MUX and REFS Update
186
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Table 73. ADC
& ( ) 13.5 1.5 ( ) 25 13
ADMUXMUXnREFS1:0 CPU ADC (ADCSRA ADIF ) ADSC ADSC ADC ADMUX ADFR ADEN ADMUX ADMUX 1. ADFR ADEN 0 2. ADC 3. ADMUX ADC
187
2486N-AVR-07/04
ADC
ADSC ADC ADSC ADC
ADC
ADC(VREF)ADC VREF 0x3FF VREF AVCC 2.56V AREF AVCCADC 2.56V(VBG) AREF ADC AREF VREF AREF VREF AREF AREF AVCC 2.56V ADC
ADC
ADC CPUI/O ADC 1. ADC ADC 2. ADC ( ) CPU ADC 3. ADC ADCCPU ADC ADC CPU ADC ADC CPU ADC ADC ADEN
188
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 95. ADC ADCn ADC ( ) (S/H) ADC10 k S/H S/H (fADC/2) ADC Figure 95.
IIH ADCn 1..100 k CS/H= 14 pF IIL VCC/2
(EMI) 1. 2. Figure 96 AVCC LC VCC 3. ADC CPU 4. ADC[3..0] (ADC4 ADC5) ADC4 ADC5 ADC
189
2486N-AVR-07/04
Figure 96. ADC
PC4 (ADC4/SDA) PC5 (ADC5/SCL)
PC1 (ADC1)
PC0 (ADC0) ADC7 GND AREF ADC6 AVCC
10H
Ideal ADC Actual ADC
PB5
ADC
n ADC GND VREF 2n (LSBs) 0 2n-1 * (0x000 0x001) (0.5 LSB) 0 LSB
Figure 97.
Output Code
Offset Error
VREF Input Voltage
190
ATmega8(L)
2486N-AVR-07/04
100nF
Analog Ground Plane
PC3 (ADC3)
GND
VCC
PC2 (ADC2)
ATmega8(L)
* (0x3FE 0x3FF) ( 1.5 LSB) 0 LSB
Figure 98.
Output Code Gain Error
Ideal ADC Actual ADC
VREF Input Voltage
*
(INL) INL0 LSB
Figure 99. (INL)
Output Code
*
(DNL) ( ) (1 LSB) 0 LSB
INL
Ideal ADC Actual ADC
VREF
Input Voltage
191
2486N-AVR-07/04
Figure 100. (DNL)
Output Code 0x3FF
1 LSB
DNL
0x000 0 VREF Input Voltage
* *
(1 LSB) 0.5 LSB ( ) 0.5 LSB
ADC
(ADIF ) ADC (ADCL, ADCH) V IN 1024 ADC = -------------------------V REF IN REF (P 192Table 74 P 193Table V V 75 ) 0x000 0x3FF 1LSB
ADC ADMUX
Bit / 7 REFS1 R/W 0 6 REFS0 R/W 0 5 ADLAR R/W 0 4 - R 0 3 MUX3 R/W 0 2 MUX2 R/W 0 1 MUX1 R/W 0 0 MUX0 R/W 0 ADMUX
* Bit 7:6 - REFS1:0: Table 74 (ADCSRA ADIF ) AREF Table 74. ADC
REFS1 0 0 1 1 REFS0 0 1 0 1 AREF Vref AVCC AREF 2.56V AREF
*
Bit 5 - ADLAR: ADC
192
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
ADLARADCADC ADLAR ADLAR ADC P 195"ADC ADCL ADCH" * Bits 3:0 - MUX3:0: ADC Table 75 (ADCSRA ADIF ) Table 75.
MUX3..0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1.23V (VBG) 0V (GND) ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7
193
2486N-AVR-07/04
ADC A ADCSRA
Bit /
7 ADEN R/W 0
6 ADSC R/W 0
5 ADFR R/W 0
4 ADIF R/W 0
3 ADIE R/W 0
2 ADPS2 R/W 0
1 ADPS1 R/W 0
0 ADPS0 R/W 0 ADCSRA
* Bit 7 - ADEN: ADC ADENADC ADC ADC * Bit 6 - ADSC: ADC ADSC ADC ADSC ( ADC ADSC ADC ADSC) 25 ADC 13 ADC ADSC "1"ADSC * Bit 5 - ADFR: ADC ADC * Bit 4 - ADIF: ADC ADC ADIF ADIE SREG I ADC ADIF 1 ADIF ADCSRA SBI CBI * Bit 3 - ADIE: ADC ADIE SREG I ADC
194
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
* Bits 2:0 - ADPS2:0: ADC XTAL ADC Table 76. ADC
ADPS2 0 0 0 0 1 1 1 1 ADPS1 0 0 1 1 0 0 1 1 ADPS0 0 1 0 1 0 1 0 1 2 2 4 8 16 32 64 128
ADC ADCL ADCH ADLAR = 0
Bit 15 - ADC7 7 R R 0 0 14 - ADC6 6 R R 0 0 13 - ADC5 5 R R 0 0 12 - ADC4 4 R R 0 0 11 - ADC3 3 R R 0 0 10 - ADC2 2 R R 0 0 9 ADC9 ADC1 1 R R 0 0 8 ADC8 ADC0 0 R R 0 0 ADCH ADCL
ADLAR = 1
Bit
15 ADC9 ADC1 7
14 ADC8 ADC0 6 R R 0 0
13 ADC7 - 5 R R 0 0
12 ADC6 - 4 R R 0 0
11 ADC5 - 3 R R 0 0
10 ADC4 - 2 R R 0 0
9 ADC3 - 1 R R 0 0
8 ADC2 - 0 R R 0 0 ADCH ADCL

R R 0 0
ADC 2 ADCL ADC ADCH 8 ADCH ADCL ADCH ADMUX ADLAR MUXn ADLAR 1 ( ) * ADC9:0: ADC ADC P 192"ADC "
195
2486N-AVR-07/04
(RWW, Read-WhileWrite)
Boot Loader MCU - (ReadWhile-Write RWW) MCU Flash Boot Loader Boot Loader ( ) Flash Boot Loader Flash Boot Loader Boot Loader Boot Loader Boot Loader * * * * * * *
RWW Boot ( Boot ) (1) RWW 1. Flash ( P 213Table 93 )
Note:
Flash Flash Boot Loader ( Figure 102) BOOTSZ P 207Table 82 Figure 102 Flash
Flash Boot (Boot 0) P 199Table 78 SPM Boot Loader Boot Loader BLS BLS SPM SPM Flash BLS Boot Loader Boot Loader (Boot 1) P 199Table 79 CPU RWW CPU Boot Loader BOOTSZ Flash ---- - (RWW) - (NRWW) RWW NRWW P 207Table 83 P 198Figure 102 * * RWW NRWW NRWW CPU
(Boot Loader Section) BLS
RWW Flash RWW Flash
Boot Loader RWW "RWW " ( ) Boot Loader RWW Boot Loader RWW Flash NRWW Flash RWW RWW ( call/jmp/lpm ) Boot Loader Boot Loader NRWW RWW (SPMCSR) RWW RWWSB RWW RWWSB RWWSBP 200 "SPMCR"
196
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
RWW NRWW Boot Loader RWW NRWW Boot Loader NRWW CPU Table 77. RWW
Z ? RWW NRWW ? NRWW CPU ? RWW ?
Figure 101. RWW NRWW
Read-While-Write (RWW) Section
Z-pointer Addresses RWW section
Z-pointer Addresses NRWW section
No Read-While-Write (NRWW) Section
CPU is Halted during the Operation Code Located in NRWW Section Can be Read during the Operation
197
2486N-AVR-07/04
Figure 102. (1)
Program Memory BOOTSZ = '11' $0000
Read-While-Write Section Read-While-Write Section
Program Memory BOOTSZ = '10' $0000
Application Flash Section
Application Flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend Program Memory BOOTSZ = '00'
Boot Loader Flash Section
End Application Start Boot Loader Flashend
Program Memory BOOTSZ = '01' $0000
Read-While-Write Section Read-While-Write Section
$0000
Application Flash Section
Application flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend
No Read-While-Write Section
End RWW, End Application Start NRWW, Start Boot Loader
Boot Loader Flash Section
Flashend
Note:
1. P 207Table 82
Boot Loader Flash Boot Loader Boot * * * * Flash MCU MCU Boot Loader Flash MCU Flash MCU Flash
Table 78 Table 79 Boot ( 2) SPM Flash / ( 3) LPM/SPM Flash /
198
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Table 78. Boot 0 ( )(1)
BLB0 1 2 BLB02 1 1 BLB01 1 0 SPM/LPM SPM SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader
3
0
0
4 Note:
0
1
1. "1" "0"
Table 79. Boot 1 (Boot Loader )(1)
BLB1 1 2 BLB12 1 1 BLB11 1 0 SPM/LPM Boot Loader SPM Boot Loader SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader Boot Loader
3
0
0
4 Note:
0
1
1. "1" "0"
Boot Loader USART SPI Boot Boot Boot Loader MCU Boot Boot
199
2486N-AVR-07/04
Table 80. Boot (1)
BOOTRST 1 0 Note: = ( 0x0000) =Boot Loader ( P 207Table 82 )
1. "1" , "0"
SPMCR
Boot Loader
Bit / 7
SPMIE
6
RWWSB
5
-
4
RWWSRE
3
BLBSET
2
PGWRT
1
PGERS
0
SPMEN SPMCR
R/W 0
R 0
R 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
* Bit 7 - SPMIE: SPM SPMIE I SPM SPMCSR SPMEN SPM * Bit 6 - RWWSB:RWW RWW ( ) RWWSB 1 RWWSB RWW RWWSRE 1 RWWSB RWWSB * Bit 5 - Res: ATmega8 "0" * Bit 4 - RWWSRE:RWW RWW() RWW(RWWSB"1") (SPMEN)RWW RWWSRE SPMEN"1" SPMRWW Flash (SPMEN ),RWW Flash RWWSRE Flash * Bit 3 - BLBSET: Boot SPMEN SPM R0 Boot R1 Z SPM BLBSET SPMCSR BLBSET SPMEN LPM ( Z Z0) P 204" " * Bit 2 - PGWRT: SPMEN SPM Flash Z R1 R0 SPM PGWRT NRWW CPU * Bit 1 - PGERS: SPMEN SPM Z R1 R0 SPM PGERS NRWW CPU * Bit 0 - SPMEN:
200
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
SPM RWWSRE BLBSET PGWRT PGERS SPM SPMEN SPM R1:R0 Z LSB Z SPM SPM SPMEN SPMEN 1 "10001" "01001" "00101" "00011" "00001"
Flash
Z SPM
Bit ZH (R31) ZL (R30) 15 Z15 Z7 7 14 Z14 Z6 6 13 Z13 Z5 5 12 Z12 Z4 4 11 Z11 Z3 3 10 Z10 Z2 2 9 Z9 Z1 1 8 Z8 Z0 0
Flash ( P 213Table 93 ) Figure 103 Boot Loader Z Z SPM Boot Loader Z LPM Z Z LSB ( Z0) Figure 103. SPM (1)
BIT Z - REGISTER PCMSB PROGRAM COUNTER
PCPAGE
15
ZPCMSB
ZPAGEMSB
10 0
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Notes:
1. P 208Table 84 2. PCPAGE PCWORD P 213Table 93
201
2486N-AVR-07/04
Flash
SPM 1 * * * * * *
2
( ) Flash 1 Boot Loader - Flash 2 P 206" " SPM Z RAMPZ "X0000011" SPMCSR SPMR1 R0 Z PCPAGE Z * * ( ) RWW NRWW NRWW CPU
Z R1:R0 "00000001" SPMCSR SPM Z PCWORD SPMCSR RWWSRE
Note: EEPROM SPM
Z RAMPZ "X0000101" SPMCSR SPMR1 R0 Z PCPAGE Z * * RWW NRWW NRWW CPU
SPM
SPM SPMCSR SPMEN SPMCSR SPM BLS RWW P 43" " Boot 11 Boot Loader Boot Loader Boot Loader Boot Loader Boot 11 Boot Loader ( ) RWW RWW SPMCSR RWWSB P 43" " BLS RWW
BLS
RWW
202
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
RWWSRE 1 RWWSB P 206" "
203
2486N-AVR-07/04
SPM
Boot Loader R0 "X0001001"SPMCSR SPM Boot Loader MCU Boot Loader
Bit R0 7 1 6 1 5 BLB12 4 BLB11 3 BLB02 2 BLB01 1 1 0 1
Boot Loader Flash Table 78 Table 79 R0 5..2 0 SPMCSR BLBSET SPMEN SPM Boot Z Z 0x0001( lOck ) R0 7 6 1 0 "1" Flash EEPROM SPMCR EEPROM Flash SPMCR EECR EEWE 0x0001 Z SPMCSR BLBSET SPMEN SPMCR CPU LPM CPU LPM CPU SPM BLBSET SPMEN BLBSET SPMEN LPM
Bit Rd 7 - 6 - 5 BLB12 4 BLB11 3 BLB02 2 BLB01 1 LB2 0 LB1
0x0000ZSPMCRBLBSET SPMEN SPMCSR CPU LPM (FLB) P 210Table 88
Bit Rd 7 FLB7 6 FLB6 5 FLB5 4 FLB4 3 FLB3 2 FLB2 1 FLB1 0 FLB0
0x0003 Z SPMCR BLBSET SPMEN SPMCSR CPU LPM (FHB) P 210Table 87
Bit Rd 7 FHB7 6 FHB6 5 FHB5 4 FHB4 3 FHB3 2 FHB2 1 FHB1 0 FHB0
"0" "1" Flash VCC CPU Flash Flash Flash Flash Flash CPU Flash ( )
204
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
1. Boot Loader Boot Loader Boot Loader 2. AVR RESET BOD 3. AVR CPU SPMCR Flash SPM Flash RC Flash Table 81 CPU Flash Table 81. SPM
Flash ( SPM ) 3.7 ms 4.5 ms
205
2486N-AVR-07/04
;- RAM Flash ; Y RAM ;Z Flash ;- ;- Boot ( Do_spm ) ; ( ) NRWW ;- r0 r1 temp1 (r16) temp2 (r17) looplo (r24) ; loophi (r25) spmcrval (r20) ; ; ;- Boot loader , .equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB
.org SMALLBOOTSTART Write_page: ; ldi spmcrval, (1<;
; ;PAGESIZEB<=256
;PAGESIZEB<=256 subi
subi sbci ldi rcall
ZL, low(PAGESIZEB) ; ZH, high(PAGESIZEB) ;PAGESIZEB<=256 spmcrval, (1<; RWW ldi spmcrval, (1<; ;PAGESIZEB<=256 ;
;PAGESIZEB<=256 subi
206
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Return: in temp1, SPMCR sbrs temp1, RWWSB ; RWWSB "1" RWW ret ; RWW ldi spmcrval, (1<;
in temp2, SREG cli ; EEPROM Wait_ee: sbic EECR, EEWE rjmp Wait_ee ; SPM out SPMCR, spmcrval spm ; SREG ( ) out SREG, temp2 ret
ATmega8
Table 82 Table 84 Table 82. Boot
Boot 128 256 512 102 Boot Loader Flash 0xF80 0xFFF 0xF00 0xFFF 0xE00 0xFFF 0xC00 0xFFF Boot ( Boot Loader ) 0xF80 0xF00 0xE00 0xC00
BOOTSZ1 1 1 0 0
BOOTSZ0 1 0 1 0
4 8 16 32
Flash 0x000 0xF7F 0x000 0xEFF 0x000 0xDFF 0x000 0xBFF
0xF7F 0xEFF 0xDFF 0xBFF
Note:
BOOTSZ Figure 102
Table 83. RWW
Flash - (RWW) - (NRWW) 96 32 0x000 - 0xBFF 0xC00 - 0xFFF
207
2486N-AVR-07/04
P 197" RWW NRWW" P 196"RWW "
Table 84. Figure 103 Z
PCMSB PAGEMSB ZPCMSB ZPAGEMSB PCPAGE PCWORD Note: PC[11:5] PC[4:0] 11 4 Z12 Z5 Z12:Z6 Z5:Z1 Z (1) ( 12 PC[11:0]) ( 64 5 PC [4:0]) Z PCMSB Z0 ZPCMSB PCMSB + 1 Z PAGEMSB Z0 ZPAGEMSB PAGEMSB + 1 ( 0)
1. Z15:Z13 Z0 SPM "0" LPM Z P 201" Flash"
208
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
ATmega8 6 ("0") ("1") Table 86 "1" Table 85.
7 6 BLB12 BLB11 BLB02 BLB01 LB2 LB1 Note: 5 4 3 2 1 0 - - Boot Boot Boot Boot (1) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( )
1. "1" "0"
Table 86. (2)
LB 1 2 3 BLB0 1 2 LB2 1 1 0 BLB02 1 1 LB1 1 0 0 BLB01 1 0 SPM LPM SPM SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader SPM/LPM Boot Loader Flash EEPROM (1) Flash EEPROM (1)
3
0
0
4 BLB1 1
0 BLB12 1
1 BLB11 1
209
2486N-AVR-07/04
Table 86. (2)
2 1 0 SPM Boot Loader SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader Boot Loader
3
0
0
4 Notes:
0
1
1. 2. "1" , "0"
ATmega8 Table 87-Table 88 "0" Table 87.
RSTDISBL(4) WDTON SPIEN(1) CKOPT(2) EESAVE BOOTSZ1 BOOTSZ0 BOOTRST Notes: 1. 2. 3. 4. 7 6 5 4 3 2 1 0 PC6 I/O RESET WDT EEPROM Boot ( Table 82) Boot ( Table 82 ) 1 ( PC6 RESET ) 1 ( WDTCR WDT ) 0 ( SPI ) 1 ( ) 1 ( EEPROM ) 0 ( )(3) 0 ( )(3) 1 ( )
SPI SPIEN CKOPT CKSEL P 23 " " BOOTSZ1..0 Boot P 207Table 82 RSTDISBL
Table 88.
BODLEVEL BODEN SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 7 6 5 4 3 2 1 0 BOD BOD 1 ( ) 1 ( BOD ) 1 ( )(1) 0 ( )(1) 0 ( )(2) 0 ( )(2) 0 ( )(2) 1 ( )(2)
210
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Notes: 1. SUT1..0 P 27Table 10 2. CKSEL3..0RC1 MHz P 23Table 2
1(LB1) EESAVE Atmel ATmega8 1. 0x000: 0x1E ( Atmel ) 2. 0x001: 0x93 ( 8 KB Flash ) 3. 0x002: 0x07 ( ATmega8)
ATmega8RC 0x000 0x0001 0x0002 0x0003 1 2 4 8 MHz 1 MHz OSCCAL P 28 " OSCCAL"
211
2486N-AVR-07/04
ATmega8 Flash EEPROM 250 ns
ATmega8 Figure 104 Table 89 XA1/XA0 XTAL1 Table 91 WR OE Table 92 Figure 104.
+5V RDY/BSY OE WR BS1 XA0 XA1 PAGEL +12 V BS2 PD1 PD2 PD3 PD4 PD5 PD6 PD7 RESET PC2 XTAL1 GND AVCC
PC[1:0]:PB[5:0]
VCC +5V
DATA
Table 89.
RDY/BSY OE WR BS1 XA0 XA1 PAGEL BS2 DATA PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC2 {PC[1:0]: PB[5:0]} I/O O I I I I I I I I/O 0: , 1: ( ). ( ). 1("0" , "1" ). XTAL 0 XTAL 1 EEPROM 2("0" , "1" ) (OE )
212
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Table 90.
PAGEL XA1 XA0 BS1 Prog_enable[3] Prog_enable[2] Prog_enable[1] Prog_enable[0] 0 0 0 0
Table 91. XA1 XA0
XA1 0 0 1 1 XA0 0 1 0 1 XTAL1 Flash EEPROM ( BS1 ) ( BS1 )
Table 92.
1000 0000 0100 0000 0010 0000 0001 0000 0001 0001 0000 1000 0000 0100 0000 0010 0000 0011 Flash EEPROM Flash EEPROM
Table 93. Flash
Flash 4K (8K ) 32 PCWORD PC[4:0] 128 PCPAGE PC[11:5] PCMSB 11
Table 94. EEPROM
EEPROM 512 4 PCWORD EEA[1:0] 128 PCPAGE EEA[8:2] EEAMSB 8

213
2486N-AVR-07/04
1. VCC GND 4.5 - 5.5V 100 s 2. RESET XTAL1 6 3. P 213Table 90 Prog_enable "0000" 100 ns 4. RESET 11.5 - 12.5V RESET +12V 100 ns Prog_enable RSTDISBL RESET RC XTAL1 1. P 213Table 90 Prog_enable "0000" 2. VCC GND 4.5 - 5.5V RESET 11.5 - 12.5V 3. 100 ns 4. (CKSEL3:0 = 0b0000) 5. RESET 0b0 6. * * * 0xFF Flash EEPROM( EESAVE ) Flash EEPROM 256
Flash EEPROM(1) Flash / EEPROM
Note: 1. EESAVE EEPRPOM
" " 1. XA1 XA0 "10" 2. BS1 "0" 3. DATA "1000 0000" 4. XTAL1 5. WR RDY/BSY 6. RDY/BSY Flash Flash P 213Table 93 Flash Flash A. " Flash" 1. XA1 XA0 "10" 2. BS1 "0" 3. DATA "0001 0000" Flash 4. XTAL1 B. 1. XA1 XA0 "00" 2. BS1 "0"
214
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
3. DATA (0x00 - 0xFF) 4. XTAL1 C. 1. XA1 XA0 "01" 2. DATA (0x00 - 0xFF) 3. XTAL1 D. 1. BS1 "1" 2. XA1 XA0 "01" 3. DATA (0x00 - 0xFF) 4. XTAL1 E. 1. BS1 "1" 2. PAGEL ( Figure 106 ) F. B E FLASH P 216Figure 105 8 ( < 256) G. 1. XA1 XA0 "00" 2. BS1 "1" 3. DATA (0x00 - 0xFF) 4. XTAL1 H. 1. BS1 = "0" 2. WR RDY/BSY 3. RDY/BSY ( Figure 106 ) I. B H Flash J. 1. XA1 XA0 "10" 2. DATA "0000 0000" 3. XTAL1
215
2486N-AVR-07/04
Figure 105. Flash (1)
PCMSB PROGRAM COUNTER
PCPAGE
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Note:
1. PCPAGE PCWORD P 213Table 93
Figure 106. Flash (1)
F
A
DATA 0x10
B
ADDR. LOW
C
DATA LOW
D
DATA HIGH
E
XX
B
ADDR. LOW
C
DATA LOW
D
DATA HIGH
E
XX
G
ADDR. HIGH
H
XX
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Note:
1. "XX" Flash
EEPROM
P 213Table 94 EEPROM EEPROM EEPROM ( P 214" Flash " )
216
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
1. A "0001 0001" 2. G (0x00 - 0xFF) 3. B (0x00 - 0xFF) 4. C (0x00 - 0xFF) 5. E ( PAGEL ) K 3 5 L EEPROM 1. BS1 "0" 2. WR EEPROM RDY/BSY 3. RDY/BSY ( Figure 107 ) Figure 107. EEPROM
K
A
DATA
0x11
G
ADDR. HIGH
B
ADDR. LOW
C
DATA
E
XX
B
ADDR. LOW
C
DATA
E
XX
L
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Flash
Flash ( P 214" Flash " ) 1. A "0000 0010" 2. G (0x00 - 0xFF) 3. B (0x00 - 0xFF) 4. OE "0" BS1 "0" DATA Flash 5. BS1 "1" DATA Flash 6. OE "1"
EEPROM
( P 214" Flash " ) 1. A "0000 0011" 2. G (0x00 - 0xFF) 3. B (0x00 - 0xFF) 4. OE "0" BS1 "0" DATA EEPROM
217
2486N-AVR-07/04
5. OE "1" ( P 214" Flash " ) 1. A "0100 0000" 2. C "0" 3. BS1 "0" BS2 "0" 4. WR RDY/BSY
218
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
( P 214" Flash " ) 1. A "0100 0000" 2. C "0" 3. BS1 "1" BS2 "0" 4. WR RDY/BSY 5. BS1 "0" ( P 214" Flash " ) 1. A "0010 0000" 2. C n "0" 3. WR RDY/BSY ( P 214" Flash " ) 1. A "0000 0100" 2. OE BS2 BS1 "0" DATA ("0" ) 3. OE "0" BS2 BS1 "1" DATA ("0" ) 4. OE "0" BS2 "0" BS1 "1" DATA ("0" ) 5. OE "1" Figure 108. BS1 BS2
Fuse low byte
0 DATA
Lock bits
0 1
Fuse high byte
1
BS1
BS2
219
2486N-AVR-07/04
( P 214" Flash " ) 1. A "0000 1000" 2. B 0x00 - 0x02 3. OE BS1 "0" DATA 4. OE "1"
( P 214" Flash " ) 1. A "0000 1000" 2. B 3. OE "0" BS1 "1" DATA 4. OE "1"
Figure 109.
t XLWL XTAL1 t DVXH Data & Contol (DATA, XA0/1, BS1, BS2) t BVPH PAGEL WR RDY/BSY t WLRH t PHPL t WL t PLWL
WLRL WH
t XHXL t XLDX
t PLBX
t BVWL
t WLBX
Figure 110. (1)
LOAD ADDRESS (LOW BYTE) LOAD DATA (LOW BYTE)
t XLXH
LOAD DATA LOAD DATA (HIGH BYTE)
tXLPH tPLXH
LOAD ADDRESS (LOW BYTE)
XTAL1
BS1
PAGEL
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. Figure 109 (tDVXH tXHXL tXLDX)
220
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 111. ( )(1)
LOAD ADDRESS (LOW BYTE)
tXLOL
READ DATA (LOW BYTE)
READ DATA (HIGH BYTE)
LOAD ADDRESS (LOW BYTE)
XTAL1
tBVDV
BS1
tOLDV
OE
tOHDZ
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. Figure 109 ( tDVXH tXHXL tXLDX)
Table 95. VCC = 5V 10%
VPP IPP tDVXH tXLXH tXHXL tXLDX tXLWL tXLPH tPLXH tBVPH tPHPL tPLBX tWLBX tPLWL tBVWL tWLWH tWLRL tWLRH tWLRH_CE tXLOL XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 WR XTAL1 PAGEL PAGEL XTAL1 PAGEL BS1 PAGEL PAGEL BS1 WR BS2/1 PAGEL WR BS1 WR WR WR RDY/BSY WR RDY/BSY (1) WR RDY/BSY XTAL1 OE
(2)
11.5

12.5 250
V A ns ns ns ns ns ns ns ns ns ns ns ns ns ns
67 200 150 67 0 0 150 67 150 67 67 67 67 150 0 3.7 7.5 0 1 4.5 9
s ms ms ns
221
2486N-AVR-07/04
Table 95. VCC = 5V 10% (Continued)
tBVDV tOLDV tOHDZ Notes: 1. 2. BS1 DATA OE DATA OE DATA Flash EEPROM tWLRH tWLRH_CE 0 250 250 250 ns ns ns
RESET SPI Flash EEPROM SCK MOSI( ) MISO( ) RESET P 222Table 96 SPI SPI SPI
Table 96.
MOSI MISO SCK PB3 PB4 PB5 I/O I O I
Figure 112. (1)
+2.7 - 5.5V VCC
MOSI MISO SCK
PB3 PB4 PB5 XTAL1 AVCC
+2.7 - 5.5V (2)
RESET
GND
Notes:
1. XTAL1 2. VCC - 0.3V < AVCC < VCC + 0.3V AVCC 2.7 - 5.5V
EEPROM MCU EEPROM 0xFF CKSEL (SCK) fck < 12 MHz 2 CPU fck 12 MHz 3 CPU > fck < 12 MHz 2 CPU fck 12 MHz 3 CPU > 222 ATmega8 SCK
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
ATmega8 SCK Figure 113 ATmega8 ( Table 98 4 ) 1. RESET SCK "0" VCC GND SCK SCK RESET 2 CPU 2. 20 ms MOSI 3. (0x53) 4 0x53 RESET 4. Flash P 213Table 93 5 LSB 7 tWD_FLASH ( Table 97) 5. EEPROM EEPROM tWD_EEPROM ( Table 97) 0xFF 6. MISO 7. RESET 8. ( ) RESET "1" VCC
223
2486N-AVR-07/04
Flash
Flash 0xFF Flash 0xFF 0xFF tWD_FLASH 0xFF 0xFF tWD_FLASH Table 97 EEPROM 0xFF 0xFF 0xFF 0xFF EEPROM 0xFF tWD_EEPROM tWD_EEPROM Table 97 Table 97. Flash EEPROM
tWD_FUSE tWD_FLASH tWD_EEPROM tWD_ERASE 4.5 ms 4.5 ms 9.0 ms 9.0 ms
EEPROM
Figure 113.
SERIAL DATA INPUT (MOSI) SERIAL DATA OUTPUT (MISO) SERIAL CLOCK INPUT (SCK)
SAMPLE
MSB
LSB
MSB
LSB
224
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Table 98.
1 1010 1100 1010 1100 0010 H000 0100 H000 2 0101 0011 100x xxxx 0000 aaaa 0000 xxxx 3 xxxx xxxx xxxx xxxx bbbb bbbb xxxb bbbb 4 xxxx xxxx xxxx xxxx oooo oooo iiii iiii RESET EEPROM Flash a:b H( ) o b H( ) i a:b EEPROM a:b o EEPROM a:b i "0" "1" P 209Table 85 "0" P 209Table 85 b o "0" "1" P 210Table 88 "0" "1" P 210Table 87 "0" "1" P 210Table 88 "0" "1" P 210Table 87
EEPROM EEPROM
0100 1100 1010 0000 1100 0000 0101 1000 1010 1100 0011 0000 1010 1100 1010 1100 0101 0000
0000 aaaa 00xx xxxa 00xx xxxa 0000 0000 111x xxxx 00xx xxxx 1010 0000 1010 1000 0000 0000
bbbx xxxx bbbb bbbb bbbb bbbb xxxx xxxx xxxx xxxx xxxx xxbb xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx oooo oooo iiii iiii xxoo oooo 11ii iiii oooo oooo iiii iiii iiii iiii oooo oooo
Note:
0101 1000
0000 1000
xxxx xxxx
oooo oooo
0011 1000
00xx xxxx
0000 00bb
oooo oooo
a = b = H =0 - 1 - o = i = x =
SPI
SPI P 230"SPI "
225
2486N-AVR-07/04
Note: AVR
*
........................................................ -55C +125C ........................................................ -65C +150C RESET............ -0.5V VCC+0.5V RESET .................................. -0.5V +13.0V .................................................................... 6.0V I/O ......................................... 40.0 mA *NOTICE: " "
VCC GND ................................ 200.0 mA
TA = -40C 85C VCC = 2.7V 5.5V ( )
VIL VIL1 VIH VIH1 VIH2 VOL VOH IIL IIH RRST Rpu ( A,B,C,D)
(3)
XTAL1 XTAL1 XTAL1 RESET XTAL1 RESET IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V IOH = -20 mA, VCC = 5V IOH = -10 mA, VCC = 3V VCC = 5.5V, ( ) VCC = 5.5V, ( )
-0.5 -0.5 0.6 0.8 VCC(2) VCC(2)

0.2 VCC(1) 0.1 VCC(1) VCC + 0.5 VCC + 0.5 VCC + 0.5 0.7 0.5
V V V V V V V V V
0.9 VCC(2)
( A,B,C,D) I/O I/O Reset I/O
4.2 2.2 1 1 30 20 80 50
A A k k
226
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
TA = -40C 85C VCC = 2.7V 5.5V ( )
4 MHz, VCC = 3V (ATmega8L) 8 MHz, VCC = 5V (ATmega8) 4 MHz, VCC = 3V (ATmega8L) 8 MHz, VCC = 5V (ATmega8) (5) VACIO IACLK tACID Notes: WDT , VCC = 3V WDT , VCC = 3V VCC = 5V Vin = VCC/2 VCC = 5V Vin = VCC/2 VCC = 2.7V VCC = 4.0V -50 750 500 5 15 2 7 28 3 20 50 mA mA mA mA A A mV nA ns
ICC
1. " " 2. " " 3. ()I/O(20 mA CC = 5V 10 mAVCC = 3V) V PDIP 1] IOL 400 mA 2] C0 - C5 IOL 200 mA 3] B0 - B7 C6 D0 - D7 XTAL2 IOL 100 mA TQFP MLF 1] IOL 400 mA 2] C0 - C5 IOL 200 mA 3] C6 D0 - D4 IOL 300 mA 4] B0 - B7 D5 - D7 IOL 300 mA IOL VOL 4. ()I/O(20 mA CC = 5V 10 mAVCC = 3V) V PDIP 1] IOH 400 mA 2] C0 - C5 IOH 100 mA 3] B0 - B7 C6 D0 - D7 XTAL2 IOH 100 mA TQFP MLF 1] IOH 400 mA 2] C0 - C5 IOH 200 mA 3] C6 D0 - D4 IOH 300 mA 4] B0 - B7 D5 - D7 IOH 300 mA IOH VOH 5. VCC 2.5V
227
2486N-AVR-07/04
Figure 114.
V IH1 V IL1
Table 99.
VCC = 2.7V - 5.5V 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL 0 125 50 50 1.6 1.6 2 8 VCC = 4.5V - 5.5V 0 62.5 25 25 0.5 0.5 2 16 MHz ns ns ns s s %
tCLCL
Table 100. RC
R [k](1) 100 33 10 Notes: C [pF] 47 22 22 f(2) 87 kHz 650 kHz 2.0 MHz
1. R 3 k - 100 k 20 pF C C C 2.
228
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Table 101 ATmega8 Figure 115 Table 101.
VIL VIH Vhys VOL tr(1) tof(1) tSP(1) Ii Ci(1) fSCL
(1) (1)
SDA SCL VIHmin VILmax I/O I/O SCL
-0.5 0.7 VCC 0.05 VCC 3 mA 0 20 + 0.1Cb
(3)(2) (2)
0.3 VCC VCC + 0.5 - 0.4 300 250 50
(2)
V V V V ns ns ns A pF kHz s s s s s s s s s s ns ns s s s s
10 pF < Cb < 400 pF(3) 0.1VCC < Vi < 0.9VCC fCK(4) > max(16fSCL, 250kHz)(5) fSCL 100 kHz
20 + 0.1Cb(3)(2) 0 -10 - 0 V CC - 0,4V ----------------------------3mA V CC - 0,4V ----------------------------3mA 4.0 0.6 4.7 1.3 4.0 0.6 4.7 0.6 0 0 250 100 4.0 0.6 4.7 1.3
10 10 400 1000ns -----------------Cb 300ns --------------Cb - - - - - - - - 3.45 0.9 - - - - - -
Rp
fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz
(6)
tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF Notes: 1. 2. 3. 4.
START ( ) SCL SCL STARTS STOP
fSCL > 100 kHz(7) fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz
STOP START
ATmega8 100% fSCL > 100 kHz Cb = fCK = CPU
229
2486N-AVR-07/04
5. ATmega8 fSCL 6. ATmega8 (1/fSCL - 2/fCK) fSCL = 100 kHz fCK 6 MHz 7. ATmega8 (1/fSCL - 2/fCK) fCK = 8 MHz fSCL > 308 kHz ATmega8 ATmega8(400 kHz) tLOW
Figure 115.
tof tLOW SCL tSU;STA SDA tHD;STA tHD;DAT tSU;DAT tSU;STO tHIGH tLOW tr
tBUF
SPI
Figure 116 Figure 117 Table 102. SPI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Note: SCK SCK / / SCK SCK SCK SS SCK SCK / / SCK SCK SS SS SS SCK 2 * tck 20 10 10 10 15 4 * tck 2 * tck 1.6 Table 50 50% 3.6 10 10 0.5 * tSCK 10 10 15 ns
1. SPI SCK / fCK < 12 MHz- 2tCLCL fCK > 12 MHz- 3tCLCL
230
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 116. SPI ( )
SS
6 1
SCK (CPOL = 0)
2 2
SCK (CPOL = 1)
4 5 3
MISO (Data Input)
MSB 7
...
LSB 8
MOSI (Data Output)
MSB
...
LSB
Figure 117. SPI ( )
18
SS
9 10 16
SCK (CPOL = 0)
11 11
SCK (CPOL = 1)
13 14 12
MOSI (Data Input)
MSB 15
...
LSB 17
MISO (Data Output)
MSB
...
LSB
X
231
2486N-AVR-07/04
Table 103. ADC
VREF = 4V, VCC = 4V ADC = 200 kHz VREF = 4V, VCC = 4V ADC = 1 MHz VREF = 4V, VCC = 4V ADC = 200 kHz VREF = 4V, VCC = 4V ADC = 200 kHz VREF = 4V, VCC = 4V ADC = 200 kHz VREF = 4V, VCC = 4V ADC = 200 kHz 13 50 VCC - 0.3(2) 2.0 GND 38.5 2.3 2.56 32 55 100 2.7 (1) (1) 10 1.75 (1) Bits LSB
( INL, DNL, , Gain, )
3
LSB
(INL)
0.75
LSB
(DNL)
0.5 1
LSB LSB
VINT RREF RAIN Notes: 1. 2. AVCC 2.7V 3. AVCC 5.5V
1
LSB
260 1000 VCC + 0.3(3)
s kHz V V V kHz V k M
AVCC
VREF VIN
AVCC
VREF
232
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
ATmega8
I/O I/O CL*VCC*f CL VCC f Figure 118. (0.1 - 1.0 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
0.1 - 1.0 MHz 3
2.5
2 ICC (mA)
1.5
5.5V 5.0V 4.5V 4.0V 3.3V 3.0V 2.7V
1
0.5
0 0 0.1 0.2 0.3 0.4 0.5 Frequency (MHz) 0.6 0.7 0.8 0.9 1
233
2486N-AVR-07/04
Figure 119. (1 - 20 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz 30
5.5V
25
5.0V 4.5V
20 ICC (mA)
15
10
3.3V 3.0V 2.7V
5
0 0 2 4 6 8 10 Frequency (MHz) 12 14 16 18 20
Figure 120. VCC ( RC 8 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 8 MHz 18 16 14 12 ICC (mA) 10 8 6 4 2 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
-40C 25C 85C
234
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 121. VCC ( RC 4 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 4 MHz 12
10
8 ICC (mA)
-40C 25C 85C
6
4
2
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 122. VCC ( RC 2 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 2 MHz 6
5
25C -40C 85C
4 ICC (mA)
3
2
1
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
235
2486N-AVR-07/04
Figure 123. VCC ( RC 1 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 1 MHz 3.5 3
25C
2.5 ICC (mA) 2 1.5 1 0.5 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
85C
-40C
Figure 124. VCC (32 kHz )
ACTIVE SUPPLY CURRENT vs. VCC
32kHz EXTERNAL OSCILLATOR 120
100
25C
80 ICC (uA)
60
40
20
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
236
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 125. (0.1 - 1.0 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
0.1 - 1.0 MHz 0.7
5.5V
0.6 0.5 ICC (mA) 0.4 0.3 0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 Frequency (MHz) 0.6 0.7 0.8 0.9 1
5.0V 4.5V 4.0V 3.3V 3.0V 2.7V
Figure 126. (1 - 20 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz 14 12 10 ICC (mA) 8 6 4 2
5.5V
5.0V 4.5V
4.0V 3.3V 3.0V 2.7V
0 0 2 4 6 8 10 Frequency (MHz) 12 14 16 18 20
237
2486N-AVR-07/04
Figure 127. VCC ( RC 8 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 8 MHz 8 7 6 5 ICC (mA) 4 3 2 1 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
-40C 25C 85C
Figure 128. VCC ( RC 4 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 4 MHz 4 3.5 3 2.5 ICC (mA) 2 1.5 1 0.5 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
-40C 25C 85C
238
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 129. VCC ( RC 2 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 2 MHz 1.8 1.6 1.4 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
-40C 85C 25C
Figure 130. VCC ( RC 1 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 1 MHz 1 0.9 0.8 0.7 ICC (mA) 0.6 0.5 0.4 0.3 0.2 0.1 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
85C 25C -40C
239
2486N-AVR-07/04
Figure 131. VCC (32 kHz )
IDLE SUPPLY CURRENT vs. VCC
32kHz EXTERNAL OSCILLATOR 40 35 30 25 ICC (uA) 20 15 10 5 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
25C
Figure 132. VCC ( )
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER DISABLED 2.5
85C
2
1.5 ICC (uA)
-40C 25C
1
0.5
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
240
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 133. VCC ( )
POWER-DOWN SUPPLY CURRENT vs. V CC
WATCHDOG TIMER ENABLED 80 70 60 50
85C 25C -40C
ICC (uA)
40 30 20 10 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 134. VCC ( )
POWER-SAVE SUPPLY CURRENT vs. V CC
WATCHDOG TIMER DISABLED 25
20
25C
15 ICC (uA) 10 5 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
241
2486N-AVR-07/04
Standby
Figure 135. Standby VCC (455 kHz )
STANDBY SUPPLY CURRENT vs. V CC
455 kHz RESONATOR, WATCHDOG TIMER DISABLED 80 70 60 50 ICC (uA) 40 30 20 10 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 136. Standby VCC (1 MHz )
STANDBY SUPPLY CURRENT vs. V CC
1 MHz RESONATOR, WATCHDOG TIMER DISABLED 70 60 50 40 30 20 10 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
242
ATmega8(L)
2486N-AVR-07/04
ICC (uA)
ATmega8(L)
Figure 137. Standby VCC (2 MHz )
STANDBY SUPPLY CURRENT vs. V CC
2 MHz RESONATOR, WATCHDOG TIMER DISABLED 90 80 70 60 ICC (uA) 50 40 30 20 10 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 138. Standby VCC (2 MHz Xtal )
STANDBY SUPPLY CURRENT vs. V CC
2 MHz XTAL, WATCHDOG TIMER DISABLED 90 80 70 60 ICC (uA) 50 40 30 20 10 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
243
2486N-AVR-07/04
Figure 139. Standby VCC (4 MHz )
STANDBY SUPPLY CURRENT vs. V CC
4 MHz RESONATOR, WATCHDOG TIMER DISABLED 140 120 100 80 60 40 20 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 140. Standby VCC (4 MHz Xtal )
ICC (uA)
STANDBY SUPPLY CURRENT vs. V CC
4 MHz XTAL, WATCHDOG TIMER DISABLED 140 120 100 80 60 40 20 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
244
ATmega8(L)
2486N-AVR-07/04
ICC (uA)
ATmega8(L)
Figure 141. Standby VCC (6 MHz )
STANDBY SUPPLY CURRENT vs. V CC
6 MHz RESONATOR, WATCHDOG TIMER DISABLED 160 140 120 100 ICC (uA) 80 60 40 20 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 142. Standby VCC (6 MHz Xtal )
STANDBY SUPPLY CURRENT vs. V CC
6 MHz XTAL, WATCHDOG TIMER DISABLED 200 180 160 140 120 ICC (uA) 100 80 60 40 20 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
245
2486N-AVR-07/04
Figure 143. I/O (VCC = 5V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 5V 160
85C
140 120
25C -40C
100
IIO (uA)
80 60 40 20 0 0 1 2 3 VOP (V) 4 5 6
Figure 144. I/O (VCC = 2.7V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 2.7V 90
85C
80 70 60
25C -40C
IIO (uA)
50 40 30 20 10 0 0 0.5 1 1.5 VOP (V) 2 2.5 3
246
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 145. (Reset) Reset (VCC = 5V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
Vcc = 5V 100
- 40C
80
25C 85C
IRESET (uA)
60
40
20
0 0 1 2 VRESET (V)
Figure 146. (Reset) Reset (VCC = 2.7V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
Vcc = 2.7V 45
-40C
40
25C
35 30 IRESET (uA) 25 20 15 10 5 0 0 0.5 1 VRESET (V) 1.5 2 2.5
85C
247
2486N-AVR-07/04
Figure 147. I/O (VCC = 5V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V 80
-40C
70
25C
60
85C
50 IOH (mA) 40 30 20 10 0 VOH (V)
Figure 148. I/O (VCC = 2.7V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V 30
25
-40C 25C 85C
20 IOH (mA)
15
10
5
0 0 0.5 1 1.5 VOH (V) 2 2.5 3
248
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 149. I/O (VCC = 5V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V 90 80 70 60
-40C 25C 85C
IOL (mA)
50 40 30 20 10 0 0 0.5 1 VOL (V) 1.5 2 2.5
Figure 150. I/O (VCC = 2.7V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V 35 30 25
-40C 25C 85C
IOL (mA)
20 15 10 5 0 0 0.5 1 VOL (V) 1.5 2 2.5
249
2486N-AVR-07/04
Figure 151. Reset I/O (VCC = 5V)
RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V 4 3.5
-40C
3
25C
Current (mA) 2.5
85C
2 1.5 1 0.5 0 2 2.5 3 VOH (V) 3.5 4 4.5
Figure 152. Reset I/O (VCC = 2.7V)
RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V 5 4.5
25C
4
-40C
3.5 Current (mA) 3 2.5 2 1.5 1 0.5 0 0 0.5 1 VOH (V) 1.5 2 2.5
85C
250
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 153. Reset I/O (VCC = 5V)
RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V 14 12 10 Current (mA) 8 6 4 2 0 0 0.5 1 VOL (V) 1.5 2 2.5
-40C 25C 85C
Figure 154. Reset I/O (VCC = 2.7V)
RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V 4.5 4
-40C
3.5
25C
3 Current (mA) 2.5 2 1.5 1 0.5 0 0 0.5 1 VOL (V) 1.5 2 2.5
85C
251
2486N-AVR-07/04
Figure 155. I/O VCC (VIH, I/O "1")
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIH, IO PIN READ AS '1' 2.5
2
-40C 85C 25C
Threshold (V)
1.5
1
0.5
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 156. I/O VCC (VIL, I/O "0")
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0' 2
1.5 Threshold (V)
-40C 25C 85C
1
0.5
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
252
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 157. I/O VCC
I/O PIN INPUT HYSTERESIS vs. VCC
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 158. Reset I/O VCC (VIH,Reset "1")
Input Hysteresis (V)
85C -40C 25C
RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. VCC
VIH, RESET PIN READ AS '1' 4 3.5 3 Threshold (V) 2.5 2 1.5 1 0.5 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
-40C 85C 25C
253
2486N-AVR-07/04
Figure 159. Reset I/O VCC (VIL,Reset "0")
RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. VCC
VIL, RESET PIN READ AS '0' 2.5
2
85C 25C -40C
Threshold (V)
1.5
1
0.5
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 160. Reset I/O VCC
RESET PIN AS I/O - PIN HYSTERESIS vs. VCC
2
1.5 Input Hysteresis (V)
-40C 85C 25C
1
0.5
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
254
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 161. Reset VCC (VIH,Reset "1")
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIH, RESET PIN READ AS '1' 2.5
2
-40C 25C 85C
Threshold (V)
1.5
1
0.5
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 162. Reset VCC (VIL,Reset "0")
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIL, RESET PIN READ AS '0' 2.5
2
85C 25C -40C
Threshold (V)
1.5
1
0.5
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
255
2486N-AVR-07/04
Figure 163. Reset VCC
RESET INPUT PIN HYSTERESIS vs. VCC
1
0.8
-40C
Input Hysteresis (V) 0.6
25C
0.4
85C
0.2
0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
BOD
Figure 164. BOD (BOD 4.0V)
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 4.0V 4.3
4.2
Rising VCC
4.1 Threshold (V)
4
Falling VCC
3.9
3.8
3.7 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C)
256
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 165. BOD (BOD 2.7v)
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 2.7V 2.8
2.7
Rising VCC
Threshold (V) 2.6
Falling VCC
2.5
2.4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C)
Figure 166. VCC
BANDGAP VOLTAGE vs. VCC
1.315
1.31 Bandgap Voltage (V)
-40
1.305
85 25
1.3
1.295
1.29 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
257
2486N-AVR-07/04
Figure 167. (VCC = 5V)
ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE
VCC = 5V 0.003 0.002 Comparator Offset Voltage (V) 0.001 0 -0.001 -0.002 -0.003
85
25C
-0.004 -0.005
-40
-0.006 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Voltage (V)
Figure 168. (VCC = 2.7V)
ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE
VCC = 2.7V 0.003 0.002 Comparator Offset Voltage (V) 0.001 0 -0.001 -0.002 -0.003 -0.004
85 25
-40
-0.005 0 0.5 1 1.5 Common Mode Voltage (V) 2 2.5 3
258
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 169. VCC
WATCHDOG OSCILLATOR FREQUENCY vs. VCC
1260 1240 1220 1200 FRC (kHz) 1180 1160 1140 1120 1100 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
-40C 25C 85C
Figure 170. 8 MHz RC
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
8.5
5.5V
8.3 8.1 7.9 FRC (MHz) 7.7 7.5 7.3 7.1 6.9 6.7 6.5 -60 -40 -20 0 20 Temperature (C) 40 60 80 100
4.0V
2.7V
259
2486N-AVR-07/04
Figure 171. 8 MHz RC VCC
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. VCC
8.5
-40C
8.3 8.1 7.9 FRC (MHz) 7.7 7.5 7.3 7.1 6.9 6.7 6.5 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
25C 85C
Figure 172. 8 MHz RC Osccal
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
16
14
12 FRC (MHz)
10
8
6
4 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE
260
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 173. 4 MHz RC
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
4.2
5.5V
4.1
4.0V
4 FRC (MHz)
3.9
2.7V
3.8
3.7
3.6
3.5 -60 -40 -20 0 20 Temperature (C) 40 60 80 100
Figure 174. 4 MHz RC VCC
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. VCC
4.2
-40C
4.1
25C
4
85C
FRC (MHz) 3.9
3.8
3.7
3.6
3.5 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
261
2486N-AVR-07/04
Figure 175. 4 MHz RC Osccal
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
8
7
6
FRC (MHz)
5
4
3
2 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE
Figure 176. 2 MHz RC
CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
2.1
5.5V
2.05
2
4.0V
FRC (MHz)
1.95
2.7V
1.9
1.85
1.8 -60 -40 -20 0 20 Temperature (C) 40 60 80 100
262
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 177. 2 MHz RC VCC
CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. VCC
2.2
2.1
-40C 25C
FRC (MHz) 2
85C
1.9
1.8
1.7 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 178. 2 MHz RC Osccal
CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
3.8
3.3
2.8 FRC (MHz)
2.3
1.8
1.3
0.8 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE
263
2486N-AVR-07/04
Figure 179. 1 MHz RC
CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
1.04
5.5V
1.02
4.0V
1 FRC (MHz)
0.98
0.96
2.7V
0.94
0.92
0.9 -60 -40 -20 0 20 Temperature (C) 40 60 80 100
Figure 180. 1 MHz RC VCC
CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. VCC
1.1
1.05
-40C
FRC (MHz)
25C
1
85C
0.95
0.9 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
264
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 181. 1 MHz RC Osccal
CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
1.9
1.7
1.5 FRC (MHz)
1.3
1.1
0.9
0.7
0.5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE
Figure 182. BOD VCC
BROWN-OUT DETECTOR CURRENT vs. VCC
30
25
20 ICC (uA)
-40C 25C 85C
15
10
5
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
265
2486N-AVR-07/04
Figure 183. ADC VCC (AREF = AVCC)
ADC CURRENT vs. VCC
AREF = AVCC 450 400
-40C
350
25C 85C
300 ICC (uA) 250 200 150 100 50 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 184. AREF VCC
AREF EXTERNAL REFERENCE CURRENT vs. V CC
250
200
85C 25C -40C
150 ICC (uA) 100 50 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
266
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 185. 32 kHz TOSC VCC ( )
32 kHz TOSC CURRENT vs. V CC
25 WATCHDOG TIMER DISABLED
20
25C
15
ICC (uA)
10 5 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 186. VCC
WATCHDOG TIMER CURRENT vs. V CC
80 70 60 50 ICC (uA) 40 30 20 10 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
85C 25C -40C
267
2486N-AVR-07/04
Figure 187. VCC
ANALOG COMPARATOR CURRENT vs. VCC
100
85C
90 80 70 60 ICC (uA) 50 40 30 20 10 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
25C -40C
Figure 188. VCC
PROGRAMMING CURRENT vs. VCC
7
-40C
6
5
25C 85C
ICC (mA)
4
3
2
1
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
268
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Figure 189. VCC (0.1 - 1.0 MHz )
RESET SUPPLY CURRENT vs. VCC
0.1 - 1 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP 4 3.5 3 2.5 ICC (mA)
5.5V 5.0V 4.5V 4.0V
2 1.5 1 0.5 0 0 0.1 0.2 0.3 0.4 0.5 Frequency (MHz) 0.6 0.7 0.8 0.9 1
3.3V 3.0V 2.7V
Figure 190. VCC (1 - 20 MHz )
RESET SUPPLY CURRENT vs. VCC
1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP 25
5.5V
20
5.0V 4.5V
ICC (mA)
15
10
3.3V
5
3.0V 2.7V
0 0 2 4 6 8 10 Frequency (MHz) 12 14 16 18 20
269
2486N-AVR-07/04
Figure 191. VCC
RESET PULSE WIDTH vs. VCC
1400 1200 1000 Pulsewidth (ns) 800 600
85C
400 200 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
25C -40C
270
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20(1) (0x40)(1) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22)
SREG SPH SPL GICR GIFR TIMSK TIFR SPMCR TWCR MCUCR MCUCSR TCCR0 TCNT0 OSCCAL SFIOR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 ASSR WDTCR UBRRH UCSRC EEARH EEARL EEDR EECR PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR UCSRA UCSRB UBRRL ACSR ADMUX ADCSRA ADCH ADCL TWDR TWAR
Bit 7
I - SP7 INT1 INTF1 OCIE2 OCF2 SPMIE TWINT SE - -
Bit 6
T - SP6 INT0 INTF0 TOIE2 TOV2 RWWSB TWEA SM2 - -
Bit 5
H - SP5 - - TICIE1 ICF1 - TWSTA SM1 - -
Bit 4
S - SP4 - - OCIE1A OCF1A RWWSRE TWSTO SM0 - -
Bit 3
V - SP3 - - OCIE1B OCF1B BLBSET TWWC ISC11 WDRF - T/C0 (8 )
Bit 2
N SP10 SP2 - - TOIE1 TOV1 PGWRT TWEN ISC10 BORF CS02
Bit 1
Z SP9 SP1 IVSEL - - - PGERS - ISC01 EXTRF CS01
Bit 0
C SP8 SP0 IVCE - TOIE0 TOV0 SPMEN TWIE ISC00 PORF CS00
9 11 11 46, 63 64 68, 94, 113 69, 94, 113 200 158 30, 62 38 68 68 28
- COM1A1 ICNC1 - COM1A0 ICES1 - COM1B1 - - COM1B0 WGM13 ACME FOC1A WGM12 PUD FOC1B CS12 PSR2 WGM11 CS11 PSR10 WGM10 CS10
55, 71, 114, 180 89 92 92 92 93 93 93 93 94 94
T/C1 - T/C1 - T/C1 - A T/C1 - A T/C1 - B T/C1 - B T/C1 - T/C1 - FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 T/C2 (8 ) T/C2 - - URSEL URSEL - EEAR7 - - - - UMSEL - EEAR6 - - - - UPM1 - EEAR5 - - WDCE - UPM0 - EEAR4 - USBS - EEAR3 EERIE - EEAR2 EEMWE AS2 WDE TCN2UB WDP2 UCSZ1 OCR2UB WDP1 UBRR[11:8] UCSZ0 - EEAR1 EEWE UCPOL EEAR8 EEAR0 EERE TCR2UB WDP0
108 110 110 110 40 145 143 17 17 17 17
EEPROM
PORTB7 DDB7 PINB7 - - - PORTD7 DDD7 PIND7 SPIF SPIE RXC RXCIE ACD REFS1 ADEN
PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 WCOL SPE TXC TXCIE ACBG REFS0 ADSC
PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 - DORD UDRE UDRIE ACO ADLAR ADFR
PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 - MSTR FE RXEN ACI - ADIF
PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 - CPOL DOR TXEN ACIE MUX3 ADIE
PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 - CPHA PE UCSZ2 ACIC MUX2 ADPS2
PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 - SPR1 U2X RXB8 ACIS1 MUX1 ADPS1
PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 SPI2X SPR0 MPCM TXB8 ACIS0 MUX0 ADPS0
61 61 61 61 61 61 61 61 61 121 121 119 141 142 142 145 181 192 194 195 195 160
SPI
USART I/O
USART
ADC ADC TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
160
271
2486N-AVR-07/04
0x01 (0x21) 0x00 (0x20)
TWSR TWBR
Bit 7
TWS7
Bit 6
TWS6
Bit 5
TWS5
Bit 4
TWS4
Bit 3
TWS3
Bit 2
-
Bit 1
TWPS1
Bit 0
TWPS0
160 158
Notes:
1. UBRRH UCSRC USART 2. 0 I/O 3. 1 AVR CBI SBI CBI SBI 0x00 - 0x1F
272
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k k 1 2 (Z) (Z) Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k "0" "1" I/O "0" I/O "1" "1" "0" "1" "0" "1" "0" T "1" T "0" "1" "0" Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C I Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2

#
1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1
PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1
R1:R0 (Rd x Rr) <<
RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC
273
2486N-AVR-07/04
BRIE BRID
k k Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Rd, Z Rd, Z+ Rd, P P, Rr Rr Rd P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b
SRAM SRAM I/O I/O I/O T T 2 2 SREG T
if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P P Rr STACK Rr Rd STACK I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1
#
1/2 1/2 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP
SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET
Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V SREG(s) SREG(s) T C C N N Z Z I I S S V V T
274
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
CLT SEH CLH
SREG T SREG SREG
T0 H1 H0 T H H
#
1 1 1
MCU NOP SLEEP WDR
( ) ( WDR/timer )

1 1 1
275
2486N-AVR-07/04
(MHz) 8 2.7 - 5.5 ATmega8L-8AC ATmega8L-8PC ATmega8L-8MC ATmega8L-8AI ATmega8L-8PI ATmega8L-8MI 16 4.5 - 5.5 ATmega8-16AC ATmega8-16PC ATmega8-16MC ATmega8-16AI ATmega8-16PI ATmega8-16MI Note: 32A 28P3 32M1-A 32A 28P3 32M1-A 32A 28P3 32M1-A 32A 28P3 32M1-A (0C 70C) (-40C 85C) (0C 70C) (-40C 85C)
wafer Atmel
32A 28P3 32M1-A 32- (1.0 mm)TQFP 28- 0.300" PDIP 32- 5 x 5 x 1.0 0.50 mm MLF
276
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
32A
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 8.75 6.90 8.75 6.90 0.30 0.09 0.45 NOM - - 1.00 9.00 7.00 9.00 7.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 9.25 7.10 9.25 7.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 32A REV. B
R
277
2486N-AVR-07/04
28P3
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
B2
A1
(4 PLACES)
C eB
0 ~ 15
REF
SYMBOL A A1 D E E1 B
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.508 34.544 7.620 7.112 0.381 1.143 0.762 3.175 0.203 - NOM - - - - - - - - - - - MAX 4.5724 - 34.798 8.255 7.493 0.533 1.397 1.143 3.429 0.356 10.160 Note 1 Note 1 NOTE
Note:
1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
B1 B2 L C eB e
2.540 TYP
09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 28P3 REV. B
R
278
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
32M1-A
D D1
1 2 3
0
Pin 1 ID E1 E
SIDE VIEW
TOP VIEW
A2
A3 A1 A
0.08 C
P D2
Pin 1 ID
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.80 - - NOM 0.90 0.02 0.65 0.20 REF 0.18 0.23 5.00 BSC 4.75 BSC 2.95 3.10 5.00 BSC 4.75BSC 2.95 3.10 0.50 BSC 0.30 - - 0.40 - - 0.50 0.60 12o 3.25 3.25 0.30 MAX 1.00 0.05 1.00 NOTE
1 2 3
P
A A1 E2 A2 A3 b D D1
b
e
L
D2 E
BOTTOM VIEW
E1 E2 e L
Notes: 1. JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.
P
0
01/15/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm Micro Lead Frame Package (MLF) DRAWING NO. 32M1-A REV. C
R
279
2486N-AVR-07/04
ATmega8 Rev. D, E, F G
ATmega8 * 32 KHz T/C2 CKOPT XTALn/TOSCn
1. 32 KHzT/C2 CKOPTXTALn/TOSCn RC XTAL1/TOSC1 XTAL2/TOSC2 32 KHz T/C2 RC CKOPTXTAL1/TOSC1XTAL2/TOSC2 XTAL1/TOSC1 XTAL2/TOSC2 20 - 36 pF ATmega8 Rev. G RC CKOPT ATmega8 Rev. G CKOPT = 0 ( ) XTAL1 XTAL2 Rev. G CKOPT (CKOPT = 1)
280
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
ATmega8
Rev. 2486M-12/03 Rev. 2486N-07/04
1. P 2" " MLF 2. P 39" " 3. P 226" " 4. ADC4 ADC5 10 P 183" " P 232" " 5. P 25" RC " " RC "
Rev. 2486L-10/03 Rev. 2486M-12/03 Rev. 2486K-08/03 Rev. 2486L-10/03
1. P 27" RC " 1. " " TBD 2. ICP ICP1 3. CALL JMP 4. P 35Table 15 tRST, P 39Table 16 , P 228Table 100 P 230Table 102 VBG 5. P 27"RC" Table 9"XTAL1XTAL2 (NC)" P 29" / " XTAL1/XTAL2 CKOPT 6. P 42" " 7. P 55" I/O SFIOR" bit 4, ADHSM 8. P 201Figure 103 2 9. P 222" " 4 10. P 224Table 97 tWD_FUSE P 225Table 98 , Byte 3 11. P 226" "
Rev. 2486J-02/03 Rev. 2486K-08/03
1. P 35Table 15 VBOT
281
2486N-AVR-07/04
2. P 232" " 3. P 233"ATmega8 " 4. P 280" "
Rev. 2486I-12/02 Rev. 2486J-02/03
1. P 23" clkASY" 2. " " "32 kHz " 3. P 83Figure 38 OCn 4. 1 5. TWI 6. P 202" ( )" SPM EEPROM 7. ADHSM 8. P 20" EEPROM " 9. XTAL1 XTAL2 P XTAL1/XTAL2/TOSC1/TOSC2" 5" B(PB7..PB0)
10. P 230"SPI " P 225"SPI " 11. P 57" C " PC6 12. P 55" B " PB6 PB7 13. P 146" " 230.4 Mbps 230.4 kbps 14. P 105" PWM " 2 PWM 15. P 156Figure 76 16. P 202" " Z " " " " 17. P 210Table 87 RSTDISBL 18. P 277" "
Rev. 2486H-09/02 Rev. 2486I-12/02 Rev. 2486G-09/02 Rev. 2486H-09/02
282
1. Rev D, E F
1. Flash 10,000 /
ATmega8(L)
2486N-AVR-07/04
ATmega8(L)
Rev. 2486F-07/02 Rev. 2486G-09/02 Rev. 2486E-06/02 Rev. 2486F-07/02
1 P 232Table 103"ADC " . 1 2 3 P 52" " P 56"MOSI/OC2 - B, Bit 3" OCS2 : P 122Table 51"CPOL CPHA " P 144Table 59"UCPOL " P 182Table 72" (1)" P 187Table 73"ADC " P 193Table 75"" P 208Table 84"Figure 103Z " 5 6 P 220" "
Rev. 2486D-03/02 Rev. 2486E-06/02
1 P 35Table 15"" P 39Table 16"" P 226DC P 232Table " " 2 P 29" " P 228Table 99" " 3 TWI TWI P 160Table 65"TWI "
Rev. 2486C-03/02 Rev. 2486D-03/02
1 P 25Table 5"" 25Table 6" P " P 26Table 8" RC " P 29Table 12" " 2 P 233"ATmega8 "
Rev. 2486B-12/01 Rev. 2486C-03/02
1 TWI TWI TWBRR TWI P 157" " P 157" "
283
2486N-AVR-07/04
2
OSCCAL 2 4 8 MHz P 28" OSCCAL" P 211" "
3
TBD P 23Table 3 P 35Table 15 P 39Table 16 P 41Table 17 , P 226"TA = -40C 85CVCC = 2.7V 5.5V ( )" P 228Table 99 P 230Table 102
4
P 212Figure 104 P 222Figure 112 AVCC
5
RESET P 213" "
284
ATmega8(L)
2486N-AVR-07/04

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