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PRELIMINARY DATA SHEET
MICRONAS
CDC16xxF-E Automotive Controller Family User Manual CDC1605F-E Automotive Controller Specification
Edition May 25, 2004 6251-606-1PD
MICRONAS
CDC16xxF-E
Contents Page 5 5 9 11 11 13 14 14 17 18 19 19 20 21 28 28 31 31 32 35 37 39 39 41 44 48 48 49 54 55 56 57 57 57 58 59 60 64 68 69 70 Section 1. 1.1. 1.2. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 3. 3.1. 3.2. 3.3. 3.4. 3.5. 4. 4.1. 4.2. 4.3. 4.4. 5. 5.1. 5.2. 5.3. 6. 6.1. 6.2. 6.3. 6.4. 7. 7.1. 7.2. 7.3. 8. 8.1. 8.2. 8.3. 8.4. 8.5. 8.6. Title Introduction Features Abbreviations Package and Pins Pin Assignment Package Outline Dimensions Multiple Function Pins Pin Function Description External Components Pin Circuits Electrical Data Absolute Maximum Ratings Recommended Operating Conditions Characteristics Recommended Crystal Characteristics Flash/EMU Port Characteristics CPU and Clock System W65C816 Operating Modes Clock System EMI Reduction Module (ERM) Memory and Boot System RAM and ROM Memory Banking Boot System Core Logic Control Register CR Reset Logic Standby Registers Test Registers Multiplier Functional Description Registers Operation of the Multiplier Power-Saving Module (PSM) Functional Description Registers Operation of Power-Saving Module Operation of RTC Module Operation of Polling Module Operation of Port Wake Module
PRELIMINARY DATA SHEET
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PRELIMINARY DATA SHEET
CDC16xxF-E
Contents, continued Page 72 72 73 75 75 77 79 81 83 85 85 86 88 90 91 92 93 93 95 95 97 99 99 100 101 102 103 105 105 107 107 108 110 110 113 113 115 115 116 119 119 121 Section 9. 9.1. 9.2. 10. 10.1. 10.2. 10.3. 10.4. 10.5. 11. 11.1. 11.2. 11.3. 11.4. 11.5. 12. 12.1. 12.2. 13. 13.1. 13.2. 14. 14.1. 14.2. 15. 15.1. 15.2. 16. 16.1. 16.2. 16.3. 16.4. 17. 17.1. 17.2. 17.3. 18. 18.1. 18.2. 18.3. 18.4. 18.5. Title Memory Patch Module Principle of operation Registers Interrupt Controller (IR) Principle of Operation Registers Interrupt Assignment Interrupt Timing Port Interrupt Module Ports Analog Input Port 0 Universal Ports U1 to U7 Universal Port Registers High Current Ports H0.0 to H3.5 High Current Port Registers A/D Converter (ADC) Operation Registers Timers (TIMER) Timer T0 Timer T1 and T2 Pulse Width Modulator (PWM) Principle of Operation Registers Capture Compare Module (CAPCOM) Principle of Operation Registers Stepper Motor Module (SMM) Functional Description Registers Principle of Operation Rotor Zero Position Detection (RZPD) LCD Module Principle of Operation Registers Software Hints for Cascading LCD Modules DMA Principle of Operation Registers Ports SW Application Hints Timings
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CDC16xxF-E
Contents, continued Page 125 126 127 128 129 130 132 134 136 137 137 143 148 150 152 152 152 153 154 155 155 155 155 158 161 164 165 166 169 171 171 171 176 176 176 177 178 182 208 210 Section 19. 19.1. 19.2. 19.3. 20. 20.1. 20.2. 20.3. 21. 21.1. 21.2. 21.3. 21.4. 21.5. 22. 22.1. 22.2. 22.3. 22.4. 23. 23.1. 23.2. 23.3. 23.4. 23.5. 23.6. 24. 24.1. 24.2. 25. 25.1. 25.2. 26. 26.1. 26.2. 26.3. 26.4. 27. 28. 29. Title Serial Synchronous Peripheral Interface (SPI) Principle of Operation Registers Timing Universal Asynchronous Receiver Transmitter (UART) Principle of Operation Timing Registers CAN Manual Abbreviations Functional Description Application Notes Bit Timing Logic Bus Coupling DIGITbus System Description Bus Signal and Protocol Other Features Standard Functions Optional Functions DIGITbus Master Module Introduction Context Functionality Registers Principle of Operation Timings Audio Module (AM) Functional Description Registers
PRELIMINARY DATA SHEET
Hardware Options Functional Description Listing of Dedicated Addresses and Corresponding Hardware Options Register Cross Reference Table V2.1 CAN RAM, memory pages 19 ... 1B CAN Registers, memory page 1C I/O Registers, memory page 1E I/O Registers, memory page 1F Register Quick Reference Differences Data Sheet History
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1. Introduction
Release Note: Revision bars indicate significant changes to the previous edition. The IC is a single-chip controller for use in automotive applications. The CPU on the chip is an upgrade of the 65C02 with 16-bit internal data and 24-bit address bus. The chip consists of timer/counters, an interrupt controller, a multichannel A/D converter, a stepper motor and LCD driver, CAN interfaces and PWM outputs.
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PRELIMINARY DATA SHEET
1.1. Features
Table 1-1: CDC16xxF Family Feature List
This Document: Item Core CPU CPU-Active Operation Modes Power Saving Modes (CPU Inactive) EMI Reduction Mode Oscillators RAM ROM 16-bit 65C816, featuring software compatibility with its 8-bit NMOS and CMOS 6500-series predecessors FAST, SLOW and DEEP SLOW WAKE and IDLE selectable in FAST mode 4 to 12 MHz Quartz and 20 to 57 kHz internal RC 6 KB ROMless, external program storage with up to 16 MB, internal 2 KB Boot ROM 256 KB Flash, bottom boot configuration, internal 2 KByte Boot ROM 2 KB 64 KB 4 MHz to 12 MHz Quartz 6 KB ROMless, external program storage with up to 16 MB, internal 2 KB Boot ROM 256 KB Flash, bottom boot configuration, internal 2 KB Boot ROM 2.75 KB 90 KB 4 KB 128 KB 6 KB 216 KB FAST and SLOW CDC1605F-E EMU CDC1607F-E MCM Flash CDC1631F-E MASK ROM CDC1605F-C EMU CDC1607F-C MCM Flash CDC1641F-C Mask ROM CDC1652F-C Mask ROM CDC1672F-C Mask ROM
CDC16xxF-E
5
Table 1-1: CDC16xxF Family Feature List, continued
This Document: Item Multiplier, 8 by 8 bit Digital Watchdog Central Clock Divider Interrupt Controller expanding NMI Port Interrupts including Slope Selection CDC1605F-E EMU 16 inputs,15 priority levels 4 inputs 10 CDC1607F-E MCM Flash CDC1631F-E MASK ROM CDC1605F-C EMU CDC1607F-C MCM Flash CDC1641F-C Mask ROM CDC1652F-C Mask ROM CDC1672F-C Mask ROM
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CDC16xxF-E
Port Wake-Up Inputs including Slope / Level Selection Patch Module Boot System
10 ROM locations allows in-system downloading of code and data into RAM via serial link
5 ROM locations -
10 ROM locations allows in-system downloading of code and data into RAM via serial link
5 ROM locations -
6 ROM locations -
Analog Reset/Alarm Clock and Supply Supervision 10-bit ADC, charge balance type ADC Reference Comparators LCD Combined Input for Regulator Input Supervision
PRELIMINARY DATA SHEET
9 channels (5 channels selectable as digital input) VREF Pin P06COMP with 1/2 AVDD reference Internal processing of all analog voltages for the LCD driver
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Table 1-1: CDC16xxF Family Feature List, continued
This Document: Item Communication DMA UART Synchronous Serial Peripheral Interfaces Full CAN modules V2.0B 1 DMA Channel for serving the Graphics Bus interface 3: UART0, UART1 and UART2 2: SPI0 and SPI1 3: CAN0, CAN1 and CAN2 with 256-byte object RAM each (LCAN000F) 1 master module 1: UART0 1: SPI0 1: CAN0 with 256-byte object RAM (LCAN000F) 1 DMA Channel for serving the Graphics Bus interface 3: UART0, UART1 and UART2 2: SPI0 and SPI1 3: CAN0, CAN1 and CAN2 with 256-byte object RAM each (LCAN0009) 1 master module 1: UART0 1: SPI0 1: CAN0 with 256-byte object RAM (LCAN0009) 1 DMA Channel for serving the Graphics Bus interface 3: UART0, UART1 and UART2 2: SPI0 and SPI1 2: CAN0 and CAN1 with 256-byte object RAM each (LCAN0009) CDC1605F-E EMU CDC1607F-E MCM Flash CDC1631F-E MASK ROM CDC1605F-C EMU CDC1607F-C MCM Flash CDC1641F-C Mask ROM CDC1652F-C Mask ROM CDC1672F-C Mask ROM
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PRELIMINARY DATA SHEET
DIGITbus Input & Output Universal Ports selectable as 4:1 mux LCD Segment/Backplane lines or Digital I/O Ports Universal Port Slew Rate Stepper Motor Control Modules with High-Current Ports 8-bit PWM Modules
1 master module
up to 52 I/O or 48 LCD segment lines (=192 segments), in groups of two configurable as I/O or LCD
HW preselectable 5 Modules, 24 dI/dt controlled ports
5 Modules: PWM0, PWM1, PWM2, PWM3 and PWM4 2
3 Modules: PWM0, PWM1, PWM2
5 Modules: PWM0, PWM1, PWM2, PWM3 and PWM4
2 Modules: PWM0, PWM1
5 Modules: PWM0, PWM1, PWM2, PWM3 and PWM4
CDC16xxF-E
Audio Module with autodecay SW select. Clock outputs Polling / Flash Timer Output
1 High-Current Port output operable in Power Saving Mode
-
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Table 1-1: CDC16xxF Family Feature List, continued
This Document: Item Timers & Counters 16-bit free running counters with Capture/ Compare modules 16-bit timers 8-bit timers Real Time Clock, Delivering Hours, Minutes and Seconds Miscellaneous Scalable layout in CAN, RAM and ROM Various randomly selectable hardware options Mask programmed according to user specification CCC0 with 3CAPCOM CDC1605F-E EMU CDC1607F-E MCM Flash CDC1631F-E MASK ROM CDC1605F-C EMU CDC1607F-C MCM Flash CDC1641F-C Mask ROM CDC1652F-C Mask ROM CDC1672F-C Mask ROM
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CDC16xxF-E
1: T0 2: T1 and T2 -
Most options software-programmable, copy from user program storage during system start-up
Most options software-programmable, copy from user program storage during system start-up
Core Bond-Out Supply Voltage Temperature Range Package Type Bonded Pins
4.5 V to 5.5 V Tcase: 0 C to +70 C
-
-
Tcase: -40 C to +105 C
Tamb: -40 C to +85 C
PRELIMINARY DATA SHEET
Ceramic 177PGA 176
Plastic 100QFP 0.65 mm pitch 100
Ceramic 177PGA 176
Plastic 100QFP 0.65 mm pitch 100
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1.2. Abbreviations
AM CAN CAPCOM CPU DMA ERM IR LCD P06COMP PINT PSM PWM RTC SM SPI T0 T1, T2 UART Audio Module Controller Area Network Module Capture/Compare Module Central Processing Unit Direct Memory Access Module EMI Reduction Module Interrupt Controller Liquid Crystal Display Module P0.6 Alarm Comparator Port Interrupt Module Power Saving Module 8-Bit Pulse Width Modulator Module Real time Clock Stepper Motor Control Module Serial Synchronous Peripheral Interface 16-Bit Timer 0 8-Bit Timers 1 and 2 Universal Asynchronous Receiver Transmitter
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PRELIMINARY DATA SHEET
CDC16xxF-E
9
CDC16xxF-E
PRELIMINARY DATA SHEET
VSS VDD
UVDD UVSS LCD Control UPort1 Data-, address- and control bus
40
8
Test RESETQ TEST XTAL1 XTAL2 Watchdog Clock ERM RC Oscillator RTC Power Saving Module
Patch Module Banking
UPort2
EVDD EVSS
CAN 1 Reset/Alarm DMA Logic 8
8-Bit Timer 1 65C816 CPU 8-Bit Timer 2 16-Bit CAPCOM 1 16 Inputs Interrupt Controller 16-Bit CAPCOM 2 16-Bit Timer 0 DIGITbus UPort3 8
Audio Module UPort4 VREF AVDD AVSS PPort0 RAM 6k x 8
Multiplier 8 by 8 bit
UART 0 UART 2
8
9
10-Bit ADC
CAN
HPort0
6
Clock Out 1 16-Bit CAPCOM 0
UPort5
Stepper Motor Control
Clock Out 0
8
HPort1
6
8-Bit PWM 2 8-Bit PWM 0
UART 1
HPort2
Boot ROM 8-Bit PWM 4
CAN 0 SPI 0 SPI 1
UPort6
8
6
HPort3
UPort7
6
8-Bit PWM 1 8-Bit PWM 3
4
HVDD1 HVSS1 HVDD2 HVSS2
Fig. 1-1: Block diagram of CDC1605F-E
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PRELIMINARY DATA SHEET
CDC16xxF-E
2. Package and Pins
2.1. Pin Assignment
15 A B C D 92 93 95 99
14 88 91 94 98
13 85 87 90 97
12 83 84 86 89
11 79 80 81 82
10 75 76 78 77
9 71 74 73 72
8 70 69 68 67
7 66 65 63 62
6 64 61 58 57
5 60 59 56 52
4 55 54 53 45
3 51 50 46 42 37 34 29 24 19 14 12 9 2
2 49 47 43 40 36 32 30 25 21 17 15 10 6 3
1 48 44 41 39 35 31 27 26 22 20 16 11 7 5 4 1 A B C D E F G H J K L M N P Q
E 104 103 100 96 F 108 105 102 101 G 110 109 107 106 H 114 113 112 111 J 115 118 117 116 K 119 120 122 121 L 123 124 125 126 Top View
177 38 33 28 23 18 13 8 1
M 127 128 130 133 140 145 150 155 160 165 170
N 129 131 134 141 144 146 151 156 161 166 169 174
P 132 135 138 142 147 149 153 157 162 164 168 172 175
Q 136 137 139 143 148 152 154 158 159 163 167 171 173 176 15 14 13 12 11 10 9 8 7 6 5 4 3 2
A1
Top View Pin 1
Fig. 2-1: Pin Map of CPGA177 Package
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CDC16xxF-E
PRELIMINARY DATA SHEET
Basic Function EADB21 EADB20 NC NC EPH2 EBE EVPA EVDA ESTOPCLK UVSS UVDD ADB7 SEG3.7 T2-OUT U3.7 ADB6 SEG3.6 CC1-OUT U3.6 ADB5 SEG3.5 SPI1-CLK-OUT SPI1-CLK-IN U3.5 ADB4 SEG3.4 T0-OUT WP0 U3.4 ADB3 SEG3.3 CC2-OUT U3.3 ADB2 SEG3.2 DIGIT-OUT DIGIT-IN U3.2 ADB1 SEG3.1 CO1 SPI1-D-IN U3.1 ADB0 SEG3.0 SPI1-D-OUT U3.0 NC NC NC Extra pin for avoiding wrong chip insertion. Connect to System Ground. NC NC NC NC SEG6.7 CAN0-TX MULTI_TEST_IN U6.7 SEG6.6 PINT1-OUT CAN0-RX/WP1 U6.6 SEG6.5 T1-OUT SPI0-D-IN U6.5 Connect to System Ground SEG6.4 SPI0-D-OUT U6.4 TEST RESETQ XTAL2 XTAL1 VSS VDD SEG6.3 SPI0-CLK-OUT SPI0-CLK-IN U6.3 SEG6.2 T1-OUT PINT2-IN/WP5 U6.2 SEG6.1 LCD-CLK-OUT PINT1-IN/WP4 U6.1 SEG6.0 LCD-SYNC-OUT PINT0-IN/WP3 U6.0 WEQ SEG1.7 CAN1-TX U1.7 CEQ SEG1.6 CAN1-RX/WP2 U1.6 ITSTOUT SEG1.5 LCD-CLK-OUT U1.5 RWQ SEG1.4 LCD-SYNC-OUT U1.4 PH2 BP3 U1.3 OEQ BP2 U1.2 BE BP1 U1.1 RDY BP0 ITSTOUT U1.0 EADB17 EADB0 EDB7 EDB6 EDB5 EDB4 EDB3 EDB2 EDB1 EDB0 Connect to System Ground EVSS1 NC NC NC NC NC EVDD1 EOEQ ECEQ EADB1 STOPCLK SMB1+ H1.5 VPQ SMB1H1.4 VPA SMB2+ H1.3 Connect to System Ground VDA SMB2SMB-COMP H1.2 DB7 SME1+/PWM2 H1.1 DB6 SME1-/PWM0 H1.0 HVDD1 HVSS1 DB5 SME2+ H0.5 DB4 SME2SME-COMP H0.4 DB3 SMA1+ H0.3 DB2 SMA1H0.2 DB1 SMA2+ H0.1 DB0 SMA2SMA-COMP H0.0 SMD1+ H3.5 SMD1H3.4 SMD2+ H3.3
Bus Mode
LCD Mode
Pin Functions Port Port Special Out Special In
Co- Pin ord. No. M8 N8 P8 Q8 Q7 M7 N7 P7 Q6 P6 M6 N6 Q5 P5 N5 M5 Q4 P4 Q3 N4 P3 Q2 E5 M4 N3 P2 Q1 P1 N2 N1 L4 M3 M2 M1 L3 K4 K3 L2 L1 K2 J4 J3 K1 J2 J1 H4 H3 H2 H1 G1 G4 G3 G2 F1 F2 F4 F3 E1 E2 E3 E4 D1 D2 C1 D3 C2 B1 D4 C3 B2 A1 A2 B3 A3 D5 C4 B4 A4 C5 D6 C6 B5 A5 B6 D7 C7 A6 B7 A7 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66
Pin CoNo. ord. 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 Q9 P9 Q10 N9 M9 P10 Q11 P11 N10 M10 N11 Q12 P12 N12 M11 Q13 P13 Q14 Q15 P14 N13 M12 P15 N14 M13 N15 M14 M15 L12 L13 L14 L15 K13 K12 K14 K15 J14 J13 J12 J15 H15 H14 H13 H12 G15 G14 F15 G13 G12 F14 E15 E14 F13 F12 E13 D15 D14 D13 E12 C15 C14 B15 A15 B14 C13 D12 A14 B13 C12 A13 B12 A12 D11 C11 B11 A11 C10 D10 B10 A10 B9 C9 D9 A9 A8 B8 C8 D8
177 1
155 154
133 132
44 45 66 67 87
88
NC = not connected, leave vacant
Pin Functions Basic Port Port Function Special In Special Out EADB22 EADB23 U7.0 U7.1 U7.2 GRDQ U7.3 GWRQ U4.0 CAN2-RX/WP7 U4.1 CAN2-TX U4.2 UART2-RX U4.3 UART2-TX U4.4 UART0-RX/WP8 U4.5 UART0-TX U4.6 CC2-IN CC1-OUT U4.7 CC1-IN Connect to System Ground U5.0 CC0-IN CO1 U5.1 INT-TEST-IN CC0-OUT U5.2 LCD-CLK-IN AM-PWM U5.3 LCD-SYNC-IN AM-OUT U5.4 IRQ UART1-TX U5.5 ABORTQ CO0 NC NC NC NC NC U5.6 PINT3/WP6 PWM2 U5.7 PINT3/UART1-RX PINT0-OUT U2.0/GD0 U2.1/GD1 U2.2/GD2 U2.3/GD3 U2.4/GD4 U2.5/GD5 U2.6/GD6 U2.7/GD7 AVSS AVDD VREF NC P0.1 P0.1 digital input P0.2 P0.2 digital input P0.3 P0.3 digital input P0.4 P0.4 digital input P0.5 P0.5 digital input P0.6 P0.6 Comparator input P0.7 P0.8 P0.9 EADB16 EADB15 EADB14 EADB13 EADB12 EADB11 EADB10 EADB9 EWEQ Connect to System Ground EADB18 EVSS2 NC NC NC NC NC NC NC EVDD2 EADB19 EADB8 EADB7 EADB6 EADB5 EADB4 EADB3 EADB2 H2.0 SMC-COMP SMC2H2.1 SMC2+ H2.2 SMC1H2.3 SMC1+ H2.4 WP9 PWM0 H2.5/POL PWM4 HVSS2 HVDD2 H3.0 PWM1 H3.1 PWM3 H3.2 SMD-COMP SMD2-
LCD Mode
Bus Mode
SEG7.0 SEG7.1 SEG7.2 SEG7.3 SEG4.0 SEG4.1 SEG4.2 SEG4.3 SEG4.4 SEG4.5 SEG4.6 SEG4.7 SEG5.0 SEG5.1 SEG5.2 SEG5.3 SEG5.4 SEG5.5
ADB8 ADB9 ADB10 ADB11 ADB12 ADB13 ADB14 ADB15
SEG5.6 SEG5.7 SEG2.0 SEG2.1 SEG2.2 SEG2.3 SEG2.4 SEG2.5 SEG2.6 SEG2.7
ADB16 ADB17 ADB18 ADB19 ADB20 ADB21 ADB22 ADB23
Fig. 2-2: Pin Assignment for CPGA177 Package
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2.540 x 14 = 35.56 0.2
11.7
0.8
1. 0.1
7.6
0.2
2.540 0.15
0.46 0.05
Micronas
2.1 0.20 2.540 x 14 = 35.56 0.2 2.540 0.15 0.4 0.1 15 14 13
96 82 106 116 126
PRELIMINARY DATA SHEET
2.2. Package Outline Dimensions
38 0.4 21 0.2 19.8
12
140
11 10
72 150
9 8
62 160
MIS-INSERT COVERING PIN
52 38 28 18 8 170
7 6 5
1
Fig. 2-3: CPGA177 Ceramic Pin Grid Array 177-Pin (Weight approx. 14g)
May 25, 2004; 6251-606-1PD
0.2 1 0.1 4.80 0.20 A B C D E F
4 3 2 1 G H J K L M N P Q
PIN No. 1 INDEX
D0022-B/1
CDC16xxF-E
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CDC16xxF-E
2.3. Multiple Function Pins
2.3.1. U-Ports
Apart from their basic function (digital I/O), Universal Ports (prefix "U") have overlaid alternative functions (see Fig. 2-2 on page 12). How to enable Basic Function, Special In and Special Out mode is explained in the functional description of the UPorts. How to enable LCD mode is explained in the functional descriptions of LCD module and U-Ports. Bus Mode is used for testing purposes only. It is controlled by the Control Register (CR) setting. Refer to section "Control Word" for more information.
PRELIMINARY DATA SHEET
How to enable Basic Function, Special In and Special Out mode is explained in the functional description of the HPorts. The Bus Mode is used for testing purposes only. It is controlled by the Control Register (CR) setting. Refer to section "Control Word" for more information.
2.3.3. Emulator Bus
In the CPGA177 package, the Emulator Bus (prefix "E") serves as connection to an external emulation hardware. In the PQFP100 MCM Package it is internally connected to the Flash program storage and is not available to the outside. Its function is controlled by register CR. Refer to section "Control Word" for more information.
2.3.2. H-Ports
Apart from their basic function (digital I/O), High Current Ports (prefix "H") have overlaid alternative functions (see Fig. 2-2 on page 12).
2.4. Pin Function Description
ABORTQ The Abort input serves as the CPU's ABORTQ input provided that flag EXTIR in register SR2 is set. Active LOW. ADB0 to ADB23 These 24 lines form the address bus for memory and I/O exchange. The function is controlled by register CR. AM-OUT This is the output signal of the AM. AM-PWM This is the output signal of the 8-bit PWM of the AM. It is intended for testing only. AVDD This is the positive power supply for ADC, P06COMP and ERM. AVDD should be kept at VDD 0.5 V. AVSS This is the negative reference for the ADC and the negative power supply for ADC, P06COMP and ERM. Connect to system ground. BE The Bus Enable output signal shows the state of the internal CPU. 1: Internal CPU has bus access. 0: Internal CPU has no bus access. BP0 to BP3 These pin functions serve as Backplane drivers for a 4:1 multiplexed LCD. CAN0-RX, CAN1-RX, CAN2-RX These signals provide the input lines for the CAN0, CAN1 and CAN2 modules. CAN0-TX, CAN1-TX, CAN2-TX These signals provide the output lines for the CAN0, CAN1 and CAN2 modules. CC0-IN, CC1-IN, CC2-IN These signals are the capture inputs of the CAPCOM0, CAPCOM1 and CAPCOM2 modules. CC0-OUT, CC1-OUT, CC2-OUT These signals are the compare outputs of the CAPCOM0, CAPCOM1 and CAPCOM2 modules. CEQ This output signal connects to external memory's CEQ pin and reduces its power consumption when CPU operates in SLOW mode. Active LOW. CO0, CO1 The signals Clock Out 0 and 1 provide frequency outputs. Both are connected to internal prescaler and multiplexer. They can be hard-wired by HW Option. Refer to section "Hardware Options" for setting the CO0 bytes 00FFABh, 00FFB2h, 00FFB3h, 00FFB6h and the CO1 byte 00FFACh. For testing purposes it is possible to drive clocks and other signals of internal peripheral modules out of CO0 and CO1. Selection is done via register TST2. DB0 to DB7 The eight bidirectional Data Bus lines provide the 8-bit data bus for use during data exchanges between the microprocessor and external memory or peripherals. The function is controlled by register CR. DIGIT-IN This is the receive input line of the DIGITbus module. DIGIT-OUT This is the transmit output line of the DIGITbus module. EADB0 to EADB23 These 24 lines form the address bus for external memory access on the Emulator Bus. The function is controlled by register CR. EBE The Emulator Bus Enable output signal shows the state of
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PRELIMINARY DATA SHEET
CDC16xxF-E
GD0 to GD7 These eight bidirectional Graphics IC Data lines provide an 8-bit DMA controlled data link to an external IC. GRDQ This Graphics IC Read line provides the control signal for read accesses via the GD7 to GD0 bus. Active LOW. GWRQ This Graphics IC Write line provides the control signal for write accesses via the GD7 to GD0 bus. Active LOW. H0.0 to H3.5 The High Current Ports are intended for use as digital I/O which can drive higher currents than the Universal Ports. Each of the high current ports H0 to H3 is six bits wide. HVDD1, HVDD2 The pins HVDD1 and HVDD2 are the positive power supply of the high current ports H0.0 to H3.5. HVDD1 feeds ports H0 and H1. HVDD2 feeds ports H2 and H3. HVDD1 and HVDD2 should be kept at VDD 0.5 V. Be careful to design the PCB traces for carrying the considerable operating current on these pins. HVSS1, HVSS2 The pins HVSS1 and HVSS2 are the negative power supply for the high-current ports H0.0 to H3.5. HVSS1 feeds ports H0 and H1. HVSS2 feeds ports H2 and H3. Both have to be hard-wired to system ground. Be careful to layout sufficient PCB traces for carrying the considerable operating current on these pins. INT-TEST-IN Test input signal for Interrupt Controller. IRQ IRQ serves as the CPU's IRQ input, provided that flag EXTIR in register SR2 is set. Active LOW. LCD-CLK-IN The Clock input of the LCD module receives the clock of an optional external LCD master driver which is used to extend the LCD driver capability. This input is active if the internal LCD module is configured as slave and the external LCD driver operates as master. LCD-CLK-OUT The Clock output of the LCD module provides a clock signal to optional external LCD slave drivers if the internal LCD module is configured as master and the other LCD drivers are slaves. LCD-SYNC-IN The Synchronization input of the LCD module receives the sync signal from an optional external LCD master driver. This input is active if the internal LCD module is configured as slave and the external LCD driver serves as master. LCD-SYNC-OUT The Synchronization output of the LCD module provides a sync signal to optional external LCD slave drivers if the internal LCD module is configured as master and the other LCD drivers are slaves. MULTI-TEST-IN This is a test input line. It is intended for factory test only. The application should not use this signal. OEQ The Output Enable output signal connects to the OEQ pin of external memory for read access. Active LOW. PH2 The System Clock output signal provides timing for external
the internal CPU. 1: Internal CPU has bus access. 0: Internal CPU has bus no access. ECEQ Emulator Bus Chip Enable output signal connects to external memory's CEQ pin and reduces its power consumption when CPU operates in SLOW mode. Active LOW. EDB0 to EDB7 These eight bidirectional Emulator Data Bus lines provide the 8-bit data bus for use during data exchanges between the microprocessor and external memory or peripherals. EOEQ The Emulator Bus Output Enable signal connects to the OEQ pin of external memory for read access. Active LOW. EPH2 This output is the system clock of the Emulator Bus. It provides the timing for external memory access. ESTOPCLK If the Emulator Stop Clock input signal is HIGH, all the peripheral modules are halted (fOSC is stopped), whereas the clock PH2 and the CPU remain active. Thus it is possible to read the registers and memory for debugging purposes. For normal operation connect ESTOPCLK to System Ground or leave it floating (internal pull-down). EVDA The Emulator Bus Valid Data Address output signal shows the state of the internal CPU. It must be considered together with the signal EVPA (Emulator Bus Valid Program Address). Each signal indicates a valid memory address when high.
Table 2-1: Valid Memory Address
EVDA, VDA 0 EVPA, VPA 0 State Internal Operation. Address and data bus available. Address bus may be invalid. Valid program address. May be used for program cache control. Valid data address. May be used for data cache control. Opcode fetch. May be used for program cache control and single step control.
0 1 1
1 0 1
EVDD1, EVDD2 These two lines form the positive power supply of the Emulator Bus drivers. EVPA Refer to EVDA. EVSS1, EVSS2 These two lines form the negative supply of the Emulator Bus drivers. Connect to system ground. EWEQ The output signal Emulator Bus Write Enable connects to the external memory's WEQ pin and activates it for write access. Active LOW.
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read or write operations. Addresses are valid (after the Address Setup Time) following the negative transition of PH2. The function is controlled by register CR. PINT0-IN, PINT1-IN, PINT2-IN The Port Interrupt 0, 1 and 2 inputs serve as inputs to the PINT. PINT3 The Port Interrupt 3 input serves as input to the PINT. HW option FFC2h has to be set to determine whether U5.6 or U5.7 is the source of PINT3-IN. PINT0-OUT, PINT1-OUT The Port Interrupt 0 and 1 outputs carry the output signals of the PINT. POL Output of the Polling Module. PWM0 to PWM4 These are the outputs of the PWM. Some of these PWM signals are directed to two pins. P0.1 to P0.9 These 9 analog ports are the multiplexed input channels of the ADC. Analog port P0.6 is additionally input to the P06COMP. The analog ports P0.1 to P0.5 can also be used as five digital input lines. The digital function of the analog ports should be disabled (P0DIN in register SR1 set to 0) when operating these ports as analog inputs to avoid leakage currents. RDY This output signal shows the state of the internal CPU. 1: CPU active 0: CPU halted by IR or DMA RESETQ This bidirectional signal is used to initialize all modules and start program execution. Two comparators distinguish three input levels: - A low level resets all internal modules. - A medium level activates all internal modules and starts program execution. An alarm signal is generated which can be directed to the interrupt controller. - A high level keeps all internal modules active and cancels the alarm signal. The RESETQ input signal must be held low for at least two clock cycles after VDD reaches operating voltage. Internal reset sources output their reset request on the RESETQ pin via an internal open drain pull-down transistor. Thus RESETQ can be wire-ored with external reset sources. The internally limited pull-down current allows direct connection to large capacitors. The connection of such a capacitor (e.g. 10 nF) is recommended to reduce the capacitive influence of the neighboring XTAL2 pin. RESETQ must be pulled up by an external pull-up resistor (e.g. 10 k). RWQ This input/output signal controls data exchange in cooperation with DB and ADB. It can be driven from the external CPU if the internal CPU is switched off. 1: CPU reads data. 0: CPU writes data.
PRELIMINARY DATA SHEET
SEG1.4 to SEG7.3 These pin functions serve as Segment drivers for a 4:1 multiplexed LCD. SMA to SME These lines are intended for driving stepper motors. They are the outputs of the SM. Two of these lines together with an external coil form an H-bridge. Thus each of the signals SMA to SME can drive a two-phase bipolar stepper motor. SMA-COMP to SME-COMP These lines are comparator inputs that connect to one line each of the SMA to SME lines. They serve to distinguish rotation from stand-still during zero detection in each stepper motor. SPI0-CLK-IN, SPI1-CLK-IN The Serial Synchronous Peripheral Interface Clock input receives the bit clock from an external master, to shift data in or out of SPI0 resp. SPI1 in slave mode. This means that the external master controls the bit stream. SPI0-CLK-OUT, SPI1-CLK-OUT The Serial Synchronous Peripheral Interface Clock output supplies the bit clock of SPI0 resp. SPI1 to an external slave, to shift data in or out of SPI0 resp. SPI1 in master mode. This means that the internal SPI controls the bit stream. SPI0-D-IN, SPI1-D-IN These are the data input lines of the SPI0 and SPI1 modules. SPI0-D-OUT, SPI1-D-OUT These are the data output lines of the SPI0 and SPI1 modules. STOPCLK If the input signal Stop Clock is HIGH, all the peripheral modules are halted (fOSC is stopped). But the clock PH2 and the CPU remain active. Thus it is possible to read the registers and memory for debugging purposes. TEST must be held high to enable STOPCLK. TEST The main function of the Test pin is to define the source for the Control Word fetch during reset. If TEST is held low during reset, the Control Word is fetched via the Emulator Bus (from internal Flash program storage in MCM package). If TEST is held high during reset, the Control Word is fetched via the Test Bus. For normal operation with internal code connect TEST to System Ground or leave it floating (internal pull-down). TEST must be held high in active mode to enable STOPCLK. T0-OUT The Timer 0 output is connected to the zero output of T0 by a divide by 2 scaler. The scaler generates a 50% pulse duty factor. T1-OUT, T2-OUT These signals are connected to the zero outputs of T1 and T2. T1-OUT is directed to several pins. UART0-RX, UART1-RX, UART2-RX These are the Receive input lines of UART0, UART1 and UART2. Polarity of the signals is settable by HW options FFB4h, respectively FFB5h. UART0-TX, UART1-TX, UART2-TX These are the data output lines of UART0, UART1 and UART2. Polarity of signals is settable by HW options FFB4h, respectively FFB5h.
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PRELIMINARY DATA SHEET
CDC16xxF-E
vector location during an interrupt sequence. VPQ is low during the last two interrupt sequence cycles, during which time the CPU reads the interrupt vector. VREF This pin is the positive reference input for the ADC. The voltage at this pin must be set to a level between 2.56 Volts and AVDD. VSS The pin VSS is the negative supply terminal of the internal digital modules (see Fig. 2-4 for external connection). WEQ The Write Enable output signals a write access to external memory. Active LOW. WP0 to WP9 The Wake Port inputs are inputs to the Port Wake Module inside the Power Saving Module. They serve as Wake Ports during power saving modes and as port interrupt inputs during CPU-active modes. XTAL1 This is the quartz oscillator or clock input pin (see Fig. 2-4 for external connection). XTAL2 This is the quartz oscillator output pin for two pin oscillator circuits (see Fig. 2-4 for external connection).
UVDD The pin UVDD is the positive supply voltage for the U-Port output stages (see Fig. 2-4 for external connection). UVSS The pin UVSS is the negative power supply for the U-Port output stages. It has to be connected to system ground (see Fig. 2-4). U1.0 to U7.3 Universal ports are intended for use as digital I/O or as LCD driver outputs. The ports U1 to U6 consist of eight bit lines each. Port U7 is 4 bits wide. VDA The signal Valid Data Address must be considered together with the signal VPA (Valid Program Address). They show the state of the internal CPU. If the internal CPU is switched off, both signals may be driven from the outside. Together they indicate a valid memory address when HIGH (see Table 2-1 on page 15). VDD The pin VDD is the positive supply voltage for the internal digital modules (see Fig. 2-4 for external connection). VPA Refer to VDA. VPQ The Vector Pull output indicates that the CPU addresses a
2.5. External Components
C = 100 n to 150 n +5 V L VDD C = 100 n to 150 n C VSS 18 p C XTAL1 HVSS 0 to 1 HVDD 0 to 1 2*C +5 V EVSS 0 to 1 EVDD 0 to 1 2*C +5 V
UVDD
System Ground
System Ground
+5 V Analog
IC
AVDD +5 V 18 p 4.7 k 47 n XTAL2 VREF 10 n C
Resetq System Ground
RESETQ
UVSS
AVSS
Analog Ground
Fig. 2-4: Recommended external supply and quartz connection for low electromagnetic interference (EMI)
To provide effective decoupling and to improve EMC behavior, the small decoupling capacitors must be located as close to the supply pins as possible. The self-inductance of these capacitors and the parasitic inductance and capacitance of the interconnecting traces determine the self-resonant frequency of the decoupling network. A frequency too low will
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CDC16xxF-E
reduce decoupling effectiveness, increase RF emissions and may affect device operation adversely. XTAL1 and XTAL2 quartz connections are especially sensitive to capacitive coupling from other PCB signals. It is strongly recommended to place quartz and oscillation capacitors as close to the pins as possible, and to shield the
PRELIMINARY DATA SHEET
XTAL1 and XTAL2 traces from other signals by embedding them in a VSS trace. The RESETQ pin adjacent to XTAL2 should be supplied with a 47nF capacitor, to prevent fast RESETQ transients from being coupled into XTAL2, to prevent XTAL2 from coupling into RESETQ, and to guarantee a time constant of 200 s sufficient for proper Wake Reset functionality.
2.6. Pin Circuits
VSUPOUT VSUPIN Input Logic GNDIN GNDOUT GNDOUT VSUPOUT VSUPIN Input Logic GNDIN
Fig. 2-5: Input Pins
Fig. 2-7: Push Pull I/O Pins
VSUPOUT VSUPIN GNDIN GNDOUT weak Input Logic
VSUPOUT VSUPIN Input Logic GNDIN GNDOUT
Fig. 2-6: Input Pins with Pull-Down
Fig. 2-8: Open Drain I/O
Table 2-2: I/O Supply Catalog
Pin Names XTAL1, XTAL2 ESTOPCLK TEST U-Ports H-Ports P-Ports EDB0 to EDB7, EADB0 to EADB23, ECEQ, EOEQ, EWEQ, EPH2, EVDA, EVPA, EBE RESETQ 2-8 2-7 HVDD AVDD EVDD UVDD HVSS UVSS EVSS UVSS Figure 2-5 2-6 VSUPOUT UVDD GNDOUT UVSS VSUPIN VDD GNDIN VSS
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PRELIMINARY DATA SHEET
CDC16xxF-E
3. Electrical Data
3.1. Absolute Maximum Ratings
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum ratings conditions for extended periods will affect device reliability. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated voltages to this high-impedance circuit.
Table 3-1: All voltages listed are referenced to ground (UVSS=HVSSn=EVSSn=AVSS=0V), except where noted. All ground pins except VSS must be connected to a low-resistive ground plane close to the IC.
Symbol VSUP Parameter Core Supply Voltage Port Supply Voltage Analog Supply Voltage SM Supply Voltage 1 SM Supply Voltage 2 Flash Port Supply Voltage 1 Flash Port Supply Voltage 2 Voltage Difference between VDD and AVDD resp. UVDD Core Supply Current Port Supply Current Flash Port Supply Current Analog Supply Current SM Supply Current @TCASE=105C, Duty Factor=0.71 1) Input Voltage Pin Name VDD UVDD AVDD HVDD1 HVDD2 EVDD1 EVDD2 VDD, AVDD UVDD VDD, VSS UVDD, UVSS EVDD1, EVSS1 EVDD2, EVSS2 AVDD, AVSS HVDD1, HVSS1 HVDD2, HVSS2 U-Ports, XTAL,RESETQ, TEST P0-Ports VREF H-Ports E-Ports Iin Io Input Current Output Current all Inputs U-Ports E-Ports H-Ports toshsl Tj Ts Pmax
1)
Min. -0.3
Max. 6.0
Unit V
VDD ISUP
-0.5 -40
0.5 40
V mA
IASUP IHSUP Vin
-20 -380 UVSS-0.5
20 380 UVDD+0.7
mA mA V
UVSS-0.5 HVSS-0.5 EVSS-0.5 0 -5 -60
AVDD+0.7 HVDD+0.7 EVDD+0.7 2 5 60 indefinite
V V V mA mA mA s C C W
Duration of Short Circuit in Port SLOW Mode to UVSS or UVDD Junction Temperature under Bias Storage Temperature Maximum Power Dissipation
U-Ports except U3.2 in DP Mode -45 -45
115 125 0.8
This condition represents the worst case load with regard to the intended application
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CDC16xxF-E
3.2. Recommended Operating Conditions
PRELIMINARY DATA SHEET
Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. Keep UVDD = AVDD during all power-up and power-down sequences. Failure to comply with the above recommendations will result in unpredictable behavior of the device and may result in device destruction. Functional operation of the device beyond those indicated in the "Recommended Operating Conditions" is not implied and may result in unpredictable behaviour, reduce reliability and lifetime of the device.
Table 3-2: All voltages listed are referenced to ground (UVSS=HVSSn=EVSSn=AVSS=0V), except where noted. All ground pins except VSS must be connected to a low-resistive ground plane close to the IC.
Symbol VDD Parameter Supply Voltage Port Supply Voltage Analog Supply Voltage Flash Port Supply Voltage 1 Flash Port Supply Voltage 2 SM Supply Voltage 1 SM Supply Voltage 2 Voltage Difference between VDD and AVDD resp. UVDD AVDD Ripple, Peak-to-Peak XTAL Clock Frequency XTAL Clock Frequency using ERM Vil Low Input Voltage Pin Name VDD UVDD AVDD EVDD1 EVDD2 HVDD1 HVDD2 VDD, AVDD UVDD AVDD XTAL1 XTAL1 U-Ports H-Ports P0-Ports TEST E-Ports Vih High Input Voltage U-Ports H-Ports P0-Ports TEST E-Ports RVil WRVil Reset Active Input Voltage Reset Active Input Voltage during Power Saving Modes and Wake Reset Reset Inactive and Alarm Active Input Voltage Reset Inactive and Alarm Inactive Input Voltage Reset Inactive during Power Saving Modes ADC Reference Input Voltage P0 ADC Input Port Input Voltage RESETQ RESETQ 0.86*VDD 4 4 Min. 4.5 Typ. 5 Max. 5.5 Unit V
HVDD VDD dAVDD fXTAL
4.75 -0.2
5
5.25 0.2 200 12 10 0.51*VDD
V V mV MHz MHz V
0.8
V V
2.2 0.9 0.6
V V V
RVim RVih WRVih VREFi P0Vi
RESETQ RESETQ RESETQ VREF P0-Ports
1.6 2.9 UVDD 0.4V 2.56 0
2.1
V V V
AVDD VREFi
V V
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PRELIMINARY DATA SHEET
CDC16xxF-E
Table 3-2: All voltages listed are referenced to ground (UVSS=HVSSn=EVSSn=AVSS=0V), except where noted. All ground pins except VSS must be connected to a low-resistive ground plane close to the IC.
Symbol Parameter Pin Name Min. Typ. Max. Unit
Clock Input from External Generator XVil XVih DXTAL Clock Input Low Voltage Clock Input High Voltage Clock Input High-to-Low Ratio XTAL1 XTAL1 XTAL1 0.8*VDD 0.45 0.55 0.2*VDD V V
3.3. Characteristics
Table 3-3: UVSS = HVSS1= HVSS2 = EVSS1 = EVSS2 = AVSS = 0 V, 4.5 V< VDD = AVDD = UVDD = EVDD1= EVDD2 < 5.5 V, 4.75 V < HVDD1 = HVDD2 < 5.25 V, TCASE = 0 to +70 C, fXTAL= 10 MHz, external components according to Fig. 2-4(unless otherwise noted)
Symbol Package Rthjc Thermal Resistance from Junction to Case 15 C/W CMOS levels on all Inputs, no Loads on Outputs difference between any two VDDs within 0.2 V VDD VDD 15 1.5 25 2.0 mA mA all Modules OFF 2), 6) all clocks disabled by hardware option settings all Modules OFF 2), 6) all hardware options set to their RESET values all Modules OFF 2), 6) all hardware options set to their RESET values fxtal = 4 MHz 6) fxtal = 10 MHz 6) internal RC oscill. Parameter Pin Na. Min. Typ. 1) Max. Unit Test Conditions
Supply Currents
IDDF IDDS
VDD FAST Mode Supply Current VDD SLOW Mode Supply Current
2.5
3.5
mA
IDDD
VDD DEEP SLOW Mode Supply Current VDD IDLE Mode Supply Current
VDD
0.75
1.0
mA
IDDI
VDD
70 180 12
135 260 55 50 0.3
A A A A mA mA mA
IDDW UIDDa AIDDa
VDD WAKE Mode Supply Current UVDD Active Supply Current AVDD Active Supply Current
VDD UVDD AVDD
1
no Output Activity, LCD Module ON ADC ON, ERM OFF ERM ON,
0.2 1
0.4 2
1) Typical
values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested.
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CDC16xxF-E
PRELIMINARY DATA SHEET
Table 3-3: UVSS = HVSS1= HVSS2 = EVSS1 = EVSS2 = AVSS = 0 V, 4.5 V< VDD = AVDD = UVDD = EVDD1= EVDD2 < 5.5 V, 4.75 V < HVDD1 = HVDD2 < 5.25 V, TCASE = 0 to +70 C, fXTAL= 10 MHz, external components according to Fig. 2-4(unless otherwise noted)
Symbol AIDDq UIDDq EIDDq HIDDq Parameter Quiescent Supply Current Pin Na. AVDD UVDD EVDD1 EVDD2 Sum of all HVDD1 HVDD2 Min. Typ. 1) 1 1 1 1 Max. 10 10 10 20 Unit A A A A Test Conditions ADC and ERM OFF no Output Activity, LCD Module OFF no Output Activity, LCD Module OFF no Output Activity, SM Module OFF
Inputs Vilh Low to High Input Threshold Voltage all Inp. except EPorts, XTAL all Inp. except EPorts, XTAL all Inp. except EPorts, XTAL U-Ports H-Ports P0-Port P06 VREF E-Ports TEST E-Ports E-DB 0.68* VDD 0.76* VDD 0.84* VDD V
Vihl
High to Low Input Threshold Voltage
0.53* VDD
0.61* VDD
0.69* VDD
V
Vilh-Vihl
Input Hysteresis
0.1* VDD
0.15* VDD
0.2* VDD
V
3)
Ii
Input Leakage Current
-1 -10 -1 -0.2 -1 -1 25 25 -170 80 80 -80
1 10 1 0.2 1 1 170 170 -25
A
0 < Vi < UVDD 0 < Vi < HVDD 0 < Vi < AVDD 0 < Vi < AVDD 0 < Vi < AVDD 0 < Vi < EVDD Vi = UVDD Vi = EVDD, when unused Vi = 0, when unused
Ipd Ipu Outputs Vol
Input Pull-Down Current Input Pull-Up Current
A A
Port Low Output Voltage
U-Ports E-Ports H-Ports 0.125
0.4 0.4 0.5
V V V
Io = 2 mA Io = 0.5 mA Io = 27 mA Io = 40 mA@TCASE = -40 C Io = 30mA@TCASE = 25 C
Vol
1) Typical
Spread of Vol Values within one SM Driver Module
H-Ports
-50
50
mV
values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested.
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PRELIMINARY DATA SHEET
CDC16xxF-E
Table 3-3: UVSS = HVSS1= HVSS2 = EVSS1 = EVSS2 = AVSS = 0 V, 4.5 V< VDD = AVDD = UVDD = EVDD1= EVDD2 < 5.5 V, 4.75 V < HVDD1 = HVDD2 < 5.25 V, TCASE = 0 to +70 C, fXTAL= 10 MHz, external components according to Fig. 2-4(unless otherwise noted)
Symbol Voh Parameter Port High Output Voltage Pin Na. U-Ports E-Ports H-Ports Min. UVDD- 0.4 EVDD- 0.4 HVDD- 0.5 HVDD- 0.125 Typ. 1) Max. Unit V V V Test Conditions Io= -2 mA Io= -0.5 mA Io = -27 mA Io = -40 mA@TCASE = -40 C Io = -30 mA @TCASE = 25 C
Voh LVol LVo1
Spread of Voh Values within one SM Driver Module LCD Port Zero Output Voltage LCD Port Low Output Voltage LCD Port High Output Voltage LCD Port Full Output Voltage Internal LCD-Low Supply Short Circuit Current Internal LCD-High Supply Short Circuit Current Port Fast Short Circuit Current Port Slow Short Circuit Current Port Slow Short Circuit Current, DP Mode
H-Ports U-Ports U-Ports
-50 -0.05 1/3 *UVDD -0.05 2/3 *UVDD -0.05 UVDD -0.05 0.3
50 0.05 1/3 *UVDD +0.05 2/3 *UVDD +0.05 UVDD +0.05
mV V V no load no load
LVo2
U-Ports
V
no load
LVoh LIo1 LIo2
U-Ports U-Ports
V mA
no load Pin Short to 2/3*UVDD Pin Short to UVSS
-0.3 U-Ports 0.3 -0.3 U-Ports U-Ports 6 1.3 10 2.5 18 5 mA mA mA
Pin short to UVDD Pin short to 1/3*UVDD Pin Short to UVDD or UVSS, Port FAST Mode Pin Short to UVDD or UVSS, Port SLOW Mode Pin Short to UVDD, Port SLOW and Double PullDown Modes
Ishf Ishs
Ishsd
U3.2
2.6
5
10
mA
Comparators VBG tBG VREFR RVlh- RVhl
1) Typical
Internal Reference Voltage Internal Voltage Reference Setup Time after Power-Up RESET Comparator Reference Voltage RESET Comparator Hysteresis, symmetrical to VREFR RESETQ RESETQ
1.125
1.25
1.375 10
V s V V
3)
1*VBG 0.25
1*VBG 0.375
values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested.
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CDC16xxF-E
PRELIMINARY DATA SHEET
Table 3-3: UVSS = HVSS1= HVSS2 = EVSS1 = EVSS2 = AVSS = 0 V, 4.5 V< VDD = AVDD = UVDD = EVDD1= EVDD2 < 5.5 V, 4.75 V < HVDD1 = HVDD2 < 5.25 V, TCASE = 0 to +70 C, fXTAL= 10 MHz, external components according to Fig. 2-4(unless otherwise noted)
Symbol WRVihl Parameter Reset Active high to low Voltage during Power Saving Modes and Wake Reset ALARM Comparator Reference Voltage ALARM Comparator Hysteresis, symmetrical to VREFA VDD Power On Reset Threshold P06 Comparator Reference Voltage P06 Comparator Hysteresis, symmetrical to VREFP06 SM Comparator Reference Voltage Pin Na. RESETQ Min. 0.6 Typ. 1) Max. 1.1 Unit V Test Conditions
VREFA AVlh- AVhl VREFPOR VREFP06 P06Vlh- P06Vhl VREFSM
RESETQ RESETQ VDD P06 P06
2*VBG 0.1 2.88* VBG 0.49* AVDD 0.1
2*VBG 0.15 2.88* VBG 0.51* AVDD 0.24
V V V V V
3) 3)
H00, H04, H12, H20, H32 RESETQ P06 H00 H04 H12 H20 H32
1/9* HVDD -0.07
1/9* HVDD +0.07
V
tCDEL
RESET, ALARM, P06, SM Comparator Delay Time
100
ns
Overdrive = 50 mV
ADC LSB INL LSB Value Integral Non-Linearity: difference between the output of an actual ADC and the line best fitting the output function (best-fit line) Zero Error: difference between the output of an ideal and an actual ADC for zero input voltage Full-Scale Error: difference between the output of an ideal and an actual ADC for full-scale input voltage Total Unadjusted Error: maximum sum of integral non-linearity, zero error and full-scale error -3 -2.5 VREF /1024 3 2.5 V LSB VREF = 2.56 V VREF = 5.12 V
ZE
-1
1
LSB
VREF = 2.56 V and 5.12 V
FSE
-1
1
LSB
VREF = 2.56 V and 5.12 V
TUE
-4 -3
4 3
LSB
VREF = 2.56 V VREF = 5.12 V
1) Typical
values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested.
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PRELIMINARY DATA SHEET
CDC16xxF-E
Table 3-3: UVSS = HVSS1= HVSS2 = EVSS1 = EVSS2 = AVSS = 0 V, 4.5 V< VDD = AVDD = UVDD = EVDD1= EVDD2 < 5.5 V, 4.75 V < HVDD1 = HVDD2 < 5.25 V, TCASE = 0 to +70 C, fXTAL= 10 MHz, external components according to Fig. 2-4(unless otherwise noted)
Symbol QE Parameter Quantization Error: uncertainty because of ADC resolution Absolute Error: difference between the actual input voltage and the full-scale weighted equivalent of the binary output code, all error sources included Conversion Range Conversion Result P0-Ports Pin Na. Min. -0.5 Typ. 1) Max. 0.5 Unit LSB Test Conditions VREF = 2.56 V and 5.12 V VREF = 2.56 V VREF = 5.12 V
AE
-4.5 -3.5
4.5 3.5
LSB
R A
AVSS INT (Vin/ LSB) 000
VREF
V hex
2.56 V < VREF < AVDD AVSS < Vin < VREF
hex 3FF hex s s pF kOhm
Vin < = AVSS Vin > = VREF
tc ts Ci Ri
Conversion Time Sample Time Input Capacitance during Sampling Period Serial Input Resistance during Sampling Period
4 2 15 5
RC Oscillator fout Output Frequency 20 35 57 kHz
Clock Supervision fSUP Clock Supervision Threshold Frequency XTAL1 70 350 kHz
SPI (Fig. 3-1, Fig. 3-2) tsoci thoci tsoce thoce tsi Data out Setup Time with internal clock Data out Hold Time with internal clock Data out Setup Time with external clock Data out Hold Time with external clock Data in Setup Time with external clock U3.0, U6.4 U3.0, U6.4 U3.0, U6.4 U3.0, U6.4 U3.1, U6.5 2/ fXTAL -60 1/ fXTAL+ 60 4) -60 60 4) 60 4) 3/ fXTAL +60 4) ns ns ns ns ns @Cl = 30 pF, port fast mode @Cl = 30 pF, port fast mode @Cl = 30 pF, port fast mode @Cl = 30 pF, port fast mode
1)
Typical values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested.
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PRELIMINARY DATA SHEET
Table 3-3: UVSS = HVSS1= HVSS2 = EVSS1 = EVSS2 = AVSS = 0 V, 4.5 V< VDD = AVDD = UVDD = EVDD1= EVDD2 < 5.5 V, 4.75 V < HVDD1 = HVDD2 < 5.25 V, TCASE = 0 to +70 C, fXTAL= 10 MHz, external components according to Fig. 2-4(unless otherwise noted)
Symbol thi Parameter Data in Hold Time with external clock Pin Na. U3.1, U6.5 Min. 1/ fXTAL+ 60 4) Typ. 1) Max. Unit ns Test Conditions
CAN (Fig. 3-3) tsrx tdtx rx-strobe Time tx-drive Time CAN rx CAN tx 0 15 10 4) 60 4) ns ns reference is XTAL1 rising edge reference is XTAL1 rising edge @Cl = 30 pF, port fast mode The input/output delay time equals to tdtxmax - tsrxmin DIGITbus (Fig. 3-4) tbtj tfed
1) Typical
Bit Time jitter Falling edge delay
DIGITOUT DIGITOUT 15 5)
10 4) tBIT/64 +60 4)
ns ns
rising edges, internal clock master reference is nominal falling edge
values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested.
2) Value may be exceeded with unusual Hardware Option setting 3) Design value only, the actually observable hysteresis may be lower due to system activity and related supply noise 4) When the ERM is active, this time value is increased by 0.121/fXTAL, e.g. 15.125 ns @8 MHz. 5) When the ERM is active, this time value is decreased by 0.121/fXTAL, e.g. 15.125 ns @8 MHz. 6) Measured with external clock. Add 100 A at 4 MHz, 115 A at 10 MHz for operation on typical quartz with SR3.XTAL
=0
(Oscillator RUN mode).
SPI-CLK-OUT tsoci thoci SPI-D-OUT SPI-D-IN
Fig. 3-1: SPI: Send and Receive Data with Internal Clock. Timing is valid for inverted clock too (Data valid at positive edge).
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PRELIMINARY DATA SHEET
CDC16xxF-E
SPI-CLK-IN tsi SPI-D-IN thi
SPI-CLK-IN tsoce thoce SPI-D-OUT
Fig. 3-2: SPI: Send and Receive Data with External Clock. Timing is valid for inverted clock too (Data valid at positive edge).
tcyc XTAL1 tdtx TX tsrx RX
Fig. 3-3: CAN I/O Timing.
tBIT DIGIT-IN DIGIT-OUT tfed nominal pulse tNPL tNPL: Nominal programmed Pulse Length. Depends on programmed phase, Baudrate and transmitted sign (0, 1, T). Should be 1/4 for sign 0, 1/2 for sign 1 and 3/4 for sign T of tBIT. tbtj tbtj
Fig. 3-4: DIGIT bus I/O Timing
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3.4. Recommended Crystal Characteristics
PRELIMINARY DATA SHEET
Table 3-4: UVSS = HVSS1 = HVSS2 = EVSS1 = EVSS2 = AVSS = 0 V, 4.5 V < VDD = AVDD = UVDD = EVDD1 = EVDD2 < 5.5 V,
4.75 V< HVDD1 = HVDD2 < 5.25 V, TCASE = 0 to +70 C Symbol fP R1 Parameter Parallel Resonance Frequency @ CL = 12 pF Series Resonance Res. for 50 ms Oscillation Start-Up time @CL = 12 pF @ fP = 4 MHz @ fP = 6 MHz @ fP = 8 MHz @ fP = 10 MHz CEXT External Oscillation Capacitances for CL = 12 pF, connected to VSS 18 Min. 4 Typ. Max. 12 Unit MHz Test Conditions
380 320 230 160 150 95 100 60
Ohm Ohm Ohm Ohm pF
START-UP RUN START-UP RUN START-UP RUN START-UP RUN
3.5. Flash/EMU Port Characteristics
Table 3-5: EVDD = VDD = 4.5 V to 5.5 V, TCASE = 0 to 70 C
Symbol tPHD tADS Parameter internal PH2 delay Address Setup Time Min. Typ. 6 15 + 0.5 20 30 8 6 9 +0.5 14 24 6 8 6 6 14 7 21 Max. 8 19 + 0.7 26 40 10 12 14 + 0.7 21 35 8 10 10 9 24 10 30 Unit ns ns ns/pf ns ns ns ns ns ns/pf ns ns ns ns ns ns ns ns ns CEDB = 0 pF CEDB = 10 pF CEDB = 30 pF CEDB = 0 pF CEDB = 0 pF CEOQ,EWQ = 0 pF CEOQ,EWQ = 0 pF CEBE = 0 pF CEBE = 0 pF CEVDA,EVPA = 0 pF CEADB = 0 pF CEADB = 10 pF CEADB = 30 pF CEADB = 10 pF Test Conditions
tADH tDSR tDSW
Address Hold Time Data Setup Read Time Data Setup Write Time
tDHR tDHW tWOS tWOH tBES tBEH tVS
Data Hold Time Read Data Hold Time Write Write/Output Enable Setup Write/Output Enable Hold Bus Enable Setup Bus Enable Hold EVDA, EVPA Setup Time
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PRELIMINARY DATA SHEET
CDC16xxF-E
tcyc XTAL1 tPHD tSCLS ESTOPCLK Ph2 EPh2 tEPHD tADS, tVS tADH EADB, EVDA, EVPA tDHR READ DATA tDHW WRITE DATA tDSW WRITE DATA tWOS EWE, EOE tBEH, tBES EBE, ECE Fig. 3-5: Emu Bus Timing tWOH tACC tDSR READ DATA tSCLH
FAST mode fOSC Ph2 RW CE WE OE
SLOW mode
Fig. 3-6: Memory Access Signals
Emulator ports: CE (=ECEQ) may be used for low power mode. Input data are latched with the rising edge of CE. Test ports: Be careful with CE working in low power mode.
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There are no input data latches at the test ports. Always pull CE down.
PRELIMINARY DATA SHEET
XTAL1 STOPCLK fOSC Ph2
Fig. 3-7: Stop Clock (only if TEST Pin = 1)
STOPCLK is used for emulation and test mode. It is active with TEST input pulled to VDD only. With the stopped fOSC all peripheral modules, such as timers and UARTs, are frozen.
But with the runni ng Ph2 clock the CPU is able to read and write the internal registers and memory. The pin ESTOPCLK has an internal pulldown. The pin STOPCLK (H1.5, Test mode) has no internal pulldown, so in test mode an external pulldown is needed.
XTAL1 EPh2 RW EADB EDB EOE EWE EDB EOE EWE Fig. 3-8: Internal/External Memory Access
Control word Bit 5 = 0 (emu mode)
internal signal external external internal internal
Control word Bit 5 = 1 (ext. mem. mode)
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PRELIMINARY DATA SHEET
CDC16xxF-E
4. CPU and Clock System
The core basically consists of the CPU, RAM and ROM. A Memory Banking module is included to allow access to more than 64 k memory with an address bus limited to 16 bits. ROM is subdivided in Boot ROM and Flash EEPROM. In normal operation, after RESET, the CPU starts executing boot loader SW code from the Boot ROM and then jumps into the Flash EEPROM. Please find detailed information in section Boot System. In mask-ROM-derivative ICs, the code execution starts in factory-defined mask ROM.
4.1. W65C816
The CPU is fully compatible to WDC's W65C816 microprocessor. This is a processor with 16-bit registers/accumulator, an 8-bit data bus and a 24-bit address bus. A software switch determines whether the processor is in the 8-bit emulation mode, supporting SW compatibility to its 8-bit predecessors, or in the 16-bit native mode. For further information on the CPU core, please refer to the WDC W65C816 Data Sheet.
Table 4-1: Major Differences between Processors and Modes
Item block moves 65C816 Emulation of little use yes FFFE.FFFF wraps D=0 D=x 8 bits 256 FFF4.FFFF 92 direct page page 1 none 65C816 Native yes no FFE6.FFE7 crosses page D=0 D=0 8 or 16 bits 256 FFE4.FFEF 92 direct page bank 0 none 65C02 none yes FFFE.FFFF wraps D=0 D=0 8 bits 178 FFFA.FFFF 64 zero page page 1 NOP
Table 4-1: Major Differences between Processors and Modes
Item ABS, X ASL, LSR, ROL, ROR with no page crossing jump indirect, operand = XXFF branch across Page decimal mode RWQ signal during readmodify-write instructions abort signal accumulator addressing modes address space bank registers 65C816 Emulation 7 cycles 65C816 Native 7 cycles 65C02 6 cycles
break flag break vector direct page indexed flags after interrupt flags after reset
5 cycles
5 cycles
6 cycles
index registers instructions
4 cycles no additional cycle RWQ=0 during modify and write cycles yes 8/8 bits 25 16 M yes
3 cycles no additional cycle RWQ=0 only during write cycle yes 16 or 8/8 bits 25 16 M yes
4 cycles add 1 cycle RWQ=0 only during write cycle no 8 bits 16 64 K none
interrupts mnemonics special page stack unused opcodes
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4.1.1. Processor Modes
The 65C816 CPU allows operation in two modes: - Native mode: 16-bit mode - Emulation mode: 8-bit mode for emulation of 65C02 properties Table 4-1 gives some details on the differences between modes. Refer to the WDC W65C816 Data Sheet for more information and on how to switch between modes. After reset, Emulation mode is active. However, Native mode is recommended for normal use. To make maximum usage of the CPU's 16-bit properties, switch to Native mode after reset.
PRELIMINARY DATA SHEET
4.1.2. Emulation of 65C02
When using the Emulation mode to design software for a derivative containing only the 65C02 8-bit CPU, care has to be taken to use only the features available with that CPU. Table 4-1 gives a comparing overview. Refer to the WDC W65C816 Data Sheet for more information.
4.2. Operating Modes
To adapt to the large variety of CPU speed and current consumption requirements, the device offers a number of operating modes: - CPU-active modes, where the CPU is clocked at selectable speeds. - Power-saving modes, where the CPU is kept reset and only certain portions of the circuit are powered. Fig. 4-1 shows how the various modes are accessed in an operating modes state diagram.
Power up
Global Reset with Ports Global Reset w/o Ports
< 50 ms (if 4 ... 12MHz XTAL was off) ~ 0,5 ms @ 8 MHz XTAL (if XTAL stays on)
< 50 ms (if 4 ... 12MHz XTAL was off) ~ 0,5 ms @ 8 MHz XTAL (if XTAL stays on) RTC, Wake Ports
WAKE/IDLE
WAKE/IDLE
RESETQ All reset sources
DEEP SLOW FAST SLOW SLOW FAST SLOW DEEP SLOW All reset sources
Fig. 4-1: Operating Modes State Diagram 4.2.1. CPU-Active Modes
The CPU can be operated in three different CPU-active modes (Table 4-2). Core modules that are also affected by CPU-active modes are: 1. Interrupt Controller with all internal and external interrupts 2. RAM, ROM/Flash and DMA 3. Watchdog Table 4-2 shows the operability of the peripheral modules in the various CPU-active modes.
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fXTAL/256 will take effect after a maximum delay of 256 fXTAL periods. Returning CPU to FAST mode is done by setting flag CPUFST to HIGH. The CPU clock frequency will immediately change to its normal fXTAL value. 4.2.1.3. DEEP SLOW Mode To further reduce power consumption beyond SLOW mode, DEEP SLOW mode also disables most of the internal peripheral clocking system. Table 4-2 shows which peripheral modules can be operated in DEEP SLOW mode. Only peripheral module clocks f5 and slower are available from the divider chain. T0 can be operated only with this limitation. To prevent undefined behavior don't switch between DEEP SLOW and FAST mode directly but select SLOW mode in between. Changing to or from DEEP SLOW mode is done by writing SR3.FCLO (see Section 6.3. "Standby Registers" on page 54 for details).
4.2.1.1. FAST Mode After reset the CPU is in FAST mode. The CPU clock and the I/O clock both equal the oscillator frequency fXTAL. 4.2.1.2. SLOW Mode To considerably reduce power consumption, the user can reduce the internal CPU clock frequency to 1/256 of the normal fXTAL value. In this CPU SLOW mode, program execution is reduced to 1/256 of the normal speed, but clocking of most other modules remains unaffected. The modules that are affected by CPU SLOW mode are: 1. CPU and Interrupt Controller with all internal and external interrupts 2. RAM, ROM and DMA 3. Watchdog Some modules must not be operated during CPU SLOW mode (e.g. CAN). Refer to module sections for details (see Table 4-2 on page 34). CPU SLOW mode is enabled by clearing flag CPUFST in standby register SR1. The CPU clock frequency reduction to
4.2.2. Power-Saving Modes
Power-saving modes are activated by the CPU. The complete core logic will immediately terminate operation and power will be reduced. The result is a device current consumption that is greatly reduced, to the amount of leakage currents. The internal SRAM and CAN-RAM keep their programmed data and all U, P, and H-Port registers keep their programmed state. However, a means to leave these modes has to be provided. As the CPU is no longer active, either an external or internal wake signal has to be generated. The external wake necessitates no device current, but to generate an internal wake requires an internal oscillator and a Real Time Clock (RTC) to run, which will cost a small amount of supply current. Please note that inadvertently entering a power-saving mode, e.g. by an external electrical overstress (EOS) condition, when no wake source has been configured previously as recovery path from this state, renders the device locked in this power saving mode. Only a RESETQ pin reset or a complete power removal and reapplication recovers the device from this state. Sufficient external shielding measures must avoid this hazard. 4.2.2.1. WAKE Mode The WAKE mode is the most current-saving operation mode. All device circuits are stopped or powered down except the Port Wake Module (Table 4-3). The Port Wake Module allows the CPU to configure up to ten fixed device ports (see the device pinout for details) as Wake Ports (WP). To prepare for WAKE mode, the CPU has to switch off the RTC and to configure the desired Wake Port(s) (see chapter "Power Saving Module", sections "Port Wake Module" and "RTC Module"). To enter WAKE mode, the CPU sets SR3.WAID. The device will immediately enter WAKE mode by resetting all circuitry, stopping all clocks, and powering down all analog circuitry. As long as all Port inputs - except analog inputs via P-ports P0.1 to P0.9 - are kept at CMOS input levels (Vil = xVSS 0.3 V and Vih = xVDD 0.3 V), the supply currents will be minimal. The device may be kept in this state indefinitely. To exit WAKE mode, the previously configured Wake Port has to switch. Immediately a Wake Reset sequence will be started internally, which pulls the RESETQ pin low and releases it as soon as all internal reset sources have become inactive. See chapter "Core Logic" for details on internal reset sources. After reset, the CPU starts in FAST mode as usual. 4.2.2.2. IDLE Mode IDLE mode allows to configure an internal wake source that wakes after a preselected period. As clock sources, either a current-saving, but imprecise internal RC oscillator, or the precise, but more current-consuming XTAL oscillator, are selectable. These circuits and the RTC are kept alive (Table 4-3) as well as the Port Wake Module. The RTC allows the CPU to select from one-second to oneday clocks as wake signal (see Section 8.4. "Operation of RTC Module" on page 68 for details). Apart from serving as wake source, the CPU may use the RTC as a real-time clock that is not halted by resets. A Polling Module, driven by a selectable RTC clock, may be configured to generate a polling pulse on H2.5 and sample the Wake Ports immediately after. Thus a periodical polling of Wake Ports may be achieved, with no continuous power consumption in external circuitry. To prepare for IDLE mode, the CPU has to configure the desired RTC wake clock (see Section 8.4. "Operation of RTC Module" on page 68 for details), beside the desired Wake Port(s) (see Section 8.6. "Operation of Port Wake Module" on page 70 for details). To enter IDLE mode, the CPU sets SR3.WAID. The device will immediately enter IDLE mode by resetting all circuitry, stopping the unused clocks, and powering down all
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Table 4-2: CPU-Active Modes and their effect on peripheral modules
Module Core Digital Watchdog IR Interrupt Controller Unit Port Interrupts Port Wake Module Memory Patch Module Analog A/D Converter ALARM, P06 and Comparators LCD Module Communication DMA UART SPI CAN DIGITbus Input & Output Ports Stepper Motor Module PWM Audio Module Clock Outputs Timers & Counters Capture Compare Module Timers RTC/Polling Module
1) 2 ) 3
PRELIMINARY DATA SHEET
FAST
SLOW
DEEP SLOW

3) 2)

3) 3)
2) 3)

2)

1)
2) 3) 2)
Avoid write access to CCxI Only clocks f5 and slower are available from Clock Divider ) Don't access registers or CAN RAM releases it as soon as all internal reset sources have become inactive. See chapter "Core Logic" for details on internal reset sources. After reset, the CPU starts in FAST mode, as usual.
analog circuitry. As long as all Port inputs - analog inputs via P-ports P0.1 to P0.9 excepted - are kept at CMOS input levels (Vil = xVSS 0.3 V and Vih = xVDD 0.3 V), the supply currents will only amount to leakage and the requirement of the enabled oscillator(s) and the slow-clocked RTC and Polling Modules. To exit IDLE mode, the previously configured Wake source has to switch. Immediately a Wake Reset sequence will be started internally, that pulls the RESETQ pin low and
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Table 4-3: Power Saving Modes and related functionality vs. CPU-Active Modes
Operating Mode Modules which can be activated: SRAM, CAN-RAM data retained Port Registers state retained Available Wake Sources Wake Ports Wake Ports and RTC
Power Saving Modes
WAKE IDLE
- Port Wake Module all WAKE Mode modules plus: - 4 ... 12 MHz XTAL and/or 20..50 k RC Oscillator - Real-Time Clock - Polling Module in principle all, for limitations see Table 4-2
CPU-Active Modes
active
active
Wake sources usable as interrupt
4.3. Clock System
This IC contains a quartz oscillator circuit that only requires external connection of a quartz and of 2 oscillation capacitors. The XTAL Oscillator generates a 4 to 12 MHz reference signal from an external quartz resonator, cf. section "Electrical characteristics" for quartz data. A reset sets the module to START-UP mode, where, at the expense of a higher current consumption, marginal quartzes receive more drive to ease start-up of oscillation. After start-up of the CPU program, register SR3.XTAL may be cleared by SW to set the XTAL Oscillator to RUN mode, where current consumption is at its standard level. Switching between START-UP and RUN modes must not be done @ FQUARZ >= 10 MHz or with the ERM active, as this might lead to unpredictable behavior of the clock system. This module is permanently active except during power saving mode, where continued operation may be selected in register OSC.XM.
Divider Chain
fXTAL = 4 ... 12MHz
XTAL Oscillator
SR1.CPUFST '1' PH2 1/256 '0'
SR3.FCLO = '1' VDD f0 f1
Table 4-4: Operating Mode Selection and Effect on Clocks
SR1.CPUFST Operating Mode PH2 f0
f2 f3 f4
. . .
Peripheral Modules
SR3.FCLO
SR3.WAID
fn
0 1 0 1
0 0 1 0
0 0 0 1
SLOW FAST DEEP SLOW WAKE/ IDLE
fXTAL/256 fXTAL fXTAL/256 VDD
fXTAL fXTAL f0 to f4 = VDD VDD
Fig. 4-2: Clock System
The oscillator clock drives a system clock divider that supplies the various modules with its specific clock. Module clock selection is software-defined in some cases, hardware or HW option-defined in other cases. The module descriptions give details.
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Section "HW Options" gives details about HW option controlled clocks, their selection and their activation. Note that specifying 1/1.5 and 1/2.5 prescaled clocks results in clock signals with 33%, respectively 20% duty factor. Two Clock Output signals CO0 and CO1 provide external visibility of internal clocks. CO0
CO0SEL.CO00, CO0SEL.CO01 HW Options F1Mux0 F1Mux1 F1Mux2 F1Mux3 HW Option Clock Out1 FFAC [4:0] SMXout
2 2
PRELIMINARY DATA SHEET
Table 4-5: HW Options and Ports
Signal HW Options Item CO0 Prescaler FMux0 FMux1 FMux2 Address FFABh FFABh FFB2h FFB3h FFB6h FFACh FFACh CO1 output U3.1 or U5.0 special out Initialization Item CO0 output Setting U5.5 special out
HW Option FFAB [6:5]
2
HW Option
4:1 Mux
1/1 1/1.5 1/2.5
CO0 CO0 Interrupt Source
FMux3 CO1 CO1 Prescaler Clock Out SMX Out
2:1 Mux
1/1 1/1.5 1/2.5
CO1 CO1 Interrupt Source
CO1SEL.CO10
HW Option Clock Out1 FFAC [6:5]
CO0SEL
7 6
x x
Clock Out 0 Selection
5
x x
4
x x
3
x x
2
x x
1
CO01 0
0
CO00 0 Res
Fig. 4-3: Clock Outputs Diagram
Signal CO0 is the output of a prescaler and a 4 to 1 multiplexer. Prescaler and input for the multiplexer are selectable by HW options (see Table 4-5). The output selection of the multiplexer is done by register CO0SEL, bits CO01 and CO00. The outputs of the prescalers are fed not only to the ports, but may also serve as interrupt source. The U-Ports assigned to function as clock outputs (see Table 4-5) have to be configured Special Out. The interrupt source output of this module is routed to the Interrupt Controller logic. But this does not necessarily select it as input to the Interrupt Controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. CO0 and CO1 are not affected by CPU SLOW mode.
w
x x
CO00, CO01 Clock Out Bit 0 and 1 w: Clock selection
Table 4-6: Clock Out 0 Selection
CO01 0 0 1 1 CO00 0 1 0 1 F1Mux0 F1Mux1 F1Mux2 F1Mux3
CO1SEL
7
w x x
Clock Out 1 Selection
6
x x
5
x x
4
x x
3
x x
2
x x
1
x x
0
CO10 0 Res
CO10 w0: w 1:
WAKE/IDLE Clock Out SMX Out
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PRELIMINARY DATA SHEET
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4.4. EMI Reduction Module (ERM)
The EMI Reduction Module distributes the electromagnetic energy radiated from VLSI embedded controllers among many spectral lines in the frequency spectrum. The module performs modulation of the quartz clock phase by selecting delay taps in a delay-locked loop in a pseudo random manner, to arrive at the system clock. The individual system clock edges thus appear delayed by pseudo randomly selected time values ranging from 0% to 10% of the quartz signal cycle length. Differening from PLL-based EMI reduction devices, the maximum dislocation of a system clock edge from its quartz reference is only +10% of the quartz signal cycle length. Due to its inherent frequency stability the module is fully applicable to ICs containing clocks, timers and synchronous communication links to other systems, e.g., CAN interfaces. Features - Reduction of Clock Related Electromagnetic Interference - DLL-Based Modulation of Clock Phase - Full Quartz Frequency Stability - Maximum Clock Edge Dislocation +10% of Cycle
Delay Locked Loop
1 2 3 13 14 15 16 71
t
delay
t
t
t
t
t
t
t
SR.ERM
enable
Control
clk Random Number Generator 1 3 2 3 4 5 6 7 8
8:1 MUX
modulated 1 clock
XTAL1
system clock 0
ERMC.CLKSEL
Fig. 4-4: Block Diagram 4.4.1. Principle of Operation 4.4.2. General Remarks
The edges of the input clock are discretely delayed by 1/71 to 15/71 (21.1%) of the low time of a clock cycle (see Fig. 4- 5). The selection of the clock edge is done by means of a pseudo-random sequence. The integral parts of the ERM are the Delay Locked Loop (DLL) and the Random Number Generator (RNG). The DLL consists of a chain of 71 controllable delay elements. Within a locked loop, the total delay time of the chain is controlled to equal the low time of the input clock. To
reduce the influence of supply noise the DLL is operated on AVDD. The RNG generates a sequence of pseudo-random values. Three bits serve to select one output from the first eight delay elements. The selected output represents the modulated clock. The selection of the three bits achieves a "high randomness" even for short time intervals. In the worst case the same output is selected three times in succession.
4.4.3. Initialization
After Reset the EMI Reduction Module is in standby mode (inactive). In standby mode, all internal registers are reset. Setting the standby bit SR1.ERM activates the ERM.
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Before entering operation, a setup time of at least 100 s has to elapse.
PRELIMINARY DATA SHEET
- The output timepoint of clocked output signals is modulated as well. - The sampling time of an ADC is modulated slightly.
4.4.4. Operation
Setting register ERMC to 01h immediately selects the phase modulated clock as system clock. Flag ERMC.CLKSEL is readable and indicates the busy state.
4.4.7. Results of Application
According to product spectrum measurements of supply current and electromagnetic radiation, the EMI Reduction Module is capable of reducing the energy in spectral lines of the frequency spectrum which occur on multiples of the oscillator frequency. The ERM distributes the spectral energy contained in oscillator harmonics over the spectrum between them. Thus the noise level is increased by a slight 1 to 2 dB. The higher the share of system events that are in synchronism with the oscillator (current peaks due to clocking in digital circuits), the more distinct the reduction in the spectrum. The reduction takes effect from the 6th oscillator harmonic up, and reaches values from 6 to12 dB over a wide range of frequencies.
4.4.5. Inactivation
To deactivate the ERM first deselect the modulated clock by resetting register ERMC to 00h. Then SR1.ERM may be reset to return the whole module to standby mode.
4.4.6. Precautions
For all modules using the modulated system clock or derived clocks, the following facts have to be kept in mind: - The maximum operating frequency is reduced. - The sampling time point of clocked inputs is modulated. For this reason, e.g., a CAN or UART module may appear less failure-tolerant.
OSCCLK
OSCCLKM
1/71
15/71 (21,1 %) 100 %
1/71
15/71 (21,1 %) 100 %
Fig. 4-5: Timing of modulated clock 4.4.8. Registers
ERMC
7
r w x x x
EMI Reduction Module Control Register
6
x x x
5
x 0 0
4
x 0 0
3
x 0 1
2
x 0 0
1
x 0 0
0
CLKSEL CLKSEL 0 Res
CLKSELClock Select r/w0:System clock is unmodulated r/w1:System clock is modulated Other bits in this register are used for test purposes. They must all be written to zero for proper operation.
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5. Memory and Boot System
5.1. RAM and ROM
On-chip RAM is composed of static RAM cells. It is protected against disturbances during reset as long as the specified operating voltages are available. The boot ROM contains up to 2 KB of firmware boot code. The functionality is described in section Boot System. The 100PQFP Multi Chip Module also contains a 256 KB Flash EEPROM of the AMD Am29F200AB type (bottom boot configuration) or Am29F200AT type (top boot configuration). These devices exhibit electrical byte program and sector erase functions. Erase sectors are of various sizes (Fig. 5- 1). Refer to the AMD data sheet for details. Future mask ROM derivatives will contain no Boot ROM and may be specified to contain less internal RAM and ROM than this IC. RAM will always grow upwards from physical address 000000h. ROM will grow down from 00FFFFh to 002000h and then upwards from 010000h.
Table 5-1: Reserved (physical) Addresses
Addresses 00FFA0 - C3 00FFC4 - E3 00FFE4 - E5 00FFE6 - E7 00FFE8 - E9 00FFEA - EB 00FFEC - ED 00FFEE - EF 00FFF0 - F1 00FFF2 00FFF3 00FFF4 - F5 00FFF6 - F7 00FFF8 - F9 00FFFA - FB 00FFFC - FD 00FFFE - FF
*)
Mode *) Emu & Native Emu & Native Native only Native only Native only Native only Emu & Native Native only Emu & Native Emu & Native Emu & Native Emu only Emu & Native Emu only Emu only Emu & Native Emu only
Usage HW Options Interrupt Controller Vectors (reserved) COP BRK ABORT NMI (expanded by Interrupt Controller) reserved IRQ Manufacturer ROM Identification reserved Control word (reserved) COP reserved ABORT NMI (expanded by Interrupt Controller) RESET IRQ/BRK
5.1.1. Address Map
depends on setting of processor status flag E: Emulation mode: E=1 Native mode: E=0
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CDC16xxF-E
PRELIMINARY DATA SHEET
phys.addr. 000000
EMU CPGA177
6KB RAM
Bottom Boot Config.
MCM PQFP100
6KB RAM
Top Boot Config.
MCM PQFP100
6KB RAM
Alternative
log.addr. 0000
Native
log.addr. 000000
001800
Reserved
001900 001A00 001B00 001C00 001D00 001E00 001F00 002000
Reserved CAN2-RAM CAN1-RAM CAN0-RAM CAN-Regs Ext. I/O I/O-Reg1
Reserved CAN2-RAM CAN1-RAM CAN0-RAM CAN-Regs Ext. I/O I/O-Reg1
reserved
CAN2-RAM CAN1-RAM CAN0-RAM CAN-Regs Ext. I/O I/O-Reg1
Bank 0 Bank 0
I/O-Reg0
I/O-Reg0
Sector 0, upper 8 KB
I/O-Reg0
Sector 0, upper 56 KB
004000
Sector 1, 8 KB
006000
Sector 2, 8 KB 7FFF 8000 FFA0 Reserved Addr.
008000 F800 Boot ROM 010000
Sector 3, 32 KB Boot ROM Sector 4, 64k Boot ROM Sector 1, 64k
Bank 1
FFFF 8000 00FFFF 010000
Bank 2
018000
256KB Flash EEPROM
256KB Flash EEPROM
FFFF 8000
Bank 1
Bank 3
020000 Sector 5, 64 KB Sector 2, 64 KB FFFF 8000 01FFFF 020000
Bank 4
028000 FFFF 8000
Bank 2
Bank 5
030000 Sector 6, 64 KB Sector 3, 32 KB FFFF 8000 02FFFF 030000
Bank 6
038000 Sector 4, 8 KB Sector 5, 8 KB Sector 6, 16 KB 040000 Sector 0, lower 8 KB Sector 0, lower 8 KB Flash Boot Loader FFFF 8000
Bank 3
Bank 7
FFFF 8000 03FFFF 040000
Bank 8
9FFF
Bank 4
041FFF
042000
mirrored Flash EEPROM
FFFFFF
mirrored Flash EEPROM
Fig. 5-1: Address Map
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PRELIMINARY DATA SHEET
CDC16xxF-E
5.2. Memory Banking
The 24-bit address bus of the 65C816 CPU allows access to 16 MB of memory space. The upper 8 bits of the addresses are delivered as bank address, which is multiplexed with the data value on the internal data/address lines of the CPU. This kind of native banking is supported by the 65C816 internal bank registers (PBR, DBR) by using the processor's native 16-bit instruction set. The CPU may be used to emulate the behavior of the 8-bit processor W65C02. This CPU only allows access to 64 KB of memory space. To allow access to the expanded memory range above 64 KB, an alternative banking logic is implemented.
*D0 ... D7
Alternative Banking Register
Alternative Banking Mode = ABM
ABA0 ... ABA7 MSB = '0' on A15 ... A23 A15 ... A23
modified 65C816
*DBA0 ... DBA7
Native Bank Latch
off NBA0 ... NBA7 LSB = *AD15
Interrupt Controller, DMA Logic
A0 ... A14
Address Decoder, Memory, I/O
A0 ... A14
*AD15 AD0 ... AD14 *Processor internal Bus
Fig. 5-2: Block diagram Memory Banking
The banking mode is toggled with flag ABM of the SR2 register: ABM = '0': Native Banking mode (default after RESET), ABM = '1': Alternative Banking mode. The alternative bank no. is programmed in the Alternative Banking Register = ABR. By setting ABM to "1" the native banking mode is switched off, and the alternative banking mode is activated instead.
5.2.2. Alternative Banking Mode
To use the CPU with the 8-bit instruction set of the 65(C)02 and reaching more than the addressable 64 KB, a specific banking hardware is implemented: The physical address range above 32 KB is separated into several banks of which only one at a time is enabled and selected by the 8-bit ABR (Alternative Banking Register), which is programmable like any other standard 8-bit peripheral register by writing the desired value into its specific address. The contents of the ABR are also readable, so the software may check the current bank at any time. The applied software is responsible for programming the ABR with the correct bank number at the right time. Since the upper 32 KB range is switched immediately after programming the ABR, correct function is not guaranteed if its changed by a program sequence running in a switched bank. ABR settings need to be done in the lower 32 KB, which is the non-switchable master bank, resp., alternative bank number 0. With ABR = 0, the lower 32 KB appear as bank 0 in the upper address range, so bank 0 is identical to the non-switchable master bank. Be careful when operating bank 0 in the upper 32 KB area. RAM, I/O pages and reserved addresses may be manipulated unintentionally. RESET initializes ABR = 1, so as to have control byte and reset vector in the same physical addresses as with active native banking mode. Also Interrupt vectors have to reside in
5.2.1. Native Banking Mode
The bank address is present on the 65C816 data/address lines during the first half of each processor bus cycle. To get the whole address bus available during the second half of the bus cycles, the bank address is demultiplexed with a transparent latch, triggered with the processor clock, PHI2(in). This mode is supported by the native instruction set since it supports the CPU's internal bank registers PBR and DBR, which values are multiplexed on the data/address lines, no matter if the processor is running in native or emulation mode. If the internal bank registers are not supplied, e.g., if only the 8-bit instruction set is applied, the address range is limited to 64 KB, the size of one Native Bank, because the banking registers keep their initial 0-values which they get during RESET. After RESET the native banking mode is active and the whole 65C816 address range of 24 bits is available.
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CDC16xxF-E
the alternative bank number 1, because the interrupt controller generates the appropriate address of bank 1, but does not change the contents of the ABR. Interrupt functions have to reside in the non-switchable master bank (alternative bank 0). Otherwise they need to be in each used bank, as after getting the vector, the unchanged contents of the ABR determine the current bank which is valid if A15 is "1". After RESET the alternative banking mode is inactive. By setting ABM to "1", the alternative banking mode is switched on.
PRELIMINARY DATA SHEET
ABR
7
r/w 0 0
Alternative Banking Register
6 5 4 3 2 1 0
Alternative Bank Address 0 0 0 0 0 1 Res
5.2.3. Memory Banking Mode Selection
In the Native Banking Mode the logical address range is identical to the physical one. In the Alternative Banking Mode A15 is lost, because a non-switched address range is necessary. This cuts the addressable space in half. To retain the physical address range without holes as is in Native Banking Mode, the addresses are multiplexed.
ABM '0' NBA7 ABA7 NBA6 ABA6 NBA5 ABA5 NBA4 ABA4 NBA3 ABA3 NBA2 ABA2 NBA1 ABA1 NBA0 ABA0 AD15 A23
A22
A21
A20
A19
A18
A17
A16
A15
Fig. 5-3: Physical Address change depending on the Banking Mode
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PRELIMINARY DATA SHEET
CDC16xxF-E
Banking Cross Reference
FF0000H ....... 7F0000H ....... 20000H 10000H 0H
Native Banking
Alternative Banking
Native Bank 255
......
Native Bank 127
......
Alternative Bank 254 *
Native Bank 2 0H 0H
Native Bank 1
Native Bank 0 Alternative Bank 4 *
( not reachable as Alternative Bank )
( not reachable as Alternative Bank )
Native Bank 2
Alternative Bank 255
Alternative Bank 5
Alternative Bank 3
Alternative Bank 3
Alternative Bank 1
FFFFH
FFFFH
FFFFH
* The logical address range is 8000H ... FFFFH Native Banks: logical addresses = physical addresses Alternative Banks: logical address range = 8000H ... FFFFH
Fig. 5-4: Banking Map shown with the max. size of addressable memory (different from the implemented amount)
Micronas
Alternative Bank 1
Alternative Bank 2
Alternative Bank 255
8000H
Native Bank 0
Native Bank 1
Native Bank 255
.......
8000H
........
( also Alternative Bank 0 * )
Alternative Bank 0 *
Alternative Bank 2 *
........
.......
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5.3. Boot System
The Boot System offers a very flexible method for the controller to receive and store data and programs, no matter if the Flash memory contains a working or faulty application, or no application at all. With the Boot System it is possible to fill the RAM with data and functions and to start execution from any address. Tasks like flash programming and diagnostic routines may be downloaded and started, either in lab, factory or in system. After RESET, the CPU executes code from the Boot ROM. Its firmware, the Boot Loader, checks whether the application software in the flash memory must be started or if data must be downloaded via one of 6 receivers: 3 UARTs and 3 CANs.
PRELIMINARY DATA SHEET
RAM
RESET
Boot ROM
Start
Termination
Boot Loader
no data to receive ? yes
Download
5.3.1. Principle of operation
After RESET the Boot ROM is active, if the Test pin is left vacant or connected to ground. The Boot Loader is started and checks whether there is a wake-up from Power Saving Mode (see Table 6-7 on page 53), i. e., if CSW2.WKID is set. If so, it starts the application software in Flash Memory (or ROM). Otherwise, it tries to detect a download condition. If no appropriate data can be received via either of its 6 interface receivers within a predefined time, the Boot Loader terminates itself by copying a program sequence into the RAM and executing it. This software part switches the Boot ROM off and starts the application software assumed within the Flash Memory. The detour via RAM is necessary because the Boot ROM hides the start-up address area of the flash memory that contains the processor Control Word and RESET Vector of the application. When detecting a download condition, the time-out condition to terminate the boot sequence is extended with the detection of every new appropriate data until the download is completed. The Boot Loader jumps to a start address, which is assumed part of the code-header downloaded before. Neither the Boot ROM is switched off, nor the Control Word or RESET Vector of the flash memory are treated automatically if a download occurs. This leaves a maximum of flexibility during and after the boot procedure.
start at downloaded address
Flash ROM
Start
Application
Fig. 5-5: Principle of the boot system
CR.IROM CR.FLASH
& &
Application enable enable RESET Vector Control Word Interrupt Vectors
5.3.2. The Boot ROM
The 2 kB Boot ROM covers the address range from 0F800H to 0FFFFH. With Test pin left vacant or pulled to low level at RESET, the Control Word is read out of the Boot ROM and copied into the Control Register. With the flag FLASH of the Control Register set to '0' the Boot ROM stays switched on and its control program, the Boot Loader, is started. In a standard application (no download request) the control program in the flash memory is started after the Boot Loader has set the flag FLASH in the Control Register to '1' to switch the Boot ROM off at the appropriate time, which enables the Flash ROM in the same address range as the Boot ROM before.
RESET Vector Control Word Interrupt Vectors
Boot ROM
Flash ROM
Start application or downloaded code
RAM
affected by SW affected by HW
Fig. 5-6: Boot ROM Selection
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PRELIMINARY DATA SHEET
CDC16xxF-E
5.3.3. The Boot Loader
RESET
yes
CSW2.WKID = '1'
no init. Watchdog
init. UART and CAN receivers refresh Watchdog init time-out = 6ms @ fXTAL = 8 MHz refresh Watchdog
Download Header
no
yes
Data Length
no
yes
Boot Identifier
no no
yes
Boot Identifier
yes no
no
download data
time-out
yes
time-out
yes
no
time-out
yes
reset UART and CAN interfaces
Application
force RESET
Start downloaded code
Fig. 5-7: Boot Loader flow-chart
During the first 480000 clock cycles (= 6 ms at 8 MHz processor clock) after reset, the Boot Loader tries to detect a start of the download condition, the so-called Boot Identifier, at one of the receivers of the 3 UARTs and 3 CANs. If the complete Boot Identifier has been received within the appropriate time, the watchdog is initialized (with the value 6 for effective 6.144 ms at fXTAL = 8 MHz) to supervise further time-out conditions. This is not only to increase security, but also because the Boot Loader could have been started by a reset other than power-on, from a running application in which the watchdog was programmed before. Therefore the Boot Loader has to program it, too, otherwise it generates a reset after the max. WD time-off, which is default after reset. Within further time-out conditions additional Boot Identifiers may occur, followed by the Download Header and the Download Data including separate Check Sums. At the end of the procedure the processor executes a jump to the start address which is part of the Download Header. If a time-out condition is met, an unexpected byte has been received or if a Check Sum error occurs, a reset is forced by the watchdog to start the Boot Loader again. This subsequently will start the application because of absence of the Boot Identifier. If the Boot Loader does not detect the Boot Identifier within the time limit, the application software assumed in the Flash ROM is started. For this purpose a software part is copied into RAM and started. It toggles the flag FLASH of the Processor Control Register to switch the BOOT ROM off and reads the Control Word out of the Flash ROM, which is accessible now, and programs the processor's Control Register with that value. Last, it starts the application by a jump to the address defined in the RESET Vector of the Flash ROM. The application can program its own watchdog value, as it was not treated by the Boot Loader before.
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5.3.4. Used Resources
5.3.4.1. RAM The Boot Loader uses and thus overwrites the contents of addresses 200H to 20DH in any case, i. e. also if CSW2.WKID is set, which means that there is a wake-up from Power Saving Mode (see Table 6-7 on page 53). If no wake-up is detected, zero page addresses F5H to FFH and stack page addresses 100H to 10AH and 1E8H to 1FFH are used in addition. 5.3.4.2. Watchdog The Boot Loader restores the RESET states of used modules before it ends, but the once programmed watchdog can not be disabled again. The watchdog gets initialized after the Boot Loader has been started by a RESET that was no wake-up, but not before the Boot Identifier has been detected (as shown in "Fig. 5-7 Boot Loader flow-chart"). Downloaded programs have to refresh the watchdog correspondingly (see "5.3.6. Interface Protocol" for details).
PRELIMINARY DATA SHEET
UART and CAN busses work asynchronously, target response would result in bus collisions.
5.3.6. Interface Protocol
The interface protocol falls into three sections: 1. Boot Identifier. It is continuously transmitted by the host. After reset, the Boot Loader waits for the Boot Identifier. 2. Download Header. It contains the start address, target address and data length. 3. Download Data. After the Download Header, the announced number of data bytes are transmitted by the host. The first byte is stored in the address defined in target address, the next one in target address + 1, and so on. After reception of the last byte the processor immediately executes a jump to the address in start address. Because the watchdog is treated during download, the downloaded program must also refresh it with the same value (= 6 for effective 6.144 ms at fXTAL = 8 MHz), starting with 06H, followed by its complement 0F9H, 06H, 0F9H, ... and so on. No more than 6 ms (at fXTAL = 8 MHz) delay is allowed as delay between the single telegrams during boot identification and download, otherwise the Boot Loader stops reception and starts the application in Flash. Time-out value (6 ms) and baud rate of UART and CAN relate to the processor clock (fXTAL). As start of a download, the host has to keep generating Boot Identifiers while the targets get a reset. After a minimum of time, when the target running is stable, the host sends the Download Header, followed by the Download Data.
5.3.5. Interfacing to a Download Source
Either one of the UARTs or CANs can be used to activate a download. The Boot Loader assumes a single-bus line as connection to the host. So either wired-or Rx/Tx interfaces or separate driver circuits may be used. To allow download to several targets connected to the same bus, the Boot Loader does not generate a receipt. Since the 5.3.6.1. UART Protocol and Timing
Boot Identifier to Rx or or A3H 26H D6H 26H D6H A3H to D6H A3H 26H to A3H 26H D6H
n bytes of Boot Identifier in correct order to 26H D6H A3H to D6H A3H 26H to A3H
Download Header, Data to SOH to to
RESET
to <= 6ms @ fXTAL = 8 MHz
Fig. 5-8: UART Timing
The expected telegram format is: 1 Start bit, 8 Data bits, 1 even parity bit and 1 Stop bit at a rate of 9600Bd at 8 MHz processor clock. To use standard K-bus drivers the UART transmitter inverters are switched on. Boot Identifier After reset the Boot Loader tries to detect the Boot ID which consists out of 3 bytes with the values 26H, D6H and A3H respectively, of which each is expected within 6 ms (at fXTAL = 8 MHz) after the preceding one. The telegram may start with any value out of this queue, but the bytes have to appear in the right order. Any other value or the event of a bigger delay being detected, stops the Boot ID detection and starts the application. Download Header The Download Header has to follow the last byte of the Boot ID, the A3H, and starts with an ASCII SOH = 01H. It is followed by the start and target addresses of the download program and its length as 16-bit values of which the low bytes are transmitted first. The Download Header terminates with a 16-bit Check Sum, low byte transmitted first, which is the 2's complement of the sum, calculated from SOH up to and
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PRELIMINARY DATA SHEET
CDC16xxF-E
Download Data As many data bytes as defined in Data Length are expected, plus a 16-bit Check Sum, low byte transmitted first, which is the 2's complement of the sum, calculated over all data. The sum of all bytes (including the Check Sum) should be zero.
including Data Length. The sum of all bytes in the Download Header (including the Check Sum) should be zero.
Table 5-2: Download Header
Field SOH Start Address Target Address Data Length Size 8 bit 16 bit 16 bit 16 bit Meaning start of Download Header Boot Loader jumps to this address after download. Boot Loader writes data to this address. Number of data bytes transmitted after Download Header (Check Sum excluded). 16-bit Check Sum from SOH to data length
Check Sum
16 bit
5.3.6.2. CAN Protocol and Timing
Boot Identifier to Rx 7FF 7FF
DLC = 0
n Boot Identifiers to 7FF
DLC = 0
Download Header to 627
DLC = 6
Download Data to 626
DLC = 1 ... 8
Download Data to 626
DLC = 1 ... 8
RESET
to <= 6ms @ fXTAL = 8 MHz
Fig. 5-9: CAN Timing
The Boot Loader expects CAN telegrams in standard format (11 bit identifier) at a bit rate of 125kBd at 8 MHz processor clock with control parameters set as follows: BPR = 7, TSEG1 = 3, TSEG2 = 2, SJW = 3, rx not inverted. Boot Identifier (ID = 7FFH, DLC = 0) After reset the Boot Loader expects the Boot Identifier within 6ms (@ fXTAL = 8 MHz), what consists out of a telegram with ID = 7FFH and DLC = 0. As the transmitter is not active, at least one additional working CAN node has to work correctly on the bus, to generate the CAN bus acknowledge bits! If the Boot ID can not be detected in time, the Boot Loader starts the application. Download Header (ID = 627H, DLC = 6) The Download Header telegram has to follow within 6 ms (@ fXTAL = 8 MHz) after the Boot ID. It contains the start and
target addresses of the download program and its length as 16-bit values with low bytes first.
Table 5-3: Download Header
Field Start Address Target Address Data Length Size 16 bit 16 bit 16 bit Meaning Boot Loader jumps to this address after download. Boot Loader writes data to this address. Number of data bytes transmitted after Download Header (Check Sum excluded).
Download Data (ID = 626H, DLC = 1 ... 8) As many data bytes as defined in Data Length are expected, plus a 16-bit Check Sum, low byte transmitted first, which is the 2's complement of the sum, calculated over all data. The sum of all bytes (including the Check Sum) should be zero.
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6. Core Logic
PRELIMINARY DATA SHEET
6.1. Control Register CR
The Control Register CR serves to configure the ways, by which certain system resources are accessed during operation. The main purpose is to obtain a variable system configuration during IC test. Upon each HIGH transition on the RESETQ pin internal hardware reads data from address location 00FFF3h and stores it to the CR. The state of the TEST and ESTOPCLK pins at this point in time, specifies which program storage source is accessed for this read. MFM Multifunction pin Mode (Tables 6-2 and 6-3)
Table 6-2: TSTTOG and MFM usage in mask ROM parts
TSTTOG 0 1 MFM 0 0 TEST pin x 0 1 x 1 x Multifunction Pins Bus mode Bus mode normal mode normal mode
Table 6-1: Control byte source
TEST 0 or NC 1 Control byte source internal BOOT ROM (standard for stand-alone operation) external via Multifunction pins in Bus mode (for test purposes only)
Table 6-3: TSTTOG, EBTRI and MFM usage in Flash and
EMU parts TSTTOG 0 1 EBT RI x x MFM TEST pin x 0 1 x 0 1 1 x Multifunction Pins Bus mode Bus mode normal mode normal mode Eulator mode Flash mode TestROM (Table 6-4) FLASH EEPROM (Table 6-5) Internal ROM (Tables 6-4 and 6-5) Emulator Bus Pins Flash mode Flash mode
The system will thus start up according to the configuration defined in address location 00FFF3h, automatically copied to register CR.
0 0
CR
7 6
Control Register
5
x
4
MFM MFM
3
2
1
IRAM IRAM
0
ICPU ICPU ROM Emu Res
r/w RESLNG TSTTOG
TSTROM IROM FLASH IROM
r/w RESLNG TSTTOG EBTRI
Value of 00FFF3h
RESLNG Reset Pulse Length r/w1: Pulse length is 16/FXTAL r/w0: Pulse length is 4096/FXTAL This bit specifies the length of the reset pulse which is output at pin RESETQ following an internal reset. If pin TEST is 1 the first reset after power on is short. The following resets are as programmed by RESLNG. If pin TEST is 0 all resets are long. TSTTOG TEST Pin Toggle (Tables 6-2 and 6-3) This bit is used for test purposes only. If TSTTOG is true in IC active mode, pin TEST can toggle the multifunction pins between Bus mode and normal mode. EBTRI Emulator Data Bus Tristate (Table 6-3)
TSTROM FLASH IROM
Table 6-4: TSTROM and IROM usage in mask ROM parts
TSTROM 1 0 x 0 IROM 1 selected program storage internal ROM internal TestROM external via Multifunction pins in Bus mode
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PRELIMINARY DATA SHEET
CDC16xxF-E
ICPU r/w1: r/w0: Internal CPU Enable internal CPU. Disable internal CPU.
Table 6-5: FLASH and IROM usage in FLASH and EMU
parts FLASH 1 0 x 0 IROM 1 selected program storage internal FLASH EEPROM resp. Emulator Bus internal BOOT ROM external via Multifunction pins in Bus mode
Table 6-6: Some commonly used settings for address location 00FFF3h. A copy is automatically transferred to the CR during IC start-up.
Code FFh ABh DFh TEST Pin 0 1 0 Operation Mode Stand-alone with internal ROM or Flash External program storage connected to Multifunction pins in Bus mode Emulator mode (CPGA177 package)
IRAM r/w1: r/w0:
Internal RAM Enable internal RAM. Disable internal RAM.
6.2. Reset Logic
6.2.1. Alarm Function
An alarm comparator on the pin RESETQ allows the detection of a threshold higher than the reset threshold. An alarm interrupt can be triggered with the output of this comparator. The interrupt source output of this module is routed to the Interrupt Controller logic. But this does not necessarily select it as input to the Interrupt Controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. The intended use of this function is made, when a system uses a 5 V regulator with an unregulated input. In this case, the unregulated input, scaled down by a resistive divider, is fed to the RESETQ pin. With falling regulator input voltage this alarm interrupt is triggered first. Then the reset threshold is reached and the IC is reset before the regulator drops out. The time interval between the occurrence of the alarm interrupt and the reset may be used to save process data to nonvolatile memory. In addition, power saving steps like turning off stepper motor drivers may be taken to increase the time interval until reset. The alarm interrupt is a level triggered interrupt. The interrupt is active as long as the voltage on pin RESETQ remains between the two thresholds of alarm and reset (see Fig. 6-1 on page 50). As long as the reset input comparator on the pin RESETQ detects the low level, all IC registers are held in reset state. 6.2.2.1. Supply Supervision An internal bandgap reference voltage is compared to VDD. A VDD level below the Supply Supervision threshold VREFPOR will permanently pull the pin RESETQ low and thus hold the IC in reset (see Fig. 6-2 on page 51). With HW Option FFB8h, bit6 = 0, this reset source can be enabled/disabled by flag CMA in register CSW0 (see Section 6.2.2.2. on page 49). 6.2.2.2. Clock Supervision The Clock Supervision monitors the frequency at the oscillator input XTAL1. A frequency level below the clock supervision threshold of fSUP (see chapter 3.3.Characteristics) will permanently pull the pin RESETQ low and thus hold the IC in reset (see Fig. 6-2 on page 51). With HW Option FFB8h, bit6 = 0, this reset source can be enabled/disabled by flag CMA in register CSW0. A frequency exceeding the specified IC frequency is not detected. There are two general operation options which can be selected in the HW Options field (address FFB8h): 1. Bit6 = 1: Clock and Supply Supervision are permanently active. They can not be deactivated. The Watchdog must be serviced by SW. This mode is recommended for all stand-alone applications requiring high operational reliability. 2. Bit6 = 0: Clock and Supply Supervision are active after reset, but can be enabled/disabled by the clock monitor active flag CMA of register CSW0. The Watchdog must be serviced only after a first write access to register CSW1. This mode is recommended for test and evaluation purposes only.
6.2.2. Internal Reset Sources
This IC contains three internal circuits that are able to generate a system reset: watchdog, supply supervision and clock supervision. All three internal resets are directed to the open drain output of pin RESETQ. Thus a "wired or" combination with external reset sources is possible. The RESETQ pin is current limited and therefore large external capacitances may be connected. All internal reset sources initially set a reset request flag. This flag activates the pull-down transistor on the RESETQ pin. An internal reset prolongation counter starts, as soon as no internal reset source is active any more. It counts 4096 FXTAL periods (for alternative settings refer to register CR) and then resets the reset request flag, thus releasing the RESETQ pin.
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CDC16xxF-E
PRELIMINARY DATA SHEET
VBG SR3.WAID 1
1,25V 10% en VBG Generator
VDD
RESETQ
VREFA
en
+
ALARM Comp.
RESET/ ALARM Interrupt Source
VREFR
en
+
RES
RESET Comp.
VREFPOR
en
+ -
POR
Supply Supervision UVDD SR0.LCD en + + LCD Supply VSS XTAL1 SR3.XTAL DBG.DSC OSC.XM '1' OSCCLK '0' VDD 1 ON 1 en run XTAL Oscillator XTAL2 RTCCLK
2/ 3UVDD
1/
3UVDD
Fig. 6-1: Analog core logic block diagram
6.2.2.3. RESET Comparator During power saving mode, the comparator function is not available and is bypassed by a simple CMOS Schmitt input. Full CMOS levels are thus required on this input in this mode.
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PRELIMINARY DATA SHEET
CDC16xxF-E
DBG.DCS SR3.WAID
& 1
VREFR + RES core reset port reset
&
RESETQ Reset extension 16 or 4096 fXTAL clocks
&
WAKE_RES reset in HW option CSW0.CMA VDD fXTAL fSUP POR wr CSW2 wr CSW2.FHR
D R Q
WDRES Watchdog
>1
RESIR
SQ R
0 1
clock supervision
1
& CLS
SR3.WAID
& 1
RESINTOUT
power on
&
1
res CSW2
core reset
wr CSW1
&
SQ R SQ R SQ R SQ R SQ R
CSW2.FHR CSW2.CLM CSW2.POR CSW2.PIN CSW2.WKID
1
SQ R CSW1.WDRES
Fig. 6-2: Reset Logic Block Diagram
6.2.2.4. Watchdog The Watchdog module serves to monitor undisturbed program execution. A failure of the program to retrigger the Watchdog within a preselectable time will pull the pin RESETQ low and thus reset the IC (Fig. 6-2 and 6-3). With HW Option FFB8h, bit6 = 0, this reset source is only enabled after a write access to register CSW1 (see Section 6.2.2.2. on page 49).
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PRELIMINARY DATA SHEET
2.write & even
CSW1 Trigger Reg1
8
3.write & odd
CSW1 Trigger Reg2
8
CSW1
1. write
Timer Register
8
1. write
CPUFST=1: fosc * 2-13 CPUFST=0: fosc * 2-13 * 2-8 clk zero
=
& &
1
load
8-Bit-Counter
2.write & even 3.write & odd reset in
1
DQ C S
HW Option 1. write SQ R
&
VDD SQ R
reset out CSW1.WDRES
power on wr CSW1
1
Fig. 6-3: Watchdog Block Diagram
The Watchdog contains a down-counter that generates a reset when it wraps from zero to FFh. It is reloaded with the content of the watchdog timer register, when, on a write access to register CSW1, watchdog trigger registers 1 and 2 contain bit complemented values. An IC reset resets the watchdog timer register to FFh, thus forcing the Watchdog to create a maximum reset interval. The Watchdog is controlled by register CSW1. The first write access to it loads the timer register value setting the Watchdog's unretriggered reset interval. The desired interval can be programmed by setting the CSW1 value to: Interval x f CPU Value = ----------------------------------- - 1 8192 6.2.2.5. Forced Hardware Reset Setting flag CSW2.FHR immediately forces the RESETQ pin low. This allows the SW to restart the whole system by HW reset. 6.2.2.6. Wake-Up Reset Entering power saving mode by setting SR3.WAID sets CSW2.WKID, but does not pull RESETQ low. However, wake-up from one of the power saving modes (signal WAKE_RES in Fig. 6-2) does pull RESETQ low.
6.2.3. External Reset Sources
As long as the reset input comparator on the pin RESETQ detects the low level, the overall IC is reset. On this pin, external reset sources may be wire-ored with the IC internal reset sources, leading to a system-wide reset signal combining all system reset sources.
The resolution of the Watchdog is 8192/fCPU. The second and all following even-numbered write accesses load watchdog trigger register 1, the third and all following odd numbered write accesses load watchdog trigger register 2. In all future, the SW has to write alternatingly to register CSW1 value and bit complement value, thus retriggering the up-counter. Failure to retrigger will result in an overflow of the up-counter generating a Watchdog reset. It is not allowed to change a chosen value. Writing a wrong value to CSW1 immediately sets the flag WDRES in register CSW1 and prohibits further retriggering of the watchdog counter. WDRES is true after a Watchdog reset. Only a Supply Supervision reset or a write access to register CSW1 clears it.
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PRELIMINARY DATA SHEET
CDC16xxF-E
write a value (not necessarily the former time value) and its bit complemented value. Using other values or changing the order of both values will cause the watchdog to generate a RESET.
6.2.4. Summary of Module Reset States
After reset the IC modules are set to the reset state (Fig. 6-7)
Table 6-7: Status after Reset
Module CPU Interrupt Controller U-Ports High current ports LCD module Watchdog Status
Table 6-8: Source of last Hardware Reset
CSW1.WDRES 0 1 0 0 0 x
4
FHR FHR 0
*)CSW2.WKID
*)CSW2.CLM
CPU FAST mode (fOSC). Interrupts are disabled. Priority registers, request flip flops and stack are cleared. Normal mode. Output is tristate. Normal mode. Output is low. Registers are reset. No display.
0 0 0 0
0 0 0 0 1 x
0 0 1 1 0 x
1 1 1 1 1 1
*)CSW2.POR
Reset Source
*)CSW2.PIN
CSW2.FHR
0 0 0 1 0 x
external from RESETQ pin internal Watchdog internal Clock Supervision internal Supply Supervision internal Forced Hardware wake-up from WAKE/IDLE
Depends on mask option. EMU option: Switched off. SW activation is possible. Stand-alone option: Permanently active. Depends on mask option. EMU option: Active. SW may toggle. Stand-alone option: Permanently active.
0 1
Clock monitor
The registers sum up the source of all HW resets that occurred since the last write to register CSW2. *)Any write access to CSW2 resets these flags to 0. The RTC can not be reset.
6.2.5. Reset Registers
CSW0
7
w x x
CSW2
7 6
x x x
Clock, Supply & Watchdog Register 2
5
WKID x 0
3
CLM x 0
2
PIN x 0
1
POR x 0
0
x x x 0 0 Res*
Clock, Supply & Watchdog Register 0
r TST x TST x x x x x x 1 Res
6
x
5
x
4
x
3
x
2
x
1
x
0
w CMA
This register controls the Supply and Clock Supervision modules. CMA w1: w0: Clock and Supply Monitor Active Both Enabled. Both Disabled.
*The Reset state in the register frame above describes the state after a write to register CSW2. Refer to Table 6-8 on page 53 for the state after a hardware reset.
TST r1: r0: WKID
TEST Pin State TEST is 1. TEST is 0. Wake Reset from WAKE/IDLE Mode (Table 6-8) Forced Hardware Reset (Table 6-8) (Table 6-8) force Reset no action Clock Supervision Reset (Table 6-8) RESETQ Pin Reset (Table 6-8) Supply Supervision Reset (Table 6-8)
CSW1
7
r w 1 1 x
Clock, Supply & Watchdog Register 1
6
x
5
x
4
x
3
x
2
x
1
x
0
WDRES
Watchdog Time and Trigger Value 1 1 1 1 1 1 Res
FHR r0: r1: w1: w0: CLM PIN
This register controls the Watchdog module. Only values between 1 and 255 are allowed. WDRES Watchdog Reset Source r1: Watchdog was reset source. Any write access to CSW1 resets this flag. First write the desired watchdog time value to this register. On further writes, to retrigger the Watchdog, alternatingly
POR
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CDC16xxF-E
6.3. Standby Registers
The Standby Registers SR0, SR1, SR2 and SR3 allow the user to switch on/off power or clock supply of single modules. With these flags it is possible to greatly influence power consumption and its related electromagnetic interference. For details about enabling and disabling procedures and the standby state refer to the specific module descriptions. The minimum IC current consumption is obtained with SR0, SR1, SR2 and SR3 set to 00h. UART0 r/w1: r/w0: ADC r/w1: r/w0: P0DIN r/w1: r/w0: SR0
7
r/w SM 0
PRELIMINARY DATA SHEET
UART 0 Module active. Module off. ADC Module Module active. Module off. Port 0 Digital Input Enable digital inputs on analog ports P0.1 to P0.5 Disable digital inputs on analog ports P0.1 to P0.5. Timer 1 Module active. Module off. EMI Reduction Module Module active. Module off.
Standby Register 0
6
PWM1 0
5
PWM0 0
4
UART2 0
3
SPI1 0
2
CAN0 0
1
CCC 0
0
SPI0 0 Res
TIM1 r/w1: r/w0: ERM r/w1: r/w0:
SM r/w1: r/w0: PWM1 r/w1: r/w0: PWM0 r/w1: r/w0: UART2 r/w1: r/w0: SPI1 r/w1: r/w0: CAN0 r/w1: r/w0: CCC r/w1: r/w0: SPI0 r/w1: r/w0:
Stepper Motor Module active. Module off. Pulse Width Modulator 1 Module active. Module off. Pulse Width Modulator 0 Module active. Module off. UART 2 Module active. Module off. SPI 1 Module active. Module off. CAN Module 0 Module active. Module off. Capture Compare Counter Module active. Module off. SPI 0 Module active. Module off.
SR2
7
r/w TIM2 0
Standby Register 2
6
PWM3 0
5
PWM2 0
4
UART1 0
3
PWM4 0
2
DGB 0
1
EXTIR 0
0
ABM 0 Res
TIM2 r/w1: r/w0: PWM3 r/w1: r/w0: PWM2 r/w1: r/w0: UART1 r/w1: r/w0: PWM4 r/w1: r/w0: DGB r/w1: r/w0:
1
TIM1 0
Timer 2 Module active. Module off. Pulse Width Modulator 3 Module active. Module off. Pulse Width Modulator 2 Module active. Module off. UART 1 Module active. Module off. Pulse Width Modulator 4 Module active. Module off. DIGITbus Master Module active. Module off. External Interrupt Enable functions IRQ on pin U5.4 and ABORTQ on pin U5.5 Disable functions IRQ on pin U5.4 and ABORTQ on pin U5.5 Alternative Banking Mode Alternative Banking mode enabled Native Banking mode enabled.
SR1
7
r/w LCD 0
Standby Register 1
6 5 4
UART0 0
3
ADC 0
2
P0DIN 0
0
ERM 0 Res
CPUFST PSLW 1 0
EXTIR r/w1: r/w0: ABM r/w1: r/w0:
LCD r/w1: r/w0: CPUFST r/w1: r/w0: PSLW r/w1: r/w0:
LCD Module Module active. Module off. CPU FAST Mode FAST mode: FCPU = FXTAL SLOW mode: FCPU = FXTAL / 256 Port Slow Mode Slow mode. Fast mode.
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PRELIMINARY DATA SHEET
CDC16xxF-E
r/w 0 : r/w 1:
1
CAN2 0
SR3
7
r/w x x
Standby Register 3
6
x x
WAKE/IDLE mode off WAKE/IDLE mode on Fast Clock off Fast clock on Fast clock off CAN Module 1 Module active. Module off. CAN Module 2 Module active. Module off.
5
x x
4
XTAL 1
3
WAID 0*)
2
FCLO 0
0
CAN1 0 Res
FCLO r/w 0 : r/w 1: CAN1 r/w1: r/w0: CAN2 r/w1: r/w0:
XTAL r/w1: r/w0: WAID
Quartz Oscillator Mode Start-Up Mode active (default after Reset). Run Mode active. WAKE/IDLE *)Reset with pin reset || VDD power on
6.4. Test Registers
Test registers are for factory test only. They must not be written by the user with values other than their reset values (00h). They are valid independent of the TEST input state. In all applications where a hardware reset may not occur over long times, it is good practice to force a software reset on these registers within appropriate intervals.
TST1
7
w 0 0
Test Register 1
6 5 4 3 2 1 0
For testing purposes only 0 0 0 0 0 0 Res
TST2
7
w 0 0
Test Register 2
6 5 4 3 2 1 0
For testing purposes only 0 0 0 0 0 0 Res
TST3
7
w 0 0
Test Register 3
6 5 4 3 2 1 0
For testing purposes only 0 0 0 0 0 0 Res
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CDC16xxF-E
7. Multiplier
The Multiplier provides the following function: - Calculation of 8 bits x 8 bits = 16 bits. It is fully supported by the WDC C-compiler WDC816CC. Features - needs no wait states
PRELIMINARY DATA SHEET
- no status signals necessary to be checked separately by the application program - for the application program the result is immediately available after writing into the multiplier register - the registers for multiplicand and multiplier are not only writable but also readable
Data Bus
8 8 16
multiplier
8
multiplicand
8
product
2-bit counter
load sh2
16
double shift right
bit 10
&
8 8
8
+
SUMA[0] COA, SUMA[7:1]
&
8 8
+
SUMB[0] COB, SUMB[7:1]
clck
latch
8
Result LSByte
Result MSByte
16
Fig. 7-1: Block diagram of the multiplier
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PRELIMINARY DATA SHEET
CDC16xxF-E
7.1. Functional Description
To obtain a 16-bit product, the application program first has to write the first factor into the 8-bit multiplicand register and then the second factor into the multiplier register. Writing the multiplier starts the multiplication. The execution of the multiplication takes 4 CPU clock (PH2) cycles. CPU instructions with absolute addressing modes take at least 4 cycles to access the product register. According to this, immediately after writing into the multiplier register, the result is available for the application program.
7.2. Registers
Two 8-bit registers serve as input and a 16-bit register delivers the result: Writing into the Multiplier register starts the execution of the multiplication.
MULCAND
7
r/w x x
Multiplicand
5 4 3 2 1 0
MULPROD
7
r x x x Res r
Multiplication Product
5 4 3 2 1 0
1 0 Res Offs
6
6
multiplicand x x x
Product high byte Product low byte x
MULPLIER
7
r/w x x
Multiplier
5 4 3 2 1 0
The Product register MULPROD holds the result of the multiplication after 4 CPU clock (PH2) cycles have elapsed.
6
multiplier x x x x x x Res
7.3. Operation of the Multiplier
Since the execution of a multiplication takes less CPU cycles than an application program needs to access the result register, multiplications are done by simply writing the multiplicand followed by the multiplier and reading the product. Precautions have to be taken in application programs using the multiplier, and in application programs which may be interrupted by a service routine also using the multiplier. If the procedure of writing the multiplicand and multiplier until reading the result register is interrupted, and the interrupt service routine overwrites the multiplier input registers, the result read by the background program is wrong. To solve this problem, the multiplier input registers have to be saved before and restored after a multiplication takes place in the interrupt service routine.
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CDC16xxF-E
8. Power-Saving Module (PSM)
To reduce the power consumption one of two Power-Saving Modes (WAKE and IDLE) can be selected. Non-power-saving modes are DEEP SLOW, SLOW and FAST, which differ from Power-Saving Modes by having the CPU running instead of a stopped CPU clock during WAKE/IDLE active. Most of the core logic is switched off in a Power-Saving Mode. Only hardware necessary for WAKE/IDLE is supplied. Features
PRELIMINARY DATA SHEET
- Power reduction down to leakage current of wake mode possible - Real-Time Clock (RTC) Module - Clock source: Built-in RC oscillator or XTAL - Up to 10 edge and level triggered Wake Ports - Wake sources: RTC Module and/or Wake Ports - Polling Module for cyclic scan of the Wake Ports - Interrupt outputs of RTC Module and Port Wake Module
Polling Module enable RC Oscillator 20..50kHz 4 ... 12MHz 1 Up to ten Wake Ports Port Wake Module & RTC wake-up
H2.5 Core Logic
AVDD, UVDD Analog Sections
RTC Module
IR RTC WAKE_RES Reset Logic IR WAPI
Port wake-up
Fig. 8-1: Power-Saving Module
The major task of the Power-Saving Module is to supply a wake-up signal (WAKE_RES) for the main system or to generate an interrupt, as shown in Fig. 8-1. WAKE_RES is necessary to get the IC out of a Power-Saving Mode. Apart from WAKE_RES, a Power-Saving Mode can only be left by activating RESETQ at pin or by a power on reset. WAKE_RES is generated by a Port Wake Module for an event-driven wakeup, combined with an RTC Module for a cyclic wake-up. The Power-Saving Module is active all the time, during power-saving mode as well as during non-power-saving mode (CPU active modes). The WAKE_RES output signal can be generated during power-saving mode only. The RTC Module has to provide the time of the day accurately down to a second, and generate an output signal, which can be used to trigger an interrupt or a wake-up signal. The RTC Module can be clocked by the on-chip quartz oscillator or by the Power-Saving Module built-in RC oscillator. The Polling Module cyclically outputs a high pulse of programmable duration at port H2.5. Some of the RTC Module taps are connected to the Polling Module for deriving the pulse period and duration. The Port Wake Module merges several Wake Ports and outputs a signal that can be used to trigger an interrupt or a wake-up signal.
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PRELIMINARY DATA SHEET
CDC16xxF-E
OSC.PRE 4...12MHz OSC.XM XTAL Oscillator en RC Oscillator en fSS fS RTCCLK 1/8 1/2 VDD wake-up fPP Poll Clk
SMX.MUX
Mux
SMX_out
20..50kHz OSC.RC OSC.SRC
RTC Module 20-Bit Rel Reg SSR Sub Sec Cnt SSC 3 7 10 14 10..19 SMX.BYP RTCC.SEL Mux RTC out CLK Mux fPC POL.OE POL.ENA & Polling Module WSC.RTC WAID WSC.P WSC.AST 1 wake-up Poll Clk Delay Counter POL.DEL POL.PER Mux poll period fPP poll out WUS.RTC SQ R & IR_RTC load fm fh fd SEC MIN HR 1 2 4 8 16 32 1 2 4 8 16 32 1 2 4 8 16 24
1Hz
& wake out
H2.5
&
WAKE_RES
WPMx.MOD CMOS Threshold UPort wake in PPort CANx-RX
& Edge/Level Trigger Mode & Enable trigger SQ R WUS.WPx 10x Port Wake Module 1 1 IR_WAPI
Fig. 8-2: Power-Saving Module Block Diagram
8.1. Functional Description
The power-saving logic combines all wake-up sources. It contains an RC oscillator, a 20-bit sub second counter, an RTC, multiplexers to select different taps of the sub second counter or of the RTC, a Polling Module and the logic for up to ten Wake Ports. The RTC Module output can generate an interrupt or a wakeup signal. All Wake Ports can generate a collective interrupt or a wake-up reset. The Polling Module drives an H-Port and generates a strobe signal to enable a Wake Port to trigger on a dedicated input level. Several internal clock signals can be output via CO1 (SMX_out).
8.1.1. RTC Module
To work as real-time counter, a sub-second counter (SSC) with its reload register (SSR) and a seconds, minutes and hours counter are part of the Power-Saving Module. As input
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CDC16xxF-E
for the sub second counter (fSS), either a clock of the quartz oscillator divided by 8 or 16 or that of the module built-in RC oscillator can be selected. The SSR has to be programmed with a value that yields a one Hertz beat fS as output signal of the SSC to clock the seconds. fS is the reload signal for SSC as well as the input clock to the seconds counter (RTC.SEC). An underrun of the down-counting SSC triggers the seconds counter to count up. 60 seconds trigger a minutes up-count (RTC.MIN), followed by the hours (RTC.HR). All stages of the three up-counters can be selected to generate an interrupt or a wake-up signal. As opposed to other internal clocks, the RTC can not be stopped (during emulation) by ESTOPCLK.
PRELIMINARY DATA SHEET
Due to the adjustment mechanism by the 20-bit reload register, the polling period is not always constant. Depending on the reload value, the polling period may vary between 0.5 and 1.5 nominal polling periods at the point of reloading. The control unit is designed for a polling period to be set equal to or greater than four times the polling delay.
8.1.3. Port Wake Module
There is a trigger mode logic (level or edge sensitive) and a wake source flag for each Wake Port. The Wake Out input is a signal from the Polling Module. The falling edge generates a strobe pulse which is used to sample the level of the Wake In input and sets the corresponding wake source flag if necessary. Instead of the strobe signal, WSC.AST may be used, e.g., if no RTC subsystem (with Polling Logic) is implemented. The corresponding WPx flag in register WUS will be forced to high as long as the programmed condition (high or low level) is met at the Wake Port. Please see Fig. 8-2 for details. The selected strobe signal source is valid for all Wake Ports. Mixing of the strobe signal sources (polling and alternative) is not possible. The wake flags of all Wake Ports are located in the wake-up source register WUS. The trigger events which can set the wake flags can be configured in the wake-up pin mode registers WPM0 to 8 either in field MOD0 or MOD1. Please refer to Table 8-9 for details about allocation of mode registers and Wake Ports. The output of each Wake Port is connected to an or gate, whose output can generate a Wake Port interrupt as well as a wake-up signal.
8.1.2. Polling Module
The polling logic periodically activates the output signal Wake Out which can be enabled by SW to drive port H2.5 (Poll Out). The rising edge of the Polling Period input (fPP) defines the start and the Polling Clock (fPC). Together with the delay counter, it defines the duration of the high time. This can be used to cyclically flash a LED or drive external circuitry. The falling edge of the Wake Out signal is used to scan the input levels of that Wake Ports (WPx) which are configured for high or low level trigger mode. Those configured ports will set the corresponding WPx flag in register WUS with the falling edge of the strobe signal. Please refer to Fig. 8-6 for timing details about the Wake Out and the strobe signals.
8.2. Registers
SRC Oscillator Source Select r/w0: 4 ... 12MHZ XTAL (divided by 8 or 16) r/w1: Don't use, factory test only r/w2: RC oscillator r/w3: Ground With OSC.LD set, writing to SRC selects a new oscillator source immediately. When OSC.LD is not set, a new oscillator source does not get valid before the next reload of the SSC. Consider that a read access returns the current source select, not a possibly requested one by a write with OSC.LD not set!
OSC
7
r/w RC 1
Oscillator Source Register
6
XK 0
5
XM 1
4
x
3
LD
2
PRE No HW reset
1
SRC
0
0
Offs
Res
RC r/w1: r/w0:
RC oscillator enable disable
XK External 32kHz XTAL (not available) r/w1: enable r/w0: disable Write to zero for future compatibility. XM r/w1: r/w0: LD r: w1: w0: PRE r/w1: r/w0: 4 ... 12MHz XTAL always enabled disabled during power-saving mode Load SRC and SSC Always read as zero Immediately selects the oscillator source according to SRC and loads SSC with SSR. No action 4 ... 12MHz XTAL / 8 or / 16 4 ... 12MHz XTAL / 16 4 ... 12MHz XTAL / 8
SSR
7
r/w r/w r/w r/w x x
Sub Second Reload Register
6
x x
5
x x
4
x x
3
x
2
x
1
x
0
x 3 2 1 0
Offs
Bit 19 to 16
Bit 15 to 8 Bit 7 to 0 No HW reset
Res
For typical settings, please refer to Tables 8-1 to 8-3. The values 0 and 1 are not allowed. To avoid programming values not expected, never write single bytes of the SSR on their own, but always all 3 bytes without an interrupt by SSC
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PRELIMINARY DATA SHEET
CDC16xxF-E
read. This is necessary, as for reading SSC the register hardware (master/slave) uses the same buffer registers as for writing SSR. Single bytes could still be filled with intermediate SSC values of a previous read. Writing SSR does not load the SSC immediately. This will be done automatically together with the next reload of the SSC. It can be forced immediately by setting OSC.LD.
WUS
7
r/w r/w RTC WP7
Wake-Up Source Register
6
x WP6
5
x WP5
4
x WP4
3
x WP3
2
x WP2
1
WP9 WP1
0
WP8 WP0 1 0
Offs
No HW reset
Res
SSC
7
r r r r x x
Sub Second Counter
6
x x
5
x x
4
x x
3
x
2
x
1
x
0
x 3 2 1 0
Offs
Bit 19 to 16
RTC r1: r0: w1: w0: WPx r1: r0: w1: w0:
Real Time Clock RTC was trigger source No trigger Clear No modification Wake Port x Wake Port was trigger source No trigger Clear No modification
Bit 15 to 8 Bit 7 to 0 No HW reset
Res
A read access to byte 0 of the SSC latches the bytes 1 and 2. This mechanism grants consistent read access to the SSC.
RTC
7
r/w r/w r/w r/w x x x x
Real Time Counter
6
x x x x No HW reset
5
x x
4
x
3
x
2
x HR MIN SEC
1
x
0
x 3 2 1 0
Offs
For proper interrupt generation some peculiarities in operating this register have to be considered. All set bits must be cleared by writing back the whole pattern that was read before. Always read and clear (write back) the whole register, byte 0 first, which will become valid when writing byte 1, even if only flags in byte 0 are in use. Every write access to byte 1 will produce an interrupt, as long as WUS contains a one.
WPMx
7
r/w x
Wake Port x Mode Register
6 5
MOD1
4
3
x
2
1
MOD0
0
0
Offs
Res
No HW reset
Res
Reading SEC latches MIN and HR. Writing HR simultaneously saves MIN and SEC in the corresponding counters. This mechanism allows consistent read and write access. Since read and write use the same latches, don't mix these access types. HR r/w0 to 23: MIN r/w0 to 59: SEC r/w0 to 59: Hours Counter Minutes Counter
MODy Trigger Mode (Table 8-5) Trigger mode for Wake Port WPx+y. For assignment of Wake Port and mode field please refer to Table 8-9.
POL
7
r/w x ENA OE
Polling Register
6
CLK x 0x00
5
4
x
3
2
PER DEL
1
0
1 0
Offs
Seconds Counter
r/w
Res
RTCC
7
r/w x
RTC Control Register
6
x
CLK
1 0
0 Res Offs
Select Polling Clock (Table 8-7) Select Polling Period (Table 8-6) Enable Polling Module enable disable Enable Polling Output enable disable
5
x
4
3
2
SEL
PER ENA r/w1: r/w0: OE r/w1: r/w0:
No HW reset
SEL
Select RTC Output (Table 8-4)
DEL Select Polling Delay Time r/w1 to 31: Delay time = DEL/fPC r/w0: Delay time = 32/fPC A write access to DEL immediately loads the 5-bit down counter. The delay time defines the duration of the Wake Out signal (Fig. 8-6).
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CDC16xxF-E
PRELIMINARY DATA SHEET
WSC
7
r/w x
Wake Source Control
6
x
Neither WUS.WPx nor the WAPI interrupt source output are affected.
1
RTC
5
x
4
x
3
x
2
AST
0
P 0
Offs
SMX
7 6
x
Signal Multiplexer Register
5
x
4
x 0x00
3
x
2
1
MUX
0
0
Offs
0x00 after VDD power on
Res r/w BYP
AST r/w1: r/w0:
Alternative to Strobe Alternative input Wake out signal from Polling Logic
Res
RTC RTC Wake-up Enable r/w1: enable r/w0: disable Neither WUS.RTC nor the RTC interrupt source output are affected. P r/w1: r/w0: Port Wake-up Enable enable disable
BYP r/w1: r/w0:
Bypass SSC RTC is clocked by fSS (test) RTC is clocked by fS (1Hz)
MUX Signal Multiplexer (Table 8-8) Defines a signal which is output as SMX_out.
Table 8-1: SSR values for fs = 1Hz with XTAL and XTAL/8 (Maximum adjusted resolution)
XTAL [MHz] 4 5 6 8 XTAL/8 [KHz ] 500 652 750 1000 Period [us] 2.00 1.60 1.33 1.00 Reload Value 500000 625000 750000 1000000 Resolution [ppm] 1.00 0.80 0.67 0.50 Per Day [ms] 86.40 69.12 57.60 43.20
Table 8-2: SSR values for fs = 1Hz with XTAL and XTAL/16 (Maximum adjusted resolution)
XTAL [MHz] 4 5 6 8 10 12 XTAL/16 [KHz ] 250 313 375 500 625 750 Period [us] 4.00 3.20 2.67 2.00 1.60 1.33 Reload Value 250000 312500 375000 500000 625000 750000 Resolution [ppm] 2.00 1.60 1.33 1.00 0.80 0.67 Per Day [ms] 172.80 138.24 115.20 86.40 69.12 57.60
Table 8-3: SSR values for fs = 1Hz with RC (Maximum adjusted resolution)
RC [KHz] 20 32,768 50 Period [us] 50.00 30.52 20.00 Reload Value 20000 32768 50000 Resolution [ppm] 25.00 15.26 10.00 Per Day [ms] 2160 1318 864
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PRELIMINARY DATA SHEET
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Table 8-4: SEL Usage
RTCC. SEL 0 1 second counter taps 2 3 4 5 6 7 minute counter taps 8 9 10 11 12 13 14 15 16 17 18 19..31 hour counter taps Tap# Gnd 1 2 4 8 16 32 1 2 4 8 16 32 1 2 4 8 16 24 Activation Never Every second Every 2 seconds Every 4 seconds at second 8, 16, 24, 32, 40, 48, 56 at second 0, 16, 32, 48 at second 0, 32 Every minute Every 2 minutes Every 4 minutes at minute 8, 16, 24, 32, 40, 48, 56 at minute 0, 16, 32, 48 at minute 0, 32 Every hour Every 2 hours Every 4 hours Every 8 hours at hour 0, 16 Every day
Table 8-5: MOD Usage
WPMx. MODy 2 x 0 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 1 0 1 1 0 1 Disabled Rising edge Falling edge Rising and falling edge High level 1) Low level 1) Both levels (every strobe signal) 1) Trigger Modes
1) In WAKE mode with alternative strobe only.
Table 8-6: PER Usage
POL. PER 0 1 2 : 9 10 11 12 13 14 15 Second Counter TAP# 10 11 12 : 19 1 2 4 8 16 32 1Hz 0.5Hz 0.25Hz at second 8, 16, 24, 32, 40, 48, 56 at second 0, 16, 32, 48 at second 0, 32 fPP fSS/2TAP#
Don't use
SEL = 4, 5, 6, 10, 11, 12 and 17 do not produce isochronous intervals.
Isochronous intervals can only be achieved by PER = 10, 11 or 12.
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PRELIMINARY DATA SHEET
Table 8-7: CLK Usage
POL. CLK 0 1 2 3 Sub Sec Tap# 3 7 10 14 fPC fSS/2TAP#
Table 8-9: Wake Ports
Name Basic Funct. WPMx WP0 WP1 WP2 U3.4 U6.6 U1.6 U6.0 U6.1 U6.2 U5.6 U4.0 U4.4 H2.4 8 6 4 2 0 WP3 WP4 WP5 WP6 WP7 WP8 WP9 WPMx.MODy 0 1 0 1 0 1 0 1 0 1
Table 8-8: MUX Usage
SMX. MUX 0 1 2 3 4 5 6 7 Name VDD fSS fS (1Hz) (wake-up) (wake-up) wake-up fPP Poll Clk SSC input (calibration) SSC output (adjustment) Test (Factory use only)
8.3. Operation of Power-Saving Module
Before entering a Power-Saving Mode, the necessary wakeup sources have to be configured carefully. The reset/wakeup reason in register CSW2 and the wake-up source register WUS have to be cleared. Please see section "CPU and Clock System" for information on entering a power-saving mode. be cleared. Flag WSC.RTC has to be set, enabling the WUS.RTC output signal to generate a wake-up signal by setting signal WAKE_RES.
8.3.2. Configuration of Interrupts
During CPU active modes, the RTC Module and the Port Wake Module can be operated as interrupt sources. The interrupts have to be configured according to section "Interrupt Controller (IR)".
8.3.1. Configuration of Wake Sources
8.3.1.1. Port Wake Module If an external event-driven wake-up is necessary, the Port Wake Module has to be configured according to section 8.6. The register WUS has to be cleared. Flag WSC.P has to be set, enabling the Port Wake Module output signal to generate a wake-up signal by setting signal WAKE_RES. If a Wake Port is to be operated in polling mode (level triggered), configuration of RTC Module and Polling Module is necessary as described in sections 8.4. and 8.5. 8.3.1.2. RTC Module If a cyclic wake-up is necessary, the RTC Module has to be configured according to section 8.4. Flag WUS.RTC has to
8.3.3. WAKE/IDLE
With setting SR3.WAID (mode = WAKE/IDLE) a core reset signal is generated immediately. A wake-up signal sets WAKE_RES to one, immediately pulling pin RESETQ to low. This sets SR1.CPUFST and disables the WAKE_RES output of the Power-Saving Module. When VDD and PH2 are detected as stable, the signal CLS is cleared and the reset extension is started. After the reset extension has finished, the pin RESETQ is released. The Core reset signal gets inactive and CSW2.WKID is set. The CPU starts execution at the reset vector address and can read the reset/wake-up reason in registers CSW1 and
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CSW2. The wake-up source can be read in register WUS and should be cleared thereafter, otherwise Wake Port interrupts are not possible.
8.3.4. Precautions
The SW has to guarantee the ability of wake-up. In the best case, a stable initialization and configuration of the wake logic is executed immediately after RESET to prevent malfunctions by an unintentionally activated power-saving mode that was not yet initialized before. The necessary Wake Ports have to be configured as inputs. Enabling wake-up by pin only is dangerous. Inadvertently or accidentally entering a power-saving mode with no wake source enabled, e. g. by a software bug, or if a flag is modified by electrical overstress (EOS) in a power-saving mode, a status may be reached which can only be terminated by a manually generated reset with low level at pin RESETQ or with a power on reset. Neither the watchdog nor the clock supervision or any other internal reset source terminates a power-saving mode. Because neither the VBG generator nor the RESET comparator are enabled during power-saving mode, proper CMOS input levels (Vil=VSS0.3 V and Vih=VDD0.3 V) are required on pin RESETQ during a wake-up reset. The external circuitry must allow the device to establish WRVil on that pin. The specified power-saving mode current consumption values are only obtainable with CMOS input levels (Vil=xVSS0.3 V and Vih=xVDD0.3 V) applied to all ports analog inputs via P-ports P0.1 to P0.9 excepted - not only the Wake ports. If an RTC-/Polling module is not used, it is advisable to switch it off to reduce current consumption. Its outputs should be disabled (see Section 8.4.3. on page 69).
8.3.5. Debug Register
To allow debugging during an active power-saving mode, e.g., read or change the contents of the RAM, or read or change the contents of I/O or processor registers, the system clock must not be switched off as done normally when a Power-Saving Mode is switched on. By setting DBG.DCS the CPU keeps on running in a power-saving mode. DBG
7
r/w x x
Debug Register
6
x x
5
x x
4
x x
3
x x
2
x x
1
x x
0
DCS 0 0
Offs
POR
DCS r/w1: r/w0:
DISABLE CPU STOP Disabled CPU stop (clock off) during power-saving mode (debugging) Stop CPU during power-saving modes (standard, no debugging)
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8.3.6. Timing
PRELIMINARY DATA SHEET
UVDD
RESETQ WAKE_RES
SR3.WAID
ON PH2
RESPORT
RESCORE
POR CLS RESIR
RESINTOUT 16 or 4096 XTAL cycles
Fig. 8-3: Power-on Reset
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UVDD
wake-up logic
RESETQ WAKE_RES CPU SR3.WAID
ON
DBG.DCS
PH2
RESPORT
RESCORE
POR
CLS
RESIR
RESINTOUT 16 or 4096 XTAL cycles
Fig. 8-4: Switching to WAKE/IDLE with DBG.DCS inactive and Wake-up
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UVDD
wake-up logic
RESETQ WAKE_RES CPU SR3.WAID
ON
DBG.DCS
PH2
RESPORT
RESCORE
POR
CLS
RESIR
RESINTOUT 16 or 4096 XTAL cycles
Fig. 8-5: Switching to WAKE/IDLE with DBG.DCS active and Wake-up
8.4. Operation of RTC Module
8.4.1. Reset
With the exception of the oscillators, which are enabled by every reset (OSC.RC = OSC.XM = 1), most parts of the logic will never be reset. Therefore, the oscillator not required has to be switched off after every reset. Furthermore, the whole logic has to be initialized after a power-on reset. As OSC.SRC is not reset by HW, an oscillator source must be selected and enabled. The SSR has to be loaded with the reload value necessary for a 1 Hz output frequency. Writing the desired oscillator source in field SRC, enabling it if necessary and setting flag LD in register OSC immediately selects the new oscillator source and loads SSR to SSC. - Changing the SSR Due to temperature or other dependencies of the oscillator it may be necessary to adjust the reload value in the SSR register from time to time. This can be done within the RTC interrupt service routine (RTC-ISR). Write the new reload value to the SSR register. Make sure that this will be completed before the next underflow of the SSC which happens to each second and simultaneously loads SSC with the new SSR value and switches the oscillator source. - Changing the oscillator source Due to switching to a Power-Saving Mode it may be necessary to change the oscillator source. This can be done
8.4.2. Oscillator Source and Sub Second Counter
The Sub Second Counter SSC generates a 1 Hz output signal at underflow (0x000000 to 0xFFFFFF). This signal loads the SSC with the content of the SSR register and switches the oscillator source select multiplexer to the desired oscillator according to the SRC field in the OSC register. This load signal can be forced by writing a one to flag LD in register OSC. On three occasions it is necessary to change SSR and OSC.SRC: - Starting the SSC for the first time (after power-on).
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8.4.5. RTC Output Multiplexer
All the taps of the second, minute and hour counters are connected to a multiplexer (Table 8-4) and can be selected as output by register RTCC.SEL. The output of this multiplexer can generate an RTC interrupt as well as a wake-up signal.
within the RTC-ISR. Select the desired oscillator source in OSC.SRC and write the corresponding reload value to the SSR register. Make sure that this will be completed before the next underflow of the SSC which happens to each second and simultaneously loads SSC with the new SSR value and switches the oscillator source. Precaution: Changing the oscillator source may cause a fragmentary clock pulse. This may result in wrong SSC and/ or RTC values and unwanted interrupt or wake pulses. Changing the oscillator source makes it necessary to: 1. Disable all output signals of the Power-Saving Module (POL.OE = WSC.RTC = WSC.P = 0) and disable RTC and WAPI interrupts. 2. Switch to the new oscillator source. 3. Initialize SSC, RTC and POL. 4. Clear WUS (WUS = 0xFFFF). 5. Enable the output signals again.
8.4.6. RTC Interrupt
The IR has to be initialized as described above. The RTC has its own interrupt vector, thus further investigation of the interrupt source is not necessary. After an interrupt, the flag WUS.RTC is set. The register WUS.RTC is not necessary for the RTC ISR, and does not have to be handled by the RTC ISR. Precaution: Please be aware that modifying RTC or RTCC may result in addtional negative edges on RTC Out. If no measures are taken, these edges will generate unwanted interrupts. A solution that would not affect the intended interrupts is reading SSC and modifying RTC or RTCC only if sufficient time is available to intercept the unwanted interrupt before the next 1 Hz clock pulse occurs. In this situation, the RTC interrupt may safely be temporarily disabled.
8.4.3. Disabling the RTC Module
This has to be done by selecting the RC oscillator (OSC.SRC=2) and disabling this source (OSC.RC=0). Selecting ground (OSC.SRC=3) disables the 32 kHz subsystem too, but this should be avoided to be compatible with future extensions.
8.4.4. Access to SSC and RTC
SSC and RTC are periodically altered by clock pulses. Even if the 32 kHz subsystem is clocked by the 4 ... 12 MHz oscillator, a CPU access to SSC and RTC can be corrupted by a clock pulse. Because this situation can't be avoided, the SSC or the RTC register have to be read twice. If there is a difference between the two accesses the read has to be repeated. After a write to register RTC it has to be read and compared to the desired value. If there is a difference, write, read and compare have to be repeated. Since the RTC is clocked not faster than in second distance, a read or write access to register RTC can be done in the RTC-ISR. Such an access is safe and guarantees a correct result as long as the RTC-ISR is finished before the next clock alters the RTC.
8.4.7. Signal Multiplexer
Various internal signals can be switched to SMX_out. The internal signal can be selected via register SMX.MUX. The possible signals are shown in Table 8-8. Only the signals fSS and fS are of general interest. The remaining signals may be used, but are intended for testing purposes. The signal fSS is useful to measure the quartz frequency and calculate the corresponding reload value for the sub-second counter with external equipment. The signal fS is useful for re-adjustment of the sub second counter, with the help of, e.g., an XTAL-driven CAPCOM counter, when driven by the internal RC oscillator. The bypass switch (SMX.BYP) allows to bypass the SSC and directly feed fSS into the second counter. This feature is intended for testing purposes only. Applications normally keep SMX.BYP cleared.
8.5. Operation of Polling Module
8.5.1. Reset
The whole logic is cleared by every kind of reset, even wakeup from power-saving mode resets the Polling Module. This means that the logic has to be initialized after every reset. The enable input (POL.ENA) and the output (POL.OE) has to be disabled. The port H2.5 has to be configured as normal, out, low for operation as polling output. Select fPC (POL.CLK) and fPP (POL.PER). Enable input and output (POL.ENA, POL.OE) and load the delay counter reload register (POL.DEL) with a non-zero value.
8.5.2. Initialization and Start
The Polling Module needs the RTC Module running, because the Polling Clock fPC is derived from sub-second counter taps, and the Polling Period fPP is derived from subsecond counter taps or second counter taps. See section 8.4. for RTC Module initialization.
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poll period Poll Clk
fpp poll delay wake out 0 strobe 3 2 1 0 0 3
Fig. 8-6: Polling Timing 8.5.3. Stop
Disable all inputs and outputs (POL.ENA=0, POL.OE=0).
8.5.4. Restart
Set POL.ENA and POL.OE to one. Initialize the delay counter reload register (POL.DEL).
8.6. Operation of Port Wake Module
WPMx.MOD
210 rising
delay &
wake in (from port)
& falling
delay &
Delay
& strobe wake in & high
1
trigger
wake out (from Polling Module) WSC.AST
strobe 1 alt. strobe & low wake in
strobe
Fig. 8-7: Edge/Level Trigger Logic 8.6.1. Reset
Neither the wake-up source register (WUS) nor the WakePort Mode registers (WPMx) are reset to a defined value by any reset source. be disabled. The source of the strobe signal has to be selected with WSC.AST if a level triggered mode must be used. The whole register WUS has to be cleared.
8.6.3. Operation
The Port Wake Module can be operated by polling. It can generate an interrupt (IR_WAPI) or a wake-up signal to leave the Power-Saving Mode. To use a level-triggered mode of a Wake Port the RTC Module and the Polling Module have to be configured to provide
8.6.2. Initialization
The corresponding ports must be configured as inputs. For every Wake Port which is to generate a wake-up signal, the trigger mode in the WPMx register has to be programmed. For every Wake Port which must not generate a wake-up signal, the trigger mode in the WPMx register has to
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the necessary Wake Out signal. The signal Wake Out is necessary for a strobe pulse at the falling edge of Wake Out. If no RTC-/Polling module is available or is not to be used, an alternative strobe signal can be used by setting flag WSC.AST to one. As long as WSC.AST is set and the programmed trigger level is applied to the corresponding pin, the flag WUS.WPx is set and can't be reset by the SW. If more than one Wake Port is operated with the alternative strobe signal, WPMx.MOD has to be disabled before WUS.WPx can be cleared. Only clearing WSC.AST during the WUS clearing procedure does not help in this case. Interrupts of other Wake Ports can be lost if the high or low time is too short. The selected strobe signal source is valid for all Wake Ports. Mixing of the strobe signals sources (polling and alternative) is not possible. If only the edge-triggered mode is used, the RTC Module and the Polling Module are not necessary for correct operation of the Port Wake Module.
8.6.4. Wake-up from Power-Saving Mode
Following the initialization described above, it is necessary to enable the Port Wake Module as wake-up source by register WSC flag P. After wake-up the reason can be read in register WUS. It should be cleared after reading, as otherwise neither wakeup nor Wake Port interrupt via IR_WAPI is possible.
8.6.5. Wake Port Interrupt
Following the initialization described above, the IR has to be initialized. All Wake Ports are directed to an interrupt vector. After an interrupt the source can be read in register WUS. It should be cleared after reading, as otherwise no further Wake Port interrupts via WAPI are possible.
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9. Memory Patch Module
The Memory Patch Module allows the user to modify up to ten hardwired ROM locations by external means. This function is useful if faulty parts of software or data are detected after the ROM code has been cast into mask ROM. Software loads addresses and the corrected code, e.g., from external non-volatile memory into the respective registers of the module. The module will then replace faulty code upon address match. Single ROM locations are directly replaced. Longer faulty sequences may be repaired by introducing a jump to a new subroutine in RAM (e.g. opcode JSR requires 3 consecutive bytes to be patched). The RAM subroutine then may consist of any number of instructions, ending with a return to the
PRELIMINARY DATA SHEET
next correct instruction in ROM. Thus it is possible to also include complex software modules. ICs which are derived from the Emulator IC may have less patch cells. In this case the upper patch cells are not available. Features - patching of read data from up to 10 different ROM locations (24-bit physical address) - automatic insertion of 1 CPU wait state for each patched access
ADB[23:0] DB[7:0]
Patch Cell 0
PMEN
Patch Enable Register
Write/Compare Enable PA[7:0]
Patch Address Register
PA[15:8] PA[23:16]
Patch Data Register
Output Enable PATOE
DBP[7:0] PH2
PSEL9...0
1
Patch Cells 1...9
Sequencer
RDY ROMEN
&
ROMACC
RWQ
Fig. 9-1: Block Diagram
9.1. Principle of operation
9.1.1. General Remarks
The logic contains ten patch cells (see Fig. 9-1 on page 72), each consisting of a 24-bit compare register (Patch Address Register, PARn), a 24-bit address comparator, a Patch Enable Register (PERn) bit and an 8-bit Patch Data Register (PDR). The current address information for a ROM access is fed to a bank of ten patch cells. In case of a match in one patch cell, and provided that the corresponding Patch Enable Register bit is set, a wait cycle for CPU is included by pulling down the RDY input of CPU for one cycle (see Fig. 9-2 on page 73). In the meantime, the module's logic disables the ROM data bus drivers, and instead places the data information from the corresponding Patch Data Register on the data bus.
9.1.2. Initialization
After reset, as bit PER0.PMEN is reset to 0, all patch cell registers are in write mode and patch operation is disabled. To initialize a patch cell, first set the corresponding PSEL bit in register PER0 or PER1 as a pointer. Then enter the 24-bit address to registers PAR2 (high byte), PAR1 (middle byte) and PAR0 (low byte) and the desired patch code to register PDR. If desired, repeat the above sequence for other patch cells. Only set one PSEL pointer bit at a time in registers PER0 and PER1.
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9.1.4. Reconfiguration
To reconfigure the Memory Patch Module, first set PER0.PMEN to 0. The module will immediately terminate patch operation. Then proceed as described in "Initialization" on page 72.
9.1.3. Patch Operation
To activate a number of properly initialized patch cells for ROM code patching, set all the corresponding PSEL bits in registers PER1, then PER0, setting bit PER0.PMEN to 1. The Memory Patch Module will immediately start comparing the current address with the setting of the enabled patch cells. In case of a match, the ROM data will be replaced by the corresponding patch cell data register setting.
PH2
ADB[23:0] A1
A2
A2
A3
A3
DB[7:0]
D1
D2
PD2
D3
PD3
RDY
PATOE
ROMEN
Fig. 9-2: Timing
9.2. Registers
PAR0
7
w PA7 1
Patch Address Register 0
6
PA6 1
PAR2
0
PA0 1 Res Note w
Patch Address Register 2
6
PA22 1
5
PA5 1
4
PA4 1
3
PA3 1
2
PA2 1
1
PA1 1
7
PA23 1
5
PA21 1
4
PA20 1
3
PA19 1
2
PA18 1
1
PA17 1
0
PA16 1
Note
Res
PAR1
7
w PA15 1
Patch Address Register 1
6
PA14 1
PDR
0
PA8 1 Res Note w
Patch Data Register
6
PD6 0
5
PA13 1
4
PA12 1
3
PA11 1
2
PA10 1
1
PA9 1
7
PD7 0
5
PD5 0
4
PD4 0
3
PD3 0
2
PD2 0
1
PD1 0
0
PD0 0
Note
Res
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PER0
7
w PSEL6 0
Patch Enable Register 0
6
PSEL5 0
5
PSEL4 0
4
PSEL3 0
3
PSEL2 0
2
PSEL1 0
1
PSEL0 0
0
PMEN 0
Note
Res
PER1
7
w x x
Patch Enable Register 1
6
x x
5
x x
4
x x
3
x x
2
PSEL9 0
1
PSEL8 0
0
PSEL7 0
Note
Res
PA23 to 0 Patch Address Upon occurrence of this address the patch cell replaces ROM data with data from PDR. PD7 to 0 Patch Data Data to replace false ROM data at certain address. PSEL0 to 9 Select Patch Cell w1: select cell for write or enable for patch w0: disable patch cell Before writing compare address or replace data of a patch cell, only one cell must be selected. In compare mode one or more patch cells can be selected. PMEN w1: w0: Patch Mode Enable enable patch mode of all cells enable write mode of all cells
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10. Interrupt Controller (IR)
The Interrupt Controller has 16 input channels. Each input has its own interrupt vector pointing to an interrupt service routine (ISR). One of 15 priority levels can be assigned to each input or the input can be disabled. The Interrupt Controller is connected to the NMI input of the CPU. However, despite the non-maskable interrupt input, it is possible to disable all interrupt sources together in the Interrupt Controller. Features - 16 interrupt inputs. - 16 interrupt vectors. - 15 individual priority levels. - Global/individual disable of interrupts. - Single interrupt service mode.
10.1. Principle of Operation
10.1.1. General Remarks
Interrupt requests are served in the order of their programmed priority level. Interrupt requests of the same priority level are served in descending order of interrupt input number. Each of the 16 interrupt inputs clears a flag in the interrupt pending register (IRRET and IRP), which can be read by the user. A pending interrupt enables the output of the corresponding priority register (IRPRI10 to IRPRIFE) which is connected to a parallel priority decoder together with the other priority registers. The decoder outputs the highest priority and its input number to a latch. The latched priority is compared with the top entry of the priority stack. The top entry of the priority stack contains the priority of the currently served interrupt. Lower entries contain interrupts with lower priority whose interrupt service routines were started but interrupted by the higher priority interrupts above. If the latched priority is lower or equal than the top of stack priority, nothing happens. If the latched priority is higher than the top of stack priority, a NMI is sent to the CPU and the latched priority is pushed on the stack. The Interrupt Controller signals an interrupt to the CPU via NMI input . After the current instruction is finished the CPU starts an interrupt sequence. First it puts the program bank register, the program counter high byte, the program counter low byte and the program status register into the stack. Then the CPU writes the vector address low byte (FFFA in 6502 mode, FFEA in 816 mode) to the bus. The Interrupt Controller recognizes this address and stops the CPU by the RDY signal. Now the Interrupt Controller writes the vector address low and high byte of the corresponding interrupt number to the bus and releases the CPU by releasing RDY. The CPU now operates with the new vector of the interrupt service routine. When the Interrupt Controller writes the new vector to the address bus, the interrupt pending flag of this vector is set, indicating that no interrupt is pending. The software must pull the top entry from the priority stack at the end of an interrupt service routine. This happens with the write access to the interrupt return register IRRET. Then the next entry (with lower priority) is visible at top of stack and is compared with the priority latch. The Interrupt Controller and related circuitry is clocked by the CPU clock and participates in CPU FAST and SLOW mode. According to Section 10.3. some of the Interrupt Controller inputs allow selection of a source by HW option (cf. Table 10-3). This configuration has to be done prior to operation. Refer to "HW Options" for setting them.
10.1.3. Initialization
After reset, all internal registers are cleared but the Interrupt Controller is active. When an interrupt request arrives, it will be stored in the respective pending register IRP/IRRET. But it will not trigger an interrupt as long as its interrupt priority register IRPRIxy is set to zero. The interrupt sources in peripheral modules have to be properly SW configurated prior to operation. Before enabling individual inputs, make sure that no previously received signal on that input has cleared its pending flag which may trigger the Interrupt Controller. Clear all pending interrupts with the flag IRC.CLEAR to avoid such an effect.
10.1.4. Operation
Activation of an interrupt input is done by writing a priority value ranging from 1h to Fh to the respective IRPRIxy register. Upon an interrupt request, pending or fresh, the Interrupt Controller will immediately generate an interrupt. During operation, changes in the priority register setting may be made to obtain varying interrupt servicing strategies. Flags IRC.DAINT, IRC.DINT and IRC.A1INT allow some variation in the Interrupt Controller response behavior.
10.1.5. Inactivation
There are two possibilities to disable an interrupt within the Interrupt Controller. Changing the priority of an interrupt input to zero disables this interrupt locally. Interrupts are globally disabled by writing a zero to flag IRC.DINT of register IRC. During the evaluation period (see also Section 10.4.: Interrupt Timing) it is not possible to suppress an interrupt by changing priority. A zero in the flag IRC.DINT of register IRC prevents the Interrupt Controller from pulling the signal NMI low. However, if this flag is set after the falling edge of NMI, the corresponding interrupt cannot be cancelled.
10.1.2. Hardware settings
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clke Priority Latch clke 4 prio A A>B & clke B 4 4 4 input # Ph2 DMAE PATCH 4 priority push NMI 4 Priority Stack 15 x 4 pull IRRET write 4 Parallel Priority Decoder clke DMAE RDY Ctrl FFFA or FFEA 4 enable A0...A15 A B A=B 4 Interrupt Vector Table 16 16
Pending Register
Priority Registers
IRPRI10
Int-Input 1
R
Q
CDC16xxF-E
S
Int-Input 2
R
Q
S
IRPRI32
Int-Input 3
R
Q
S
Int-Input 4
R
Q
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S
IRPRIFE
Int-Input 15
R
Q
S
Int-Input 16
R
Q
S
Clear Request
PRELIMINARY DATA SHEET
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Fig. 10-1: Block Diagram
PRELIMINARY DATA SHEET
CDC16xxF-E
ished before critical data access and no further ISR can interrupt it. As it is now possible that an ISR (Interrupt Service Routine) can lengthen the time between the disable interrupt instruction (DI) and the enable interrupt instruction (EI) indefinitely, it is necessary that an ISR first saves registers and enable interrupt flags and then enables interrupts. After interrupt execution enable flags and registers must be restored. This guarantees that other interrupts are not locked out during interrupt execution.
10.1.6. Precautions
10.1.6.1. Return from Interrupt The write access to the IRRET must be performed just before the RTI command at the end of the interrupt service routine. After a write access to this location it is guaranteed that the next command (should be RTI) will be processed completely before a new interrupt request is signalled to the CPU. If the RTI command does not immediately follow the write to IRRET, an interrupt with the same priority may be detected before the corresponding RTI is processed. A stack underflow may occur because this may happen several times. An interrupt with a higher priority than the one actually served, may interrupt between the write access to IRRET and the belonging RTI command. Now an interrupt request from the interrupted low priority interrupt may occur during service of the high priority interrupt. This one will be served after the RTI command of the high priority interrupt and before the RTI command of the first interrupted low priority interrupt. In this case, the return address and the PSW of the same interrupt are stored twice on the stack. This may happen several times and can cause a problem if the stack size is calculated without sufficient buffer or if the interrupt load is too high, which means that there is no time for the background loop. 10.1.6.2. Disable Interrupt If an opcode fetch of a disable interrupt instruction (DI) happens one clock cycle after the falling edge of NMI (see Section 10.4.1. on page 81), it is possible, that an interrupt service routine (ISR) is active, though the corresponding interrupt is disabled. That is why after disabling an interrupt, and before accessing critical data, at least one uncritical instruction is necessary. This guarantees that the ISR is fin-
Save Registers
Save Interrupt Enable Flags
Enable Interrupts
Execute Interrupt
Restore Interrupt Enable Flags
Restore Registers
Write to IRRET
RTI
10.2. Registers
w1: Cancel this feature. w0: Disable Interrupt Controller after interrupt. This is the enable flag for the flag A1INT function.
0
x CLEAR x Res
IRC
7
r w x x
Interrupt Control Register
6
x x
5
x x
4
x RESET x
3
DAINT DAINT 1
2
DINT DINT 1
1
x A1INT x
DINT r1: r0: w1: w0:
Disable interrupt Interrupts are enabled. All interrupts are disabled. Enable interrupts according to priority setting. Disable all interrupts.
RESET w1: w0:
Reset No action. Momentary reset of the Interrupt Controller, all internal registers are cleared. The reset of the Interrupt Controller happens with writing zero to this Flag. It is not necessary to write a one to finish the reset. The standard Interrupt Controller function is performed by setting all flags to one. A hardware reset of the Interrupt Controller is performed by setting RESET low and the other flags to high. DAINT r1: r0: Disable after interrupt Don't disable after interrupt. Disable Interrupt Controller after interrupt.
A1INT Allow one interrupt w1: No action. w0: Serve one interrupt. This is a momentary signal. With DAINT = 0, only one interrupt (with the highest priority) will be served. The Flags DAINT and A1INT must be considered in common. They provide the possibility to serve interrupts one by one, only when the main program has enough time (see Table 10-1 on page 78). CLEAR w1: w0: Clear all requests No action. Momentarily clears all interrupt requests.
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PRELIMINARY DATA SHEET
Table 10-1: Single Interrupt Service
DAINT 0 0 1 A1INT 1 0 x Resulting function Disable after current interrupt. Serve one interrupt request. Normal interrupt mode.
IRPRI54
7
r/w 0 0
Interrupt Priority, Inputs 4 and 5
6
PRIO5 0 0 0 0
5
4
3
2
PRIO4
1
0
0
0
Res
IRPRI76
7
r/w
Interrupt Priority, Inputs 6 and 7
6
PRIO7
5
4
3
2
PRIO6
1
0
IRE
7
w
Interrupts Enable Register
6 5 4 3 2 1 0
0
0
0
0
0
0
0
0
Res
A write access enables interrupts according to priority setting (same effect as setting IRC.DINT) 0 0 0 0 0 0 0 0 Res
IRPRI98
7
r/w 0 0
Interrupt Priority, Inputs 8 and 9
6
PRIO9 0 0 0 0
5
4
3
2
PRIO8
1
0
IRE
Enable Interrupts
A write access to this memory location enables interrupts according to priority setting (same effect as setting IRC.DINT). Enabling interrupts using this register take effect not before the execution of the command, following the write access to IRE.
0
0
Res
IRPRIBA
7
r/w
Interrupt Priority, Inputs 10 and 11
6
PRIO11
5
4
3
2
PRIO10
1
0
IRRET
7
r w IPF7
Interrupt Return Register
6
IPF6
0
0
0
0
0
0
0
0
Res
5
IPF5
4
IPF4
3
IPF3
2
IPF2
1
IPF1
0
IPF0
IRPRIDC
7
Res r/w 0 0
Interrupt Priority, Inputs 12 and 13
6
PRIO13 0 0 0 0
A write access signals to the Interrupt Controller that the current request has been served 1 1 1 1 1 1 1 1
5
4
3
2
PRIO12
1
0
0
0
Res
IPF0 to 7 Interrupt Pending Flag of Input 0 to 7 r1: No interrupt is pending. r0: Interrupt is pending. w: Current request is finished. For interrupt pending flags 8 to 15, please refer to the description of register IRP. A write access to this memory location signals to the Interrupt Controller that the current request has been served.
IRPRIFE
7
r/w 0 0
Interrupt Priority, Inputs 14 and 15
6
PRIO15 0 0 0 0
5
4
3
2
PRIO14
1
0
0
0
Res
IRPRI10
7
r/w 0 0
Interrupt Priority, Inputs 0 and 1
6
PRIO1 0 0 0 0
5
4
3
2
PRIO0
1
0
PRIOn Priority of input number n r: Priority of the corresponding interrupt input. w: Priority of the corresponding interrupt input. Priority zero prevents the Interrupt Controller from being triggered, but the pending register is not affected. All incoming
Res
0
0
IRPRI32
7
r/w 0 0
Interrupt Priority, Inputs 2 and 3
6
PRIO3 0 0 0 0
5
4
3
2
PRIO2
1
0
0
0
Res
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PRELIMINARY DATA SHEET
CDC16xxF-E
requests are stored in the pending registers. Of two inputs with the same PRIO setting, the input with the higher number has priority (see Table 10-2 on page 79).
IRP
7 6
IPF14 1
Interrupt Pending Register
5
IPF13 1
4
IPF12 1
3
IPF11 1
2
IPF10 1
1
IPF9 1
0
IPF8 1 Res
Table 10-2: PRIOn usage
PRIOn 0h 1h : Fh resulting function Interrupt input is disabled Interrupt input is enabled with lowest priority : Interrupt input is enabled with highest priority
r
IPF15 1
IPF8 to 15 Interrupt Pending Flag of Input 8 to 15 r1: No interrupt is pending. r0: Interrupt is pending. For interrupt pending flags 0 to 7, please refer to description of register IRRET.
10.3. Interrupt Assignment
While most interrupt assignments are hard-wired, some are configured via HW option (see Fig. 10-3 on page 81).
Table 10-4: INT-MUX 1 = HW Option addr. FFC0H Table 10-3: Interrupt assignment
bit 1 Interrupt Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Interrupt Vector Address 00FFE2-E3 00FFE0-E1 00FFDE-DF 00FFDC-DD 00FFDA-DB 00FFD8-D9 00FFD6-D7 00FFD4-D5 00FFD2-D3 00FFD0-D1 00FFCE-CF 00FFCC-CD 00FFCA-CB 00FFC8-C9 00FFC6-C7 00FFC4-C5 Interrupt Source INT-MUX 7 INT-MUX 8 Timer 0 PINT0 PINT1 INT-MUX 1 INT-MUX 2 INT-MUX 3 CC2OR CAN 0 INT-MUX 9 UART 0 TX/RX RESET/ALARM INT-MUX 4 INT-MUX 5 INT-MUX 6 FFC0h FFC1h FFC1h bit 5 0 0 1 1 bit 4 0 1 0 1 selects PINT3-IN SPI 1 UART 1 CC1 COMP FFC2h FFC0h FFC0h FFC0h HW Option FFC1h 1 FFC1h 1 1 Timer 1 0 CAN 2 0 0 bit 0 0 1 selects CC0 COMP Timer 2
Table 10-5: INT-MUX 2 = HW Option addr. FFC0H
bit 3 0 0 1 1 bit 2 0 1 0 1 selects UART 2 P06 COMP SPI 0 Timer 1
Table 10-6: INT-MUX 3 = HW Option addr. FFC0H
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PRELIMINARY DATA SHEET
Table 10-7: INT-MUX 4 = HW Option addr. FFC0H
bit 7 0 0 1 1 bit 6 0 1 0 1 selects CAN 2 SPI 0 DMA PINT3-IN
Table 10-11: INT-MUX 8 = HW Option addr. FFC1H
bit 7 0 0 1 1 bit 6 0 1 0 1 selects CC1OR PINT2-IN IR-RTC IR-WAPI
Table 10-8: INT-MUX 5 = HW Option addr. FFC1H
bit 1 0 0 1 1 bit 0 0 1 0 1 selects Timer 2 UART 1 SPI 1 DMA
Table 10-12: INT-MUX 9= HW Option addr. FFC2H
bit 1 0 0 1 1 bit 0 0 1 0 1 selects CAN 1 UART 1 IR-RTC IR-WAPI
10.3.1. Interrupt Multiplexer Table 10-9: INT-MUX 6= HW Option addr. FFC1H
bit 3 0 0 1 1 bit 2 0 1 0 1 selects Timer 2 DIGITbus UART 2 PINT2-IN Ten interrupt inputs are directly connected to the respective module's interrupt output. Six interrupt inputs, 4 to 6 and 13 to 15, allow source selection via multiplexers. The multiplexers are configured by HW Option. Please refer to section HW Options for details.
Table 10-10: INT-MUX 7 = HW Option addr. FFC1H
bit 5 0 0 1 1 bit 4 0 1 0 1 selects CC0OR UART 1 IR-RTC IR-WAPI
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PRELIMINARY DATA SHEET
CDC16xxF-E
16 Interrupt inputs
Interrupt sources of peripheral modules
Mux 1 Mux 2 Mux 3 Mux 4 Mux 5 Mux 6 3 Mux 7 Mux 8 Mux 9 Programming of multiplexer in HW Option field Assignment is implementation specific
Interrupt Controller
Assignment is implementation specific
Fig. 10-3: Interrupt Assignment and Multiplexer
10.4. Interrupt Timing
10.4.1. Interrupt Response Time
The interrupt response time is calculated from the interrupt event up to the first interrupt vector on the address bus. After an interrupt event, the Interrupt Controller starts evaluation with the first falling edge of Phi2. Evaluation requires one clock cycle until the Interrupt Controller pulls the signal NMI low. After the falling edge of NMI the CPU finishes the actual command. If the falling edge of NMI occurs one clock cycle before an opcode fetch, the following command will be finished too. Then PC and status will be saved on stack before the low byte of the interrupt vector is written to the address bus.
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82
Finish actual command and save status. (Save status = 5 clocks (+ 1 clock if in Native Mode)). FFFA or FFEA 1) DMA Access Vector first Byte Second Byte Opcode ISR
Interrupt
Ph2
CDC16xxF-E
Interrupt Request
NMI
A0...A15
RDY
Clear Request
Interrupts enabled
DMAE
1) FFFA in 6502 mode
FFEA in 816 mode
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Fig. 10-4: Timing Diagram
PRELIMINARY DATA SHEET
Micronas
PRELIMINARY DATA SHEET
CDC16xxF-E
10.5. Port Interrupt Module
Port interrupts are the interface of the Interrupt Controller to the external world. Four U-Port pins are connected to the module via their special input lines. Port interrupt 0 and 1 can scale down the interrupt load by prescalers. Port interrupt 2 and 3 share the interrupt input with signals from other sources. HW Option programmable multiplexers define which signal is actually connected to the Interrupt Controller.
IRPP.P0INT4 0 PINT0-IN U6.0
SO
U5.7 PINT0-OUT PINT0 Interrupt Source
SI
1/4
1 IRPP.P1INT32 0
SO
U6.6 PINT1-OUT PINT1 Interrupt Source
PINT1-IN U6.1
SI SI
1/32
1
IRPM0
HW Option Mux6 INT-MUX 6 Interrupt Source INT-MUX 4 Interrupt Source INT-MUX 3 Interrupt Source
U6.2 PINT2-IN U5.6 PINT3-IN
HW Option
SI
0
HW Option Mux4
1 U5.7 PINT3-IN
SI
HW Option Mux3
Fig. 10-5: Port Interrupts
The user can define the trigger mode for each port interrupt by the interrupt port mode register. The Port interrupt prescaler can be switched by the interrupt port prescaler register. The pulse duty factor of the prescaler output is 50%. The Trigger Mode defines on which edge of the interrupt source signal the Interrupt Controller is triggered. The triggering of the Interrupt Controller is shown in Fig. 10-6 and Fig. 10-7 for port prescaler active (P1INT32 or P0INT4 = 1).
Table 10-13: Module-specific settings
Module Name PINT0 HW Options Item Address Initialization Item PINT0-IN PINT0-OUT PINT1 PINT1-IN PINT1-OUT PINT2 PINT3 Interrupt multiplexer 6 Input pin selection Interrupt multiplexer 4 Interrupt multiplexer 3 FFC1h FFC2h FFC0h FFC0h PINT2-IN PINT3-IN Setting U6.0 special in U5.7 special out U6.1 special in U6.6 special out U6.2 special in U5.6 or U5.7 special in
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PRELIMINARY DATA SHEET
Table 10-14: PITn usage
IRPM0
7
w 0 PIT3 0 0
Interrupt Port Mode Register 0
6 5
PIT2 0 0
4
3
PIT1
2
1
PIT0
0
PITn 0h
Trigger Mode Interrupt source is disabled Rising edge Falling edge Rising and falling edges Port 1 interrupt prescaler Indirect mode, 1:32 prescaler Direct mode, bypass prescaler Port 0 interrupt prescaler Indirect mode, 1:4 prescaler Direct mode, bypass prescaler
0
0
0
Res
1h 2h 3h P1INT32 w1: w0: P0INT4 w1: w0:
PITn Port interrupt trigger number n This field defines the trigger behavior of the associated port interrupt (Table 10-14).
IRPP
7
w x
Interrupt Port Prescaler Register
6
x
5
x
4
x
3
x
2
x
1
0
P1INT32 P0INT4 0 0 Res
Port U6.0 1 1/4 prescaler output Interrupt (low active) Interrupt (low active) Interrupt (low active) 2 3 4 1 2 3 4 1 2 3 4 Independent of trigger mode Falling edge Rising edge Falling and rising edge trigger mode
Fig. 10-6: Interrupt Timing (1/4 Prescaler On)
Port U6.1 32 1/32 prescaler output Interrupt (low active) Interrupt (low active) Interrupt (low active) 1 2 15 16 17 18 31 32 Independent of trigger mode Falling edge trigger Rising edge trigger Falling and rising edge trigger mode
Fig. 10-7: Interrupt Timing (1/32 Prescaler On)
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PRELIMINARY DATA SHEET
CDC16xxF-E
11. Ports
Three kinds of ports exist. The analog input port, Port 0, serves as input for the analog-to-digital converter. The universal ports, U1 to U7, serve as digital I/O and can be configured as LCD drivers. The high current ports, H0 to H3, serve as digital I/O and can be configured as stepper motor drivers.
11.1. Analog Input Port 0
The 9-bit-wide analog input port is called Port 0. Five of these analog input pins can additionally be configured as digital inputs. One pin is connected to a comparator, which can be selected as interrupt source. Features - 9-bit analog input multiplexer. - 5 bits additionally usable as digital input ports.
P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9
3 4 5 6 7 8
2
1
To A/D converter
9
To Alarm Comparator SR1.P0DIN
7 rd 6 5 4 3 2 1 0
x
x
x
P0PIN
Fig. 11-1: Port 0 with Input Multiplexer and Undervoltage Alarm Comparator
The nine analog input lines are connected to a multiplexer. The output of this multiplexer is connected to a 10-bit A/D converter. Port P0.6 is input of an undervoltage alarm comparator which is described in the A/D converter section. Five of the analog input pins (P0.1 to P0.5) may be used as digital inputs if enabled by setting the flag P0DIN in the Standby Register SR1. The digital value of the input pins can be read in the Port 0 Pin register P0PIN. These ports should either be used as analog or digital inputs. P1 to P5 r1: r0: Port 0 Digital Input 1 to 5 High level at input pin. Low level at input pin.
P0PIN
7
r x x
Port 0 Pin Register
6
x x
5
P5 x
4
P4 x
3
P3 x
2
P2 x
1
P1 x
0
x x Res
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11.2. Universal Ports U1 to U7
There are 52 Universal Port pins. The universal ports U1 to U6 are 8 bits wide. The universal port U7 is 4 bits wide. Features
PRELIMINARY DATA SHEET
- SW selectable as digital I/O or LCD driver. - LCD mode: 1:4 multiplex, 5 V supply. - I/O mode: Tristate output, current limited. - Individually programmable to deliver constant current (slew rate). - Schmitt hysteresis input buffer.
UxM.PMODE VDD
0
Special In UxD read DBy
VSS slow/fast UVDD
1
1 1
Special Out
QD DATA
Ux.y
0
0
UVSS OR
QD N/S
UxD write
UxSEG.Sy
QD TRI
UxSEG.Ty From LCD module
x: Port number 1 to 7 y: Port pin number 0 to 7
Fig. 11-2: Universal Port Circuit Diagram
Universal ports can be operated in different modes:
Table 11-1: Universal Ports Operating Modes
Modes Port Mode Normal Input and Special Input Normal Output Special Output LCD Mode Function The SW uses the ports as digital input. The port input is additionally connected to specific hardware modules. The SW uses the ports as latched digital tristate output. The output signals of specific hardware modules are directly port output source. The port bit serves as backplane/segment driver for an LC Display.
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PRELIMINARY DATA SHEET
CDC16xxF-E
The output sequence timing on backplane and segment output ports in LCD Mode is controlled by the LCD module. Please refer to section LCD Module for information about operation of this module. As generation of the backplane port output sequence is fully done by the LCD module, no segment setting is necessary for these ports. Port bits in LCD mode will always read as logical 0 as the port input buffer is turned off.
The Universal Port bits can be switched to LCD or Port mode in groups of two. The flag PMODE must be cleared to use port pins in LCD mode. If PMODE is set, they serve as I/O ports. In both LCD and Port mode, the Port Slow mode may be defined for each individual Universal port bit. It reduces the current drive capability of the output stage. After reset, all Universal Ports are in port, tristate condition.
11.2.1. Port Mode
Each port bit can be individually configured to several port modes. The output driver of each pin can be disabled (tristated) by setting the flag UxSEG.Ty. Set the S flag to select the source of the output value. For Port mode, the UxM registers have to be set for mode selection, the UxSEG registers have to be properly set for individual port bit configuration and the UxD registers serve as I/O registers. Table 11-2 shows configurations of flags if the corresponding flag PMODE is true (Port mode)
11.2.3. Port Slow Mode
The output drivers of all port pins together can be configured to operate in Fast or Slow mode by the Port Slow mode flag PSLW in register SR1. All U-Ports exhibit two operating regions in the DC output characteristic (see Fig. 11-3). Near zero output voltage the internal driver transistors operate non-limited, to offer a low on-resistance. With larger output voltages, however, a limit is imposed on the output current. This measure helps to fight supply current transients and related EMI noise during port switching.
Table 11-2: Port Mode Register Settings
Mode Normal Input S x T 1 D x Function READ of register UxD returns port pin input levels to data bus. WRITE to register UxD changes level of port pin output drivers. READ of register UxD returns the UxD register setting to the data bus. Special Input Special Output x x x Port pin input level is presented to special hardware. Special hardware drives port pin. READ of register UxD returns port pin input levels to data bus. In Port Mode, Special Input mode is always active. This allows manipulating the input signal to the special hardware through Normal Output operations by software. As the Special Output mode allows reading the pin levels, the output state of the special hardware may be read by the CPU. Ishs Port Slow Mode
Io
Nonlimited region Limited region
Normal Output
0
0
Data
Ishf
Port Fast Mode
1
0
x
0
1V
2V
3V
4V
5V
Vol
Fig. 11-3: Typical U-Port pull-down DC output characteristic (pull-up characteristic is complementary). In this limited operating region, Port Fast mode and Port Slow mode select two different current limits Ishf and Ishs. Port Slow mode reduces the output current to a value where the output may even be shorted continuously to either supply rail. Thus, wired or-configurations can be put into practice. The external load resistance should be greater than 5 kOhms in Port Slow mode. Please note that in Port Normal Output mode, a READ of register UxD returns the UxD register setting, not the pin levels.
11.2.2. LCD Mode
For LCD Mode, the UxM registers have to be cleared for mode selection and the UxSEG registers serve as segment output data registers.
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With PSLW = 0 all ports are in Fast Mode. Only port bits that are enabled via HW option will switch to Port Slow Mode with PSLW = 1. A port pin is in Fast Mode all the time if a zero is programmed to the appropriate HW option bit. It is not possible to switch this pin to Slow Mode. If a one is programmed, the pin can be toggled between Fast and Slow Mode by the
PRELIMINARY DATA SHEET
flag PSLW. Please refer to section HW Options for information on port/option assignment. It is recommended to place all LCD ports in the Port Slow mode.
11.3. Universal Port Registers
Universal Port Data Registers UxD contain input/output data of the corresponding port. The "x" in UxD means the number of the port. Thus UxD stands for U1D to U7D. Remember that port U7 is only 4 bits wide. For this reason not all of the described registers and flags are available for U7.
UxSEG32
7
w x
Universal Port x Segment Register of Ux.3 and Ux.2
6 5
T3
4
x
3
x
2
S2
1
T2
0
x Port
S3
w SEG3.3 SEG3.2 SEG3.1 SEG3.0 SEG2.3 SEG2.2 SEG2.1 SEG2.0 LCD
UxD
7
r/w D7 0
Universal Port x Data Register
6
D6 0
0
0
1
0
0
0
1
0
Res
5
D5 0
4
D4 0
3
D3 0
2
D2 0
1
D1 0
0
D0 0 Res
UxM32
7 6
x 0
Universal Port x Mode Register of Ux.3 and Ux.2
5
x 0
4
x 0
3
x 0
2
x 0
1
x 0
0
PMODE 1 Res
D0 to 7 Universal Port Data Input/Output r: Read pin level resp. data latch. w: Write data to data latch. To use a port pin as software output, the appropriate driver must be activated and the S flag must be programmed to Normal Mode. Universal Port Segment registers UxSEG together with the Universal Port Mode registers UxM are used to configure the appropriate ports in Port Mode. In LCD Mode the registers UxSEG contain the data for two segments each. For instance, register U2SEG76 and U2M76 control port U2, bits 7 and 6. Registers U1SEG10, U1SEG32, U1M10, U1M32 and U3SEG32 differ from the corresponding control registers of other ports in LCD mode. Please refer to the special description of these registers at the end of this section.
w
x 0
UxSEG54
7
w x
Universal Port x Segment Register of Ux.5 and Ux.4
6 5
T5
4
x
3
x
2
S4
1
T4
0
x Port
S5
w SEG5.3 SEG5.2 SEG5.1 SEG5.0 SEG4.3 SEG4.2 SEG4.1 SEG4.0 LCD 0 0 1 0 0 0 1 0 Res
UxM54 UxSEG10
7
w x
Universal Port x Mode Register of Ux.5 and Ux.4
6
x 0
Universal Port x Segment Register of Ux.1 and Ux.0
6 5
T1
7
w x 0
5
x 0
4
x 0
3
x 0
2
x 0
1
x 0
0
PMODE 1 Res
4
x
3
x
2
S0
1
T0
0
x Port
S1
w SEG1.3 SEG1.2 SEG1.1 SEG1.0 SEG0.3 SEG0.2 SEG0.1 SEG0.0 LCD 0 0 1 0 0 0 1 0 Res
UxSEG76
7 6
S7
Universal Port x Segment Register of Ux.7 and Ux.6
5
T7
4
x
3
x
2
S6
1
T6
0
x Port
UxM10
7
w x 0
Universal Port x Mode Register of Ux.1 and Ux.0
6
x 0
w
x
5
x 0
4
x 0
3
x 0
2
x 0
1
x 0
0
PMODE 1 Res
w SEG7.3 SEG7.2 SEG7.1 SEG7.0 SEG6.3 SEG6.2 SEG6.1 SEG6.0 LCD 0 0 1 0 0 0 1 0 Res
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PRELIMINARY DATA SHEET
CDC16xxF-E
UxM76
7
w x 0
Universal Port x Mode Register of Ux.7 and Ux.6
6
x 0
U1SEG10
7
w Res x
Universal Port 1Segment Register of U1.1 and U1.0
6 5
T1
5
x 0
4
x 0
3
x 0
2
x 0
1
x 0
0
PMODE 1
4
x
3
x
2
S0
1
T0
0
x Port LCD
S1
w LCDSLV 0 0 1 0 0 0 1 0
S0 to S7 Normal/Special Mode Flag 0 to 7 w1: Special Mode. Special hardware drives pin. w0: Normal Mode. Data latch drives pin. The corresponding Port Mode flag PMODE must be true to make this flag valid. The S flag defines from which source the port pin is driven if its output driver is active (T = 0). T0 to T7 Tristate Flag 0 to 7 w1: Output driver is tristate w0: Output driver is active The corresponding Port Mode flag PMODE must be true to make this flag valid. SEGh.0 to .3 LCD Segment Driver High, Bits 0 to 3 SEGl.0 to .3 LCD Segment Driver Low, Bits 0 to 3 In LCD Mode each port pin is controlled by a field of four LCD Segment bits. Each segment register UxSEG contains two fields of segment data, each four bit wide. "h" stands for the high, "l" for the low pin number. For instance, U2SEG76.SEG7.3 to U2SEG76.SEG7.0 control LCD segments driven by port U2.7. Please refer to Pin Assignment and Description for segment/ pin number assignment. Information about the usage of the LCD Segment field will be found at the functional description of the LCD Module. PMODE Port Mode Flag Select the mode of the corresponding port pins. w1: The two port pins are in Port mode. w0: The two port pins are in LCD mode.
Res
LCDSLV LCD Module is Slave Select the mode of the LCD module. w1: LCD module is slave. w0: LCD module is master. A write access to this memory location simultaneously loads all segment information of all universal ports in LCD mode into the display. The flag LCDSLV is available only in LCD mode. This flag is not available in other universal port registers.
U1SEG32
7
w x 0
Universal Port 1Segment Register of U1.3 and U1.2
6
S3 0
5
T3 1
4
x 0
3
x 0
2
S2 0
1
T2 1
0
x 0 Port Res
11.3.2. Special Register Layout of Universal Port 3.2
U3.2, in Port Special Output mode, provides the DIGITbus connection. For this purpose it can be switched into a Double Pull-down Mode (DPM) by setting U3SEG32.DPM2, where - the short circuit current Ishs is doubled (with Port Slow Mode enabled for U3.2 by HW Option, and SR1.PSLW set to 1) - the output configuration is pull-down, not the standard push-pull. By these means, this port may be configured to operate as connection to the wired-or, single-wire DIGITbus with external pull-up resistor.
11.3.1. Special Register Layout of Universal Port 1
Universal Port 1 pins U1.0 to U1.3 provide backplane signals in LCD Mode. To operate any ports as LCD segment driver it is necessary to switch these ports to LCD mode. All four pins will be switched together (not in groups by two) to LCD Mode by clearing the flag PMODE in register U1M30. Thus, U1M30 replaces U1M10 and U1M32.
U3SEG32 U1M30
7
w x 0
Universal Port 3 Segment Register of U3.3 and U3.2
6 5
T3
Universal Port 1 Mode Register of U1.3 to U1.0
6
x 0
7
w x
4
x
3
DPM2
2
S2
1
T2
0
x Port
5
x 0
4
x 0
3
x 0
2
x 0
1
x 0
0
PMODE 1 Res
S3
w SEG3.3 SEG3.2 SEG3.1 SEG3.0 SEG2.3 SEG2.2 SEG2.1 SEG2.0 LCD 0 0 1 0 0 0 1 0 Res
As backplane ports U1.0 to U1.3 require no segment data setting, SEG bits are not available in register U1SEG10 and U1SEG32.
DPM w1: w0:
Double Pull-Down Mode Output driver is pull-down, Ishs (Port Slow mode) doubled. Standard.
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11.4. High Current Ports H0.0 to H3.5
The High Current Ports 0, 1, 2 and 3 are used to drive coils of stepper motors. Each port is 6 bits wide. They are similar to universal ports, but as the name says, they can drive higher currents. H-Ports can be operated via software like Universal Ports (Port Mode). Their Special Out connections are connected with the stepper motor module, or with the PWM output. Features - Tristate output. - 30 mA output current.
PRELIMINARY DATA SHEET
- Schmitt hysteresis input buffers. - Reduced slew rate of current and voltage for driving resistive, capacitive or inductive loads.
HxD read VDD DBy VSS HVDD
1
Special In
Hx.y
High
0 QD DATA
Special Out HxD write
QD N/S
HVSS
HxNS.Sy
QD TRI
HxTRI.Ty
x: Port number 0 to 3 y: Port pin number 0 to 5
Fig. 11-4: High Current Port Circuit Diagram
The H-Ports H0 and H1 are supplied by the power supply pins HVDD1 and HVSS1. The H-Ports H2 and H3 are supplied by the power supply pins HVDD2 and HVSS2. HxTRI.Ty is used to switch the output driver on and off, and HxNS.S defines the mode of each port pin. Table 11-3 shows the various selectable modes.
Table 11-3: Register Settings
Mode Special Input Special Output S x T x D x Function Port pin input level is presented to special hardware. Special hardware drives port pin. READ of register HxD returns port pin input levels to data bus. The Special Outputs of high current ports are connected to the Stepper Motor module or some PWMs. Please refer to Pin Assignment and Description for information on assignment of PWMs to H-Port pins.
Table 11-3: Register Settings
1 0 x Mode Normal Input S x T 1 D x Function READ of register HxD returns port pin input levels to data bus. WRITE to HxD changes level of output, READ of HxD reads pin level
Normal Output
0
0
Data
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PRELIMINARY DATA SHEET
CDC16xxF-E
The N-channel and the P-channel transistor of the output driver are controlled separately. Thus crossover currents are eliminated. The output levels of the ports during and after reset are low, to avoid floating coils.
Twenty of the twenty-four high-current ports are connected to the stepper motor control module. Two high-current ports, together with a coil, form an H-Bridge. Two H-Bridges are necessary to operate a stepper motor. The twenty stepper motor outputs can thus drive five stepper motors.
11.5. High Current Port Registers
High Current Port Data registers are used to input/output digital values. The "x" means the number of the port. Thus HxD stands for H0D, H1D, H2D or H3D.
HxD
7
r/w x 0
High Current Port x Data Register
6
x 0
5
D5 0
4
D4 0
3
D3 0
2
D2 0
1
D1 0
0
D0 0 Res
D0 to 5 H-Port Data Input/Output r: Read pin level . w: Write data to data latch. To use a port pin as output, the appropriate driver must be activated and its S flag must be set to normal mode (S = 0). The High Current Tristate and Normal/Special registers (HxTRI and HxNS) are used to configure the corresponding port.
HxTRI
7
w x 0
High Current Port x Tristate Register
6
x 0
5
T5 0
4
T4 0
3
T3 0
2
T2 0
1
T1 0
0
T0 0 Res
HxNS
7
w x 0
High Current Port x Normal/Special Register
6
x 0
5
S5 0
4
S4 0
3
S3 0
2
S2 0
1
S1 0
0
S0 0 Res
S0 to S5 Normal/Special Mode Flag 0 to 5 w1: Special Mode. Special hardware drives pin. w0: Normal Mode. Data latch drives pin. The S flag defines from which source the port pin is driven if its output driver is active (T = 0). T0 to T5 w1: w0: Tristate Flag 0 to 5 Output driver is tristate Output driver is active
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12. A/D Converter (ADC)
This 10-bit analog-to-digital converter allows the conversion of an analog voltage in the range of 0 to URef, into a digital value. A multiplexer connects the ADC to one of 9 analog input ports. A sample and hold circuit holds the analog voltage during conversion. The duration of the sampling time is programmable. The A/D conversion is done by a charge balance A/D converter using successive approximation. Features
PRELIMINARY DATA SHEET
- A/D converter with 10-bit resolution. - Successive approximation, charge balance type. - Input multiplexer with 9 analog channels. - Sample and hold circuit. - 4/8/16/32 s conversion selectable for optimum throughput/accuracy balance. - 2.5 V to 5 V external reference input. - Zero standby current, 300 A active current.
SR1.ADC 0
AVDD
VREF
1
P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9 AVSS
4
3 4 5 6 7 8
2
1 A S&H D
10
9
2
AD1 TSAMP
r 7 9 6 8 5 7 4 6 3 5 2 4 1 3 0 2 7 6
AD0 CHANNEL x
5 w r 2 1 1 0 0
x
4
x
3
x
EOC CMPO
CMPO interrupt source
Fig. 12-1: Block Diagram
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PRELIMINARY DATA SHEET
CDC16xxF-E
12.1. Operation
12.1.1. ADC
After reset, the module is off (zero standby current). The module is enabled by the flag SR1.ADC. The user must be sure that the flag End of Conversion (EOC) in register AD0 is true, before he starts to operate the module. A write access to register AD0 indicating sample time and channel number starts the conversion. The flag EOC signals the end of conversion. The 10-bit result is stored in the registers AD1 (8 MSB) and AD0. The conversion rate depends on the software, the oscillator frequency, and the programmed sample time. The module may be operated in CPU FAST or SLOW mode. 12.1.1.1. Conversion Law The result of A/D conversion is described by the following formula: The voltage on the reference input pin VREF can be set to any level in the range from 2.56 V to AVDD. 12.1.1.2. Measurement Errors The result of the conversion mirrors the voltage potential of the sampling capacitance (typically 15 pF) at the end of the sampling time. This capacitance has to be charged by the source through the source impedance within the sampling time period. To avoid measurement errors, system design has to make sure that at the end of the sampling period, the potential error on the sampling capacitance is less than 0.1 LSB. Measurement errors can occur, when the voltage of high impedance sources has to be measured: - To reduce these errors, the sampling time may be increased by programming the field TSAMP in register AD1. - In cases where high impedance sources are only rarely sampled, a 100 nF capacitor from the input to AVSS is a sufficient measure to ensure that the potential on the sampling capacitance reaches the full source potential, even with the shortest sampling time. - In some high impedance applications a charge pumping effect may noticeably influence the measurement result: Charge pumping from a high potential to a low potential source will occur when such two sources are measured alternatingly. It results in a DC current that appears as flowing from the high potential source through the IC into the low potential source. This current is explained by the fact that during the sampling periods the high potential source always up-charges the sampling capacitance while the low potential source always discharges it.
U In DV = INT ------------- 1LSB
where
U Ref 1LSB = ----------1024
DV = Digital Value; INT = Integer part of the result
DV 3FF 3FE 3FD
12.1.2. P0.6 Comparator
03 02 01 00 1 23 1021 1023 UIn [LSB] In addition to the A/D converter the module contains a comparator. The level on port P0.6 is compared to AVDD/2. The state of the comparator output can be read at flag CMPO in register AD0. The interrupt source output of this module is routed to the Interrupt Controller logic. But this does not necessarily select it as input to the Interrupt Controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. The CMPO interrupt source is gated with an internal clock. This is the reason why interrupts are generated as long as the level at P0.6 is lower than the internal reference.
Fig. 12-2: Characteristic Curve
12.2. Registers
A write access to register AD0 starts the A/D conversion of the written channel number and sampling duration. The flag EOC signals the end of conversion. The result is stored in register AD1 (bit 9 to 2) and in register AD0 (bit 1 and 0).
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PRELIMINARY DATA SHEET
AD0
7
r w 0 EOC
ADC Register 0
6
CMPO
reset, CHANNEL is set to zero. No channel is selected in this case.
2
x
5
x
4
x
3
x
1
AN1
0
AN0
Table 12-2: ADC Input Multiplexer
CHANNEL Port Pin P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9
TSAMP 0 x x 0
CHANNEL 0 0 0 Res
1H 2H
AD1
7
r AN9
ADC Register 1
6
AN8
3H
2
AN4
5
AN7
4
AN6
3
AN5
1
AN3
0
AN2
4H 5H 6H
EOC End of Conversion r1: End of conversion r0: Busy EOC is reset by a write access to the register AD0. EOC will be set after the module has been enabled by setting SR1.ADC. Wait until EOC is set before starting the first conversion. CMPO Comparator Output r1: P0.6 is lower than reference. r0: P0.6 is higher than reference. Zero means that the voltage at P0.6 is higher than the comparator reference voltage. TSAMP Sampling Time TSAMP adjusts the sample time and the conversion time. The total conversion time is 20 clock cycles longer than the sample time.
7H 8H 9H
AN 9 to 0 Analog Value Bit 9 to 0 The 10-bit analog value is in the range of 0 to 1023. The 8 MSB can be read from register AD1. The two LSB can be read from register AD0. The result is available until a new conversion is started.
Table 12-1: Sampling Time Adjustment
TSAMP 0H 1H 2H 3H tSample 20 TOSC 60 TOSC 140 TOSC 300 TOSC tConversion 40 TOSC 80 TOSC 160 TOSC 320 TOSC
Sampling starts one clock cycle after completion of the write access to AD0. CHANNEL Channel of Input Multiplexer CHANNEL selects from which pin of port P0 the conversion is done. The MSB of CHANNEL is bit 3. No port pin is connected to the ADC, if values are selected which are not recommended by Table 12-2. In this case the result is not defined because the input of the A/D converter is open. After
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PRELIMINARY DATA SHEET
CDC16xxF-E
13. Timers (TIMER)
Three general-purpose timers are implemented. T0 is a 16bit timer, T1 and T2 are 8-bit timers.
13.1. Timer T0
Timer T0 is a 16-bit auto-reload down counter. It serves to deliver a timing reference signal to the IR, to output a frequency signal or to produce time stamps. Features - 16-bit auto-reload counter - Time value readable - Interrupt source output - Frequency output
w HW Option clk
Reload-Reg. 16
TIM0 1/2 tclk tclk TIM0 underflow & 1/2 res T0 Interrupt Source T0-OUT
r clk
16 bit Auto-reload Down counter
Fig. 13-1: Timer T0 Block Diagram 13.1.1. Principle of Operation
13.1.1.1. General Remarks The timer's 16-bit down-counter is clocked by the input clock and counts down. Falling below zero, it generates an output pulse (underflow) to get reloaded with the value in its reload register which is counted down subsequently. T0 is not affected by CPU SLOW mode. 13.1.1.3. Precautions 13.1.1.2. Operation The clock input frequency can be set via HW option (see Table 13-1 on page 96). Prior to entering active mode, the U-Ports assigned to function as T0-OUT outputs have to be properly SW initialized (Table 13-1). The ports have to be configured Special Out. Refer to "Ports" for details. T0 is always active (no standby mode). After reset, the timer starts counting with reload value FFFFh generating a maximum period output signal. A new time value is loaded by writing to the 16-bit register TIM0, high byte first. Upon writing the low byte, the reload register is set to the new 16-bit value, the counter is reset, and immediately starts down-counting with the new value. Falling below zero, the counter generates a reload signal, which can be used to trigger an interrupt. The same signal is connected to a divide-by-two scaler to generate the output signal T0-OUT with a pulse duty factor of 50%. The interrupt source output of this module is routed to the Interrupt Controller logic. But this does not necessarily select it as input to the Interrupt Controller. Check section "Interrupt 16-bit CPU commands do not generally keep to a certain order in addressing high and low bytes of a register. Make sure that the command used performs reading a 16-bit value low byte first and writing high byte first. In case of uncertainty use 8-bit commands. A load with a new value within a time period of < tclk/2 before a scheduled Interrupt Source output signal, can no longer cancel this signal. It will appear at the Interrupt Source output anyway (See fig. 13-2 for details). Controller" for the actually selectable sources and how to select them. The state of the down-counter is readable by reading the 16bit register TIM0, low byte first. Upon reading the low byte, the high byte is saved to a temporary latch, which is then accessed during the subsequent high byte read. Thus, for time stamp applications, read consistency between low and high byte is guaranteed.
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PRELIMINARY DATA SHEET
clk tclk counter 2 1 0 Reload Value Reload Value - 1
underflow critical period for loading interrupt
Fig. 13-2: Timer0 Timing
Table 13-1: Module specific settings
Module Name T0 HW Options Item Input clock Address FFA0h Initialization Item T0-OUT output Setting U3.4 special out Enable Bit
13.1.2. Registers
TIM0L
7
r w 1
T0 low byte
6 5 4 3 2 1 0
Read low byte of down-counter and latch high byte Write low byte of reload value and reload down-counter 1 1 1 1 1 1 1 Res
TIM0H
7
r w 1 1
T0 high byte
6 5 4 3 2 1 0
Latched high byte of down-counter High byte of reload value 1 1 1 1 1 1 Res
TIM0 has to be read low byte first and written high byte first.
Table 13-2: Reload Register Programming
Reload value 0000h 0001h 0002h : FFFFh Output interrupt source frequency is divided by 1 2 3 : 65536 Output T0-OUT is divided by 2 4 6 : 131072
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PRELIMINARY DATA SHEET
CDC16xxF-E
13.2. Timer T1 and T2
Timer T1 and T2 are 8-bit auto-reload down counters. They serve to deliver timing reference signals to the IR or to output frequency signals. Table 13-3 describes implementation-specific HW Option addresses and enable flags of T1 and T2. Features - 8-bit auto-reload counter - Interrupt source output - Frequency output
w HW Option clk
Reload-Reg. 8 tclk
TIMx 1/2 tclk Tx Interrupt Source 1/2 res Tx-OUT
& enable
clk
8 bit Auto-reload Down counter
underflow
&
Fig. 13-3: Timer T1 and T2 Block Diagram 13.2.1. Principle of Operation
13.2.1.1. General Remarks The timer's 8-bit down-counter is clocked by the input clock and counts down. Falling below zero, it generates an output pulse (underflow) to get reloaded with the value in its reload register which is counted down subsequently. Tx is not affected by CPU SLOW mode. 13.2.1.2. Operation The clock input frequencies can be set via HW options (see Table 13-3 on page 98). After reset, the 8-bit timer is in standby (inactive) mode. Prior to entering active mode, proper SW initialization of the U-Ports assigned to function as Tx-OUT outputs has to be made (Table 13-3). The ports have to be configured Special Out. Refer to "Ports" for details. To initialize a timer, reload register TIMx can be set to the desired time value already in standby mode. To enter active mode, set the corresponding enable bit in the standby registers (see Table 13-3 on page 98). The timer will immediately start counting down from the time value present in register TIMx. During active mode, a new time value is loaded by simply writing to register TIMx. Upon writing, the counter is reset, and immediately starts counting down from the new time value. Falling below zero, the counter generates a reload signal, which can be used to trigger an interrupt. The same signal is connected to a divide-by-two scaler to generate the output signal Tx-OUT with a pulse duty factor of 50%. The interrupt source output of this module can be, but need not be, connected to the interrupt controller directly or via multiplexer. This is a HW option which is done by the factory only. Please refer to section Interrupt Controller. Returning Tx to standby mode by resetting its respective enable bit will halt its counter and will set its outputs LOW. The register TIMx remains unchanged. The state of the down-counter is not readable. 13.2.1.3. Precautions A load with a new value within a time period of < tclk/2 before a scheduled Interrupt Source output signal, can no longer cancel this signal. It will appear at the Interrupt Source output anyway (See fig. 13-4 for details). Furthermore, disabling the timer within a time period of < tclk/ 2 before a scheduled Interrupt Source output signal, will immediately generate an extra Interrupt Source output signal. Reenabling the timer afterwards will lead to generation of the previously scheduled Interrupt Source output signal, because it was stored internally. This latter Interrupt Source output signal will be generated even if a new time value is loaded during the inactive time.
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PRELIMINARY DATA SHEET
clk tclk counter 2 1 0 Reload Value Reload Value - 1
underflow critical period for disabling/enablig and/or loading interrupt
Fig. 13-4: Timer1 and 2 Timing
Table 13-3: Module-specific settings
Module Name T1 T2 HW Options Item Input clock Input clock Address FFA7h FFA8h Initialization Item T1-OUT output T2-OUT output Setting U6.2 or U6.5 special out U3.7 special out SR1.TIM1 SR2.TIM2 Enable Bit
13.2.2. Registers
TIM1
7
w 0 0 0
Timer 1
6 5 4 3 2 1 0
Reload value 0 0 0 0 0 Res
TIM2
7
w 0 0
Timer 2
6 5 4 3 2 1 0
Reload value 0 0 0 0 0 0 Res
Table 13-4: Reload Register Programming
Reload value 00h 01h 02h : FFh Output interrupt source frequency is divided by 1 2 3 : 256 Output Tn-OUT is divided by 2 4 6 : 512
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PRELIMINARY DATA SHEET
CDC16xxF-E
14. Pulse Width Modulator (PWM)
A PWM is an 8-bit reload down-counter with fixed reload interval. It serves to generate a frequency signal with variable pulse width or, with an external low pass filter, as a digital-to-analog converter. The number of PWMs implemented is given in Table 14-1. The "x" in register names distinguishes the module number. Features - 8bit pulse width modulator - Wide range of HW option selectable cycle frequencies
PWMx
w
0 HW Option period 1 0 HW Option clock 1
Pulse Width Register
8 clk load
S Q
PWMx 0 1
8 bit down counter
zero
R
SR.PWMx
Fig. 14-1: PWM Block Diagram
14.1. Principle of Operation
14.1.1. General Remarks
A PWM's 8-bit down-counter is clocked by its input clock and counts down to zero. Reaching zero, it stops and sets the output to LOW. A period input pulse reloads the counter with the content of the PWM register, restarts it and sets the output to HIGH. A PWM is not affected by CPU SLOW mode.
14.1.4. Operation
After reset, a PWM is in standby mode (inactive) and the output signal PWMx is LOW. For entering active mode, set the respective enable bit (Table 14-1). Then write the desired pulse width value to register PWMx. Each PWM will start producing its output signal immediately after the next subsequent input pulse on its period input. During active mode, a new pulse width value is set by simply writing to the register PWMx. Upon the next subsequent input pulse on its period input the PWM will start producing an output signal with the new pulse width value, starting with a HIGH level. Returning a PWM to standby mode by resetting its respective enable flag will immediately set its output LOW. The state of the down-counters is not readable.
14.1.2. Hardware settings
The clock and period input frequencies can be set via HW option (Table 14-1). For full resolution a clock-to-period frequency ratio of 256 is recommended. Should other ratios be used, make sure that the combination of clock, period and pulse width setting allow the PWM to generate an output signal with a LOW transition. Some of the PWM outputs share pins with outputs of other modules. The output multiplexer is controlled by HW option (Table 14-1).
14.1.3. Initialization
Prior to entering active mode, proper SW initialization of the H-Ports and U-Ports assigned to function as PWMx outputs has to be made (Table 14-1). The ports have to be configured Special Out. Refer to "Ports" for details.
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Table 14-1: Module specific settings
Module Name HW Options Item PWM0 Clock and period H1.0 SME/PWM0 output multiplexer PWM1 PWM2 Clock and period Clock and period H1.1 SME/PWM2 output multiplexer PWM3 PWM4 Clock and period Clock and period Address FFA1h FFA2h FFC2h FFA3h FFA4h FFA5h FFA6h FFC2h FFA1h FFA2h FFA3h FFA4h PWM3 output PWM4 output PWM1 output PWM2 output Initialization Item PWM0 output
PRELIMINARY DATA SHEET
Enable Bit
Setting H1.0 or H2.4 special out SR0.PWM0
H3.0 special out H1.1 or U5.6 special out
SR0.PWM1 SR2.PWM2
H3.1 special out H2.5 special out
SR2.PWM3 SR2.PWM4
14.2. Registers
PWMx
7
w 0 0
PWMx Register
6 5 4 3 2 1 0
Pulse width value 0 0 0 0 0 0 Res
Table 14-2: Pulse Width Programming
Pulse width value 00h 01h 02h : FEh FFh
1)
Pulse duty factor 0% (Output is permanently low) 1/256 2/256 : 254/256 100% (Output is permanently high) 1)
Pulse duty factor 255/256 is not selectable.
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PRELIMINARY DATA SHEET
CDC16xxF-E
15. Capture Compare Module (CAPCOM)
The Capture Compare Module (CAPCOM) is a complex relative timer. It comprises a free-running 16-bit Capture Compare Counter (CCC) and a number of Subunits (SU). The timer value can be read by SW. A SU is able to capture the relative time of an external event input and to generate an output signal when the CCC exceeds a predefined timer value. Three types of interrupts enable interaction with SW. Special functionality provides an interface to the asynchronous external world. - 16-bit free running counter with read out. - 16-bit capture register. - 16-bit compare register. - Input trigger on rising, falling or both edges. - Output action: toggle, low or high level. - Three different interrupt sources: overflow, input, compare - Designed for interface to asynchronous external events
HW Option fclk
SR0.CCC
clk
CCC
Timer Value
16
ofl
CCCOFL Interrupt Source
2 2
CC0I
1 0
CAP CMP OFL LAC RCR X X X
CC0M
MCAP MCMP MOFL
FOL
OAM
IAM
CC0-IN
00 01 10 11 Input Action Logic
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
& CC0OR Interrupt Source
&
>1
3
2
&
CC0-OUT
LOW 0 0 TOGGLE 0 1 10 11 Output Action Logic
>1
16 reset load
A B
=
16-Bit Capture-Register 16-Bit Compare-Register
r w 16
CC0COMP Interrupt Source
Subunit 0
CC0
Timer Value
16
ofl
CC1-IN CC1-OUT
CC1OR
Subunit 1
Timer Value
16
CC1COMP ofl
CC2-IN CC2-OUT
CC2OR
Subunit 2
CC2COMP
Fig. 15-1: CAPCOM Module Block Diagram
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CDC16xxF-E
15.1. Principle of Operation
15.1.1. General Remarks
The Capture Compare Module (CAPCOM, Fig. 15-1) contains one common free-running 16-bit counter (CCC) and a number of capture and compare subunits (SU). More details are given in Table 15-1. The timer value can be read by SW from 16-bit register CCC. The CCC provides an interrupt on overflow. Each SU is able to capture the CCC value at a point of time given by an external input event processed by an Input Action Logic. A SU can also change an output line level via an Output Action Logic at a point of time given by the CCC value. Thus, a SU contains a 16-bit capture register CCx to store the input event CCC value, a 16-bit compare register CCx to program the Output Action CCC value, an 8-bit interrupt register CCxI and an 8-bit mode register CCxM. Two types of interrupts per SU enable interaction with SW. For limitations on operating the CAPCOM module in CPU SLOW mode, see section 15.1.5.3. SU1
PRELIMINARY DATA SHEET
Table 15-1: Unit specific settings
Subunit SU0 HW Options Item Input clock Initialization Setting U5.1 special out U5.0 special in U4.6 & U3.6 special out U4.7 special in U3.3 special out U4.6 special in SR0. CCC Enable Bit
Address Item FFA9h CC0OUT CC0-IN CC1OUT CC1-IN
SU2
CC2OUT CC2-IN
15.1.2. Hardware Settings
The CCC clock frequency must be set via HW option (Table 15-1). Refer to "HW Options" for setting them. The state of the counter is readable by reading the 16-bit register CCC, low byte first. Upon reading the low byte, the high byte is saved to a temporary latch, which is then accessed during the subsequent high byte read. Thus, for time stamp applications, read consistency between low and high byte is guaranteed. The CCC is free-running and will overflow from time to time. This will cause generation of an overflow interrupt event. The interrupt (CCCOFL) is fed directly to the Interrupt Controller and also to all SUs where further processing takes place.
15.1.3. Initialization
After system reset the CCC and all SUs are in standby mode (inactive). In standby mode, the CCC is reset to value 0000h. Capture and compare registers CCx are reset. No information processing will take place, e.g., update of interrupt flags. However, the values of registers CCxI and CCxM are only reset by system reset, not by standby mode. Thus it is possible to program all mode bits in standby mode and a predetermined startup out of standby mode is guaranteed. Prior to entering active mode, proper SW configuration of the U-Ports assigned to function as Input Capture inputs and Output Action outputs has to be made (Table 15-1). The Output Action ports have to be configured as special out and the Input Capture ports as special in. Refer to "Ports" for details. 15.1.3.1. Subunit For a proper setup the SW has to program the following SU control bits in registers CCxI and CCxM: Interrupt Mask (MCAP, MCMP, MOFL), Force Output Logic (FOL, 0 recommended), Output Action Mode (OAM), Input Action Mode (IAM), Reset Capture Register (RCR, 0 recommended), and Lock After Capture (LAC). Refer to section 15.2. for details. Please note that the compare register CCx is reset in standby mode. It can only be programmed in active mode.
15.1.5. Operation of Subunit
15.1.5.1. Compare and Output Action To activate a SUs compare logic the respective 16-bit compare register CCx has to be programmed, low byte first. The compare action will be locked until the high byte write is completed. As soon as CCx setting and CCC value match, the following actions are triggered: - The flag CMP in the CCxI register is set. - The CCxCOMP interrupt source is triggered. - The CCxOR interrupt source is triggered when activated. - The Output Action logic is triggered. Four different reactions are selectable for the Output Action signal: according to field CCxM.OAM (Table 15-2) the equal state will lead to a high or low level, or toggling or inactivity on this output. Another means to control the Output Action is bit CCxM.FOL. E.g. rise-mode and force will set the output pin to high level, fall-mode and force to low level. This forcing is static, i.e., it will be permanently active and may override compare events. Thus it is recommended to set and reset shortly after that, i.e., to pulse the bit with SW. Toggle mode of the Output Action logic and forcing leads to a burst with clock-frequency and is not recommended.
15.1.4. Operation of CCC
For entering active mode of the entire CAPCOM module set the enable bit (Table 15-1). The CCC will immediately start up-counting with the selected clock frequency and will deliver this 16-bit value to the SUs.
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come possible problems, the Input Capture Interrupt flag CCxI.CAP is double-buffered. If a second or even more input capture interrupt events occur before the interrupt flag is cleared (i.e. SW was not able to keep track), the flag goes to a third state. Two consecutive writes to this bit in register CCxI are then necessary to clear the flag. This enables SW to detect such a multiple interrupt situation and eventually to discard the capture register value, which always relates to the latest input capture event and interrupt. The internal CAPCOM module control logic always runs on the oscillator frequency, regardless of CPU SLOW mode. Avoid write accesses to the CCxI register in CPU SLOW mode since the logic would interpret one CPU access as many consecutive accesses. This may yield unexpected results concerning the functionality of the interrupt flags. The following procedure should be followed to handle the capture interrupt flag CAP: 1. SW responds to a CAPCOM interrupt, switching to CPU FAST mode if necessary and determining that the source is a capture interrupt (CAP flag =1). 2. The interrupt service routine is processed. 3. Just before returning to main program, the service routine acknowledges the interrupt by writing a 1 to flag CAP. 4. The service routine reads CAP again. If it is reset, the routine can return to main program as usual. If it is still set an external capture event overrun has happened. Appropriate actions may be taken (i.e. discarding the capture register value etc.). 5. go to 3.
15.1.5.2. Capture and Input Action The Input Action logic operates independently from the Output Action logic and is triggered by an external input in a way defined by field CCxM.IAM. As shown in Table 15-3 it can completely ignore events, trigger on rising or falling edge or on both edges. When triggered, the following actions take place: - Flag CCxI.CAP is set. - The CCxOR interrupt source is triggered when activated. - The 16-bit capture register CCx stores the current CCC value, i.e., the "time" of the external event. Read CCx low byte first. Further compare action will be locked until the subsequent high byte read is completed. Thus a coherent result is ensured, no matter how much time has elapsed between the two reads. Some applications suffer from fast input bursts and a lot of capture events and interrupts in consequence. If the SW cannot handle such a rate of interrupts, this could evoke stack overflow and system crash. To prevent such fatal situations the Lock After Capture (LAC) mode is implemented. If bit CCxI.LAC is set, only one capture event will pass. After this event has triggered a capture, the Input Action logic will lock until it is unlocked again by writing an arbitrary value to register CCxM. Please make sure that this write only restores the desired setting of this register. Programming the Input Action logic while an input transition occurs may result in an unexpected triggering. This may overwrite the capture register, lock the Input Action logic, if in LAC mode, and generate an interrupt. Please ensure that SW is prepared to handle such a situation. For testing purposes, a permanent reset (FFFFh) may be forced on capture register CCx by setting bit CCxI.RCR. Please make sure that the reset is only temporary. 15.1.5.3. Interrupts Each SU supplies two internal interrupt events: 1. Input Capture event and 2. Comparator equal state. As previously explained, interrupt events will set the corresponding flags in register CCxI. In addition to the above mentioned two, the CCC Overflow interrupt event sets flag CCxI.OFL in each SU. Thus, three interrupt events are available in each SU. The corresponding flags are masked with their mask bits in register CCxM and passed to a logical or. The result (CCxOR) is fed to the interrupt controller as a first interrupt source. In addition, the Comparator equal (CCxCOMP) interrupt is directly passed to the interrupt controller as second interrupt source. Thus a SU offers four types of interrupts: CCC overflow (maskable ored), input capture event (maskable ored) and comparator equal state (maskable ored and non-maskable direct). All interrupt sources act independently, parallel interrupts are possible. The interrupt flags enable SW to determine the interrupt source and to take appropriate action. Before returning from the interrupt routine, the corresponding interrupt flag should thus be cleared by writing a 1 to the corresponding bit location in register CCxI. The interrupts generated by internal logic (CCC Overflow and Comparator equal) will trigger in a predetermined and known way. However, as explained in 15.1.5.2. erroneous input signals may cause some difficulties concerning the Input Capture input, as well as interrupt handling. To over-
15.1.6. Inactivation
The CAPCOM module is inactivated and returned to standby mode (power down mode) by setting the enable bit to 0. Section 15.1.3. applies. CCxI and CCxM are only reset by system reset, not by standby mode.
15.1.7. Precautions
16-bit CPU commands do not generally keep to a certain order in addressing high and low bytes of a register. Make sure that the command used performs reading and writing a 16-bit value low byte first. In case of uncertainty use 8-bit commands.
15.2. Registers
The CAPCOM module counter has to be read low byte first to avoid inconsistencies.
CCC
7
r 0 0
CAPCOM Counter low byte
6 5 4 3 2 1 0
Read low byte and lock CCC 0 0 0 0 0 0 Res
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PRELIMINARY DATA SHEET
CCC
7
r 0 0
CAPCOM Counter high byte
6 5 4 3 2 1 0
CCxI
7
r/w CAP 0
CAPCOM x Interrupt Register
6
CMP 0
5
OFL 0
4
LAC 0
3
RCR 0
2
x 0
1
x 0
0
x 0 Res
Read high byte and unlock CCC 0 0 0 0 0 0 Res
CCxM
7
r/w MCAP 0
CAPCOM x Mode Register
6
MCMP 0
5
MOFL 0
4
FOL 0
3
OAM 0
2
1
IAM
0
0
0
0
Res
CAP r1: r0: w1: w0: CMP r1: r0: w1: w0: OVL r1: r0: w1: w0:
Capture Event Event. No Event. Clear flag. No change. Compare Event Event. No Event. Clear flag. No change. Overflow Event Event. No Event. Clear flag. No change.
MCAP r/w1: r/w0: MCMP r/w1: r/w0: MOFL r/w1: r/w0:
Mask CAP Flag Enable. Disable. Mask CMP Flag Enable. Disable. Mask OVL Flag Enable. Disable.
FOL Force Output Action Logic r/w1: Force Output Action logic. r/w0: Release Output Action logic. This flag is static. As long as FOL is true neither comparator can trigger nor SW can force, by writing another "one", the Output Action logic. After forcing it is recommended to clear FOL unless Output Action logic should not be locked. OAM r/w: Output Action Mode Defines behavior of Output Action logic.
LAC Lock After Capture r/w1: Enable. r/w0: Disable. Refer to section 15.1.5.2. RCR r/w1: r/w0: CCx
7
r
Reset Capture Register Reset capture register permanently to FFFFh. Release capture register. CAPCOM x Capture/Compare Register low byte
6 5 4 3 2 1 0
Table 15-2: OAM usage
Bit 32 00 01 10 11 IAM r/w: Output Action Logic Modes
w
Read low byte of capture register and lock it. Write low byte of compare register and lock it. 1 1 1 1 1 1 1 1 Res
Disabled, ignore trigger, output low level. Toggle output. Output low level. Output high level.
r
CCx
7 6
CAPCOM x Capture/Compare Register high byte
5 4 3 2 1 0
Read high byte of capture register and unlock it. Write high byte of compare register and unlock it. 1 1 1 1 1 1 1 1 Res
Input Action Mode Defines behavior of Input Action logic.
w
Table 15-3: IAM usage
Bit 10 00 01 10 11 Input Action Logic Modes Disabled, don't trigger. Trigger on rising edge. Trigger on falling edge. Trigger on rising and falling edge.
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16. Stepper Motor Module (SMM)
The SMM serves to control air-cored movements or stepper motors that are directly coupled in H-bridge formation to HPorts. Upon CPU programming it creates all waveforms necessary to position the drive pointer as desired. The number of motors that are controllable by subunits (control units) of the module is given in Table 16-4. Features - Multichannel pulse width modulated output - Outputs offset for improved EMC properties - Four quadrant operation - 8-bit resolution - HW Option selectable output cycle frequency
16.1. Functional Description
An 8-bit, free-running counter FRC (see Fig. 16-2) operates on the fSM input clock (generally 4MHz) and creates an 8-bit counter word that is fed to a number of control units SMx. A control unit (Fig. 16-2) contains 8-bit sine and cosine compare registers. One comparator each is associated with these registers and creates a compare signal when register content and FRC word are equal. An output flip-flop associated with each comparator is set when the FRC word is zero and reset by the respective compare signal. A delay stage associated with each control unit delays the flip-flop output signals by a fixed number of fSM cycles to achieve non-synchronism between the output signals of the various control units, thus achieving an improved EMC behavior of the SMM (cf. Fig. 16-1). According to the setting of a quadrant register associated with each control unit, each of a unit's two output signals is multiplexed to signals SMxn+ and SMxn- so as to properly control 2 individual H-Ports that form an H-bridge together with the connected motor coil. By these means, a control unit supplies two H-bridges with signals SMx1+, SMx1-, SMx2+ and SMx2- to function as variable pulse width modulator outputs with selectable polarity. Summing up: when the compare registers are set to the sine and cosine value of a desired rotor angle and the quadrant register is set to the desired quadrant, an air-cored movement or a stepper motor connected to the unit's 4 H-Ports will carry the proper average coil currents of proper polarity so that its rotor will assume the desired rotary angle. Three registers control readjustment of a rotor to a new angle. Sine, cosine and unit/quadrant registers serve as temporary storage of new sine, cosine, related quadrant and unit selection values. A scheduler logic times the synchronous downloading of the three buffered words to the respective unit's sine, cosine and quadrant registers, so as to avoid inconsistencies among them. A busy bit may be read out, signalling completion of the downloading.
1/ftrig ftrig =fSM /28 SMA1+ SMA1- SMA2+ tdA = 0/ fSM SMA2- SMB1+ SMB1- SMB2+ tdB = 1/ fSM SMB2- Example: SMB in 4th quadrant
Example: SMA in 1st quadrant
Fig. 16-1: Timing Diagram of Output Signals
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PRELIMINARY DATA SHEET
SR0.SM
SMVC w xx
SEL
3
x QUAD
fSM fSM /256
Busy ftrig fCLK
Scheduler
8bit FRC
OVFL
SMVSIN r xxxxxxxB Sine register w
5 Comparator sin A "=" sin A comp. latch (reload register) RS DELAY Q 0/f SM sin Quadrant register and decoder SMA1+ SMA1Load A SMA2+ SMA2-
Load
Comparator cos A "=" cos A comp. latch (reload register)
RS
DELAY Q 0/f SM
cos
SMA
4 SMB1+ SMB1DELAY 1 / fSM
SMVCOS Cosine register
sin B / cos B
Load B SMB2+
w
SMB
3
SMB2-
SMC1+ SMC1sin C / cos C DELAY 2 / fSM Load C SMC2+
SMC
2
SMC2-
SMD1+ SMD1sin D / cos D DELAY 3 / fSM Load D SMD2+
SMD
1
SMD2HW Option
SME1+ sin E / cos E DELAY 4 / fSM Load E SME1SME2+
SME
PWM2-OUT PWM0-OUT
SME2-
Fig. 16-2: Block Diagram of Output Generation Circuit
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16.2. Registers
SMVC
7
w x x
SMM Control Register
6
x x 0
SMVSIN
1
QUAD 0 0 Res
SMM Sine Register
6
x
5
4
SEL 0
3
2
x
0
r w
7
x
5
x
4
x
3
x
2
x
1
x
0
BUSY
0
x
8bit Sine Value 0 0 0 0 0 0 0 0 Res
SEL QUAD
Control unit Selection field (Table 16-1) Quadrant selection field (Table 16-2)
Table 16-1: SEL usage
SEL 000 001 010 011 100 selected control unit SMA SMB SMC SMD SME
SMVCOS
7
w 0 0
SMM Cosine Register
6 5 4 3 2 1 0
8bit Cosine Value 0 0 0 0 0 0 Res
BUSY r0: r1:
Scheduler Busy Flag Scheduler not busy Scheduler busy, do not write registers SMVC, SMVCOS, SMVSIN
Table 16-3: Usage of SMVSIN and SMVCOS registers
Value 00h 01h 02h Duty factor 0/256 (continuously low) 1/256 2/256 : 254/256 255/256 1) Pulse Diagram
No other values are permitted.
Table 16-2: QUAD setting and resulting control unit output
signal function QUAD Control unit output signal function SMx1+ 00 01 10 11 sine sine VSS VSS SMx1VSS VSS sine sine SMx2+ cosine VSS VSS cosine SMx2VSS cosine cosine VSS
: FEh FFh
1)
256/256 (continuously high) is not available.
16.3. Principle of Operation
The SMM may only be operated in CPU FAST mode.
16.3.2. Initialization
Prior to entering active mode, proper SW initialization of the H-Ports assigned to function as H-bridge outputs SMxn+ and SMxn- has to be made (Table 16-4). The H-Ports have to be configured Special Out. Refer to "Ports" for details.
16.3.1. Hardware settings
Prior to entering active mode, the fSM input clock has to be set by HW Option (see Table 16-4 on page 108). A frequency value of 4 MHz is recommended, resulting in a pulse width modulator cycle frequency of 4 MHz/256. Some H-Ports may receive the output signals either of the SMM or of PWM modules as an alternative. Refer to Table 16-4 for the necessary settings. Refer to section "HW Options" for details.
16.3.3. Operation
After reset, the SMM is in standby mode (inactive). The output lines to the H-Ports are low.
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Table 16-4: Unit specific settings
Contr. Unit SMA SMB SMC SMD SME All SME/PWM selection Input clock selection FFC2h FFAEh HW Options Item Address Initialization Item SMAn+/- outputs SMBn+/- outputs SMCn+/- outputs SMDn+/- outputs SMEn+/- outputs Setting
PRELIMINARY DATA SHEET
Enable Bit
H0.0 to H0.3 special out H1.2 to H1.5 special out H2.0 to H2.3 special out H3.2 to H3.5 special out H0.4 to H1.1 special out
SR0.SM
For entering active mode, set bit SR0.SM. The FRC will immediately start counting but the control units' output lines will still be low. 16.3.3.1. Generating Output After entering active mode, the SMM's control units are ready to receive sine, cosine and quadrant values. First load the unit/quadrant information to register SMVC, then the cosine value to register SMVCOS and at last the sine value to register SMVSIN. Upon writing SMVSIN, the scheduler logic will set flag SMVSIN.BUSY and load the buffered values to the respective unit's sine, cosine and quadrant registers on the next zero transition of the FRC, after a maximum of 256 fSM input clock cycles. After completing the
download, flag BUSY is reset and the respective unit will immediately start producing the output signals with the desired timing (see Table 16-3) on the proper pins (see Table 16-2). The above procedure for loading values to a first unit is repeated for all others. Make sure that the BUSY flag is 0 before rewriting registers SMVC, SMVCOS and SMVSIN.
16.3.4. Inactivation
Returning the SMM to standby mode by resetting bit SR0.SM will immediately halt the FRC, return all output signals to 0, reset all internal registers.
16.4. Rotor Zero Position Detection (RZPD)
In addition to above descriptions this module supports the Rotor Zero Position Detection by supplying motor blockage information. The Rotor Zero Position Detection capability is protected by a patent from Siemens VDO Automotive (SV) and may only be used with SV's prior approval.
16.4.2. Registers
SMVCMP
7
r/w x x
SMM Comparator Register
6
x x
5
ACRD 0
4
ACRB 0
3
x x
2
ACRE 0
1
ACRC 0
0
ACRA 0 Res
16.4.1. Functional Description
Each control unit contains circuitry to detect an induced voltage resulting from the rotation of the connected motor's rotor (Fig. 16-3). A comparator compares the input voltage from one of the unit's H-Ports to 1/9th of the supply voltage. A capture logic opens a capture window and samples the comparator output. The capture result signal supplies a rotor blockage information necessary for the Rotor Zero Position Detection in all cases where the CPU has lost track of the display angle of a pointer that is driven by the motor via a mechanical transmission.
ACRA to E r0: r1: w0: w1:
Analog Comparator Control and Result for SMA to SME Capture result: no induced voltage detected Capture result: induced voltage detected Stop capture and clear result flag Start capture
16.4.3. Principle of Operation
The RZPD can only be operated together with the Stepper Motor module. Switching SR0.SM connects/disconnects the comparators from supply and resets all registers. During Rotor Zero Position Detection one of a unit's H-Ports (Table 16-5) temporarily has to be operated as an input to an internal analog comparator. Reconfigure this port as Special Input. Refer to "Ports" for details.
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CDC16xxF-E
fCPU
SMA
SMA-COMP + -
Debouncer and measurement window R S Result latch
0
SMB-COMP
+ - + - + - + -
SMB
4
SMC-COMP
SMC
1
SMD-COMP
SMD
5
SME-COMP
SME
2
HVDD1 SR0.SM 8R R
HVDD2 r/w x x D B x E C A SMVCMP
54 210
8R R
Fig. 16-3: Block Diagram of Rotor Zero Position Detection Circuit
tor input voltage - are received, a '1' may be read from the questioned unit's result flag SMVCMP.ACRx, indicating that the Rotor Zero Position Detection is under way. Resetting the questioned unit's control bit SMVCMP.ACRx to 0 stops the sampling and resets the result flag. When, after a restart of the above sampling procedure and after a sufficiently long capture period, a '1' was still not read from the questioned unit's result flag SMVCMP.ACRx, this indicates that the Rotor Zero Position Detection is complete. Parallel Rotor Zero Position Detection on all control units is permitted. After completion of Rotor Zero Position Detection, reconfigure the comparator input port as Special Out.
Table 16-5: RZPD input ports
Contr. Unit SMA SMB SMC SMD SME Initialization Item SMA-COMP input SMB-COMP input SMC-COMP input SMD-COMP input SME-COMP input Setting H0.0 special in H1.2 special in H2.0 special in H3.2 special in H0.4 special in
Reading of the induced voltage at the measured motor winding is started by setting the questioned unit's control bit SMVCMP.ACRx to 1. The respective analog comparator's output will now be sampled. Once three consecutive '1' samples (spaced 1/fCPU) - indicating a sufficient analog compara-
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17. LCD Module
The Liquid Crystal Display (LCD) Module is designed to directly drive a 1:4 multiplexed liquid crystal display. It generates all signals necessary to drive 4 backplane and 48 segment lines which are output via U-Ports in LCD mode. Up to 192 segments or pixels can be controlled if all U-Ports are designated as segment outputs. In addition, the module provides functions that enable the user to cascade it with external expansion ICs providing more segment lines. It can be operated as master or slave in such an extended system. Features - 1:4 multiplex - 5 V supply
PRELIMINARY DATA SHEET
- Maximum of 192 segments - Cascadable with external expansion ICs - 0.3 mA buffered 1/3 and 2/3 voltage divider - Zero standby current - 200 A no load active current - Frame frequency HW Option selectable
17.1. Principle of Operation
17.1.1. General Remarks
Each LCD pixel or segment which is controlled by the LCD module is located at the crossing point of a segment line and a backplane line. The LCD module co-ordinates the output sequences of backplane and segment lines (see Fig. 17-3 on page 112).
17.1.2. Hardware settings
The LCD frame frequency is settable by HW option FFADh. The resulting frame frequency is the selected input frequency, divided by 120. It should be in the range from 50 Hz to 200 Hz. For best electromagnetic interference results it is recommended to operate all segment and backplane U-Ports in Port Slow mode. Refer to "Ports" for more details and to "HW-Options" for setting the corresponding HW options. Set flag PFST in register SR1 to HIGH to enable Port Slow mode.
BP3 BP2 BP1 BP0 SEGn-1 SEGn SEGn+1
17.1.3. Initialization
After reset, the LCD module is in standby mode (inactive) and all U-Ports are in Port mode, non-conducting. All U-Ports designated to function as backplane or segment outputs are to be set to LCD mode. Refer to "Ports" for more details. This will set these U-Ports to output LOW state. After reset the content of the segment registers is undefined. It must be set by writing the desired segment information to registers UxSEGy and by validating it by a write access to register U1SEG10 (write 00h for master mode, FFh for slave mode), before the LCD module is enabled.
Fig. 17-1: Segments and Backplanes
A segment pin can drive 4 different voltage levels (UVDD, 1/ 3 VDD, 2/3 VDD, VDD) in LCD mode. The output of each segment pin is controlled by the segment field of the corresponding UxSEGy register. Each such register contains the segment fields of two neighboring segment pins. A segment field is 4 bits wide. Each flag (0 to 3) of a segment field corresponds to a backplane line (BP0 to BP3). If the segment flag, corresponding with the backplane line BPx is true, the segment at the crossing of the two lines is on (black). The LCD module does not contain a display ROM translating character information into segment code. The advantage is that arbitrary characters or displays can be generated just by changing the program code. Segment information is directly entered by writing to the corresponding UxSEGy register. It is validated (loaded to all corresponding slave registers) for all segment U-Ports simultaneously by a write access to register U1SEG10. Two internal voltage sources provide the U-Port circuits and the backplane generator with the voltage levels 1/3 UVDD and 2/3 UVDD. These levels are generated by a buffered resistor divider.
17.1.4. Operation
For entering active mode, set flag LCD in register SR1. Each segment and backplane U-Port will immediately start producing its LCD output signal according to the segment information provided during initialization. During active mode, a new segment information is entered by simply writing the desired segment information to registers UxSEGy and by validating it by a write access to register U1SEG10 (write 00h while in master mode, FFh while in slave mode). Each segment and backplane U-Port will immediately start producing an LCD output signal according to the new segment information. Returning the LCD module to standby mode by resetting flag LCD in register SR1 will immediately return all segment and backplane U-Ports to the output LOW state.
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UVDD
HW Option
HW Option
1/1
fclk U1SEG10.LCDSLV SR1.LCD
8 x frame frequency UVDD
1/1,5 1/2,5
Fig. 17-2: Block Diagramm
SR1.LCD 1/15 R + R
reset
2/ 3UVDD
0
PRELIMINARY DATA SHEET
LCD CLK IN
1
LCD CLK OUT
overflow
8 State Counter + R
3
0
1
LCD SYNC IN
/3UVDD
1 UVSS
LCD SYNC OUT
U1SEG54
2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
U7SEG32
3
Back Plane Generator
1000010000100001 3
May 25, 2004; 6251-606-1PD
3
wr U1SEG10
load
3
UVDD
2/ UV 3 DD 1 /3UVDD
Analog Switch Analog Switch and and Segment Driver Segment Driver
Analog Switch Analog Switch and and Segment Driver Segment Driver
Analog Analog Analog Analog Switch Switch Switch Switch and and and and Backplane Backplane Backplane Backplane Driver Driver Driver Driver
UVSS 0 1 0 1 0 1 0 1
3
0 1
2
0 1
1
0 1
0
0
1
U1M54. PMODE
U7M32. PMODE
U1M30. PMODE
U1.5
U1.4
U7.3
U7.2
U1.3
U1.2
U1.1
U1.0
CDC16xxF-E
111
CDC16xxF-E
PRELIMINARY DATA SHEET
1 Frame VDD 2/3 Back plane BP0 1/3 0
Segment off Segment on
Back plane BP1
Back plane BP2
Back plane BP3 Seg-No. SEG63_ Bit-No. 3210 0000 Pin-No. SEG6.3
SEG64_
1000
SEG6.4
SEG65_
0110
SEG6.5
SEG66_
1010
SEG6.6
SEG67_
1111
SEG6.7
Fig. 17-3: Frame Timing Diagram
The state of the segment registers is not readable. All LCD operations are not affected by CPU SLOW mode.
For master mode, set flag LCDSLV in register U1SEG10 LOW. The module always directs signal LCD-SYNC-OUT to pins U1.4 and U6.0 and LCD-CLK-OUT to pins U1.5 and U6.1. They connect to external slave ICs' SYNC-IN and CLK-IN inputs for synchronization. For slave mode, set flag LCDSLV in register U1SEG10 HIGH. Configure pins U5.2 and U5.3 to receive signals LCDSYNC-IN and LCD-CLK-IN from an external master IC's SYNC-OUT and CLK-OUT outputs. These signals will then substitute the LCD module's own HW option frame frequency settings. Starting up and shutting down such an expanded system is described in section 17.3.
17.1.5. Cascading of LCD Driver Modules
For expansion purposes, the LCD module may be cascaded with external LCD driver ICs. Master or slave mode is selectable for the LCD module while in standby mode. Special signals provide phase and frequency synchronism for the LCD frame among the cascaded ICs.
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CDC16xxF-E
puts a full swing and the segment driver outputs a full swing of opposite polarity.
A segment at a crossing of backplane and segment lines is turned black when at the same time the backplane driver out-
17.2. Registers
U-Port registers U1SEG10, U1SEG32 and U1M30 play special roles during operation of the LCD module. Register U1SEG54 is an example for any Universal Port Segment Register with exception of U1SEG10 and U1SEG32. Refer to section Ports for detailed description. SEG15.3 Segment # 3 of Pin U1.5 This bit defines the segment at the crossing of the lines SEG1.5 (Pin U1.5) and BP3 (U1.3). w1: Segment is on (black) w0: Segment is off (white) SEG15.2 Segment # 2 of Pin U1.5 This bit defines the segment at the crossing of the lines SEG1.5 (Pin U1.5) and BP2 (U1.2). SEG15.1 Segment # 1 of Pin U1.5 This bit defines the segment at the crossing of the lines SEG1.5 (Pin U1.5) and BP1 (U1.1). SEG15.0 Segment # 0 of Pin U1.5 This bit defines the segment at the crossing of the lines SEG1.5 (Pin U1.5) and BP0 (U1.0).
U1SEG10
7
w LCDSLV 0
Universal Port x Segment Register of Ux.1 and Ux.0
6
x 0
5
x 1
4
x 0
3
x 0
2
x 0
1
x 1
0
x 0 LCD Res
LCDSLV LCD Module is Slave w1: validate all segment information and select slave mode w0: validate all segment information and select master mode
U1SEG54
7 6
Universal Port 1 Segment Register of Pin U1.5 and U1.4
5 4 3 2 1 0
w SEG15.3 SEG15.2 SEG15.1 SEG15.0 SEG14.3 SEG14.2 SEG14.1 SEG14.0 LCD 0 0 1 0 0 0 1 0 Res
17.3. Software Hints for Cascading LCD Modules
17.3.1. Power-On and Start-Up Procedure
1. The SW in master and slave configures the corresponding IC. 4. The master LCD module is switched on. LCD-CLK-OUT and LCD-SYNC-OUT switch to "01". 5. The slave CPU detects the bit combination "01" and immediately switches on the slave LCD module. The slave LCD now generates a display. Note: During the time that the slave needs to detect the bit combination "01", master and slave operate asynchronously. Suggestion: limit time to approximately 100 to 200 ms. 6. The LCD modules now operate in controlled synchronization.
Table 17-1: Suggested sequence
Master Load LCD display register. Clear flag LCDSLV. LCD-CLK-OUT, and LCD-SYNC-OUT: Configure universal ports as Special Out Ports. Slave Load LCD display register. Set flag LCDSLV. LCD-CLK-IN, and LCD-SYNC-IN: Configure universal ports as Special In Ports.
17.3.2. Operation
In order to obtain optimum synchronization of LCD switchover, a change of display must be coordinated between master and slave (preferably via IPI) so that the time lag between write accesses to U1SEG10 of the master and of the slave is kept as small as possible. Suggestion: Lower ms range or customer specification.
2. Optionally the slave signals to the master via handshake link or an inter processor interface (IPI) that it is ready to display. 3. The slave continuously scans the inputs LCD-CLK-IN and LCD-SYNC-IN for the bit combination "01" (SW debouncing required).
17.3.3. Power-Off Procedure
1. (Optional) The processor which decides that the display is
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to be switched off signals this to the other via IPI. 2. The slave continuously scans the inputs LCD-CLK-IN and LCD-SYNC-IN for the bit combination "11" (SW debouncing required). 3. The master LCD module is switched off. LCD-CLK-OUT and LCD-SYNC-OUT switch to "11". 4. The slave CPU detects the bit combination "11" and immediately switches off the slave LCD module. Note: Keep time delay as short as when switching on. 5. All LCD ports then output a low signal. The LCD display is now inactive.
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18. DMA
The DMA module allows read and write access to an external IC with minimum CPU interaction. The module is intended to support the operation of external LCD driver ICs (e.g. SED1560 by Epson): The DMA module copies 8 bit pixel data bytes by direct memory access (DMA) to the external IC's graphic RAM with the help of that IC's internal autoincrement address counter, and without CPU interaction. Other off-chip registers, allowing control of the display behavior (blinking, scrolling, etc.), are written and read by CPU operations supported and timed by the DMA module. The CPU programs the DMA module to copy an array of data from the internal to the external IC's memory. The CPU writes to or reads from external registers while the DMA module generates the necessary timing and control signals. Features - 3 operating modes: direct memory write access (DMA) without CPU interaction, support and timing of CPU write access to ext. registers, support and timing of CPU read access to ext. registers - 16 MB maximum DMA block size - one byte DMA block alignment, no confinement to banks - DMA sequence interruptible by CPU or interrupt controller - CPU cycles are stolen only during CPU bus access - flag for CPU-DMA conflict - Interrupt on DMA transfer finished - External bus cycle time selectable from Fxtal/2 to Fxtal/ 256 - Automatic generation of CPU wait states to support read access to external registers * chip internal signals BE VPA*, VDA*
*
DMA Logic
control
RDY CPU ADB DB 24 8 U7.2 U7.3 U-Port GBus Ifc Mem U2
fix
CS GRDQ GWRQ
n
GADB LCD driver
8
GDB
Fig. 18-1: Block Diagram
18.1. Principle of Operation
18.1.1. DMA Write Mode
To select the desired write timing, the corresponding bits have to be set in the DMA Initial Condition Register (DIC). To obtain the 8-bit pixel data GDB7 .. 0 on the U2.7 .. U2.0 pins, all U2 bits have to be configured as port, normal, outputs. To obtain the GWRQ control output on U7.3, this port has to be configured as port, special, output. Other signals necessary to control the external IC have to be realized by software using other ports. The range of internal addresses to be transmitted is finally set by first writing the 3 (lower) physical start address bytes to registers DSA2, DSA1, DSA0, then the 3 (upper) physical end address bytes to registers DEA2, DEA1 and DEA0. The module generates the physical 24-bit address, as it is presented to the memory, even with alternative banking mode. Refer to the Memory Banking section for translation of logical addresses as generated by the CPU to physical addresses.
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Upon writing DEA0 the DMA module will immediately begin presenting data on U2 and corresponding control signals on U7.3. During the necessary DMA access cycles to the internal addresses a wait cycle is generated for the CPU whenever it tries to perform a bus cycle itself. During operation, a DMA transfer active status bit (DCS.DTA) is readable from the DMA Control and Status register DCS to indicate that a requested transfer is not finished. A busy status bit (DCS.BSY) is readable to indicate that the DMA is currently active and not halted by the Interrupt Controller or by software. Other bits in the DCS are writable to immediately stop a running DMA sequence, and to restart it, or to allow the Interrupt Controller, when active, to stop and when inactive, to restart it. Upon reaching the end address setting the DMA module finishes operation. At this time the DMA interrupt source output is triggered. The interrupt source output of this module is routed to the Interrupt Controller logic. But this does not necessarily select it as input to the Interrupt Controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them.
PRELIMINARY DATA SHEET
sary to control the external IC have to be realized by software using other ports. The CPU configures and operates U2 as port, normal, output. Upon the CPU writing the U2 Data Register (U2D), the DMA module will present corresponding control signals for one write cycle to the external IC on U7.3. If the CPU tries to rewrite U2D before the previous cycle is finished, the DMA module halts the CPU by generating the appropriate number of wait cycles. During operation a busy status bit (BSY) in the DMA Control and Status Register (DCS) is readable to indicate the busy condition.
18.1.3. CPU Read Mode
To select the desired read timing and to use U2 data reads as cycle trigger the corresponding bits have to be set in the DMA Initial Condition Register (DIC). To obtain the GRDQ control output on U7.2, this port has to be configured as port, special, output. Other signals necessary to control the external IC have to be realized by software using other ports. The CPU configures and operates U2 as port, normal, input. Upon the CPU reading the U2 Data Input (U2D), the DMA module will present corresponding control signals for one read cycle from the external IC on U7.2. The DMA module halts the CPU by generating the appropriate number of wait cycles, until the data read cycle from the external IC is complete. Thus one CPU read of U2D is sufficient to read data from external IC.
18.1.2. CPU Write Mode
To select the desired write timing and to use U2 data writes as cycle trigger, the corresponding bits have to be set in the DMA Initial Condition Register (DIC). To obtain the GWRQ control output on U7.3, this port has to be configured as port, special, output. Other signals neces-
18.2. Registers
The DMA control registers are located in the I/O area. out rewriting the start address register every single time. Only the end address has to be updated in this case. The end address has to be initialized with the address pointing to the first byte after the block to be transferred. Writing the low byte of the end address (DEA0) starts the DMA sequence. The first transfer starts after the next opcode fetch. The compare signal stops the DMA sequence if both pointers, DSAx and DEAx, point at the same memory location. A start or restart is not possible in this case. The DMA Control and Status Register (DCS) shows the CPU whether a requested DMA transfer is not yet finished (DTA flag), whether a DMA transfer is active and not halted, or a CPU access is not yet finished (BSY flag), or if a DMA CPU conflict (DCC flag) has occurred. DCC is set true, if the data, mode or tristate register of U-Port 2 is addressed by the CPU though the DMA logic is active. DCC will not be set, if the respective registers of U-Port 7 are addressed. It allows the CPU to stop (interrupt) and start (continue) a DMA sequence. Furthermore, it lets the CPU define whether an interrupt may stall a DMA sequence.
Table 18-1: DMA Control Registers
Mnemonic DCS DIC DSA0 DSA1 DSA2 DEA0 DEA1 DEA2 Name DMA Control/Status DMA Initial Configuration Start Address 0 (low byte) Start Address 1 Start Address 2 End Address 0 (low byte) End Address 1 End Address 2
The registers DSAx (start address) and DEAx (end address) are writable by the CPU. Write the address of the first byte to be transferred into the start address register. After the DMA has finished it points to the first byte after the transferred block. This makes it easy to transfer consecutive blocks with-
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23
16 15
87
0
End Address Register (0...23) (End Address + 1)
=
DTA
23
16 15
87
0
Start Address (0...23) Upcounter
24 DMAE 0...23 ADB (0...23)
Fig. 18-2: DMA Address Generator
With BSY true, the CPU must neither access the ports or the DMA address registers, nor change the DMA Initial Configuration register (DIC). Even after interrupting a DMA sequence by setting the STP flag, it is necessary to guarantee that the BSY flag was cleared by the DMA logic, before changing those registers. With DSI active a DMA sequence is stopped while an interrupt is served. In this case the DMA sequence doesn't lengthen an interrupt service routine. The start of an interrupt sends a stop signal to the DMA logic. Only the first of the nested interrupts sends this stop signal. The end of an interrupt (the last interrupt if they are nested) sends a start signal to the DMA logic. From this reason, each interrupt can start a DMA sequence if DSI is true. The only way to avoid a wrong start is to guarantee that the two address registers DSAx and DEAx point to the same memory location. DSI active implies other restrictions to the user: You can stop a DMA sequence within an interrupt, but it is not continued until the end of the last of nested interrupts. You can start a DMA sequence within an interrupt and it is not stopped by nested interrupts, until the main program is interrupted again. Normally, a DMA sequence will be started by writing the end address to the appropriate registers. Writing to DEA0 starts the DMA sequence. So this byte has to be written last. If a DMA sequence is interrupted by SW, it has to be continued by rewriting DEA0 or by writing a one to BSY. A new DMA sequence may be started too by setting BSY, if the end address hasn't changed. In this case the start address has to be rewritten because it points at a position after the last transferred byte. The DMA Initial Configuration Register (DIC) contains wait state stuff like the duration of external access cycles or whether wait states should be generated. If the flag WSA (Wait States Active) is cleared, the U-Port 2 may be used as normal I/O or LCD port. In this case no wait states are generated with CPU access but with DMA access. The bits WSA, WS0, WS1 and WS2 must not be modified if DTA or BSY are true.
DCS
7
r/w x 0
DMA Control and Status Register
6
x 0
5
x 0
4
DTA 0
3
DSI 0
2
DCC 0
1
STP 0
0
BSY 0
Note
Res
DTA r1: r0:
DMA Transfer Active DMA transfer active. No DMA transfer active.
DSI DMA Stopped by Interrupt r/w1: DMA stops during interrupt. r/w0: DMA continues during interrupt. DSI should only be modified when DTA is zero. DCC r1: r0: w0: STP w1: w0: BSY r1: r0: w1: w0: DMA CPU Conflict DMA CPU conflict. No DMA CPU conflict. Clears DCC flag. Stop DMA sequence Stops the DMA sequence. Nothing happens. Busy DMA or CPU sequence is active. DMA or CPU sequence is not active. Starts the DMA sequence. Nothing happens.
The two flags BSY and STP should be used in common. Table 18-2 shows the possible bit combinations.
Table 18-2: BSY and STP Usage
STP 0 0 1 1 BSY 0 1 0 1 No action Start DMA sequence Stop DMA sequence Not allowed
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DIC
7
w x 0
DMA Initial Configuration Register
6
WS2 0
5
WS1 0
4
WS0 0
3
x 0
2
x 0
1
x 0
0
WSA 0
Note
WSA Wait States Active w1: Wait states at CPU access to U2 and generation of GWRQ and GRDQ. w0: No wait states (RDY) and no control signals (GWRQ, GRDQ) at CPU access. At DMA wait states are always generated. The wait state logic controls the duration of external bus cycles (see Table 18-3 on page 118). It defines the maximum number of cycles the CPU is stopped. Not each kind of access stops the CPU the maximum number of cycles. Only a read from the external memory causes the wait state logic to generate the (programmable) maximum number of wait states. A write stops the CPU only if the previous access is not finished. A DMA sequence causes the CPU to stop for one Phi2 clock at each byte transfer. The next DMA happens after n-1 Phi2 clocks if n is the programmed number of wait states. The timing in Table 18-4 relate on a system clock of 10MHz. The external address has to be written by SW to the data latch. So the SW must guarantee the required address setup time. The GWRQ high to GWRQ low time ratio is symmetrical at DMA accesses. The SW has to guarantee the required GWRQ high time at CPU accesses. In this case the programmer can not rely on self timing with the RDY signal. At consecutive write accesses the GWRQ high time is exactly 2 Phi2 clocks.
Res
WS2 to 0 Wait States Bit 2 to 0 Write only field for programming the number of wait states.
Table 18-3: Wait States
WS2 to 0 0 1 2 3 4 5 6 7 #WS 2 4 8 16 32 64 128 256 Ext. Bus Frequency Phi2/2 Phi2/4 Phi2/8 Phi2/16 Phi2/32 Phi2/64 Phi2/128 Phi2/256 @ 10 MHz 5 M (Reset) 2.5 M 1.25 M 625 k 312.5 k 156.25 k 78 k 39 k
Table 18-4: Bus timing at 10 MHz
#WS tWDS min. tACC max. tDWH max. tDDH max. tCWH max. 2 125 150 100 4 325 350 200 8 725 750 400 16 1525 1550 800 32 3125 3150 1600 64 6325 6350 3200 128 12725 12750 6400 256 25525 25550 12800 Units ns ns ns ns ns
50 (always constant 1/2 Phi2) 200 (always constant 2 Phi2)
tWDS: Write data setup time tACC: Read access time tDWH: DMA write high time tDDH: DMA write data hold time tCWH: CPU write high time
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18.3. Ports
The access to external memory is done by universal ports. The assignment to external signals is shown in Table 18-5. Table 18-6 shows the settings of the port configuration registers in different modes.
Table 18-5: Port Assignment
Port U2.0 : U2.7 1) U7.2 U7.3 Name GDB0 : GDB7 GADB GRDQ GWRQ External address bus External read signal External write signal External data bus
1) Any universal port may be used as address output port. Table 18-6: Port Configurations
Mode DMA Write, CPU Write Register U2SEG10, 32, 54, 76 U2M10, 32, 54, 76 U7SEG32 U7M32 CPU Read U2SEG10, 32, 54, 76 U2M10, 32, 54, 76 U7SEG32 U7M32 Setting 00H 01H 44H 01H 22H 01H 44H 01H Normal, out Port mode Special, out Port mode Normal, in Port mode Special, out Port mode
18.4. SW Application Hints
CPU must run in CPU FAST mode when accessing external memory. Don't try to access (CPU or DMA) in CPU SLOW mode. Port fast mode is recommended, to guarantee the timing between control signals and data. Don't try to access the external memory or the involved ports while a DMA sequence is running (DCS.DTA=1). The ports must be initialized depending on the kind of access (DMA, write, read). Don't reconfigure ports or addresses (DSAx, DEAx) as long as the flags DCS.DTA or DCS.BSY are true. This may cause problems, particularly if more than two wait states are programmed. The flag BSY will be set if the CPU accesses external addresses too. BSY will be cleared after the transfer cycle has finished. All involved ports and external addresses may be read or written as long as there is no DMA working (DTA=0, BSY =0). If a DMA is working (DTA=1) or a CPU access to an external address is not finished (BSY=1), it is neither allowed to access the involved ports and the DMA start and end address pointers, nor to change the configuration of the wait state logic. If there is an access, this is a programming error. Both accesses (DMA and CPU) are disturbed. A flag signals the occurrence of this conflict for debugging purposes. There are two different modes to operate the DMA logic. In the DMA high priority mode a DMA sequence is not affected by an interrupt. DMAs take place during an interrupt service routine. Each DMA steals one cycle of the ISR. In the DMA low priority mode, a DMA sequence is stalled by an interrupt and continues after the end of the ISR. The ISR is not lengthened by an active DMA sequence.
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18.4.1. DMA High Priority Mode
The flag DSI is, and remains, set to zero. A DMA may interrupt an interrupt service routine. A DMA sequence may be started, stopped, the registers and ports may be modified everywhere if you make sure that the flags BSY/DTA are false. The overall initialization has to be done once after each reset. Overall initialization: - Configure WSA, WS0, WS1 and WS2. Set DSI to zero. - Switch data port U2.0 to U2.7 to normal mode. - Switch address port to normal mode and activate output driver. - Switch control port U7.2 and U7.3 to special mode and activate output driver. CPU read: DMA write: - Activate output driver of data port U2.0 to U2.7. - Write destination address to address port. - Write start address to registers DSA2 to DSA0. - Write end address + 1 to registers DEA2 to DEA0. Writing to register DEA0 starts the DMA sequence. CPU write: - Activate output driver of data port U2.0 to U2.7. - Write external address to address port. - Write to data port U2. CPU read: - Deactivate output driver of data port U2.0 to U2.7. - Write external address to address port. - Read from data port U2. CPU write: DMA write:
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- Activate output driver of data port U2.0 to U2.7. - Write destination address to address port. - Clear DSI. - Write start address to registers DSA2 to DSA0. - Write end address + 1 to registers DEA2 to DEA0. Writing to register DEA0 starts the DMA sequence. - Set DSI.
- Activate output driver of data port U2.0 to U2.7. - Write external address to address port. - Write to data port U2.
- Deactivate output driver of data port U2.0 to U2.7. - Write external address to address port. - Read from data port U2. 18.4.2.1. Unwanted DMA Interrupts in Low Priority Mode On leaving interrupt service in Low Priority Mode (DSI=1), the DMA-HW generates a compare of start and end address register. If they are not equal, a halted DMA sequence is continued. But if they are equal, a DMA interrupt is generated instantly. DMA interrupts are generated at every compare, if the result is equal. Thus, an unwanted DMA interrupt is generated every time the DSI function tries to restart a DMA that has no transfers pending. To work around these unwanted interrupts, the following measures should be taken: - No special measures have to be taken if a new DMA sequence is initiated within the DMA ISR (Interrupt Service Routine). - If no new DMA sequence has to be initiated within a DMA ISR, it is necessary to either clear flag DSI (High Priority Mode), or to disable the DMA interrupt at the Interrupt Controller, within the DMA ISR. - After starting a DMA sequence from within the main routine, DSI has to be set and/or DMA interrupt has to be enabled again.
18.4.2. DMA Low Priority Mode
With the flag DSI set to one, any interrupt will stop a DMA sequence. The user may modify the DMA logic setting within an ISR as long as flag DTA is zero. If you want to stop a running DMA sequence by setting flag STP, it is advisable to clear flag DSI with the same write access to DSC. Otherwise the next interrupt would restart this interrupted DMA sequence. The overall initialization has to be done once after each reset. Overall initialization: - Configure WSA, WS0, WS1 and WS2. Set DSI to one. - Switch data port U2.0 to U2.7 to normal mode. - Switch address port to normal mode and activate output driver. - Switch control port U7.2 and U7.3 to special mode and activate output driver.
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18.5. Timings
Phi2 ADB DB GADB GDB
CPU CPU DMA-Dest.-Adr. DMA1 DMA2 DMA3 DMA-Src-1 DMA1 CPU1 CPU1 DMA-Src-2 DMA2 CPU2 CPU2 DMA-Src-3 DMA3 CPU4 CPU4
tDDH GWRQ VPA * VDA * RDY * BE * DMAE * Count * Busy *
DMA internal DMA external
* chip internal signals
Fig. 18-3: DMA Write, WS = 2
Every second cycle is stolen from the CPU. The external DMA transfer lasts 2 cycles. The CPU computes an internal operation at the same time with the third DMA. In this case the CPU is not stopped. CPU3 is not visible on the buses ADB or DB.
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Phi2 ADB DB GADB GDB
CPU CPU DMA-Dest-Adr DMAx DMA1 DMA2 DMA-Src-1 DMA1 CPU1 CPU1 CPU2 CPU2 CPU3 CPU3 DMA-Src-2 DMA2 CPU4 CPU4
tWDS GWRQ tDWH RDY * BE * DMAE * Count * Busy *
DMA internal DMA external
tDDH
* chip internal signals
Fig. 18-4: DMA Write, WS = 4
Phi2 ADB DB GADB GDB GWRQ
CPU internal CPU external CPU1 CPU1 CPU1 CPU1
Fig. 18-5: CPU Write, WS = 2
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Phi2 ADB DB GADB GDB GWRQ RDY * tCWH
CPU1 CPU1 CPU2 CPU1 CPU1 CPU2 CPU2
CPU internal
CPU external
* chip internal signals
Fig. 18-6: CPU Write, WS = 4, with RDY because CPU rewrites to fast.
Phi2 ADB DB GADB GDB GRDQ RDY * tACC
CPU1 CPU1 CPU1 CPU1
CPU internal
* chip internal signals
Fig. 18-7: CPU Read, WS = 2
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Phi2 ADB DB GADB GDB GRDQ RDY *
CPU internal CPU1 CPU1 CPU1 CPU1
* chip internal signals
Fig. 18-8: CPU Read, WS = 4
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19. Serial Synchronous Peripheral Interface (SPI)
An SPI module provides a serial input and output link to external hardware. An 8 or 9-bit data frame can be transmitted synchronized to an internally or externally generated clock. The number of SPIs implemented is given in Table 19-1. The "x" in register names distinguishes the module number. Features - 8 or 9-bit frames - Internal or external clock - Programmable data valid edge - Three internal clock sources programmable - Input deglitcher for clock and data
HW Option
SPIx-D-IN
SI
1
0 0
Deglitcher
1 1
0
shift in
1 HW Option
SPIx-D-OUT
SO
1
0
0
shift out
8 1 1 RXSEL BIT8 INTERN 7 6 5 4 3 2
SPIxD
1 0
Deglitcher
7 LEN9 3xTosc NEDGE
SPIxM
6 5 4 3 2 1 0
SPIx Interrupt Source
Scheduler
clk
D1 D0 0 0 F0SPI 0 1 F1SPI 1 x F2SPI
SR0.SPIx
0
SPIx-CLK-OUT
SO
clkout
2
1
1
SPIx-CLK-IN
SI
Deglitcher 1
0
1 HW Option HW Option extclk 0
F0SPI F1SPI F2SPI
1 0 CSF0/1
1/1 3:1 MUX 1/1,5 1/2,5
intclk 1 INTERN
2
Fig. 19-1: Block Diagram
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19.1. Principle of Operation
19.1.1. General Remarks
A SPI serves as an 8 or 9 bit wide input/output shift register. Either an internally or an externally generated clock can be used to shift data in and out. The input SPIx-D-IN is connected to the LSB of the shift register. The output of the shift register is connected to output signal SPIx-D-OUT. Thus each time a frame is transmitted by shifting bits out, bits are shifted in simultaneously and vice versa. Deglitchers in the data and clock input paths are active only in external clock mode. The input and output can be inverted by HW Option. If the deglitcher is active, input changes polarity after three consecutive samples have shown the same new polarity. Thus, a delay of three oscillator clock cycles is introduced. This feature imposes a limit on the maximum transmission frequency. The interrupt source output of this module is routed to the Interrupt Controller logic. But this does not necessarily select it as input to the Interrupt Controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. SPIs are not affected by CPU SLOW mode.
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Table 19-1: Module specific settings
Module HW Options Initialization Name Item Address Item Setting All SPIs F0SPI clock F1SPI clock F2SPI clock SPI0 D in inversion D out inversion Prescaler FFAFh SPI0-D- U6.5 IN special input in SPI0-D- U6.4 special OUT out output SPI0CLK-IN input SPI0CLKOUT output SPI1 D in inversion D out inversion Prescaler FFB0h U6.3 special in U6.3 special out SR0. SPI1 SR0. SPI0 FFB1h FFB0h FFAFh Enable Bit
FFAFh
FFAEh
19.1.2. Hardware settings
Clock frequency settings and the polarity of the data connections of the SPIs can be set via HW Options (Table 19-1). Refer to "HW Options" for setting them.
19.1.3. Initialization
After reset, a SPI is in standby mode (inactive). Prior to entering active mode, proper SW configuration of the U-Ports assigned to function as data in- or outputs and clock in- or outputs has to be made (Table 19-1). Refer to "Ports" for details. For entering active mode of a SPI, set the respective enable bit (Table 19-1). Prior to operation, the desired clock frequency and telegram length have to be selected. 19.1.3.1. Clock Source The SPI can be operated as clock master, using an internally generated clock, or as clock slave, using an externally generated clock. The flag INTERN must be set in the SPIxM Mode register to operate the SPI as clock master. There are several options for selection of the internal clock. Each input of a 3 to 1 multiplexer can be programmed by HW Options to a different frequency. These three input frequencies F0SPI, F1SPI and F2SPI are used for all SPIs. The output of the 3 to 1 multiplexer is programmed by way of clock selection field (CSF) in register SPIxM. This clock can be used as shift clock directly or divided by 1.5 or 2.5. This selection is done by HW Option too. The shift clock is output by signal SPIx-CLK-OUT which can be inverted by the flag NEDGE of register SPIxM. If flag INTERN is zero, the SPI operates as clock slave and an externally generated clock is used. The external clock is
SPI1-D- U3.1 special IN in input SPI1-D- U3.0 OUT special output out SPI1CLK-IN input SPI1CLKOUT output U3.5 special in U3.5 special out
FFB0h
FFAEh
input by signal SPIx-CLK-IN and can be inverted by the flag NEDGE. The data valid edge of the clock is defined by flag NEDGE in register SPIxM. 19.1.3.2. Telegram Length Flag LEN9 in register SPIxM defines the length of a transferred frame. The ninth bit of the shift register is read or written at the location of flag BIT8 in register SPIxM.
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any running receive or transmit operation and will reset all internal registers.
19.1.4. Operation
19.1.4.1. Transmit Mode Transmission is initiated by a write access to data register SPIxD. The SPI will immediately begin transmitting the selected number of data bits out from its shift register, in synchronism with the selected clock. A write access during a transmission is ignored. The frame is transmitted MSB first. In nine-bit mode flag BIT8 is MSB of the shift register (Fig. 19-2, 19-3). At the end of the frame, an interrupt source signal is generated which may be selected to trigger an interrupt. 19.1.4.2. Receive Mode The receive mode must be activated by a write access to register SPIxD. The SPI will immediately begin clocking in the selected number of data bits into its shift register, in synchronism with the selected clock. At the end of the frame, an interrupt source signal is generated which may be selected to trigger an interrupt.
19.1.6. Precautions
A single-wire bus is easiest implemented by a wired-or configuration of the SPIx-D-OUT output port and the open drain output of the external transmitter: simply configure the SPIx-D-OUT output port in Port Slow mode, always operate it in Port Special Output mode and connect it directly to the external open drain output. An external pull-up resistor is not necessary in this configuration because the SPIx-D-OUT output port supplies the necessary pull-up drive. If the SPIx-D-OUT output port has to be operated in Port Fast mode, this simple scheme is not possible, because the pull-down action of the external open drain output may exceed the absolute maximum current rating of the SPIx-DOUT output port. A discrete external wired-or is recommended for this situation. During operation, please make sure that the external clock does not start until after SPIxD has been written, otherwise correct data transfer is not be guaranteed. Attention must be paid to the neutral level of the external clock. Neutral level is defined high when data are valid on the rising clock edge. Neutral level is low otherwise.
19.1.5. Inactivation
Returning an SPI module to standby mode by resetting its respective enable bit (Table 19-1) will immediately terminate
19.2. Registers
The following registers are available once for SPI0 and SPI1 each. INTERN r/w0: r/w1: NEDGE r/w0: r/w1: Internal/External Clock Selection Use external clock. Use internal clock. Negative Edge Selection Data valid at rising edge. Data valid at falling edge.
SPIxD
7
r/w 0 0
SPI x Data Register
6 5 4 3 2 1 0
Bit 7 to 0 of Rx/Tx Data 0 0 0 0 0 0 Res
CSF Clock Selection Field w: (Table 19-2) With these two bits one out of three internal clocks can be selected (see Fig. 19-1 on page 125).
SPIxM
7
r w BIT8 BIT8 0
SPI x Mode Register
6
LEN9 LEN9 0
Table 19-2: CSF usage
1
x CSF 0 0 Res
5
4
3
2
x x 0
0
x
RXSEL INTERN NEDGE RXSEL INTERN NEDGE 0 0 0
CSF 1 0 0 0 0 1 x
Source of internal clock
F0SPI F1SPI F2SPI
BIT8 r/w: LEN9 r/w0: r/w1: RXSEL r/w0: r/w1:
Bit 8 of Rx/Tx Data Rx/Tx data bit. Frame Length 9 Bit Selection 8 bit mode. 9 bit mode. Receive Selection Input active. Low level at input.
1
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19.3. Timing
PRELIMINARY DATA SHEET
wr SPIxD clk out SPIx-D-OUT SPIx-D-IN SPIx Int. Src. D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
Fig. 19-2: Nine bit frame. Data valid at rising edge.
wr SPIxD clk out SPIx-D-OUT SPIx-D-IN SPIx Int. Src. D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
Fig. 19-3: Eight bit frame. Data valid at falling edge.
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20. Universal Asynchronous Receiver Transmitter (UART)
A UART provides a serial Receiver/Transmitter. A 7-bit or 8bit telegram can be transferred asynchronously with or without a parity bit and with one or two stop bits. A 13-bit baud rate generator allows a wide variety of baud rates. A twoword receive FIFO unburdens the SW. Incoming telegrams are compared with a register value. Interrupts can be triggered on transmission complete, reception complete, compare and break. The number of UARTs implemented is given in Table 20-1. The "x" in register names distinguishes the module number. Features - 7-bit or 8-bit frames. - Parity: None, odd or even. - One or two stop bits. - Receive compare register. - Two-word receive FIFO. - 13-bit baud rate generator.
UAxIF
2 ADR 1 BRK 0 RCVD r 2 ADR
UAxIM
1 BRK 0 RCVD w
UAxD
r
UAxCA compare address register
w
rx FIFO
&
3
8
=
8
8
UART Interrupt Source
>1
&
break
rx shift register
2 of 3
rx
&
received 4
rx control
tx control
RBUSY EMPTY TBUSY OVRR BRKD FRER PAER FULL
tx shift register
r w
tx
1
tx
7 7
6 6
5 5
4 4
3 3 STPB
2 2 ODD
1 1 PAR
0 0 LEN
UAxD tx data register
w
UAxC
4
UAxBR1 clk
clk
UAxBR0
clk
1/8
fBR fsample
5 bit down cnt
zero
8 bit down counter
zero
Fig. 20-1: Block Diagram
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20.1. Principle of Operation
20.1.1. General Remarks
A UART module contains a receive shift register that serves to receive a telegram via its RX input. A FIFO is affixed to it that stores two previously received telegrams. A transmit shift register serves to transmit a telegram via its TX output. Other features include a receive compare function, flexible interrupt generation and handling, and a set of control, error and status flags that facilitate management of the UART by SW. The interrupt source output of this module is routed to the Interrupt Controller logic. But this does not necessarily select it as input to the Interrupt Controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. A programmable baud rate generator generates the required bit clock frequency. A UART module is not affected by CPU SLOW mode. A UART module is only capable of receiving telegrams that differ by no more than 2.5% from its own baud rate setting.
PRELIMINARY DATA SHEET
20.1.3. Initialization
After reset, a UART is in standby mode (inactive). Prior to entering active mode, the U-Ports assigned to function as RX input and TX output have to be properly SW configurated (Table 20-1). The RX port has to be configured Special In and the TX port has to be configured Special Out. Refer to "Ports" for details. For entering active mode of a UART, set the respective enable bit (Table 20-1). Prior to operation, the desired baud rate, telegram format, compare address and interrupt source configuration have to be done. 20.1.3.1. Baud Rate Generator The receive and transmit baud rate is internally generated. The Baud Rate registers UAxBR0 (low byte) and UAxBR1 (high byte) serve to enter the desired 13bit setting. Write UAxBR0 first, UAxBR1 last. The baud rate generator is a 13-bit down-counter which is clocked by fOSC. It generates the sample frequency: f OSC f sample = -------------------------------------------------------------------------------Value of Baud Rate Registers + 1 Its output frequency fsample is divided by eight to generate the baud rate (bit/second).
20.1.2. Hardware settings
The polarity of most RX and TX connections of the UART can be set via HW Options (See Table 20-1 and Fig. 20-2). Refer to "HW Options" for setting them.
SR.UARTx tx fOSC clk UARTx
HW Option
0
UARTx-TX
f OSC f sample BR = ---------------------------------------------------------------------------------------------- = -------------( Value of Baud Rate Registers + 1 ) x 8 8
1
1
SO
UARTx-RX f OSC Value of Baud Rate Registers = ---------------- - 1 BR x 8
0
rx 1
1
SI
HW Option
Fig. 20-2: Context Diagram
20.1.3.2. Telegram Format The format of a telegram is configured in the Control and Status register UAxC. A telegram starts with a start bit followed by the data field. The data field consists of 7 or 8 data bit. There can be a parity bit after the data field. The telegram is finished by one or two stop bits (see Table 20-3 on page 134).
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Table 20-1: Module-specific settings
Module Name UART0 HW Options Item RX inversion TX inversion UART1 RX inversion TX inversion UART2 RX inversion TX inversion Address FFB4h FFB4h FFB5h FFB5h FFB4h FFB4h Initialization Item UART0-RX input UART0-TX output UART1-RX input UART1-TX output UART2-RX input UART2-TX output Setting U4.4 special in U4.5 special out U5.7 special in U5.4 special out U4.2 special in U4.3 special out SR0.UART2 SR2.UART1 SR1.UART0 Enable Bit
20.1.3.4. Interrupt S0 S0 S0 S0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 7 P T0 T1 7 T0 T1 Four signals can trigger the UART interrupt source output. Three of them set their own flags in the Interrupt Flag register UAxIF and can be enabled by setting bits in the Interrupt Mask register UAxIM. 1. When the flag TBUSY in register UAxC is set to zero, the interrupt source output is triggered. This indicates that a transmission is finished and the transmit buffer is empty. There is neither an interrupt flag to indicate this event, nor a mask flag to disable this interrupt. 2. RCVD is generated by the receive control logic at the end of each received telegram even if the FIFO is full. This signal is enabled by setting the corresponding bit in register UAxIM. 3. BRK is generated by the receive control logic each time a break is detected. This signal is enabled by setting the corresponding bit in register UAxIM. 4. ADR is generated by the address comparator. This signal is enabled by setting the corresponding bit in register UAxIM. BRK and ADR also set flags in the Interrupt Flag register UAxIF when enabled. The first RCVD interrupt, when the FIFO has been empty before, sets a flag in UAxIF too. Even if all interrupts are enabled in register UAxIM, the interrupt source output is triggered only once within a telegram. UAxIF flags remain valid until the end of the next telegram. ADR is not generated and the ADR flag is not set if a frame or parity error was detected in the corresponding telegram.
6 T0 6 7 P T0
S = Start bit P = Parity bit
T0 = 1. stop bit T1 = 2. stop bit
Fig. 20-3: Examples of Telegram Formats
The level of the start bit is always opposite to the neutral level. The level of the stop bits is always the same as the neutral level. If a parity bit is programmed, odd or even parity can be selected.
Table 20-2: Definition of Parity Bit
Parity Flag odd odd even even Number of Ones odd even odd even Parity Bit 0 1 1 0
20.1.4. Operation
With proper HW configuration and SW initialization, a UART module is ready to transmit and receive telegrams in the selected format. 20.1.4.1. Transmit
As a general rule, the parity bit completes the number of ones in the data field to the selected parity. 20.1.3.3. Compare Address The content of the Compare Address register UAxCA is compared with each received telegram. If they match, the interrupt flag ADR is set and the interrupt source signal is triggered. The MSB of register UAxCA must be set to zero if transmission of a seven bit data field is configured in register UAxC.
A write access to UART Data register UAxD immediately loads the transmit shift register and starts transmission by sending the start bit. The flag TBUSY in register UAxD is set. At the end of transmission the interrupt source signal is triggered and the flag TBUSY is reset. To avoid data corruption, ensure that flag TBUSY is LOW before writing to UAxD.
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20.1.4.2. Receive A first negative edge of a telegram on the RX line of a UART starts a receive cycle and sets the flag RBUSY in UAxC. After reception of the last bit of the telegram, the telegram content, together with its status information, is transferred to the receive FIFO and an interrupt is generated. RBUSY is reset. Telegram data are available in register UAxD, telegram status in register UAxC. During reception, the following checks are performed according to the register UAxC setting: 1. A parity error is detected if the parity of the received telegram does not match the programmed parity. The flag PAER in register UAxC is set in this case. Differing telegram length settings in register UAxC and receiver may also cause parity errors. 2. A frame error is detected if the level of start or stop bits violate the transmission rule. The flag FRER in register UAxC is set in this case. 3. A break condition is detected if the receive input remains low for one complete telegram duration. When a break starts during telegram, this condition must extend over another telegram length to be properly detected. This event sets the flag BRKD in register UAxC and can trigger the interrupt source output if enabled. After a break, the receive input must be high for at least 1/4 of the bit length before a new telegram can be received. Telegrams of an external RS232 interface are correctly received, even if they are transmitted without gaps (the start bit immediately follows the stop bit of the preceding telegram). 20.1.4.3. Receive FIFO
PRELIMINARY DATA SHEET
The receive FIFO is able to buffer the data fields of two consecutive telegrams. But not only the data field of a telegram is double-buffered, the related information is double-buffered too. The flags PAER, FRER and BRKD in register UAxC apply to a certain telegram and are thus double-buffered. The receive FIFO is full if two telegrams have been received but the SW has not yet read register UAxD. If there is a third telegram, it is not written to the FIFO and its data are lost. The flags EMPTY, FULL and OVRR show the status of the FIFO. EMPTY indicates that there is no entry in the FIFO. FULL will be set with the second entry in the receive FIFO and indicates that there is no more entry free. OVRR indicates that there was a third telegram which could not be written to the FIFO. Status flags are readable as long as the corresponding data field was not read from register UAxD. As soon as a FIFO entry is read out, the status flags of this entry are lost. They are overwritten by the flags of the second entry. SW first has to read the flags and then the corresponding FIFO entry. The flags PAER, FRER and BRKD apply to a certain telegram and are only valid if there is at least one entry in the FIFO (EMPTY = 0). The flags EMPTY, FULL and OVRR apply to the FIFO and are valid all the time.
20.1.5. Inactivation
Returning a UART module to standby mode by resetting its respective enable bit (Table 20-1) will immediately terminate any running receive or transmit operation and will reset all internal registers.
20.2. Timing
The duration of a telegram results from the total telegram length in bits (LTG) (see Table 20-3 on page 134) and the baud rate (BR).
L TG t TG = --------BR
The incoming signal is sampled with the sample frequency and filtered by a 2 of 3 majority filter. A falling edge at the output of the majority filter starts the receive timing frame for the telegram. An individual bit is sampled with the fifth sample clock pulse within that timing frame (cf. Fig. 20-4 and Fig. 20-5). If a bit was the last bit of its telegram, reception of a new telegram can start immediately after this sample. With a receive telegram, interrupt source is triggered and flags are set just after the sample of the last stop bit. With a transmit telegram, interrupt source is triggered and BUSY reset after the nominal end of the last stop bit.
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1 fsample rxdat asynchron 1. sample 2. sample 3. sample start data sample clock
2
3
4
5
6
7
8
startbit
bit 0
bit 1
indicates the recognition of the low level of the filtered input signal
Fig. 20-4: Start of Telegram
1 fsample rxdat asynchron 1. sample 2. sample 3. sample start data sample clock Rx Interrupts Tx Interrupt BUSY
2
3
4
5
6
7
8
1. stopbit
2. stopbit
startbit
Flags are set
Fig. 20-5: End of Telegram
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20.3. Registers
LEN w0: w1:
1 0
PRELIMINARY DATA SHEET
UAxD
7
r w x x
UART x Data Register
6 5 4 3 2
Length of Frame 7-bit frame. 8-bit frame.
Receive register Transmit register x x x x x x Res
Table 20-3: Telegram Format and Length
LEN 0 PAR 0 0 1 1 0 0 1 1 STPB 0 1 0 1 0 1 0 1 Format S, 7D, T0 S, 7D, T0, T1 S, 7D, P, T0 S, 7D, P, T0, T1 S, 8D, T0 S, 8D, T0, T1 S, 8D, P, T0 S, 8D, P, T0, T1 LTG 9 10 10 11 10 11 11 12
UAxC
7
r RBUSY 0 w x x
UART x Control and Status Register
6
BRKD x x x
0 0
5
FRER x x x
4
OVRR 0 x x
3
PAER x STPB 0
2
EMPTY 1 ODD 0
1
FULL 0 PAR 0
0
TBUSY 0 LEN 0 Res Res
0 1 1
RBUSY r0: r1: BRKD r0: r1: FRER r0: r1: OVRR r0: r1: PAER r0: r1:
Receiver Busy Not busy. Busy. Break Detected No break. Break. Frame Error Detected No error. Error. Overrun Detected No overrun. Overrun. Parity Error Detected No error. Error.
1 1
UAxBR0
UART x Baud Rate Register low byte
7
w 0
6
5
4
3
2
1
0
Bit 7 to 0 of Baud Rate 0 0 0 0 0 0 0 Res
UAxBR1
7
w x -
UART x Baud Rate Register high byte
6
x -
EMPTY Rx FIFO Empty r0: Not empty. r1: Empty. There is at least one entry present if EMPTY is zero. PAER, FRER and BRKD are not valid if EMPTY is set. FULL r0: r1: Rx FIFO Full Not full. Full.
5
x -
4
3
2
1
0
Bit 12 to 8 of Baud Rate 0 0 0 0 0 Res
The Baud Rate Registers UAxBR0 and UAxBR1 have to be written low byte first to avoid inconsistencies. UAxBR0 is the low byte. Valid entries in the Baud Rate Registers range from 1 to 8191. Don't operate the baud rate generator with its reset value zero.
TBUSY Transmitter Busy r0: Not busy. r1: Busy. Do not write to register UAxD as long as BUSY is true. STPB w0: w1: ODD w0: w1: PAR w0: w1: Stop Bits One stop bit. Two stop bits. Odd Parity Even parity. Odd parity. Parity On No parity. Parity on.
UAxCA
7
w 0 0
UART x Compare Address Register
6 5 4 3 2 1 0
Bit 7 to 0 of address 0 0 0 0 0 0 Res
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UAxIM
7
w x -
UART x Interrupt Mask Register
6
x -
5
x -
4
x -
3
x -
2
ADR 0
1
BRK 0
0
RCVD 0 Res
ADR w0: w1: BRK w0: w1: RCVD w0: w1:
Mask Compare Address Detected Disable interrupt. Enable interrupt. Mask Break Detected Disable interrupt. Enable interrupt. Mask Received a Telegram Disable interrupt. Enable interrupt.
UAxIF
7
r Test -
UART x Interrupt Flag Register
6
Test -
5
Test -
4
Test -
3
Test -
2
ADR x
1
BRK 0
0
RCVD 0 Res
Test ADR r0: r1: BRK r0: r1: RCVD r0: r1:
Reserved for test (do not use) Compare Address Detected No Interrupt. Interrupt pending. Break Detected No Interrupt. Interrupt pending. Received a Telegram No Interrupt. Interrupt pending.
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21. CAN Manual
This manual describes the user interface of the CAN module. For further information about the CAN bus, please refer to the CAN specification 2.0B from Bosch. Features - Bus controller according to CAN Licence Specification 1992 2.0B - Supports standard and extended telegrams - FullCAN: at least 16 Rx and Tx telegrams - Variable number of receive buffers - Programmable acceptance filter Single, group or all telegrams received. - Time stamp for each telegram - Overwrite mode programmable for each telegram - Programmable baud rate. Max. 1 MBd @ 8 MHz - Sleep mode
PRELIMINARY DATA SHEET
The CAN interface is a VLSI module which enables coupling to a serial bus in compliance with CAN specification 2.0B. It controls the receiving and sending of telegrams, searches for Tx telegrams and interrupts and carries out acceptance filtering. It supports transmission of telegrams with standard (11 bit) and extended (29 bit) addresses. The CAN interface can be configured as BasicCAN or FullCAN. It enables several active receive and transmit telegrams and supports the remote transmission request. The number of telegrams which can be handled depends mainly on the size of the communication RAM (16 byte per telegram), the system clock and the transmission speed. A maximum of 254 telegrams can be handled. A mask register makes it possible to receive different groups of telegram addresses with different receive telegrams. Transmitting or receiving of a telegram as well as the occurrence of an error can trigger an interrupt.
CPU CAN Bus Address
Error Managem. Logic Global Control and Status Register CAN RAM
Data Interrupt Source (Com. Area)
Bit Timing Logic
Protocol Manager Interface Managm. Logic Rx/TxBuffer
Rx. Obj.
Tx. Obj.
Fig. 21-1: Block diagram of the CAN bus interface
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21.1. Abbreviations
BI BTL CAN CA CO CM CRC DLC EoCA Ext. ID Ext. Tg GCS CAN Bus Interface Bit Timing Logic Controller Area Network Communication Area Communication Object Communication Mode Cyclic Redundancy Code Data Length Code End of CA Extended Identifier Extended Telegram Global Control and Status Register ID IML Rx. Obj. RxTg Std. ID Std. Tg TD Tg TQ Tx. Obj. TxTg Identifier Interface Management Logic Receive Object Receive Telegram Standard Identifier Standard Telegram Telegram Descriptor Telegram Time Quantum Transmit Object Transmit Telegram
21.2. Functional Description
21.2.1. HW Description
The CAN bus interface consists of the following components: Bit Timing Logic: Scans the bus and synchronizes the CAN bus controller to the bus signal. Protocol Manager: The PM monitors or generates the composition of a telegram and performs the arbitration, the CRC and the bit stuffing. It controls the data flow between Rx/Tx buffer and CAN bus. It also drives the Error Management Logic. Error Management Logic: Adds up the error messages received from the protocol manager and generates error messages when particular values are exceeded. Guarantees the error limitation as per the CAN Spec. V2.0B. Interface Management Logic: The IML scans the Communication Area (CA) in the CAN-RAM for transmit telegrams. As soon as it finds one, it enters it into the Rx/Tx buffer and reports it to the protocol manager as ready for transmission. If a telegram is received, the IML carries out the acceptance filtering, i.e. scans the CA, taking into account the Identifier Mask Register in the GCS, for a Tg with the appropriate address. After correct reception, it copies the Tg from the Rx/ Tx buffer to the CA. The IML also reports to the CPU the valid transfer of a telegram or given errors per interrupt. The interrupt source output of this module is routed to the Interrupt Controller logic. But this does not necessarily select it as input to the Interrupt Controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. Rx/Tx buffer: This is used to buffer a full telegram (ID, DLC, data) during sending and receiving. Global Control and Status Register: The GCS contains registers for the configuration of the BI. It also contains error and status flags and an identifier mask. The Error Counter and the Capture Timer can be read from the GCS. Receive Object: The BI enters received telegrams into a matching Rx-Object. It can be retrieved from the application. Transmit Object: The application enters data into the TxObject and reports it ready for transmission. The BI sends the telegram as soon as the bus traffic allows. For the effect of CPU clock modes on the operation of this module, refer to section "CPU and Clock System" (see Table 4-2 on page 34).
21.2.2. Memory Map
From the CAN bus interface the user sees two storage areas in the user RAM area. The BI is configured with the Global Control and Status Registers (GCS). It also indicates the status here. The communication area (CA) contains the Rx and Tx telegrams. The communication area lies in the CAN-RAM. The end of the Com. Area is fixed by the first control byte of an object whose 3 MSBs contain only ones (Communication Mode = 7 = EoCA). The area after this is available to the user. The CA consists of communication objects (COs). A CO consists of 6 bytes telegram descriptor (TD), 8 data bytes and the Time Stamp which is 2 bytes long. The TD contains the address (ID) and the length of a telegram (DLC) as well as control bits which are needed for access to the CO and for the transmission of a telegram. In the BasicCAN and the FullCAN versions, all the communication objects have the same, maximum size of 16 byte. Unassigned storage locations in the data area of a CO can be freely used. The maximum number of COs is limited by the time which the CAN interface has to search for an identifier in the Com. Area.
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21.2.3. Global Control and Status Registers (GCS)
The GCS registers can be used to determine the behavior of the CAN interface. As well as flags for the interrupts, halt and sleep modes, they also contain interrupt index, ID mask, bus
PRELIMINARY DATA SHEET
timing, error status, output control registers, baud rate prescalers, Tx and Rx error counters as well as the capture timer.
Global Control and Status
Communication Area CTR STR ESTR IDX IDM BT1 BT2 BT3 ICR OCR TEC REC ESM CTIM
0 Control
Status Error Status Interrupt Index ID Mask 28 ... 21 ID Mask 20 ... 13 ID Mask 12 ... 5 ID Mask 4 ... 0 Bit Timing 1 Bit Timing 2 Bit Timing 3 Input Control Output Control Transmit Error Counter Receive Error Counter 15 Error Status Mask 16 Capture Timer low 17 Capture Timer high
0 Control 1 ID 28 ... 21 2 ID 20 ...13
ID 12 ... 5 ID 4 ... 0 and Control DLC and Control Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Time Stamp low 15 Time Stamp high 16 TD Data and Time Stamp
Com.-Obj. 1
Telegram Descriptor TD
Com.-Obj. 2
31 32 TD
Data and Time Stamp
Com.-Obj. 3
47
n*16 TD
Data and Time Stamp
Com.-Obj. n
n*16+15 (n+1)*16 Control: CM = 7
Fig. 21-2: Memory allocation Access modes: r: read w: write i: init (BI halted) w0: clear w1: set
End of Com. Area
halt acknowledge is indicated in the status register (HACK). Re-initialization can be carried out in the halt mode (HACK is set). After this, the halt flag must be deleted again. After a reset, HLT is set. If HLT is set during a Tx-Tg and this has to be repeated (error or no acknowledge), the BI stops yet. The corresponding TxCO is still reserved, however, and can no longer be operated from BI. Therefore, when HLT is set, the CA should always be re-initialized if the last Tx-Tg has not been correctly transmitted (Status Transfer Flag is still deleted). If HLT is set during the BI is in Bus-Off mode, the BI stops after Bus-Off mode is finished. Flag BOFF is cleared then and receive and transmit error counters are reset to zero. SLP Sleep r/w0: Run. r/w1: Sleep. The BI goes into the sleep mode when the sleep flag is set and a started Tg is terminated. The sleep mode is finished as
CANxCTR
7
r/w HLT 1
Control Register
6 5
GRSC 0
4
EIE 0
3
GRIE 0
2
GTIE 0
1
BOST 0
0
rsvd x Res
SLP 0
HLT Halt r/w0: Run. r/w1: Halt. Switches the CAN interface into the halt mode. Transmissions which have been started are brought to an end. The
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all the flags in the error status register are either deleted or masked, ERS is also deleted. As long as a bit is set in the CANxESTR and not masked, the ERS bit is also set in the status register. If EIE has been set in the control register, an interrupt is triggered too; i.e. the value 254 is entered in the register CANxIDX as soon as it is free, and the interrupt source output is triggered. To erase a bit in the CANxESTR the user must write a one at the appropriate place. Places at which he writes a zero will not be changed. Because it makes sense to erase only those bits which have previously been read, only the value which has been read has to be re-written.
soon as a dominant bus level is detected, or the sleep flag is deleted. GRSC Global Rescan r0: Don't rescan. r/w1: Rescan. The microprocessor can set this flag in order to initiate a transmit telegram search at the beginning of the Com. Area. The BI resets the bit. The BI also sets the GRSC flag if the flag RSC has been set in a telegram descriptor of a Tx-Tg just operated, and thereby initiates a rescan. If the microprocessor writes a zero, nothing happens. EIE r/w0: r/w1: GRIE r/w0: r/w1: GTIE r/w0: r/w1: Error-Interrupt-Enable Disabled. Enabled. Global Rx-Interrupt-Enable Disabled. Enabled. Global Tx-Interrupt-Enable Disabled. Enabled.
CANxESTR
7
r/w GDM 0
Error Status Register
5
ECNT 0
6
CTOV 0
4
BIT 0
3
STF 0
2
CRC 0
1
FRM 0
0
ACK 0 Res
BOST Bus-Off Stop Select r/w0: Don't stop when leaving Bus-Off mode. r/w1: Stop when leaving Bus-Off mode. The flag HLT is set by the BI after leaving the Bus-Off recovery sequence. The SW has to restart the CAN module in this case after re-initialisation. Consider the flag HACK even in this case.
Read-Modify-Write operations on single flags of this register must be avoided. Unwanted clearing of other flags of this register may be the result otherwise. GDM Good Morning r0: No wake-up. r1: Wake-up. w0: Unaffected. w1: Clear. Is set by the BI when it is aroused from the sleep mode by a dominant bus level. The user must delete it. CTOV Capture Time Overflow r0: No overflow. r1: Overflow. w0: Unaffected. w1: Clear. Is set by the BI when the capture timer (CTIM) overflows. The user must delete it. ECNT Error Counter Level r0: No error counter. r1: Error counter. w0: Unaffected. w1: Clear. Is set by the BI as soon as the transmit error counter or the receive error counter exceeds a limit value. The user must delete it. BIT Bit Error r0: No bit error. r1: Bit error. w0: Unaffected. w1: Clear. Is set by the BI when a transmitted bit is not the same as the bit received. The user must delete the flag. STF Stuff Error r0: No stuff error. r1: Stuff error. w0: Unaffected. w1: Clear. Is set by the BI when 6 identical bits are received successively in one Tg. The user must delete it. CRC r0: r1: w0: CRC Error No CRC error. CRC error. Unaffected.
CANxSTR
7
r HACK 1
Status Register
6 5
EPAS 0
4
ERS 0
3
rsvd x
2
rsvd x
1
rsvd x
0
rsvd x Res
BOFF 0
HACK Halt-Acknowledge r0: Running. r1: Halted. Is set by the BI when it enters the halt mode. It is deleted again when the halt mode is exited. BOFF Bus-Off r0: Bus active. r1: Bus off. With this flag the BI indicates whether the node is still actively participating in the bus. If the transmit error counter reaches a value of > 255 (overflow), the node is separated from the bus and the flag is set. The Bus-Off mode is left after the Bus-Off recovery sequence. The flag CANxCTR.BOST defines the behavior after leaving Bus-Off mode. EPAS Error-Passive r0: Error active. r1: Error passive. With this flag the BI indicates whether the node is still participating in the bus with active Error Frames. If an error counter has reached a value > 127, the node only transmits passive error frames and the flag is set. ERS Error-Status r0: No Errors. r1: Errors. This flag is set when the BI detects an error and the apropriate error flag is not masked in the error status mask register. It is set even if an error counter is greater than 96. It means that a bit has been set in the error status register. As soon as
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w1: Clear. Is set by the BI when the CRC received does not coincide with the CRC calculated. The user must delete it. FRM Form Error r0: No form error. r1: Form error. w0: Unaffected. w1: Clear. Is set by the BI when an incorrect bit is received in a field with specified bit level (start of frame, end of frame, ...). The user must delete it. ACK Acknowledge Error r0: No acknowledge error. r1: Acknowledge error. w0: Unaffected. w1: Clear. Is set by the BI when there is no acknowledge for a transmitted Tg. The user must delete it.
PRELIMINARY DATA SHEET
CANxBT1
7
r/w MSAM 0
Bit Timing Register 1
6 5
BPR 0
4
BPR 0
3
BPR 0
2
BPR 0
1
BPR 0
0
BPR 0 Res
SYN 0
MSAM r/w0: r/w1: SYN r/w0: r/w1:
Multi Sample Bus level is determined only once per bit. Bus level is determined three times per bit. Sync On Synchronization with falling edges only. Synchronization with rising edges too.
BPR Baud Rate Pre-scaler r/w: Pre-scaler value. The baud rate pre-scaler sets the length of a time quantum for the bit timing logic. tQ = tXTAL x (BPR + 1).
CANxIDX
7
r/w 1 1
Interrupt Index Register
6 5 4 3 2 1 0
With the 6-bit counter it is possible to extend tQ by a factor of 1...64. Values from 0 to 63 are allowed. 0: tQ = tXTAL 1: tQ = tXTAL x 2 2: tQ = tXTAL x 3 3: tQ = tXTAL x 4
Interrupt Index 1 1 1 1 1 1 Res
etc.
The interrupt index indicates the source of the interrupt. If a transmission has been the cause of an interrupt, the interrupt index points to the corresponding telegram descriptor (CANxIDX = 0..253). If an error has been responsible for the interrupt, the interrupt index designates the error status register (CANxIDX = 254). After dealing with the interrupt, the user must eliminate the cause of the interrupt and set the interrupt index to minus one (255 = EMPTY). As soon as CANxIDX is empty, the BI can enter a new index and initiate an interrupt. An interrupt can only be initiated when CANxIDX contains the value 255.
CANxBT2
7
r/w rsvd 0
Bit Timing Register 2
6 5
TSEG2 0
4
TSEG2 0
3
TSEG1 0
2
TSEG1 0
1
TSEG1 0
0
TSEG1 0 Res
TSEG2 0
CANxIDM
7
r/w r/w r/w r/w 0
Identifier Mask Register
6 5 4 3 2 1 0
low
TSEG2 Time Segment 2 r/i: TSEG2 value. TSEG2 determines the number of time quanta after the sample point. Permitted entries: 1...7 (result in 2...8 TQ). TSEG1 Time Segment 1 r/i: TSEG1 value. TSEG1 determines the number of time quanta before the sample point. Permitted entries: 2...15 (result in 3...16 TQ).
Identifier Mask Bits 29 to 21 Identifier Mask Bits 20 to 13 Identifier Mask Bits 12 to 5 Identifier Mask Bits 4 to 0 0 0 0 0 x 0 x 0 x 0
CANxBT3
high Res
Bit Timing Register 3
6 5
rsvd x
7
r/w rsvd x
4
rsvd x
3
rsvd x
2
SJW 0
1
SJW 0
0
SJW 0 Res
rsvd x
r/w0: Don't care. r/w1: Compare. The identifier mask register is 29 bits long; the MSB is in the MSB position in the lowest byte address. The CANxIDM defines a mask for the acceptance of address groups. Only the permitted bits are used for comparison with a received identifier. Whether the mask is used can be determined individually for each receive object.
SJW Synchronization Jump Width r/i: SJW value. SJW defines by how many TQs a bit may be lengthened or shortened because of resynchronization. Permitted entries: 1...4 (result in 1...4 TQ). Values greater than 4 must not be used.
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PRELIMINARY DATA SHEET
CDC16xxF-E
CANxICR
7
r/w rsvd x
Input Control Register
6 5
rsvd x
CANxESM
1
REF1 0
Error Status Mask Register
5
EECT 1
4
rsvd x
3
rsvd x
2
XREF 0
0
REF0 0 Res r/w
7
EGDM 1
6
ECTV 1
4
EBIT 1
3
ESTF 1
2
ECRC 1
1
EFRM 1
0
EACK 1 Res
rsvd x
XREF r/w0: r/w1: able. REF1 r/w0: r/w1: nal. REF0 r/w0: r/w1:
External Reference The internal reference is used. The external reference is used where availUse Reference for RxD1 RxD is used as inverted input signal. Supply voltage is used as inverted input sigUse Reference for RxD0 RxD is used as input signal. Ground is used as input signal.
Every flag of the CANxESTR can be enabled/disabled generating an interrupt by modifying the corresponding flag in register CANxESM. EGDM r/w0: r/w1: ECTV r/w0: r/w1: EECT r/w0: r/w1: EBIT r/w0: r/w1: ESTF r/w0: r/w1: ECRC r/w0: r/w1: EFRM r/w0: r/w1: Enable Good Morning Disable. Enable. Enable Capture Time Overflow Disable. Enable. Enable Error Counter Level Disable. Enable. Enable Bit Error Disable. Enable. Enable Stuff Error Disable. Enable. Enable CRC Error Disable. Enable. Enable Form Error Disable. Enable. Enable Acknowledge Error Disable. Enable.
CANxOCR
7
r/w rsvd x
Output Control Register
5
rsvd x
6
rsvd x
4
rsvd x
3
rsvd x
2
rsvd x
1
rsvd x
0
ITX 0 Res
ITX r/w0: r/w1:
Inverted transmission Tx output is not inverted. output is inverted.
CANxTEC
7
r 0 0
Transmit Error Counter
6 5 4 3 2 1 0
Counter Bit 7 to 0 0 0 0 0 0 0 Res
EACK r/w0: r/w1:
CANxCTIM CANxREC
7
r x x 0 0
Capture Timer
5 4 3 2 1 0
low high 0 0 0 Res
Receive Error Counter
6 5 4 3 2 1 0
r Counter Bit 6 to 0 r 0 0 0 0 0 Res
7
6
Timer Bit 7 to 0 Timer Bit 15 to 8 0 0 0 0 0
The Capture Timer is incremented with a clock pulse derived from the CAN bus. As it can only be read byte-wise, the low byte must be read first. The corresponding high byte is latched at the same time. When CANxCTIM overflows, the flag CTOV in the error status register is set. The Capture Timer will not be incremented during CAN module sleep mode (SLP = 1).
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21.2.4. Communication Area (CA)
The CA is located in the CAN-RAM. It consists of com. objects each of which is 16 bytes long. The CA begins at address 0 of the CAN-RAM with the first byte of a CO. It ends with the first byte of a CO which contains ones in its 3 MSBs (communication mode = 7 = EoCA). The following bytes can be used by the application. If the CAN-RAM is filled completely with COs, there is no place left and no need to mark the end of CA. Every telegram which this node is to receive or transmit, is represented by a CO. As well as the data and the time stamp, this also contains a header, the telegram descriptor (TD), in which the attributes of the communication object are stored.
PRELIMINARY DATA SHEET
The COs are entered into the CA in order of priority . This starts with the highest priority (the lowest identifier). The identifier defines the priority of a Tg. If the first eleven bits of an ext. Tg are the same as the identifier of a std. Tg, the Tg with standard identifier has higher priority. 21.2.4.1. Telegram Descriptor (TD) The telegram descriptor is 6 bytes (TD0 to TD5) long and forms the beginning of a CO. Telegrams with std. and ext. identifiers have different TDs. They differ only in the length of the identifiers. 18 bits are therefore not allocated in the TD of a std. Tg. They cannot be used by the application because they are overwritten by the reception of a Tg.
Extended Addr. Format (EXF is set) 0 1 28 2 20 3 12 44 5 ID DLC
7 6 5 4 3 2 1 0
Standard Addr. Format (EXF is deleted) rsvd LCK 21 13 5 0 1 28 2 20 3 4 5 don't use DLC TIE ID 18 don't use EXF RSR ACC RIE SR TS
7 6 5 4 3 2 1 0
CM
RSC MID OW ID ID ID
CM
RSC MID OW ID don't use
rsvd LCK 21
0 EXF RSR ACC TIE RIE SR TS
Fig. 21-3: Extended and Standard TD Map Forms of access: r: read w: write i: init (BI halted or CM = inactive) w0: clear w1: set CM Communication Mode r/i: Mode. CM defines the type of telegram. 0: Inactive 1: Send 2: Receive 3: Fetch 4: Provide 5: Rx-All 6: rsvd 7: EoCA Inactive. No participation in the bus traffic. Send data. Receive data. Fetch data via remote frame. Have data fetched via remote frame. Receive every telegram. Don't use (provis. EoCA). End of Communication Area. cessed, the search for active Tx objects is started at the beginning of the communication area. Otherwise, the search continues at this transmit object until the end of the CA is reached. From there, the system jumps back to the beginning of the CA. MID Mask Identifier r/w0: Don't mask. r/w1: Mask. If MID has been deleted, the identifier received is compared bit-by-bit with the identifier from the telegram descriptor, i.e. the entire identifier must be the same so that the telegram received is transferred into this CO. If MID has been set, only bits which are allowed in the ID mask register of the GCS are used for the comparison. OW Overwrite r/w0: Don't overwrite. r/w1: Overwrite. When OW is set, the com. object may be overwritten even if the application has not yet fetched the contents (TS set). The BI must of course obtain right of access (LCK deleted). LCK Lock r/w0: BI has right of access. r/w1: BI does not has right of access. Lock determines the right of access for the BI. ID r/i: Identifier Identifier.
As long as the CO is inactive (CM = 0) or locked (LCK = TRUE), the BI accesses the first byte of the CO only by reading. All other bytes are neither read nor written. The inactive mode is suitable therefore for re-configuration of a CO online; i.e. while the node is taking part in the bus traffic. RSC r/w0: r/w1: If the rescan Rescan Don't rescan. Rescan. bit has been set in a transmit object just pro-
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PRELIMINARY DATA SHEET
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SR Send Request r0: Successful transmission. r/w1: Send request. With SR, the microprocessor issues a send request. Both the microprocessor and the BI write the SR flag. If the microprocessor writes a one, the telegram is sent. The BI deletes the SR flag after successful transmission. TS Transfer Status r/w0: Ready for Transfer. r/w1: Successful transfer. The TS flag is set by BI after a successful transfer and is deleted by the microprocessor after a com. object has been processed. 21.2.4.2. Data Field The data field consists of 8 Byte. They are filled with telegram data according to the DLC. Unused data bytes (DLC less than 8) can be used by the user. 21.2.4.3. Time Stamp TIMST Time Stamp r: Counter value. The last two bytes in the CO are used for the time stamp. At each SoF (Start of Frame) the free-running 16-bit counter CANxCTIM is loaded into a register. When the Tg has been correctly transmitted, this register is copied to the two time stamp bytes of the corresponding CO.
The ID contains the address of the telegram. 11 bits in the standard mode or 29 bits in the extended mode. ACC Access r/w0: CPU does not have right of access. r/w1: CPU has right of access. Access determines the right of access for the CPU. The CPU should not modify this flag after initialization. In operation mode only the BI modifies it and the CPU reads it. RSR Remote Send Request r/w0: Remote telegram received. r/w1: Corresponding data transmitted. In the provide mode, RSR signals a send request from outside; in the fetch mode it means that a remote Tg is being sent. It is set by the BI if a remote telegram has been received. It is deleted as soon as the corresponding data telegram has been transmitted. EXF Extended Format r/w0: Standard. r/w1: Extended. In order to send/receive telegrams with extended address format, this flag must be switched on. For standard telegrams it is deleted. DLC Data Length Code r/w: Data length. The DLC defines the number of data bytes transmitted. Only telegrams with 0 to max. 8 data bytes are transmitted. If the DLC of a TxTg contains a value >8, the entered DLC and exactly 8 bytes will be transmitted. In the case of RxTgs the received DLC, and therefore also values > 8 will be entered by BI. TIE Tx Interrupt Enable r/w0: Disable. r/w1: Enable. Masks the Tx interrupt for this com. object. RIE Rx Interrupt Enable r/w0: Disable. r/w1: Enable. Masks the Rx interrupt for this com. object.
Data 5 Data 6 Data 7 14 Time Stamp low 15 Time Stamp high Fig. 21-4: Time stamp
21.3. Application Notes
21.3.1. Initialization
After reset, a CAN Module is in standby mode (inactive). Prior to entering active mode, proper SW configuration of the U-Ports assigned to function as RX input and TX output has to be made (Table 21-1). The RX port has to be configured Special In and the TX port has to be configured Special Out. Refer to "Ports" for details. For entering active mode of a CAN, set the respective enable bit (Table 21-1). In the initialization phase, a configuration of the CAN node takes place. The mode of operation of the BTL and the bus coupling is set. The communication area is created in the CAN-RAM. The different telegrams are specified in it. The CAN node must be halted (HACK = TRUE) to carry out the initialization. After a reset, the flags HLT and HACK are set and initialization can take place. If initialization is required on-line, the flag HLT must be set. However, the BI must terModule Name CAN0 Initialization Item CAN0-RX input CAN0-TX output CAN1 CAN1-RX input CAN1-TX output CAN2 CAN2-RX input CAN2-TX output Setting U6.6 special in U6.7 special out U1.6 special in U1.7 special out U4.0 special in U4.1 special out SR3.CAN2 SR3.CAN1 SR0.CAN0 Enable Bit Table 21-1: Module-specific settings
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minate any current transmission before it comes to a halt. For the user this means that he must wait until HACK has been set. If HLT is deleted after initialization, then BI begins to participate in the bus traffic and to scan the CA for tasks. During initialization, the error status register (CANxESTR) and the interrupt index (CANxIDX) should be deleted, otherwise no interrupts can be initiated. The error status mask register default value after reset is not masked. If telegrams with different identifiers are to be received in a single CO, the identifier mask register must be initialized. This defines which bit of the ID received must be the same as the ID in the CO. Bit timing registers 1, 2 and 3 and the output control registers 1 and 2 must be initialized in all cases. The CA must be created in the CAN-RAM. The different COs are created one after the other starting at the address 0. It is important at this point that the three MSBs have been set in the first byte after the last CO, i.e. at an address divisible by 16 (CM = End of CA). This is not necessary if the CAN-RAM is completely filled with COs. Communication mode (CM), identifier, data length code, extended format flag (EXF) and remote send request flag must be initialized in each CO. Lock flag (LCK) must be deleted and access flag (ACC) must be set, in order that the BI may also view this CO. Transfer status flag (TS) must be deleted so that interrupts are not initiated erroneously.
PRELIMINARY DATA SHEET
ACC = FALSE; if (LCK == FALSE) { /* BI has right of access */ } ACC = TRUE;
Fig. 21-6: Access to a CO by the BI The BI does not wait at a CO until it becomes free. The BI scans the CA from beginning to end. After a TxTg has been transmitted, the next TxTg entered is reported ready to send. It makes sense to enter the COs in the CA in order of their priority. The priority is determined by the ID. The lowest ID has the highest priority. If the first bits of an extended ID are identical with a standard ID, the standard ID has higher priority. The CO with the highest priority is at the beginning of the CA. This ensures that Tx-Tgs with high priority are transmitted first when a rescan is initiated. 21.3.2.2. Configuration A CO may be configured only in the inactive and/or locked mode or when HACK has been set. Otherwise it can lead to access conflicts between the user and BI. The communication mode (CM) is determined in the configuration phase. The identifiers are also entered. The flag EXF must not be overlooked. The flag RSR and DLC determine whether and how many data bytes will be transmitted in the telegram. The interrupts can be permitted. In case of a receive telegram it is necessary under certain circumstances to set the flags MID and OW. In case of a transmit telegram, the flag RSC must be adjusted. 21.3.2.3. Transmit Telegram CM = Send A transmit telegram is used to send data. How many data bytes will be sent is fixed in the DLC. The data is entered directly after the TD. Unused data bytes can be freely used by the user. If after the transmission of this telegram the user would like the next Tx-Tg in the CA to be sent, he deletes the RSC flag. If he sets the RSC, then the transmit search starts again at the beginning of the CA. The RSR flag has to be deleted. The set SR flag tells BI that this telegram is to be sent; SR can be likened to a postage stamp. The TS flag must be deleted before the CO is released with the deletion of LCK. If the BI finds a CO whose SR flag has been set, it reserves this (ACC = FALSE) and reports it "ready to send". It will be transmitted as soon as no higher-priority telegrams occupy the bus. After successful transmission, it deletes the flag SR and sets TS. The setting of ACC re-releases the CO. Whether an interrupt will be triggered depends on whether CANxIDX in the GCS contains the value minus one (255) and transmit interrupts are permitted. The user should now reserve the CO, reset the flag TS and delete CANxIDX so that other interrupts can also be reported. Should he wish to send further data, he can now enter this.
21.3.2. Handling the COs
21.3.2.1. Principles If the user wishes to access a CO, then he must lock out the BI from access to it. Also the BI reserves access for itself to one CO. In this case the user may not have access. When scanning the CA, the BI ignores inactive or locked COs; i.e. it reads only the first byte and then jumps to the next CO. Reservations Procedure If the user wants to access a com. object, he must first set LCK. Then he must read ACC. If it is TRUE, he has right of access. After the operation he must delete LCK.
LCK = TRUE; if (ACC == TRUE) { /* CPU has right of access */ } LCK = FALSE; _______________ or _________________ LCK = TRUE; while (ACC == FALSE) { /* wait until BI is ready */ } /* CPU has right of access */ LCK = FALSE;
Fig. 21-5: Access to a CO by the user When the BI is accessing a com. object, it first deletes ACC and then reads LCK. If LCK is FALSE, it has right of access.
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PRELIMINARY DATA SHEET
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/* copy data */ TS = FALSE; LCK = FALSE;
21.3.2.4. Receive Telegram CM = Receive With a receive telegram, data is received. If the EXF flag and the unmasked bits of the identifier of a received telegram are the same as those of a receive CO, the telegram will be copied to the CO. ID, DLC and data bytes are overwritten by the received ID, DLC and data. Only as many data bytes as the received DLC specify will be overwritten (max. 8). The DLC actually received will be entered. A permitted receive CO is only used when TS has been deleted or OW has been set. Once a telegram has been received and copied to a CO, the flag TS is set. An interrupt will also be initiated if receive interrupts are permitted and CANxIDX contains the value minus one (255). If the user detects the reception of a telegram (TS set), he must reserve the CO. Then he can read the data and, before releasing the CO again, delete TS. 21.3.2.5. Receive All Telegrams CM = Rx-All If, while searching for an RX-CO, the BI comes across a free Rx-All-CO, the received telegram will be entered here without regard to ID and EXF. Rx-All-COs should be applied at the end of the CA. 21.3.2.6. Fetch Telegram
/* release CO */
Instead of waiting for the answer, it is also possible for notification to be given by a receive interrupt. 21.3.2.7. Provide Telegram CM = Provide A provide CO is used to prepare data for fetching. It is the counterpart of a fetch CO. In a provide CO the RSR flag is cleared. It will be set and deleted by the BI. The data can be prepared in two ways: In the first case, the user does not become active until a remote frame has been received (Rx interrupt or polling from RSR). After the CO has then been reserved, the data is written, the SR flag is set and the CO is released. The BI then ensures that the data is transferred back. In the second case, the data has already been entered, SR has been set and TS deleted before the request. When the remote frame is received, the user does not need to become active. Also, no Rx interrupt will be initiated. The data is simply fetched. In this case the requesting RTR telegram must contain the correct DLC because, with an RTR telegram too, a received DLC overwrites the local DLC. In both cases a Tx interrupt can occur after the data telegram has been transmitted. 21.3.2.8. Data Length Code The data length code is 4 bits long. It can therefore contain values between 0 and 15. In principle, no more than 8 bytes can be transmitted. Empty data telegrams (DLC = 0) are also possible. If a telegram with a DLC greater than 8 is received, this value will be written into the DLC of the CO, but exactly 8 bytes of data will be copied. If the DLC of a Tx-CO contains a value greater than 8, this DLC will be transmitted, but only 8 bytes of data. 21.3.2.9. Overwrite Mode The BI normally processes a CO only when the transfer status TS has been deleted; i.e. the user has processed the CO since the last transmission. In the case of COs with which telegrams are received, the TS flag can be by-passed. If overwrite (OW) is permitted, the BI may overwrite a previously received telegram. When accessing data therefore, the user always receives the most up-to-date data.
CM = Fetch
A fetch CO is used to request data from another node. This is done by sending a telegram with the identifier of the desired data. The remote transmission request flag is set in this Tg. No data is therefore sent with it. If another node has the desired data available, this is transmitted with the same ID as soon as bus traffic allows. In this mode, only the reception of the data telegram can trigger an interrupt. The sequence of a fetch cycle is represented for the user in pseudo-code.
if (TS == FALSE && SR == FALSE) /* CO is empty */ { LCK = TRUE; /* claim CO */ /* wait until BI released this CO */ while (ACC == FALSE) {/* do anything else */} SR = TRUE; /* send this Tg */ TS = FALSE; LCK = FALSE; /* release CO */ }
The BI now transmits the telegram with the RTR flag set. The other node receives the Tg, provides the data and returns the telegram with RTR flag deleted. After the reply telegram has been received, the BI sets the flag TS. The user waits for the data.
21.3.3. Interrupts
All interrupts are enabled or disabled by the global interrupt enable flags, GTIE for Tx interrupts, GRIE for Rx interrupts and EIE for error interrupts in the CANxCTR register. Each error interrupt can also be masked individually in the Error Status Mask register. A Tx interrupt can be enabled in the corresponding CO with the Tx interrupt enable flag TIE. An Rx interrupt can be enabled in the corresponding CO with the Rx interrupt enable flag RIE. An interrupt can only be initiated when the interrupt index CANxIDX is empty (minus one). To initiate an interrupt, the BI enters the number (0...253) of the appropriate CO in the
/* wait for answer */ while (TS == FALSE) {/* do anything else */} LCK = TRUE; /* claim CO */ /* wait until BI released this CO */ while (ACC == FALSE) {/* do anything else */}
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CANxIDX. When an error interrupt is involved, the number 254 is entered. The BI attempts to initiate an interrupt immediately after successful transfer. If this does not work (CANxIDX not empty), the interrupt is pending (also error interrupt). The BI permanently scans the CA. If, while doing so, it finds a CO whose interrupt condition is satisfied (e.g. TIE and TS are set), it generates an interrupt. This means that interrupts not yet reported will not be reported in the sequence of their occurrence, but in the sequence in which they are discovered later. The interrupt service routine of the user must read the CANxIDX. The interrupt source is stored here. If CANxIDX points to a CO (0...253), the user must reserve this. After this, he must first delete TS so that this CO does not initiate an interrupt again. Only then he may release CANxIDX (CANxIDX = 255) so that the BI can enter further interrupts.
PRELIMINARY DATA SHEET
tus register. This means that the value 254 is written in CANxIDX and an interrupt is generated when EIE has been set. An error interrupt is deleted by first deleting CANxESTR and then releasing CANxIDX. The 5 flags BIT, STF, CRC, FRM and ACK originate from the protocol manager. The flag GDM (Good Morning) is not an error flag. GDM is set when the BI is aroused from the sleep mode by a dominant bus level. The flag ECNT (error counter level) indicates that an error counter has exceeded a limit value. It is set when the transmit error counter exceeds the values 95, 127 and 255 or the receive error counter exceeds the values 95 and 127. When the BI is in the Bus-Off mode, it no longer actively participates in the bus traffic. Nor does it receive telegrams, but continues to observe the bus. As soon as the BI has detected 128 x 11 successive recessive bits, it either reverts to the error-active mode if flag BOST is zero, or it sets the flag HLT and enters the HALT mode if flag BOST is set. At the same time the error counters are cleared. A Bus-Off sequence triggers two interrupts, if the error interrupt is enabled. The first interrupt (ECNT=TRUE) indicates that the transmit error counter has exceeded the value 255. This means that the module is in the Bus-Off mode now (BOFF=TRUE). The receive error counter is used to count the reception of 128 x 11 successive recessive bits in the Bus-Off mode. This is the reason for the second interrupt (ECNT=TRUE), which indicates that the receive error counter has exceeded the value 95 (warning level). The second interrupt can be ignored in Bus-Off mode. The error interrupt can be disabled during Bus-Off mode to avoid this second interrupt.
21.3.4. Rescan
The normal transmit strategy searches for the next transmit CO in the CA. If all the transmit COs are ready to send, they are processed one after the other. This is a democratic strategy. If higher-priority TxTgs are reported in the meantime, these are not processed until the complete list has been finished. With rescan, the search for Tx telegrams is started again at the beginning of the CA. By this means the user can force the normal strategy to be interrupted and a search to be made first of all for higher-priority TxTgs. A transmit CO already reported will of course be transmitted first. The rescan requirement can be achieved dynamically, when a transmit CO is reported, by setting the global rescan flag GRSC. It is also possible to configure a rescan strategy statically. Each Tx-CO has the rescan flag RSC. If it is set, the system starts from the beginning with the transmit search after this CO has been processed. It is possible, for instance, to set RSC in the low-priority Tx-COs. Each time a low-priority TxCO has been handled, the search continues for higher-priority objects. The user must ensure that each Tx-CO is processed.
21.3.7. Layout of the CA
The CA contains all COs beginning with the lowest identifier. The three MSBs must be set in the byte after the last CO (End of CA). If the BI has received an identifier complete, it starts at the beginning of the CA with the search for an appropriate RxCO. If a rescan is initiated, the BI also starts from the beginning with the transmit search. 21.3.7.1. Buffers
21.3.5. Time Stamp
The time stamp of a CO shows the user how much time has elapsed since the transmission of the object. For this purpose, he compares the time stamp with the capture timer CANxCTIM. Because the time stamp contains the value of the CANxCTIM at the time of the start of transmission, the difference is proportional to the time which has elapsed. The time stamp mechanism also enables network-wide synchronization. A master transmits a Tg. All nodes note the transmission time (local time). Then the master transmits its own (global) transmission time. The difference between local and global time shows by how much one's own clock (timer) is wrong.
Several successive receive COs may be allocated with the same identifier. The BI stores a received Tg in the first free Rx-CO. Using this mechanism it is possible to construct a receive buffer. If RIE is set in the last CO, the CPU is not informed until the buffer is full. 21.3.7.2. Basic/Full CAN For a Basic CAN application, a single Tx-CO will be used. All outgoing telegrams will be transmitted with this. The user must receive all Rx-Tgs and must himself decide whether he needs it (acceptance filtering). For this case it is possible to use an Rx-All-CO. But it is necessary to ensure that this can be processed before the next Tg arrives. For this reason, it is a good idea to employ 2 or 3 Rx-All-COs as buffers after the Tx-CO. In the case of a FullCAN application, one uses the built-in acceptance filtering and sets up a CO specifically for each desired Rx-Tg and Tx-Tg.
21.3.6. Errors
In the error status register (CANxESTR) error messages and status data are collected which can generate an error interrupt. As long as a flag is set in the CANxESTR and not masked in the CANxESM, the flag ERS is also set in the sta-
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Tx-objects, and 2 Rx-buffers
If the CAN-RAM is not big enough, mixed strategies are also possible. The acceptance filtering, of course, burdens the CPU with communication tasks.
TD: CM=Send
Tx-Obj
TD: CM=Send
Tx-Obj
TD: CM= Rec. All
Rx-Obj
TD: CM= Rec. All
Rx-Obj
TD: CM= Rec. All
Rx-Obj
TD: CM= Rec. All
Rx-Obj
TD:CM = 7
End of Com. Area
TD: CM= Rec. All
Rx-Obj
Fig. 21-7: Example: CA of a BasicCAN with 2 Rx-buffers TD: CM= Rec. All TD: CM= Receive Rx-Obj TD:CM = 7 End of Com. Area Rx-Obj
Fig. 21-9: Example: CA of a BasicCAN with 4 Rx-buffers TD: CM=Send Tx-Obj 21.3.7.3. Bus Monitor With some Rx-All-COs it is possible to construct a userfriendly bus monitor. The CPU has merely to observe whether anything has been received. The contents of the CO must be stored. The transmission time can be calculated from the time stamp. 21.3.7.4. Maximum number of COs TD: CM= Receive Rx-Obj The maximum number of COs depends on the size of the CAN-RAM, the baud rate, the system clock, the BI and the CPU accesses to the CAN-RAM. - The BI can handle a maximum of 254 objects. The limiting factor is the 8-bit register CANxIDX in the GCS. CANxIDX can contain 256 different values. The values 255 (empty) and 254 (error) are reserved. The remaining values 0...253 can indicate 254 objects. - The maximum number of COs is, of course, limited to a greater extent by the size of the CAN-RAM. The BI can only access the CAN-RAM. Therefore the CA can only be applied there. 16 bytes are reserved for each CO. One extra byte for coding EoCA after the last CO must not be forgotten. The CAN-RAM area after the EoCA is freely available to the user. No EoCA is necessary if the CAN-RAM is filled completely with COs.
TD: CM=Send
Tx-Obj
TD: CM= Rec. All
Rx-Obj
TD: CM= Rec. All
Rx-Obj
TD:CM = 7
End of Com. Area
Fig. 21-8: Example: CA of a FullCAN with 2 Rx-objects, 2
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There is a maximum number of 16 COs possible in a CAN-RAM of 256 bytes. Z BI K BI = ------ZG CAN RAM Size Max. Number CO = ---------------------------------------16 - The next limiting factor can be calculated from the baud rate and system clock. After the BI has received an identifier, it must be possible for it to scan the entire CA before the telegram comes to an end.
PRELIMINARY DATA SHEET
K BI t CA SCAN Max. Number CO = ---------------------------------t CO SCAN ZBI is the number of BI cycles in the total cycles (ZG), over a relatively long period (mean value). KBI therefore represents a correction factor. Example for an 8-bit CPU:
t CA SCAN Max. Number CO = ---------------------t CO SCAN t CO SCAN = 9 t XTAL t CA SCAN = 28 t Bit t Bit = ( 3 + TSEG1 + TSEG2 ) t Q t Q = ( BPR + 1 ) t XTAL tCA Scan is the time from having received an ID to the end of a minimum telegram (11 bit ID, no data), which is at the BI's disposal to scan the CA. tCO Scan is the worst case time needed by the BI to process an object (A value of 6 I/O cycles is a more realistic size than 9). With an input frequency of 8 MHz and a baud rate (1/tbit) of 1 MBd, the BI could handle 24 COs. Naturally, this value needs to be rounded off. - The value thus calculated is further limited, however, by the CPU accesses to the CAN-RAM. Each I/O cycle required by the CPU to write or read data in the CANRAM is missing from the BI. The BI is halted by CPU accesses. This reduces the time which the BI has to scan the CA. Where there is a reduced CPU clock, in particular, the user should have only limited access to the CANRAM.
The Load and Store-Accu commands require 4 cycles. OP code Adr.L Adr.H DB Of the 4 cycles, only the last occupies the CAN-RAM. If a block move without loop is programmed, LDA 600; STA 680; LDA 601; STA 681; etc. then only 3 of 4 cycles remain for the BI, i.e. 75%. KBI would then be 0.75. The maximum number of COs is then 18. This applies only when source and destination lie in the CANRAM. If one of the two lies outside, then KBI is 0.875. If, of course, a loop is programmed, LDA 600,X ZBI = 3 of 4 STA 680,X ZBI = 3 of 4 DEX ZBI = 2 of 2 BNE NXT ZBI = 2 of 2 10 of 12 cycles are available to the BI. This gives a KBI of 0.833. The BI can then handle 20 COs. If source or destination are not in the CAN-RAM, there are as many as 22. Example for an 16-bit CPU: The Load and Store-Accu commands require 5 cycles. OP code Adr.L Adr.H DBL DBH Of the 5 cycles, the last two occupy the CAN-RAM. In the worst case, 3 of 5 cycles remain for the BI, i.e. 60%. KBI would then be 0.6. The maximum number of COs is then 14.
21.4. Bit Timing Logic
In the bit timing logic the transmission speed (baud rate) and the sample point within one bit will be configured. By shifting the sample point it is possible to take account of the signal propagation delay in different buses. Furthermore, the nature of the sampling and the bit synchronization can also be defined.
21.4.2. Bit Timing
A bit duration consists of a programmable number of TQCLK cycles. The cycles are split up into the segments SYNCSEG, TSEG1 and TSEG2. 21.4.2.1. Bit Timing Definition
21.4.1. Baud Rate Pre-scaler
The baud rate pre-scaler is a 6-bit counter. It divides the system clock down by the factor 1...64. The output is the clock for the bit timing logic. This clock TQCLK defines the time quantum (tQ). The time quantum is the smallest time unit into which a bit is subdivided.
Sync.Seg. It is expected that a bit will begin in the synchronization segment. If the bit level changes, the resynchronization ensures that the edge lies inside this segment. The sync.seg is always one time quantum long. Prop.Seg. This part of a bit is necessary to compensate for delay times
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of time quanta by which a bit may be lengthened or shortened by resynchronization.
of the network. It is twice the sum of the signal propagation delay on the bus plus input comparator delay plus output driver delay. Phase Seg. Phase segments 1 and 2 are necessary to compensate phase differences. They can be lengthened or shortened by resynchronization. Sample Point The bus level is read at this point and interpreted as a received bit. TSEG1 The CAN implementation combines propagation delay segment and phase segment 1 to form time segment TSEG1. TSEG2 TSEG2 corresponds to phase segment 2. SJW The synchronization jump width gives the maximum number
t Bit = t SYNCSEG + t TSEG1 + t TSEG2 t Q = t XTAL ( BPR + 1 ) t SYNCSEG = 1 t Q t TSEG1 = ( TSEG1 + 1 ) t Q t TSEG2 = ( TSEG2 + 1 ) t Q t SJW = SJW t Q
tBit 1 Time quant Sample Point
Sync Seg tSYNCSEG
Prop Seg tTSEG1
Phase Seg1
Phase Seg2 tTSEG2
def. CAN-SPEC impl. CAN
Fig. 21-10: Bit Timing Definition The baud rate is then calculated as follows: The information processing time is the internal processing time. After reception of a bit (sample point) this time is needed to calculate the next bit for transmission. With a baud rate of 1 MBd a bit should be at least 8 tQ long. In case of a triple sample mode (MSAM = 1), the following boundary condition must also be observed:
1BR = ------t Bit t Bit = t XTAL ( BPR + 1 ) ( 3 + TSEG1 + TSEG2 ) f XTAL BR = ---------------------------------------------------------------------------------------( BPR + 1 ) ( 3 + TSEG1 + TSEG2 )
t TSEG1 t PROP + t SJW + 2t Q The triple sample mode offers better immunity to interference signals. In the single sample mode a higher transmission speed is possible. For high baud rates and maximum bus length, neither SYN nor MSAM may be switched on. Bosch advises against both adjustment facilities. When an input filter matched to the baud rate or a bus driver is used, the triple sample mode is not necessary. If SYN is set, synchronization will also be made with the soft edge (dominant to recessive) and this will mean higher demands being imposed on the clock tolerances. 21.4.2.3. Influence of ERM on CAN Timing When 29 bits are transferred without intermediate resynchronization and with a synchronization jump width of 4 time
21.4.2.2. Bit Timing Configuration Certain boundary conditions need to be observed when programming the bit timing registers. The correct location of the sample point is especially important with maximum bus length and at high baud rate.
t TSEG2 2 t Q t TSEG2 t SJW t TSEG1 3 t Q t TSEG1 t TSEG2 t TSEG1 t PROP + t SJW
= Information Processing Time
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quants and prescaler value of 0, the CAN module can handle a maximum baudrate offset of 4 f BAUD ------------------------------2 29 f XTAL With fXTAL = 8MHz and fBAUD = 1MBd the result is 0.86%. The ERM introduces a limited uncertainty in the position of the actual sample time point which may vary from clock to clock by 0 to 0.121 fXTAL. Due to this phase modulation, the above maximum baud rate offset is reduced by a small amount: 0.121 f BAUD -------------------------------2 29 f XTAL With fXTAL = 8MHz and fBAUD = 1MBd the result is 0.026%, and the maximum baud rate offset is reduced to 0.83%. Furthermore, due to this modulation, the propagation delay that the CAN node can produce increases by 0.121 fXTAL. During system design, this increased delay has to be taken into consideration. 0,121 Prop.Seg. 2 f XTAL ext. delay + t dtxmax - t srxmin + ------------- f
XTAL
PRELIMINARY DATA SHEET
21.4.2.4. Synchronization The BTL carries out synchronization at an edge (change of the bus level) in order to compensate for phase shifts between the oscillators of the different CAN nodes. 21.4.2.5. Hard Synchronization Hard synchronization is carried out at the start of a telegram. The BTL ensures that the first negative edge is in the sync. seg. 21.4.2.6. Resynchronization Resynchronization takes place during the transmission of a telegram. If the BTL detects an edge outside the sync. seg., it can lengthen or shorten the bit. If it detects the edge during TSEG1, tTSEG1 is lengthened. If it detects the edge during TSEG2, tTSEG2 is shortened. In this way, it ensures that the edges lie in the sync. seg. TSJW is the maximum time a bit can be lengthened or shortened. Two forms of resynchronization are possible. In normal operation, synchronization is carried out only with the negative edge (recessive to dominant). At low transmission speeds, synchronization can also be carried out with the rising edge (SYN = 1).
21.5. Bus Coupling
The bus coupling describes the connection of the internal signals rx (receive line) and tx (transmit line) to the pins to the CAN bus. The output pins are push/pull drivers for TLL levels. The input pins are also designed for TTL levels. Integrated transceivers (Siliconix Si9200, Philips 82C250 etc.) are available for physical coupling in the high-speed range in compliance with ISO/DIS 11898. For a laboratory system a "minimum bus" can be constructed by means of a wire-Or circuit. To utilize the advantages of differential signal transmission, an analogue comparator is necessary.
0
ITX TxD
1
tx 1
+5V
1
REF1
RxD
0
OR
0 1
rx
REF0
Fig. 21-11: Bus Coupling
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Table 21-2: Logical Level Transmitting ITX 0 0 1 1 tx 0 1 0 1 TxD 0 1 1 0 Bus Level Dominant Recessive Recessive Dominant inverted Remarks direct
Table 21-3: Logical Level Receiving REF1 REF0 RxD rx Bus Level Remarks
0 0 0 1 1 1
0 1 1 0 0 1
x 0 1 0 1 x
1 1 0 0 1 0
Does not work Recessive Dominant Dominant Recessive Does not work direct inverted
Bus
+5V
CAN +5V
1
REF1
RxD
0
OR
0 1
rx
REF0 ITX
TxD
0 1
tx 1
Fig. 21-12: Minimum Bus
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22. DIGITbus System Description
PRELIMINARY DATA SHEET
22.1. Bus Signal and Protocol
The DIGITbus is a single-line serial master-slave-bus that allows clock recovery from the sign stream. Data on the bus is represented by a pulse width modulated signal. There are three different signs: "0": 25% High Time "1": 50% High Time "T": 75% High Time address length is one bit. The minimum data field length is zero bit. Telegrams with more than one data field are also permitted. For instance TTTTAAATDDDDTDDDDDTT is a valid telegram format on the DIGITbus. A telegram consisting of one address only is possible, too. In this case, the length of the data field is zero.
bit time 0 1 T T T Address T T T T T T
A permanently high bus (100% High Time) means that the bus is passive high. The bus is active if there are consecutive T-Signs, ones or zeros. A permanently low bus (0% High Time) is interpreted as bus reset or failure indicator. Reasons may be shorts, or opens, or even a low level forced by a bus node to indicate an internal failure or reset condition. The sign "T" is used to provide a system-wide clock for the bus nodes and to separate the address and data fields and consecutive telegrams. A telegram normally consists of an address and a data field separated by one "T". These fields may be as long as necessary. Thus the length of an address or data field may carry information. The end is marked by a "T". The end of a telegram is marked by two T-Signs.
A data field is preceded by an address field and separated from this by a single "T". It is followed by one T-Sign. After reception of two T-Signs the telegram is finished and valid. In the idle phase (no information exchange) of the bus traffic, only the bus clock is transmitted.
T
T
T
T
T
T
T
T
T
T
T
T
After the reception of two consecutive T-Signs, all bus nodes have to be prepared to receive a new telegram starting with an address field. They are ready to send an address after the reception of four consecutive T-Signs. The modification of a T-Sign to a zero or one is done by pulling the bus line to low (dominant state) at the right time. This is done by a master sending an address or a data bit or by a slave sending a data bit. When reading data from a slave, the master first sends the address. After receiving the address , the slave waits one TSign and then modifies the following T-Signs to zeros and ones which the master can recognize. Slaves do not have the possibility to become active on the bus if they want to communicate a local event or if they need data from a master. It is a polling bus. Only a master is able to send an address. The master has to scan the slaves for their data. But it is possible to transfer data from one slave directly to another slave. The master has to transmit an address for which one slave is the source and the second slave is the destination. Telegrams on the bus are broadcast. Every bus node may receive them.
T
T
Address
T
Data
T
T
T
One system implementation may be confined to certain address and/or data field lengths, thus reducing the hardware or software requirements. The transmitter of an address has to guarantee that the address is preceded by four T-Signs at least. An isolated data field is not possible. Each non-"T" sequence, which is preceded by two or more consecutive TSigns, must be interpreted as an address. An address field is valid after the reception of the following "T". The minimum
22.2. Other Features
There are two possibilities for a slave to signal a local event to the master. They are called wake-up and bus reset.
22.2.1. Wake-up
If the DIGITbus is passive high, (permanent high level for more than one bit period), a slave can pull the bus line down
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edges. The bus nodes see the edges at different times. This causes them to pull the bus line delayed. To compensate this effect, the phase correction mechanism allows the bus nodes to adjust their internal counters. The master sends a special address, to which the slave answers with a single zero. The master measures the time between the rising and the falling edge. With this value, he can calculate a phase correction value and transmit it to the slave. The slave may use it to adjust his internal counter. The Phase Correction has to be done separately for each bus node.
to low level. This will awake the master who has to store this event in a flag, to start the bus clock and to scan the bus for the source of this event. The minimum low time of the reset pulse is 1/16 of the nominal bit time (1/Baudrate).
22.2.2. Bus Reset
The rising edge of a bit or bus clock is only controlled by the bus node which generates the bus clock (clock master). No other bus node may hold down the bus line at that moment. When the clock master releases the bus line at the end of a bit, he must watch the bus line. If the bus level does not rise after at least 1/2 bit time, this must be interpreted as a protocol violation. Delay of 1/2 of a bit time is the latest moment for a master. He can indicate this protocol violation if the rising edge is delayed 1/8 bit time. Slaves may use this mechanism to signal an exception to the master. They must pull down the bus for at least 2 bit times. After such an event, normal communication may be impossible until the PLL of bus nodes have synchronized again.
22.2.4. Abort Transmission
The Abort Transmission feature is an option that allows the implementation of some kind of rip cord with the DIGITbus. In the event of an alarm, the SW of the sending master bus node may break the current telegram and send another telegram instead. The reception of an address/data field cannot be stopped. The transmission of the alarm telegram is delayed until after the end of the reception in this case. Only the currently sending bus node can abort the transmission.
22.2.3. Phase Correction
On a physical bus the signal edges may be delayed by the bus load. An extra delay may be added by different trigger
22.3. Standard Functions
The following standard functions have to be included in every DIGITbus implementation.
22.3.4. Receive Address
Every slave and all multimaster-capable bus nodes must be able to receive an address. For a receiver, a valid address field must be preceded by two consecutive T-Signs. To verify a received address it is not sufficient to compare the value. The length of the address must be correct too, because of the arbitrary length of the address field.
22.3.1. Send Bus Clock
The Bus Clock is the sequence of T-Signs on the DIGITbus. The rising edges of the bus signal are of constant distance. Only one bus node may generate this Bus Clock even in a multimaster system. All bus nodes use this stream of T-Signs to generate telegrams. The bus clock generator knows two states. "Active Bus" means the transmission of the Bus Clock. "Passive Bus" means permanent high bus level. "Passive Bus" may be a low power mode.
22.3.5. Send Data
Every master must be able to send a data field, and some slaves are also able to. A data field is preceded by an address or data field and one T-Sign.
22.3.2. Receive Bus Clock
Bus nodes which do not generate the bus clock need an internal clock for their operation. They may use a separate clock source or derive their clock from the bus clock by a PLL. Bus nodes which use own clock sources nevertheless have to synchronize on the bus clock if they want to transmit or receive data.
22.3.6. Receive Data
Every master must be able to receive a data field, and some slaves are also able to. A data field is preceded by an address or data field and one T-Sign. It is a good idea to verify the length of a received data field, if possible. But data fields of variable lengths are possible too.
22.3.3. Send Address
The Address is the first bit field in a telegram. Only a master may send this field. The sender must guarantee that at least two consecutive T-Signs have been visible on the DIGITbus before sending this field. Therefore he has to send four TSigns. If one of those four transmitted T-signs is disturbed, only one of the separated telegrams is corrupted for a receiver. Sending of an address requires synchronization on the bus clock and, in the case of a multimaster system, collision detection and arbitration capability.
22.3.7. Collision Detection
Collision detection together with arbitration is necessary in multimaster systems. It is necessary to avoid the disturbance of telegrams if two masters try to send a telegram at the same time. As long as both transmit the same sign (one or zero) at the same time, they don't detect a collision. If one master is sending a one and the other is sending a zero, a zero will be seen at the bus. In this case the master whose one was modified to the zero, immediately stops sending and should receive this telegram. The sender has to arbitrate his part of the telegram. Write telegram: TTTTTAAAATDDDDTTTTT
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Read telegram: TTTTTAAAATDDDDTTTTT The separator (T-Sign) after an address or data field is object of arbitration too.
PRELIMINARY DATA SHEET
In a single master system arbitration loss has to be managed as a bus error.
22.4. Optional Functions
The following optional functions may be designed into a certain DIGITbus implementation.
22.4.7. Receive Reset
The clock master generates the rising edge at the end of a bit time. He will detect the reset condition described above and set a flag if the rising edge is delayed for at least 1/8 of the bit time.
22.4.1. Abort Transmission
A master controlling the transmission of a telegram can abort the sending of the address and data field. After four T-Signs after the last bit he can send another, more urgent telegram. If he is receiving a data field from a slave, he must wait until the slave has finished the data field. Then he can insert a new telegram.
22.4.2. Measure Pulse Width
The capability to measure the pulse width of a high pulse at the DIGITbus may be used for a phase correction by some bus nodes. The bus node generating the bus clock sends a data read telegram to another bus node. The other bus node answers with a data field which consists of a single zero. The pulse width of this zero is measured by the master. With this value he can calculate a phase correction value and transmit it to this bus member, which may adjust its time slots to the system dependencies.
22.4.3. Correct Phase
Bus nodes which do not generate the bus clock may use the procedure described above to adjust their phase. They have to answer to a special address with sending back a zero. Afterwards they will receive a correction value with another special address. With this value they can adjust the point where they pull the bus line to modify a "T" to a one or a zero.
22.4.4. Generate Wake-up
If the DIGITbus is passive high (no bus clock, always high level), the clock master may become wake-up by pulling the bus level to low (dominant state) for 1/16 bit time at least. All nodes without the clock master may be able to do that.
22.4.5. Receive Wake-up
If there is a low pulse of at least 1/64 bit time on a passive high DIGITbus, the clock master must start to transmit the bus clock by sending T-Signs. All Masters with a bus clock generation unit must be able to do so in a system which uses this feature.
22.4.6. Generate Reset
During active DIGITbus a slave may be allowed to pull down the bus line longer than up to the end of the actual bit time (2 bit times at least). The rising edge at the end of the bit will be delayed in this case. This will disturb the bus clock for all bus nodes.
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23. DIGITbus Master Module
23.1. Introduction
The DIGITbus is a single-line serial master-slave-bus that allows clock recovery from the sign stream. The address and data field are of arbitrary length. The DIGITbus Master module is a HW-Module for connecting a single-chip controller to the DIGITbus. It generates the bus clock and manages short telegrams autonomously. Transmission and reception of long telegrams are supported by a FIFO each. The DIGITbus Master may be used in a single or in a multimaster bus system. Features - Single master in a singlemaster system. - Clock master in a multimaster system. - Passive master in a multimaster system. - Bus clock generation. - Receive and transmit a telegram with address and data field. - Transmit FIFO and receive FIFO. - Collision detection and arbitration. - Abort transmission. - Sleep mode. - Bus monitor mode. - Measurement of pulse width for phase correction. - Phase correction. - Reception of wake-up and bus reset signal. - Register interface to the CPU.
23.2. Context
Apart from reset and clock line, the interface to the CPU consists of registers connected to the internal address and data bus. An output signal may be connected to the interrupt controller. A modified universal port builds the output logic which is connected with its special input and output to the DIGITbus Master. This provides an easy way for the SW to hold the bus line permanent low or high, or investigate bus level directly, without support of DIGITbus Master HW. An open drain output instead of a push/pull output is necessary for the universal port to build a single-line wired-and bus.
from clock divider ADB R/W DB Reset Interrupt
DIGITbus Master rx tx
Universal Port with Open Drain Output SI SO Port Pin
+U
DIGITbus Other Transmitter
Fig. 23-1: Context Diagram
23.3. Functionality
23.3.1. 3-bit-Prescaler
The programmable 3-bit-Prescaler supplies the module with clock signals. It scales down the clock divider clock by factor 1, 2, 3 to 8 (see Table 23-2 on page 158). The output is 64 times the bus clock. The desired input frequency from the clock divider is hardware programmable.
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23.3.2. Internal Clocks
In low-power mode, the clock supply of the whole module with exception of the receive bit logic can be stopped. The receive bit logic needs a clock in low-power mode too, as it must filter and watch the bus line for a wake-up signal.
PRELIMINARY DATA SHEET
corresponding field is entered into the FIFO unless the field length is not a multiple of 8. An entry into the address register is inserted into the bus clock after the reception of 4 consecutive T-signs. An entry into the data register is inserted into the bus clock after the reception of a non-T-sign and one T-sign. Thus it is possible to append a second data field (maybe acknowledge) after the reception of a telegram. The transmit FIFO may be flushed to abort a transmission. It is also flushed if the transmit telegram logic is active and a collision is detected.
23.3.3. Transmit T
The transmit T logic sends a continuous stream of T-signs, if active. It outputs a permanent high if it is inactive.
23.3.4. Transmit Bit
Depending on the input signals, the transmit bit logic modifies the T-signs to ones or zeros. A phase correction can be done by adjusting the start time of a transmit bit sequence. Other bus behavior than sending zeros, ones or T-signs may be enforced by the SW using the universal port in normal mode directly. The bus line may be released or pulled low.
23.3.10. Receive FIFO
The receive FIFO will be filled from the receive shift register. It has two exit addresses. One for the field length and field type and one for the bit field. The field length has to be read before the corresponding field is taken from the FIFO. The receive FIFO will be frozen if it is full. The receive shift register will be overwritten.
23.3.11. Interrupt 23.3.5. Receive Bit
The receive bit logic samples the bus level at a frequency of 64 times of the bus clock. It filters the input signal and decodes the input stream to supply the receive telegram logic with the logical bus signals (0, 1 and T) and the receive clock. In addition, it measures the pulse width of each non Tsign. It creates a bus reset signal if the active bus is held down beyond the end of a bit time. It creates a wake-up signal if there is a low level on the passive high bus. Several flags of the status registers are connected with the interrupt source signal by a logical-OR. The interrupt output can be masked by a flag in the control register.
23.3.6. Send Telegram
The send telegram logic will be enabled by the transmit FIFO and the receive telegram logic when four consecutive Tsigns have been received. It supports the transmit bit logic with the transmit bit sequence. If it recognizes the beginning of a new field, it waits one bit time (separator T-sign).
23.3.7. Receive Telegram
The receive telegram logic traces the bus and indicates the state to the status register and other related modules. The received bit field is written to the receive FIFO. The receive telegram logic is active all the time. Even if the module is transmitting a telegram, all bits must also be received in a multimaster system, because arbitration may be lost. Reception of own telegrams can be disabled (in a singlemaster system).
23.3.8. Collision Detection
The collision detection logic compares each incoming bit with the currently outgoing bit. A difference is signalled to the send telegram logic. If the module is transmitting, the send telegram logic is stopped immediately, and the transmit FIFO and shift register are flushed.
23.3.9. Transmit FIFO
The transmit FIFO has five entry addresses. One for the field length of address or data field, one for a address byte, one for a data byte, one for more address bytes and one for more data bytes. The field length has to be written once before the
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PRELIMINARY DATA SHEET
CDC16xxF-E
ADB R/W
Address Decoder
DIGITbus Master
run from clock divider 3-Bit-Prescaler DIGITbus Interrupt Source Control/Status T-Seq. DB Phase Tx Field Length Tx Addr. Field Tx Data Field Reset Tx More Addr. Field Tx More Data Field wake-up/bus reset arbitration lost & 0-Seq. 64 x bus clk 1-Seq. tx 64 x bus clk generate bus clock Transmit T
full flush T dat Transmit Telegram TxSR rise
Transmit Bit
TxFIFO
Collision Detection
RxSR rx external only Receive Telegram
rxclk
data lost RxFIFO empty T dat
txclk
Receive Bit
rx
Rx Field Length Rx Field
64 x bus clk
Pulse Width
Fig. 23-2: Block Diagram
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23.4. Registers
The register mnemonic prefix "DG" stands for DIGITbus. PSC r/w:
PRELIMINARY DATA SHEET
Prescaler Scaling value
Table 23-1: Register Mapping Table 23-2: Clock Prescaler
Addr. Offs. 0 1 2 3 4 5 6 7 Mnem. DGC0 DGC1 DGS0 DGRTMD DGTL DGS1TA DGTD DGRTMA Status 1 reserved Rx Field Rx Length readable writable PSC hex Control 0 Control 1 Status 0 Tx More Data 0 1 2 3 Tx Addr. Tx Data Tx More Addr. 4 5 6 7 1 2 3 4 5 6 7 8 Divide by Bus Clock in kHz @ 6 MHz 93.75 46.9 31.25 23.4 18.75 15.6 13.4 11.7 @ 8 MHz 125.0 62.5 41.7 31.25 25.0 20.8 17.9 15.6 @ 10 MHz 156.25 78.1 52.1 39.1 31.25 26.0 22.3 19.5
Tx Length
An "x" in a writable bit location means that this flag is reserved. The user has to write a zero to this location for further compatibility. An "x" in a readable bit location means that this flag is reserved. A read from this location results in an undefined value.
DGC1
7
r/w INTE 0
Control Register 1
6
ENEM 0
5
ENOF 0
4
x x
3
2
PHASE
1
0
DGC0
7
r/w RUN 0
Control Register 0
0 0 0 0 Res
6
GBC 0
5
ACT 0
4
RXO 0
3
X x
2
1
PSC 2 to 0
0
0
0
0
Res
INTE r/w1: r/w0: ENEM r/w1: r/w0: ENOF r/w1: r/w0:
Enable Interrupt Enable interrupt Disable interrupt Enable Not Empty Interrupt Enable Disable Enable Not Full Interrupt Enable Disable
RUN Run r/w1: Module clock is active. r/w0: Module is not clocked. The module is absolutely inactive if RUN is zero. Other flags are not functional then. GBC r/w1: r/w0: Generate Bus Clock Module generates bus clock No bus clock
ACT Activate r/w1: Module is active (reception and transmission). r/w0: Module is sleeping (low power mode). Only the receive bit logic is active in the low-power mode. RXO r/w1: r/w0: Receive External Only Don't receive own telegrams. Receive all.
PHASE Phase Correction Field r/w: Transmit phase. The start of the transmit frame can be selected in increments of 1/64 of a total bit time related to the rising edge. Values between 0 and 15 are possible, but only the interval from 0 to 9 results in correct behavior.
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PRELIMINARY DATA SHEET
CDC16xxF-E
Bit time Transmitted
0 16 32 48 0
RxFIFO NEM
0 16 32 48 0
Received Phase delay Corrected
4 16 32 48 0
Interrupt
PHASE = Start value of transmit counter.
TxFIFO Fig. 23-3: Phase Correction EMPTY NOF
DGS0
7
w r x RDL x
Status Register 0
6
x NEM 0
5
x NOF 1
4
TGV
3
PV
2
ERR
1
x
0
ARB
Interrupt Fig. 23-4: Rx- and TxFIFO Timing
Res
0
0
0
x
0
RDL Receive Data Lost r1: Data lost r0: No data lost This flag is set if the receive FIFO is full and the shift register tries to store its contents to the FIFO, because a new bit arrives. In this case the FIFO is frozen but the shift register is overwritten. It must be interpreted and cleared by the user. It is cleared by reading an entry from the FIFO. NEM Rx FIFO is Not Empty r1: There is at least one entry to read. r0: Empty. (see Fig. 23-4 on page 159) NOF Tx FIFO is Not Full r1: There is at least one entry free. r0: Full. It generates an interrupt only at the precise moment when the limit is passed. It doesn't generate interrupts when the FIFO is empty (see Fig. 23-4 on page 159). TGV Telegram Valid r1: Telegram valid r0: Telegram not valid w0: Clear flag This flag will be set if two consecutive T-signs have been received. It is reset by the HW if a non-T-sign is received. It can be cleared by the user if the related telegram is evaluated. Protocol Violation Wake-up if bus is passive high. Bus reset if bus is active. r0: No trouble w0: Clear flag It must be interpreted and cleared by the user. It is set when the receive bit logic enters or leaves state passive high or when it enters the state passive low. PV r1:
ERR Error r1: Fatal error. r0: No error w0: Clear flag The HW sets this flag either if a dominant level is transmitted and a recessive level is detected (collision error), or if there was a wrong edge within a received bit. If a collision error is detected during transmission, the flag ARB will be set too and transmission stops immediately. This flag has to be cleared by the user. ARB Arbitration Lost r1: Arbitration lost. r0: No arbitration loss. w0: Clear flag This flag will be set if a collision is detected during transmission. It must be cleared by the user. The transmit buffer is flushed if ARB is true. It is impossible to write to the transmit FIFO as long as ARB is true. Wait until flag TGV is true before reloading TxFIFO. This is automatically done if ARB is evaluated within the TGV interrupt subroutine only. The Flags RDL, NEM, NOF, TGV, and PV trigger the interrupt source signal (see Section 23.5.7. on page 163).
DGS1TA
7
w r 0 STATE 1
Status 1 & Tx Address Register
6 5 4 3 2 1 0
Transmit Address PW5 to 0 0 0 0 0 0 0 Res
The first byte of an address field must be written to DGS1TA.
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STATE r: Bus State State of receive bit logic.
PRELIMINARY DATA SHEET
Table 23-4: LEN usage, Receive and Transmit Length
LEN 210 1 2 3 4 5 6 7 0 001 010 011 100 101 110 111 000 Valid Bit Numbers 76543210 _______x ______xx _____xxx ____xxxx ___xxxxx __xxxxxx _xxxxxxx xxxxxxxx
Table 23-3: Receiver States
STATE 00 01 10 11 Bus Passive low Passive high Active low Active high
PW Pulse Width r: Pulse width The pulse width of the most recent non-T-sign is stored in this register. It is measured in increments of 1/64 of the bus clock period.
DGRTMD
7
w r RDL 0 NEM 0
Rx Length & Tx More Data Register
6 5 4 3 2 1 0
The examples in Table 23-5 illustrate the interpretation of register DGRTMD. They are valid for an address field (FTYP = 1) or a data field (FTYP = 0).
Table 23-5: DGRTMD Interpretation Examples
LEN EOFLD 1 0 1 0 Last byte of a field. The six rightmost bits belong to the field. A byte of a field. All bits belong to the field. At least one byte follows. Last byte of a field. Eight bits belong to the field. Impossible.
Transmit More Data FTYP x EOFLD x x x x LEN2 to 0 x x Res
6 0 0 0
More bytes of a data field must be written to DGRTMD. The read part of register DGRTMD is associated with the front entry in the receive FIFO (the receive field DGRTMA). It has to be read and interpreted before the corresponding FIFO entry. RDL Receive Data Lost r1: Data lost r0: No data lost The flag RDL from the status register DGS0 is mirrored here. It is cleared by a read access to register DGRTMA. NEM Receive FIFO is Not Empty r1: There is at least one entry. r0: Empty The flag NEM from the status register DGS0 is mirrored here. FTYP, EOFLD, LEN and register DGRTMA are not valid if NEM is false. FTYP r1: r0: Field Type Address field Data field
DGRTMA
7
w r x x
Rx Field & Tx More Address Register
6 5 4 3 2 1 0
Transmit More Address Receive Field x x x x x x Res
More bytes of an address field must be written to DGRTMA. The bytes of a received field must be read from register DGRTMA. The meaning of this field (address or data) is defined by the flag FTYP. Received bytes of a bit field are right-aligned. The last byte of a long bit field (with the LSB) may be filled partially. To get the whole bit field right-aligned it is necessary to shift all preceding bytes to the right. A read access to this register takes the top entry of the receive FIFO. Both registers DGRTMA and DGRTMD are overwritten by the next FIFO entry as result of a read access.
EOFLD End of Field r1: Last byte of a field r0: Not last byte of a field If EOFLD is set, the corresponding FIFO entry is the last part of the actual field. The next entry, if there is one, belongs to a new field. LEN Length of Field r: Length of valid data bit The three-bit length does not limit the overall length of the corresponding field. The field length defines how many bits of the front entry of the receive FIFO carry valid bits. They are right-aligned (Table 23-4). The real length of the field is unlimited. The user must count the bytes fetched from the FIFO to calculate the real field length.
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PRELIMINARY DATA SHEET
CDC16xxF-E
LEN Length of Field w: Length of address or data field. These three bits correspond to the first byte of a bit field. They define how many bits of this byte carry valid information and should be transmitted (see Table 23-4 on page 160). DGTL must be written before the first byte of the actual bit field is written to the FIFO. It only has to be written once for each bit field. The overall length of the bit field is not limited.
DGTL
7
w x x r x x
Transmit Length Register
6
FLUSH 0 EMPTY 1
5
x x x x
4
x x x x
3
x x x x
2
1
LEN2 to 0
0
0 x x
0 x x
0 x x
Res
Res
DGTD The Transmit Length Register is associated with the whole field (address or data) which will be written into the transmit FIFO. It has to be written before the first entry of the field. FLUSH Flush Tx FIFO w1: Empty Tx FIFO and abort transmission. w0: No action. This flag will be reset by the HW autonomously. After FLUSH wait at least one bit time before rewriting TxFIFO. EMPTY r1: r0: Tx FIFO is Empty No transmit telegram in FIFO. Transmit telegram in FIFO.
7
w x x
Transmit Data Register
6 5 4 3 2 1 0
Transmit Data x x x x x x Res
The first byte of a data field must be written to DGTD. The first byte of a bit field (with the MSB) which is entered into DGS1TA or DGTD, may be partially filled. In the following bytes all bits must contain valid data.
23.5. Principle of Operation
23.5.1. Reset
The module reset signal resets all registers and internal HW. The same module reset signal does a standby bit in a standby register. Setting flag RUN in register DGC0 resets all internal HW and registers, with exception of registers DGC0, DGC1, DGS0 and DGS1TA. These registers are accessible all the time, they are not reset by any setting of the DIGITbus Master flags. Internal HW is reset to an inactive state (not transmitting, not receiving). Internal counters are reset to zero. FIFOs and shift registers are empty. Internal representations of the bus line are reset to passive bus level (high).
23.5.2. Initialization
The corresponding port must be configured as special out open drain. After reset, and after setting flag DGB in standby register SR2, the DIGITbus master is inactive. The global enable flag RUN must be set together with the appropriate prescaler entry PSC, to activate the module. 23.5.2.1. Clock Master The flag GBC (generate bus clock) must be set, if the DIGITbus master should generate the bus clock. The module now acts as clock master of the connected DIGITbus system. It outputs a stream of T-signs. 23.5.2.2. Receiver/Transmitter Registers C0 C1 reset S1.TSTn Setting the flag ACT activates the receive and transmit logic. From now on, all telegrams are received in the receive FIFO. Writing to the transmit FIFO initiates transmission of a telegram. The bus clock (T-signs) must be activated some time before the first telegram is transmitted. This is necessary, as other modules may use a PLL for generating the internal clock from the bus clock. No telegram shall be transmitted before all modules have locked on the bus clock. 23.5.2.3. Singlemaster System In a singlemaster system (no collision possible), you can suppress reception of transmitted telegrams by setting flag RXO (receive external only). This unburdens the CPU from clearing the receive FIFO of those telegrams.
SR2.DGB reset RQ
C0.RUN reset RQ
Internal HW and remaining registers
Fig. 23-5: Reset Structure
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23.5.2.4. Multimaster System In a multimaster system it is necessary that each transmitted telegram is received too, because arbitration may be lost and then the transmitter becomes a receiver. If arbitration has not been lost, the receive FIFO must be read to empty it. The flag RXO has to be cleared in a multimaster system.
PRELIMINARY DATA SHEET
complete emptiness of transmit FIFO. After reset, FLUSH or ARB wait until flag TGV is true before rewriting TxFIFO. Short telegrams can be completely buffered in the FIFO. Managing long telegrams is a SW job. The SW must buffer long telegrams and write the parts in time. The transmit FIFO is intended to unburden the CPU from immediate reaction to a NOF interrupt. If an entry becomes free, the SW has time to write, as long as it needs to transmit two FIFO entries and the contents of the transmit shift register. This time must not necessarily be the duration of sending 24 bits. Possibly, only one bit of each remaining FIFO entry has to be sent. The transmit FIFO is not intended for telegram tracking. Only one transmit telegram at a time must be entered.
Table 23-6: Operating modes
RUN 0 1 GBC x 0 ACT x x RXO x x Remarks Standby mode Passive master. External bus clock generation is necessary. Clock master Sleep mode Active mode Receive all. (Recommended in multimaster system) Receive external only. (Recommended in singlemaster system)
23.5.4. Reception
Every non-T-sign is shifted into the receive shift register. If it is full, or if a T-sign was received, the shift register is stored into the receive FIFO. This is done until the receive FIFO is full. In this case, the FIFO is frozen, but the shift register continues operation. The flag RDL indicates the latter case. If the shift register is stored to the receive FIFO because a Tsign was received, the corresponding flag EOFLD is set, indicating that this is the last entry of a field. The corresponding flag FTYP is modified at the same time. If two or more consecutive T-signs were received in front of the actual field, it is set, indicating that this field has to be interpreted as an address field. If only one T-sign has been received in front of the actual field, it is cleared, indicating that it has to be interpreted as a data field. The flag TGV is set if two consecutive T-signs were received. This is the moment to read status flags and Receive FIFO. The flags PV and ERR have to be interpreted. Even if an error has occurred, the Receive FIFO must be emptied by reading it because every telegram or fragment is stored there. Otherwise reception of the next telegram may overflow the receive FIFO, which is indicated by flag RDL. Every time you want to read DGRTMA, it is ingenious to read DGRTMD first, because DGRTMD and DGRTMA are overwritten with a read access to DGRTMA. 23.5.4.1. Receive FIFO The receive FIFO contains entries as long as flag NEM is true. Short telegrams can be buffered completely in the receive FIFO. SW must buffer long telegrams and read parts of it in time.
1 1 1 1
1 0 x x
x 0 1 1
x x x 0
1
x
1
1
23.5.3. Transmission
Transmission is initiated by writing a telegram into the transmit FIFO. If the field length is not a multiple of 8 bit, the total field length module 8 has to be written to register DGTL. This must be done once for each field, and before any entry in registers DGS1TA, DGTD, DGRTMA or DGRTMD. If the total field length is a multiple of 8, it is not necessary to write the field length into register DGTL. The first entry of a field (address or data) has to be written right-aligned to register DGS1TA (address) or DGTD (data). Further entries of the same field, if it is longer than 8 bit, have to be written to DGRTMA (more address) or DGRTMD (more data). A telegram is transmitted MSB first, hence fields have to be written to transmit FIFO MSB first. A new address field is transmitted if at least four consecutive T-signs were on the bus. A new data field is transmitted if there was exactly one T-sign. If the last bit of a field was transmitted and there are no more entries in the transmit FIFO, the transmitter stops sending. After reception of two consecutive T-signs the telegram valid flag TGV is set. This is the signal for the SW to evaluate whether transmission was correct or whether an arbitration loss or an error have cancelled transmission (flags ARB, PV and ERR). In the latter case SW must initiate retransmission. A telegram has been transmitted correctly if ARB and ERR are false and EMPTY is true. 23.5.3.1. Transmit FIFO SW must ascertain that there is an empty entry in the transmit FIFO, before writing to it. Flag NOF (not full) indicates that there is at least one entry free. Flag EMPTY indicates
23.5.5. Sleep Mode
Only the receive bit logic is active in sleep mode. Neither transmission nor reception of telegrams is possible. A wake-up (passive high to low edge) is signalled by flag PV. The DIGITbus master is not automatically activated by a wake-up. This has to be done by SW. The flag PV can be used to trigger an interrupt. Switching to Sleep Mode while a telegram is being transmitted can cause problems. Hence, please make sure that bus clock generation is switched off only if bus is idle (T-signs).
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PRELIMINARY DATA SHEET
CDC16xxF-E
- Wrong port configuration of DIGITbus Master. - Disturbances on bus line. - DIGITbus Master HW damaged.
23.5.6. Abort Transmission
Writing a one to flag FLUSH aborts the transmission of a telegram after completion of the actual transmitted bit, if the DIGITbus master is the transmitter. The transmit FIFO is emptied and another, more urgent telegram can be transmitted. Transmission of the new telegram starts as soon as 4 consecutive T-signs have been received after the aborted telegram. It is not possible to abort a telegram or a field which is transmitted by another bus node.
23.5.11. Precautions
Don't use indirect addressing when you write to a DIGITbus register. An unwanted read access to the same address can be the result and a read access to the RxFIFO output register modifies the content of this FIFO. Received data are lost in this case. If a telegram is aborted by FLUSH, normally there is a TGV interrupt with the reception of the second T sign after the last bit of the aborted telegram. The next TGV interrupt signals the transmission of the alarm telegram. If a transmit telegram is aborted by FLUSH before transmission has actually started, then the first TGV interrupt of the aborted telegram doesn't occur. In this case the TGV interrupt signals the transmission of the alarm telegram. Don't access DIGITbus registers in CPU SLOW mode. This can cause interrupts. Operation of the module in CPU SLOW mode is allowed.
23.5.7. Interrupt
Five flags (RDL, NEM, NOF, TGV, PV) are connected to the interrupt source output by an or operation. This output can be enabled globally by flag INTE. The interrupt generation of two flags (NEM, NOF) can be enabled locally by flags ENEM and ENOF. A rising edge of a flag triggers the interrupt source output.
INTE RDL ENEM NEM ENOF NOF TGV PV & OR & & DIGITbus Interrupt Source
Fig. 23-6: Interrupt Sources 23.5.8. Measure Pulse Width
The pulse width (high time) of every non-T sign is stored with the falling edge of the bus signal in status register DGS1TA in the field PW. T-signs don't affect PW. It must be read before the falling edge of the next non-T sign.
23.5.9. Correct Phase
The rising edge of the bus signal can be delayed by inner (sampling and filter) or outer (bus load) influences. This delayed rising edge resets a 6-bit transmit counter in the transmit bit logic. The transmit counter pushes the bus line low when it reaches 15 (transmitting 0) or 31 (transmitting 1). It releases the bus line when it reaches 55. The transmit counter is reset to a value which contains two zeros at the most significant position and the four PHASE bits of the control register DGC1 at the least significant position. This allows an adjustment of the transmitted non T signs between 0 and 1/15 of the whole bit length.
23.5.10. Error
The setting of flag ERR may have one of the following causes: - Wrong baud rate of DIGITbus Master or other bus nodes.
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23.6. Timings
PRELIMINARY DATA SHEET
Bus Clock Tx stream txa Rx stream TGV NEM ARB collision Fig. 23-7: Tx Timing D T T T T T A A T D D T T T T D T T T T T A A T D D T T T T
Bus Clock Tx stream txa Rx stream TGV NEM ARB collision D T T T T T A A T D D T T T T D T T T T T T T T T T T T T T
Fig. 23-8: Rx Timing
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PRELIMINARY DATA SHEET
CDC16xxF-E
24. Audio Module (AM)
The Audio Module AM provides a gong output signal that may be used to drive a speaker circuit. The output signal is a square wave signal with selectable gong frequency. The gong signal amplitude is defined by the pulse-width of a PWM signal. An internal accumulator is selectable to automatically decrease this pulse-width, and thus the gong amplitude following an exponential function. Features - Programmable gong frequency - Programmable gong duration - Programmable initial amplitude - Gong can be stopped and retriggered - Generation of an exponentially decreasing gong amplitude function without CPU interaction
1/
13
32
13
+
Adder Data Bus
13 8 13 13
'1FH' Write AMAS (Start/Stop gong sound)
5
AMAS
LSB's
Amplitude - Latch (13 Bit)
MSB
8 13
Read AMAS SQ R Data Bus (Bit 7) AMA U 5.2 AM-PWM &
COMP Amplitude=0 ?
HW Options AM Clock
&
FCL= 4 MHz
8
AMMCA
0
AM Trigger
&
8 Bit - PWM FPWM = 15.625 kHz 7-Bit Counter
CLK 1 /n Clear Counter Set Frequency-Register
7
VDD
U 5.3 AM-OUT
FGONG 1/ 2
CLR
5-Bit Counter
CLK 1/( n) 2 Clear Counter Set Decrement-Register
3
FDecrement
AMA
Write AMF
Data Bus
Write AMDEC
Data Bus
Fig. 24-1: Block diagram of the audio module
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24.1. Functional Description
The gong sound frequency is adjusted with the Audio Module Frequency Register (AMF). FGONG is FPWM divided by twice the [AMF value + 1]. The length of AMF is 7 bit, so values from 0 to 127 can be written. The initial gong sound amplitude is set by writing the Audio Module Amplitude & Status Register (AMAS), this write also starts the gong sound. An active audio module is indicated by the read only Audio Module Active Bit (AMA) in the AMAS. Every 1st..32nd cycle of the gong sound frequency (depending on the Audio Module Decrement Register (AMDEC)), a new amplitude value is calculated (FDecrement). The falling edge of the amplitude decrement frequency FDecrement latches the output of the adder into the amplitude latch (13 bit), and simultaneously the 8 MSB's into the PWM. During the first low cycle of FGONG following the active FDecrement edge, the PWM ialready runs with the newly calculated amplitude, but takes effect at the output not until the next high cycle of FGONG. FGONG is modulating the PWM-output to generate the gong sound frequency, while the decreasing PWM-value generates an exponentially decreasing amplitude. As soon as the 8 MSBs of the amplitude latch reach zero, the AMA will be reset, which deactivates the audio module. The audio module is only operable in the CPU FAST mode.
PRELIMINARY DATA SHEET
24.1.5. Stop Gong
The gong sound will stop automatically, as soon as the amplitude value in the AMAS reaches zero. This will reset the AMA, which indicates the inactive audio module. To stop the gong sound, just write 00H into the AMAS. The gong sound then will stop immediately with the writing of 00H. (also indicated by AMA). A continuous tone will never stop automatically. It can also be stopped by writing 00H into AMAS.
24.1.6. Decay of Sound
The decay characteristic used for this gong sound is described by the following exponential function (see Fig. 24- 3 on page 168): An = A0 (1 - 1/32)n with A0 = initial amplitude An = amplitude after n FDecrement cycles n = int (t * FDecrement )
Each FDecrement cycle the amplitude is decreased by 1/32. FDecrement is determined by the value of GDF in the register AMDEC and by the value of the Audio Module Frequency Register (AMF): for FDecrement = FGong / 2 GDF GDF settings of 0 .. 5 With GDF settings of 6 and 7 the gong sound amplitude update frequency FDecrement is zero (continuous tone). The time constant of the above exponential function is defined as the time interval within which the amplitude A is decreasing to 36.8%. Given
24.1.1. Hardware Settings
The AM clock frequency FCL is set by HW option FFB7h. The AM trigger frequency FPWM (PWM reload frequency) is set by HW option FFC3h. Select 4MHz for FCL and FCL/256 for FPWM to achieve the standard Audio Module functionality.
24.1.2. Initialization
To connect the audio module output with the corresponding output pin (U5.3), U5M32.PMODE has to be set to switch U5.3 (and U5.2) into the Port Mode. Additionally, U5.3 has to be switched into the Special Out Mode: U5SEG32.T3 = 0 and U5SEG32.S3 = 1. There is one register to set the gong sound frequency (AMF) and another one to set the gong sound duration (AMDEC) before the gong sound can be started. Both their reset values are zero.
1 n 0, 368 = 1 - ----- 32
the number n of FDecrement cycles needed to reduce the initial amplitude to 36.8% is This means that is correlating with FDecrement. The higher FDecrement, the shorter is . With an initial amplitude of FFH the total time t255->0 needed to reach zero amplitude in the 8 Bit - AMAS is n = 193 FDecrement cycles, which is approximately 6. n 32
24.1.3. Start Gong
The gong sound is started by writing the initial amplitude value into the Audio Module Amplitude & Status Register (AMAS). Simultaneously with the write to AMAS the Flag Audio Module Active (AMA) is set, which enables the FPWMand FCL-inputs. The setting of AMA to '1' also enables the FGONG- and FDecrement - counter.
t 255 0
1 2 = 193 ------------------------ = 193 ---------------F GONG F Decrement
GDF
24.1.4. Restart Gong
It's possible to restart the gong sound simply by writing a new initial amplitude value to the AMAS (independently from the former initial value or the current value of the register. Note: The current amplitude value can't be read out). The new gong sound will start immediately with a low cycle of FGONG.
With an initial amplitude lower than FFH the gong sound duration is shorter. To sum up, it can be said that the total duration of the gong sound depends on FGong, set with AMF, the setting of the Gong sound Duration Factor GDF and the setting of the initial amplitude (see Table 24-1 on page 167). Please note
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PRELIMINARY DATA SHEET
CDC16xxF-E
that senseless combinations of register values are also possible.
Table 24-1: Total gong sound running time from A0 = FFH to AFinal = 00H for selected gong sound frequencies
(approx. 6; FPWM=15.625 kHz) GDF=0 FGong (AMF) 61.0 Hz 100 Hz 601 Hz 2.60 kHz 7.81kHz (max.) (min.) 3.20 s 1.95 s 0.324 s 75.0 ms 25.0 ms 6.39 s 3.9 s 0.649 s 150 ms 49.9 ms 12.8 s 7.8 s 1.30 s 300 ms 99.9 ms 25.6 s 15.6 s 2.60 s 600 ms 200 ms 51.1 s 31.2 s 5.19 s 1.2 s 399 ms 86.6 s 62.4 s 10.4 s 2.4 s 799 ms
GDF=1
GDF=2
GDF=3
GDF=4
GDF= 5
Conditions: (FPWM = 15.625 kHz; FGONG = 601 Hz; AMDEC value = 2, FDecrement = 150.25Hz)
A 100 %
zoomed gong output signal
after 0 s (initial)
B
50 % after 0.146 s (0.68)
FPWM
PWM Pulse Duty Factor
0
1
2
3
12 13 14 FGONG
15
25
26
C
15 %
after 0.398 s (1.87)
4x A Gong Output Pin
FGONG
4x B
4x C
FDecrement
start gong time 0s 0.146 s (0.68) 0.398 s (1.87) new amplitude (n.a.) n.a. n.a. n.a. n.a.
Fig. 24-2: Example sections of the audio module output signal
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168 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 time
AMAS (MSB of amplitude latch)
260
CDC16xxF-E
240
Fig. 24-3: Decay of Sound - Function
220
200
180
160
140
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100
36.8%
80
60
40
13.5%
20
5.0%
1.8%
8
16
24
32
40
48
1/FDecrement
1
2
3
4
5
6
no. FDecrement-cycles
PRELIMINARY DATA SHEET
Micronas
PRELIMINARY DATA SHEET
CDC16xxF-E
24.2. Registers
The Audio Module control registers are located in the I/O area. It's possible to write a new gong sound frequency during an active audio module (AMA = '1').
Table 24-2: Audio Module Control Registers
Mnemonic AMAS AMF AMDEC Name Audio Module Amplitude/Status Audio Module Frequency Audio Module Decrement
Table 24-3: Examples for AMF-values
AMF - value 127 : 77 : (max.) resulting FGong 61.0 Hz : 100 Hz : 601 Hz : 2.60 kHz : (min.) 7.81kHz (max.) (min.)
AMAS
7
w r AMA 0 x x
Audio Module Amplitude and Status Register
6 5 4 3 2 1 0
Note
12 : 2
Initial Amplitude x x x x x x x x x x x x Res
: 0
Initial Amplitude A write access to this register starts or stops the gong sound, while the value written is the initial gong sound amplitude. Writing the value 00H into this register during an active gong sound deactivates the gong sound immediately, while writing a value > 00H is restarting the gong sound immediately with the new Initial Amplitude. wxx: (Re-)Start gong sound with Initial Amplitude. w00: Stop gong sound. AMA Audio Module Active Flag This flag indicates an active Audio Module generating a gong sound. r1: Audio Module is active. r0: Audio Module is not active.
AMDEC
7
w AMMCA 0
Audio Module Decrement Register
6
x -
5
x -
4
x -
3
x -
2
1
GDF
0
Note
0
0
0
Res
AMMCA w1: w0:
Audio Module Maximal Constant Amplitude Flag Activate the AMMCA mode. Deactivate the AMMCA mode.
AMF
7
w x 0
Audio Module Frequency Register
6 5 4 3 2 1 0
Note
Sound Frequency 0 0 0 0 0 0 Res
With the flag AMMCA the Audio Module Maximal Constant Amplitude (AMMCA) mode is selected. If this Flag is set, the gong sound with the maximum, not decreasing amplitude is available at the audio module output pin. The only difference between this tone and a 'normal' gong sound is the constant, not decreasing amplitude. The handling of this tone (i.e. start, stop, frequency, duration) is the same. The tone is started by writing an initial value to AMAS, but this value will only influence the duration of the tone, not its amplitude. GDF Gong sound Duration Factor
With this register the gong sound frequency is programmed. The PWM frequency is divided by twice the register value increased by one. The value which has to be written, resp. the resulting gong sound frequency is calculated with:
F PWM value = ------------------- - 1 2F GONG F GONG F PWM = ------------------------------2 ( value + 1 )
This register sets the gong sound duration in dependence of FGONG. With GDF=0 the amplitude will be decreased every FGONG - cycle, values 1 to 5 will result in a amplitude update frequency of FGONG / 2 to FGONG / 32 according this equation:
F GONG F Decrement = ---------------GDF 2
GDF = 0...5
With the 7bit value ranging from 0 to 127, the programmable gong sound frequency range is 61 Hz .. 7.81 kHz (see Table 24-3 on page 169).
A value of 6 or 7 means no decrease of the amplitude, so a continuous tone with the initial amplitude will be generated (FDecrement = 0). To stop the continuous tone write a '00H' to AMAS or change the gong sound duration factor to let the
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tone decay. It's possible to change GDF during an active gong sound (AMA = '1').
PRELIMINARY DATA SHEET
Table 24-4: Definition of GDF
GDF 0H 1H 2H 3H 4H 5H 6H continuous tone 7H gong sound duration factor 1 2 4 8 16 32
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CDC16xxF-E
25. Hardware Options
25.1. Functional Description
Hardware Options are available in several areas to adapt the IC function to the host system requirements: - clock signal selection for most of the peripheral modules from fosc to fosc/217 plus some internal signals (see Table 25-2 on page 175) - interrupt source selection for interrupt inputs 0, 1, 5, 6, 7, 10, 13, 14 and 15 - Special Out signal selection for some U- and H-ports - Rx/Tx polarity selection for SPI and UART modules - U-port Port Slow Mode selection The setting of the Hardware Option takes place in two steps: 1. selection is done by programming dedicated address locations with the desired options' code 2. activation is done by a read access to these dedicated address locations at least once after each reset. Address locations 00FFB8h through 00FFBFh do not allow random setting. Their respective Hardware Options are hardwired and can only be altered by changing a production mask for this IC. By default all U-Ports have the Port Slow Option set with the exception of U1.0 to U1.3 (Port Fast Option set). The Watchdog and Clock Monitor are SW activated by default. Future mask ROM derivatives of this IC will not require (but will tolerate) activation of option settings by read accesses because ROM as well as options will be hard-wired. Instead, the manufacturer will automatically process the setting of the dedicated address locations, as given in the ROM code file, to set the required mask changes. To ensure compatible option settings in this IC and mask ROM derivatives when run with the same ROM code, it is recommended to always read locations 00FFA0h through 00FFC3h directly after reset. Be aware that the non-programmable locations 00FFB8h through 00FFBFh may not be compatible among this IC and the mask ROM derivative.
25.2. Listing of Dedicated Addresses and Corresponding Hardware Options
Table 25-1: Hardware-Option-Dedicated Addresses
7 00FFA0 x 00FFA1 x 00FFA2 x 6 5 4 3 2 1 0
Timer 0 Clock Options x x Clock options f1 to f31
PWM0, PWM3 Clock Options x x Clock options f0 to f31 (all)
PWM0, PWM3 Trigger Options x x Clock options f0 to f31 (all)
The high pulse width of the trigger period must be greater than the high pulse width of the clock the PWM is provided with. 00FFA3 x 00FFA4 x PWM1, PWM4 Clock Options x x Clock options f0 to f31 (all)
PWM1, PWM4 Trigger Options x x Clock options f0 to f31 (all)
The high pulse width of the trigger period must be greater than the high pulse width of the clock the PWM is provided with.
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Table 25-1: Hardware-Option-Dedicated Addresses
7 00FFA5 x 00FFA6 x 6 5 4 3 2
PRELIMINARY DATA SHEET
1
0
PWM2 Clock Options x x Clock options f0 to f31 (all)
PWM2 Trigger Options x x Clock options f0 to f31 (all)
The high pulse-width of the trigger period must be greater than the high pulse-width of the clock the PWM is provided with. 00FFA7 x 00FFA8 x 00FFA9 x 00FFAA x 00FFAB x Timer 1 Option x Timer 2 Option x x Clock options f0 to f31 (all) x Clock options f0 to f31 (all)
CAPCOM Counter Clock Option x x Clock options f0 to f31 (all)
DIGITbus Clock Option x x Clock options f0 to f31 (all)
Clock Out 0: Mux0 Prescaler and Clock Option x0: Mux out direct 01: Mux out / 1.5 11: Mux out / 2.5 Clock Out 1: Prescaler and Clock Option x0: direct 01: 1/ 1.5 11: 1/ 2.5 LCD Module Prescaler and Clock Option x0: direct 01: 1/ 1.5 11: 1/ 2.5 Clock options f0 to f31 (all) Clock options f0 to f31 (all) Clock options f0 to f31 (all)
00FFAC x
00FFAD x
00FFAE x
SMM, SPI0, SPI1 Clock Prescaler and SMM Clock Option x0: direct 01: 1/ 1.5 11: 1/ 2.5 Clock options f0 to f31 (all)
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CDC16xxF-E
Table 25-1: Hardware-Option-Dedicated Addresses
7 00FFAF SPI0-D-OUT 0: direct 1: inverted 6 5 4 3 2 1 0
SPI0 Input, Output and F0SPI Clock Option 1) SPI0-D-IN 0: direct 1: inverted x Clock options f0 to f31 (all)
1) FFAE, Bits 6 & 5 define also the SPI0 and SPI1 prescaler setting. 00FFB0 SPI1-D-OUT 0: direct 1: inverted SPI1 Input, Output and F1SPI Clock Option 1) SPI1-D-IN 0: direct 1: inverted x Clock options f0 to f31 (all)
1) FFAE, Bits 6 & 5 define also the SPI0 and SPI1 prescaler setting. 00FFB1 x 00FFB2 x 00FFB3 x 00FFB4 UART0 Tx 0: direct 1: inverted 00FFB5 UART1 Tx 0: direct 1: inverted 00FFB6 x 00FFB7 x 00FFB8 x F2SPI Clock Options x x Clock options f0 to f31 (all)
Clock Out 0: Mux1 Clock Option x x Clock options f0 to f31 (all)
Clock Out 0: Mux2 Clock Option x x Clock options f0 to f31 (all)
UART0, UART2 Input and Output UART0 Rx 0: direct 1: inverted UART2 Tx 0: direct 1: inverted UART2 Rx 0: direct 1: inverted x x x x
UART1 Options UART1 Rx 0: direct 1: inverted x x x x x x
Clock Out 0: Mux3 Clock Option x x Clock options f0 to f31 (all)
AM Clock Option x x Clock options f0 to f31 (all)
Clock Monitor Options Wdog & Clk Monitor: 0: deact. by Software 1: always active x x x x x x
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CDC16xxF-E
Table 25-1: Hardware-Option-Dedicated Addresses
7 00FFB9 6 5 4 3 2
PRELIMINARY DATA SHEET
1
0
Universal Port 1 Slow/Fast Options 0: Fast mode pin only 1: Slow or fast mode pin possible
00FFBA
Universal Port 2 Slow/Fast Options 0: Fast mode pin only 1: Slow or fast mode pin possible
00FFBB
Universal Port 3 Slow/Fast Options 0: Fast mode pin only 1: Slow or fast mode pin possible
00FFBC
Universal Port 4 Slow/Fast Options 0: Fast mode pin only 1: Slow or fast mode pin possible
00FFBD
Universal Port 5 Slow/Fast Options 0: Fast mode pin only 1: Slow or fast mode pin possible
00FFBE
Universal Port 6 Slow/Fast Options 0: Fast mode pin only 1: Slow or fast mode pin possible
00FFBF x
Universal Port 7 Slow/Fast Options x x x 0: Fast mode pin only 1: Slow or fast mode pin possible
00FFC0 Mux4: 00 01 10 11 00FFC1 Mux8: 00 01 10 11 CC1OR PINT2-IN IR-RTC IR-WAPI CAN 2 SPI 0 DMA PINT3-IN
Interrupt Sources Multiplexer 1 to 4 Mux3: 00 01 10 11 PINT3-IN SPI 1 UART 1 CC1 COMP Mux2: 00 01 10 11 UART 2 P06 COMP SPI 0 Timer 1 Mux1: 00 01 10 11 CC0 COMP Timer 2 CAN 2 Timer 1
Interrupt Sources Multiplexer 5 to 8 Mux7: 00 01 10 11 CC0OR UART 1 IR-RTC IR-WAPI Mux6: 00 01 10 11 Timer 2 DIGITbus UART 2 PINT2-IN Mux5: 00 01 10 11 Timer 2 UART 1 SPI 1 DMA
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PRELIMINARY DATA SHEET
CDC16xxF-E
Table 25-1: Hardware-Option-Dedicated Addresses
7 00FFC2 H-Port 1.1 0: SME 1: PWM2 6 5 4 3 2 1 0
Interrupt Sources Multiplexer 9 and Port Multiplexer x H-Port 1.0 0: SME 1: PWM0 PINT3-IN 0: at U5.6 1: at U5.7 x x Mux9: 00 01 10 11 CAN 1 UART 1 IR-RTC IR-WAPI
00FFC3 x
AM Trigger Option x x Clock options f0 to f31 (all)
Table 25-2: Clock Option Selection Code
Clock Option Number f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18
Clock Signal fOSC/20 fOSC/21 fOSC/22 fOSC/23 fOSC/24 fOSC/25 fOSC/26 fOSC/27 fOSC/28 fOSC/29 fOSC/210 fOSC/211 fOSC/212 fOSC/213 fOSC/214 fOSC/215 fOSC/216 fOSC/217 VSS
Selection Code xxx0.0000 xxx0.0001 xxx0.0010 xxx0.0011 xxx0.0100 xxx0.0101 xxx0.0110 xxx0.0111 xxx0.1000 xxx0.1001 xxx0.1010 xxx0.1011 xxx0.1100 xxx0.1101 xxx0.1110 xxx0.1111 xxx1.0000 xxx1.0001 xxx1.0010
Clock Option Number f19 f20 f21 f22 1) f23 f24 f25, 26, 27 f28 f29, 30 f31
Clock Signal Timer 0 VSS fSM fSM/28 fCC0IN fCC1IN VSS fOSC/22 VSS fOSC/210
Selection Code xxx1.0011 xxx1.0100 xxx1.0101 xxx1.0110 xxx1.0111 xxx1.1000 xxx1.1001 ... xxx1.1100 xxx1.1101 ... xxx1.1111
If the leading "x" in the Clock sampling table are not used for the purpose of coding other options, they must be replaced by zeros. 1) Clock option f22 is only available if the Stepper Motor Module has been enabled by the standby bit.
If the leading "x" in the Clock sampling table are not used for the purpose of coding other options, they must be replaced by zeros. 1) Clock option f22 is only available if the Stepper Motor Module has been enabled by the standby bit.
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CDC16xxF-E
26. Register Cross Reference Table V2.1
PRELIMINARY DATA SHEET
26.1. CAN RAM, memory pages 19 ... 1B
Address (hex) 1900 ... 19FF 1A00 ... 1AFF 1B00 ... 1BFF CAN0_RAM CAN0-RAM CAN1_RAM CAN1-RAM Mnemonic CAN2_RAM Block CAN2-RAM
26.2. CAN Registers, memory page 1C
Address (hex) 1C00 1C01 1C02 1C03 1C04 1C05 1C06 1C07 1C08 1C09 1C0A 1C0B 1C0C 1C0D 1C0E 1C0F 1C10 1C11
Mnemonic CAN0CTR CAN0STR CAN0ESTR CAN0IDX CAN0IDM
Block CAN0
Address (hex) 1C40 1C41 1C42 1C43 1C44 1C45 1C46 1C47
Mnemonic CAN1CTR CAN1STR CAN1ESTR CAN1IDX CAN1IDM
Block CAN1
CAN0BT1 CAN0BT2 CAN0BT3 CAN0ICR CAN0OCR CAN0TEC CAN0REC CAN0ESM CAN0CTIM
1C48 1C49 1C4A 1C4B 1C4C 1C4D 1C4E 1C4F 1C50 1C51
CAN1BT1 CAN1BT2 CAN1BT3 CAN1ICR CAN1OCR CAN1TEC CAN1REC CAN1ESM CAN1CTIM
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PRELIMINARY DATA SHEET
CDC16xxF-E
Address (hex) 1C80 1C81 1C82 1C83 1C84 1C85 1C86 1C87 1C88 1C89 1C8A 1C8B 1C8C 1C8D 1C8E 1C8F 1C90 1C91
Mnemonic CAN2CTR CAN2STR CAN2ESTR CAN2IDX CAN2IDM
Block CAN2
CAN2BT1 CAN2BT2 CAN2BT3 CAN2ICR CAN2OCR CAN2TEC CAN2REC CAN2ESM CAN2CTIM
26.3. I/O Registers, memory page 1E
Address (hex) 1E64 1E65 1E66 1E67 1E68 1E69 1E70 1E71
Mnemonic PAR0 PAR1 PAR2 PDR PER0 PER1 WUS
Block Patch Module
Address (hex) 1E74 1E75 1E76 1E78 1E79 1E7A
Mnemonic SSR
Block Power Saving Module
SSC
Power Saving Module
1E7C 1E7D 1E7E 1E80
RTC
WPM0
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PRELIMINARY DATA SHEET
Address (hex) 1E81 1E82 1E83 1E84 1E88 1E90 1E94 1E98 1E99 1E9C 1EA0 1EA1 1EA2 1EA3
Mnemonic WPM2 WPM4 WPM6 WPM8 WSC OSC RTCC POL
Block Power Saving Module
SMX MULCAND MULPLIER MULPROD Multiplier
26.4. I/O Registers, memory page 1F
Address (hex) 1F00 1F01 1F02 1F08 1F09 1F0A 1F0B 1F0C 1F0F 1F10 1F11 1F12 1F13 Mnemonic CSW0 CR ERMC SR0 SR1 SR2 SR3 DBG ABR SPI0D SPI0M SPI1D SPI1M SPI1 Debug Register Memory Banking SPI0 ERM Core Logic Block Core Logic Address (hex) 1F14 1F15 1F18 1F19 1F1A 1F1B 1F1C 1F1D 1F1E 1F1F 1F20 1F21 1F22 1F23 Mnemonic CO0SEL CO1SEL UA1D UA1C UA1BR0 UA1BR1 UA1IM UA1CA UA1IF IRE IRC IRRET IRPRI10 IRPRI32 Interrupt Controller UART1 Block Core Logic
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PRELIMINARY DATA SHEET
CDC16xxF-E
Address (hex) 1F24 1F25 1F26 1F27 1F28 1F29 1F2A 1F2B 1F2C 1F2D 1F2E 1F2F 1F30 1F32 1F33 1F34 1F35 1F36 1F37 1F38 1F39 1F4E 1F4F 1F50 1F51 1F52 1F54 1F55 1F5A 1F5B 1F5C 1F5D
Mnemonic IRPRI54 IRPRI76 IRPRI98 IRPRIBA IRPRIDC IRPRIFE IRP IRPM0 IRPP AMAS AMF AMDEC U2D U2SEG10 U2M10 U2SEG32 U2M32 U2SEG54 U2M54 U2SEG76 U2M76 TIM0
Block Interrupt Controller
Address (hex) 1F5E 1F5F 1F60 1F61 1F64 1F65 1F66 1F67 1F68
Mnemonic PWM3 PWM4 CSW1 CSW2 UA2D UA2C UA2BR0 UA2BR1 UA2IM UA2CA UA2IF CC0M CC0I CC0
Block PWM
Core Logic
UART2
Audio Module
1F69 1F6A 1F6C
Capture Compare Module
Universal Port 2
1F6D 1F6E 1F6F 1F70 1F71 1F72 1F73 1F74 1F75
CC1M CC1I CC1
CC2M CC2I CC2
Timer 0
1F76 1F77
PWM0 PWM1 PWM2 TIM1 TIM2 SMVC SMVSIN SMVCOS SMVCMP
PWM
1F7C 1F7D 1F7E
CCC
P0PIN H0NS H0TRI H0D H1NS H1TRI H1D
Analog Input Port 0 High Current Port 0
Timer 1, 2
1F80 1F81
Stepper Motor Module
1F82 1F84 1F85 1F86
High Current Port 1
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PRELIMINARY DATA SHEET
Address (hex) 1F88 1F89 1F8A 1F90 1F91 1F92 1F98 1F99 1F9A 1F9B 1F9C 1F9D 1F9E 1F9F 1FA0 1FA1 1FA2 1FA3 1FA4 1FA5 1FA6 1FA8 1FA9 1FAC 1FAE 1FAF 1FB0 1FB1 1FB2 1FB3 1FB4 1FB5
Mnemonic H2NS H2TRI H2D H3NS H3TRI H3D U1D U1SEG10 U1SEG32 U1M30 U1SEG54 U1M54 U1SEG76 U1M76 UA0D UA0C UA0BR0 UA0BR1 UA0IM UA0CA UA0IF AD0 AD1 U3D U3SEG10 U3M10 U3SEG32 U3M32 U3SEG54 U3M54 U3SEG76 U3M76
Block High Current Port 2
Address (hex) 1FB8 1FBA 1FBB
Mnemonic U4D U4SEG10 U4M10 U4SEG32 U4M32 U4SEG54 U4M54 U4SEG76 U4M76 U5D U5SEG10 U5M10 U5SEG32 U5M32 U5SEG54 U5M54 U5SEG76 U5M76 U6D U6SEG10 U6M10 U6SEG32 U6M32 U6SEG54 U6M54 U6SEG76 U6M76 U7D U7SEG10 U7M10 U7SEG32 U7M32
Block Universal Port 4
High Current Port 3
1FBC 1FBD 1FBE
Universal Port 1
1FBF 1FC0 1FC1 1FC4 1FC6 1FC7 1FC8 1FC9
Universal Port 5
UART0
1FCA 1FCB 1FCC 1FCD 1FD0 1FD2 1FD3
Universal Port 6
AD Converter
1FD4 1FD5
Universal Port 3
1FD6 1FD7 1FD8 1FD9 1FDC 1FDE 1FDF 1FE0 1FE1
Universal Port 7
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PRELIMINARY DATA SHEET
CDC16xxF-E
Address (hex) 1FE8 1FE9 1FEA 1FEB 1FEC 1FED 1FEE 1FEF 1FF0 1FF1 1FF2 1FF3 1FF4 1FF5 1FF6 1FF7 1FFD 1FFE 1FFF
Mnemonic DCS DIC DSA
Block DMA
DEA
DGC0 DGC1 DGS0 DGRTMD DGTL DGS1TA DGTD DGRTMA TST3 TST1 TST2
DIGITbus
TST
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27. Register Quick Reference
PRELIMINARY DATA SHEET
Table 27-1: A/D Converter
Mnemonic Register Name Addr. (hex) 7 AD0 ADC Register 0 1FA8 6 Register Configuration 5 4 3 2 1 0 12.2. Section
r w
EOC
CMPO
x
x
x
x
AN1
AN0
TSAMP 0 0 x x 0
CHANNEL 0 0 0 Res
AD1
ADC Register 1
1FA9
r
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
Table 27-2: Audio Module
Mnemonic Register Name Addr. (hex) 7 AMAS Audio Module Amplitude & Status Register 1F2D 6 Register Configuration 5 4 3 2 1 0 24.2.
x x x x x x Res
Section
w r AMA 0 x x x x
Initial Amplitude x x x x
AMF
Audio Module Frequency Register
1F2E
w
x 0 0
Sound Frequency 0 0 0 0 0 Res
AMDEC
Audio Module Decrement Register
1F2F
w AMMCA 0
x -
x -
x -
x 0
GDF 0 0 Res
Table 27-3: Capture-Compare-Unit
Mnemonic Register Name Addr. (hex) 7 CC0M CAPCOM 0 Mode Register 1F6C 6 Register Configuration 5 4 3 2 1 0 15.2.
0 Res
Section
r/w
MCAP 0
MCMP 0
MOFL 0
FOL 0 0
OAM 0 0
IAM
CC0I
CAPCOM 0 Interrupt Register
1F6D
r/w
CAP 0
CMP 0
OFL 0
LAC 0
RCR 0
x 0
x 0
x 0 Res
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PRELIMINARY DATA SHEET
CDC16xxF-E
Table 27-3: Capture-Compare-Unit, continued
Mnemonic Register Name Addr. (hex) 7 CC0 CAPCOM 0 Capture/ Compare Register low byte 1F6E 6 Register Configuration 5 4 3 2 1 0 15.2. Section
r w 1
Read low byte of capture register and lock it. Write low byte of compare register and lock it. 1 1 1 1 1 1 1 Res
CAPCOM 0 Capture/ Compare Register high byte
1F6F
r w 1
Read high byte of capture register and unlock it. Write high byte of compare register and unlock it. 1 1 1 1 1 1 1 Res
CC1M
CAPCOM 1 Mode Register
1F70
r/w
MCAP 0
MCMP 0
MOFL 0
FOL 0 0
OAM 0 0
IAM 0 Res
CC1I
CAPCOM 1 Interrupt Register
1F71
r/w
CAP 0
CMP 0
OFL 0
LAC 0
RCR 0
x 0
x 0
x 0 Res
CC1
CAPCOM 1 Capture/ Compare Register low byte
1F72
r w 1
Read low byte of capture register and lock it. Write low byte of compare register and lock it. 1 1 1 1 1 1 1 Res
CAPCOM 1 Capture/ Compare Register high byte
1F73
r w 1
Read high byte of capture register and unlock it. Write high byte of compare register and unlock it. 1 1 1 1 1 1 1 Res
CC2M
CAPCOM 2 Mode Register
1F74
r/w
MCAP 0
MCMP 0
MOFL 0
FOL 0 0
OAM 0 0
IAM 0 Res
CC2I
CAPCOM 2 Interrupt Register
1F75
r/w
CAP 0
CMP 0
OFL 0
LAC 0
RCR 0
x 0
x 0
x 0 Res
CC2
CAPCOM 2 Capture/ Compare Register low byte
1F76
r w 1
Read low byte of capture register and lock it. Write low byte of compare register and lock it. 1 1 1 1 1 1 1 Res
CAPCOM 2 Capture/ Compare Register high byte
1F77
r w 1
Read high byte of capture register and unlock it. Write high byte of compare register and unlock it. 1 1 1 1 1 1 1 Res
Micronas
May 25, 2004; 6251-606-1PD
183
CDC16xxF-E
Table 27-3: Capture-Compare-Unit, continued
Mnemonic Register Name Addr. (hex) 7 CCC CAPCOM Counter low byte 1F7C 6
PRELIMINARY DATA SHEET
Register Configuration 5 4 3 2 1 0
Section
r 0 0
Read low byte and lock CCC 0 0 0 0 0 0 Res
15.2.
CAPCOM Counter high byte
1F7D
r 0 0
Read high byte and unlock CCC 0 0 0 0 0 0 Res
Table 27-4: Controller Area Network 0
Mnemonic Register Name Addr. (hex) 7 CAN0CTR Control Register 1C00 6 Register Configuration 5 4 3 2 1 0 21.2.
Res
Section
r/w
HLT 1
SLP 0
GRSC 0
EIE 0
GRIE 0
GTIE 0
BOST 0
rsvd x
CAN0STR
Status Register
1C01
r
HACK 1
BOFF 0
EPAS 0
ERS 0
rsvd x
rsvd x
rsvd x
rsvd x Res
CAN0ESTR
Error Status Register
1C02
r/w
GDM 0
CTOV 0
ECNT 0
BIT 0
STF 0
CRC 0
FRM 0
ACK 0 Res
CAN0IDX
Interrupt Index Register
1C03
r/w 1 1 1
Interrupt Index 1 1 1 1 1 Res
CAN0IDM
Identifier Mask Register
1C04 1C05 1C06 1C07
r/w r/w r/w r/w 0
Identifier Mask Bits 29 to 21 Identifier Mask Bits 20 to 13 Identifier Mask Bits 12 to 5 Identifier Mask Bits 4 to 0 0 0 0 0 x 0 x 0 x 0
low
high Res
CAN0BT1
Bit Timing Register 1
1C08
r/w
MSAM 0
SYN 0
BPR 0
BPR 0
BPR 0
BPR 0
BPR 0
BPR 0 Res
CAN0BT2
Bit Timing Register 2
1C09
r/w
rsvd 0
TSEG2 0
TSEG2 0
TSEG2 0
TSEG1 0
TSEG1 0
TSEG1 0
TSEG1 0 Res
CAN0BT3
Bit Timing Register 3
1C0A
r/w
rsvd x
rsvd x
rsvd x
rsvd x
rsvd x
SJW 0
SJW 0
SJW 0 Res
184
May 25, 2004; 6251-606-1PD
Micronas
PRELIMINARY DATA SHEET
CDC16xxF-E
Table 27-4: Controller Area Network 0, continued
Mnemonic Register Name Addr. (hex) 7 CAN0ICR Input Control Register 1C0B 6 Register Configuration 5 4 3 2 1 0 21.2.
Res
Section
r/w
rsvd x
rsvd x
rsvd x
rsvd x
rsvd x
XREF 0
REF1 0
REF0 0
CAN0OCR
Output Control Register
1C0C
r/w
rsvd x
rsvd x
rsvd x
rsvd x
rsvd x
rsvd x
rsvd x
ITX 0 Res
CAN0TEC
Transmit Error Counter
1C0D
r 0 0 0
Counter Bit 7 to 0 0 0 0 0 0 Res
CAN0REC
Receive Error Counter
1C0E
r
x x 0 0
Counter Bit 6 to 0 0 0 0 0 0 Res
CAN0ESM
Error Status Mask Register
1C0F
r/w
EGDM 1
ECTV 1
EECT 1
EBIT 1
ESTF 1
ECRC 1
EFRM 1
EACK 1 Res
CAN0CTIM
Capture Timer
1C10 1C11
r r 0 0 0
Timer Bit 7 to 0 Timer Bit 15 to 8 0 0 0 0 0
low high Res
Table 27-5: Controller Area Network 1
Mnemonic Register Name Addr. (hex) 7 CAN1CTR Control Register 1C40 6 Register Configuration 5 4 3 2 1 0 21.2.
Res
Section
r/w
HLT 1
SLP 0
GRSC 0
EIE 0
GRIE 0
GTIE 0
BOST 0
rsvd x
CAN1STR
Status Register
1C41
r
HACK 1
BOFF 0
EPAS 0
ERS 0
rsvd x
rsvd x
rsvd x
rsvd x Res
CAN1ESTR
Error Status Register
1C42
r/w
GDM 0
CTOV 0
ECNT 0
BIT 0
STF 0
CRC 0
FRM 0
ACK 0 Res
CAN1IDX
Interrupt Index Register
1C43
r/w 1 1 1
Interrupt Index 1 1 1 1 1 Res
Micronas
May 25, 2004; 6251-606-1PD
185
CDC16xxF-E
Table 27-5: Controller Area Network 1, continued
Mnemonic Register Name Addr. (hex) 7 CAN1IDM Identifier Mask Register 1C44 1C45 1C46 1C47 6
PRELIMINARY DATA SHEET
Register Configuration 5 4 3 2 1 0
Section
r/w r/w r/w r/w 0
Identifier Mask Bits 29 to 21 Identifier Mask Bits 20 to 13 Identifier Mask Bits 12 to 5 Identifier Mask Bits 4 to 0 0 0 0 0 x 0 x 0 x 0
low
21.2.
high Res
CAN1BT1
Bit Timing Register 1
1C48
r/w
MSAM 0
SYN 0
BPR 0
BPR 0
BPR 0
BPR 0
BPR 0
BPR 0 Res
CAN1BT2
Bit Timing Register 2
1C49
r/w
rsvd 0
TSEG2 0
TSEG2 0
TSEG2 0
TSEG1 0
TSEG1 0
TSEG1 0
TSEG1 0 Res
CAN1BT3
Bit Timing Register 3
1C4A
r/w
rsvd x
rsvd x
rsvd x
rsvd x
rsvd x
SJW 0
SJW 0
SJW 0 Res
CAN1ICR
Input Control Register
1C4B
r/w
rsvd x
rsvd x
rsvd x
rsvd x
rsvd x
XREF 0
REF1 0
REF0 0 Res
CAN1OCR
Output Control Register
1C4C
r/w
rsvd x
rsvd x
rsvd x
rsvd x
rsvd x
rsvd x
rsvd x
ITX 0 Res
CAN1TEC
Transmit Error Counter
1C4D
r 0 0 0
Counter Bit 7 to 0 0 0 0 0 0 Res
CAN1REC
Receive Error Counter
1C4E
r
x x 0 0
Counter Bit 6 to 0 0 0 0 0 0 Res
CAN1ESM
Error Status Mask Register
1C4F
r/w
EGDM 1
ECTV 1
EECT 1
EBIT 1
ESTF 1
ECRC 1
EFRM 1
EACK 1 Res
CAN1CTIM
Capture Timer
1C50 1C51
r r 0 0 0
Timer Bit 7 to 0 Timer Bit 15 to 8 0 0 0 0 0
low high Res
186
May 25, 2004; 6251-606-1PD
Micronas
PRELIMINARY DATA SHEET
CDC16xxF-E
Table 27-6: Controller Area Network 2
Mnemonic Register Name Addr. (hex) 7 CAN2CTR Control Register 1C80 6 Register Configuration 5 4 3 2 1 0 21.2.
Res
Section
r/w
HLT 1
SLP 0
GRSC 0
EIE 0
GRIE 0
GTIE 0
BOST 0
rsvd x
CAN2STR
Status Register
1C81
r
HACK 1
BOFF 0
EPAS 0
ERS 0
rsvd x
rsvd x
rsvd x
rsvd x Res
CAN2ESTR
Error Status Register
1C82
r/w
GDM 0
CTOV 0
ECNT 0
BIT 0
STF 0
CRC 0
FRM 0
ACK 0 Res
CAN2IDX
Interrupt Index Register
1C83
r/w 1 1 1
Interrupt Index 1 1 1 1 1 Res
CAN2IDM
Identifier Mask Register
1C84 1C85 1C86 1C87
r/w r/w r/w r/w 0
Identifier Mask Bits 29 to 21 Identifier Mask Bits 20 to 13 Identifier Mask Bits 12 to 5 Identifier Mask Bits 4 to 0 0 0 0 0 x 0 x 0 x 0
low
high Res
CAN2BT1
Bit Timing Register 1
1C88
r/w
MSAM 0
SYN 0
BPR 0
BPR 0
BPR 0
BPR 0
BPR 0
BPR 0 Res
CAN2BT2
Bit Timing Register 2
1C89
r/w
rsvd 0
TSEG2 0
TSEG2 0
TSEG2 0
TSEG1 0
TSEG1 0
TSEG1 0
TSEG1 0 Res
CAN2BT3
Bit Timing Register 3
1C8A
r/w
rsvd x
rsvd x
rsvd x
rsvd x
rsvd x
SJW 0
SJW 0
SJW 0 Res
CAN2ICR
Input Control Register
1C8B
r/w
rsvd x
rsvd x
rsvd x
rsvd x
rsvd x
XREF 0
REF1 0
REF0 0 Res
CAN2OCR
Output Control Register
1C8C
r/w
rsvd x
rsvd x
rsvd x
rsvd x
rsvd x
rsvd x
rsvd x
ITX 0 Res
CAN2TEC
Transmit Error Counter
1C8D
r 0 0 0
Counter Bit 7 to 0 0 0 0 0 0 Res
Micronas
May 25, 2004; 6251-606-1PD
187
CDC16xxF-E
Table 27-6: Controller Area Network 2, continued
Mnemonic Register Name Addr. (hex) 7 CAN2REC Receive Error Counter 1C8E 6
PRELIMINARY DATA SHEET
Register Configuration 5 4 3 2 1 0
Section
r
x x 0 0
Counter Bit 6 to 0 0 0 0 0 0 Res
21.2.
CAN2ESM
Error Status Mask Register
1C8F
r/w
EGDM 1
ECTV 1
EECT 1
EBIT 1
ESTF 1
ECRC 1
EFRM 1
EACK 1 Res
CAN2CTIM
Capture Timer
1C90 1C91
r r 0 0 0
Timer Bit 7 to 0 Timer Bit 15 to 8 0 0 0 0 0
low high Res
Table 27-7: Core Logic
Mnemonic Register Name Addr. (hex) 7 CSW0 Clock, Supply and Watchdog Register 0 1F00 6 Register Configuration 5 4 3 2 1 0 6.
Res
Section
w
x x
x x
x x
x x
x x
x x
x x
CMA 1
CR
Control Register
1F01
r/w RESLNG TSTTOG
x
MFM MFM
TSTROM IROM FLASH IROM
IRAM IRAM
ICPU ICPU
ROM Emu Res
r/w RESLNG TSTTOG EBTRI
Value of 00FFF3h
SR0
Standby Register 0
1F08
r/w
SM 0
PWM1 0
PWM0 0
UART2 0
SPI1 0
CAN0 0
CCC 0
SPI0 0 Res
SR1
Standby Register 1
1F09
r/w
LCD 0
CPUFST PSLW 1 0
UART0 0
ADC 0
P0DIN 0
TIM1 0
ERM 0 Res
SR2
Standby Register 2
1F0A
r/w
TIM2 0
PWM3 0
PWM2 0
UART1 0
PWM4 0
DGB 0
EXTIR 0
ABM 0 Res
SR3
Standby Register 3 Reset with pin reset || VDD power on
*)
1F0B
r/w
x x
x x
x x
XTAL 1
WAID 0
*)
FCLO 0
CAN2 0
CAN1 0 Res
CO0SEL
Clock Out 0 Selection
1F14
w
x x
x x
x x
x x
x x
x x
CO01 0
CO00 0 Res
188
May 25, 2004; 6251-606-1PD
Micronas
PRELIMINARY DATA SHEET
CDC16xxF-E
Table 27-7: Core Logic, continued
Mnemonic Register Name Addr. (hex) 7 CO1SEL Clock Out 1Selection 1F15 6 Register Configuration 5 4 3 2 1 0 6.
Res
Section
w
x x
x x
x x
x x
x x
x x
x x
CO10 0
CSW1
Clock, Supply and Watchdog Register 1
1F60
r w
x
x
x
x
x
x
x
WDRES
Watchdog Time and Trigger Value 1 1 1 1 1 1 1 1 Res
CSW2
Clock, Supply and Watchdog Register 2
1F61
r w
TST x TST
x x x
WKID x 0
FHR FHR 0
CLM x 0
PIN x 0
POR x 0
x x x
0 0 Res*
*The
Reset state in the register frame above describes the state after a write to register CSW2. Refer to Table 6-8 on page 53 for the state after a hardware reset.
Table 27-8: Debug Register
Mnemonic Register Name Addr. (hex) 7 DBG Debug Register 1F0C 6 Register Configuration 5 4 3 2 1 0 8.3.5. Section
r/w
x x
x x
x x
x x
x x
x x
x x
DCS 0
0 POR
Table 27-9: DIGITbus
Mnemonic Register Name Addr. (hex) 7 DGC0 Control Register 0 1FF0 6 Register Configuration 5 4 3 2 1 0 23.4.
0 Res
Section
r/w
RUN 0
GBC 0
ACT 0
RXO 0
X x 0
PSC 2 to 0 0
DGC1
Control Register 1
1FF1
r/w
INTE 0
ENEM 0
ENOF 0
x x 0 0
PHASE 0 0 Res
DGS0
Status Register 0
1FF2
w r
x RDL x
x NEM 0
x NOF 1
TGV
PV
ERR
x
ARB
0
0
0
x
0
Res
Micronas
May 25, 2004; 6251-606-1PD
189
CDC16xxF-E
Table 27-9: DIGITbus, continued
Mnemonic Register Name Addr. (hex) 7 DGRTMD Rx Length & Tx More Data Register 1FF3 6
PRELIMINARY DATA SHEET
Register Configuration 5 4 3 2 1 0
Section
w r RDL 0 NEM 0 FTYP x
Transmit More Data EOFLD x x x x LEN2 to 0 x x Res
23.4.
DGTL
Tx Length Register
1FF4
w
x x
FLUSH 0 EMPTY 1
x x x x
x x x x
x x x x 0 x x
LEN2 to 0 0 x x 0 x x Res Res
r
x x
DGS1TA
Status 1 & Tx Address Register
1FF5
w r 0 STATE 1 0
Transmit Address PW5 to 0 0 0 0 0 0 Res
DGTD
Tx Data Register
1FF6
w x x x
Transmit Data x x x x x Res
DGRTMA
Rx Field & Tx More Address Register
1FF7
w r x x x
Transmit More Address Receive Field x x x x x Res
Table 27-10: DMA
Mnemonic Register Name Addr. (hex) 7 DCS DMA Control and Status Register 1FE8 6 Register Configuration 5 4 3 2 1 0 18.2.
Res
Section
r/w
x 0
x 0
x 0
DTA 0
DSI 0
DCC 0
STP 0
BSY 0
DIC
DMA Initial Configuration Register
1FE9
w
x 0
WS2 0
WS1 0
WS0 0
x 0
x 0
x 0
WSA 0 Res
DSA
DMA Start Address
1FEA 1FEB 1FEC
w w w 0 0 0
Bit 7 to 0 Bit 15 to 8 Bit 23 to 16 0 0 0 0 0 Res
190
May 25, 2004; 6251-606-1PD
Micronas
PRELIMINARY DATA SHEET
CDC16xxF-E
Table 27-10: DMA, continued
Mnemonic Register Name Addr. (hex) 7 DEA DMA End Address 1FED 1FEE 1FEF 6 Register Configuration 5 4 3 2 1 0 18.2. Section
w w w 0 0 0
Bit 7 to 0 Bit 15 to 8 Bit 23 to 16 0 0 0 0 0 Res
Table 27-11: EMI Reduction Module
Mnemonic Register Name Addr. (hex) 7 ERMC EMI Reduction Module Control Register 1F02 6 Register Configuration 5 4 3 2 1 0 4.4.8. Section
r w
x x x
x x x
x 0 0
x 0 0
x 0 1
x 0 0
x 0 0
CLKSEL CLKSEL 0 Res
Table 27-12: High Current Port 0
Mnemonic Register Name Addr. (hex) 7 H0NS High Current Port 0 Normal/Special Register High Current Port 0 Tristate Register 1F80 6 Register Configuration 5 4 3 2 1 0 11.5.
Res
Section
w
x 0
x 0
S5 0
S4 0
S3 0
S2 0
S1 0
S0 0
H0TRI
1F81
w
x 0
x 0
T5 0
T4 0
T3 0
T2 0
T1 0
T0 0 Res
H0D
High Current Port 0 Data Register
1F82
r/w
x 0
x 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0 Res
Table 27-13: High Current Port 1
Mnemonic Register Name Addr. (hex) 7 H1NS High Current Port 1 Normal/Special Register 1F84 6 Register Configuration 5 4 3 2 1 0 11.5.
Res
Section
w
x 0
x 0
S5 0
S4 0
S3 0
S2 0
S1 0
S0 0
Micronas
May 25, 2004; 6251-606-1PD
191
CDC16xxF-E
Table 27-13: High Current Port 1, continued
Mnemonic Register Name Addr. (hex) 7 H1TRI High Current Port 1 Tristate Register 1F85 6
PRELIMINARY DATA SHEET
Register Configuration 5 4 3 2 1 0
Section
w
x 0
x 0
T5 0
T4 0
T3 0
T2 0
T1 0
T0 0 Res
11.5.
H1D
High Current Port 1 Data Register
1F86
r/w
x 0
x 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0 Res
Table 27-14: High Current Port 2
Mnemonic Register Name Addr. (hex) 7 H2NS High Current Port 2 Normal/Special Register High Current Port 2 Tristate Register 1F88 6 Register Configuration 5 4 3 2 1 0 11.5.
Res
Section
w
x 0
x 0
S5 0
S4 0
S3 0
S2 0
S1 0
S0 0
H2TRI
1F89
w
x 0
x 0
T5 0
T4 0
T3 0
T2 0
T1 0
T0 0 Res
H2D
High Current Port 2 Data Register
1F8A
r/w
x 0
x 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0 Res
Table 27-15: High Current Port 3
Mnemonic Register Name Addr. (hex) 7 H3NS High Current Port 3 Normal/Special Register High Current Port 3 Tristate Register 1F90 6 Register Configuration 5 4 3 2 1 0 11.5.
Res
Section
w
x 0
x 0
S5 0
S4 0
S3 0
S2 0
S1 0
S0 0
H3TRI
1F91
w
x 0
x 0
T5 0
T4 0
T3 0
T2 0
T1 0
T0 0 Res
H3D
High Current Port 3 Data Register
1F92
r/w
x 0
x 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0 Res
192
May 25, 2004; 6251-606-1PD
Micronas
PRELIMINARY DATA SHEET
CDC16xxF-E
Table 27-16: Interrupt Controller
Mnemonic Register Name Addr. (hex) 7 IRE Interrupt Enable Register 1F1F 6 Register Configuration 5 4 3 2 1 0 10.2. Section
w
A write access enables interrupts according to priority setting (same effect as setting IRC.DINT) 0 0 0 0 0 0 0 0 Res
IRC
Interrupt Control Register
1F20
r w
x x
x x
x x
x RESET x
DAINT DAINT 1
DINT DINT 1
x A1INT x
x CLEAR x Res
IRRET
Interrupt Pending and Return Register
1F21
r w
IPF7
IPF6
IPF5
IPF4
IPF3
IPF2
IPF1
IPF0
A write access signals to the Interrupt Controller that the current request has been served 1 1 1 1 1 1 1 1 Res
IRPRI10
Interrupt Priority, Inputs 0 and 1
1F22
r/w 0 0
PRIO1 0 0 0 0
PRIO0 0 0 Res
IRPRI32
Interrupt Priority, Inputs 2 and 3
1F23
r/w 0 0
PRIO3 0 0 0 0
PRIO2 0 0 Res
IRPRI54
Interrupt Priority, Inputs 4 and 5
1F24
r/w 0 0
PRIO5 0 0 0 0
PRIO4 0 0 Res
IRPRI76
Interrupt Priority, Inputs 6 and 7
1F25
r/w 0 0
PRIO7 0 0 0 0
PRIO6 0 0 Res
IRPRI98
Interrupt Priority, Inputs 8 and 9
1F26
r/w 0 0
PRIO9 0 0 0 0
PRIO8 0 0 Res
IRPRIBA
Interrupt Priority, Inputs 10 and 11
1F27
r/w 0 0
PRIO11 0 0 0 0
PRIO10 0 0 Res
IRPRIDC
Interrupt Priority, Inputs 12 and 13
1F28
r/w 0 0
PRIO13 0 0 0 0
PRIO12 0 0 Res
IRPRIFE
Interrupt Priority, Inputs 14 and 15
1F29
r/w 0 0
PRIO15 0 0 0 0
PRIO14 0 0 Res
IRP
Interrupt Pending Register
1F2A
r
IPF15 1
IPF14 1
IPF13 1
IPF12 1
IPF11 1
IPF10 1
IPF9 1
IPF8 1 Res
Micronas
May 25, 2004; 6251-606-1PD
193
CDC16xxF-E
Table 27-16: Interrupt Controller, continued
Mnemonic Register Name Addr. (hex) 7 IRPM0 Interrupt Port Mode Register 0 1F2B 6
PRELIMINARY DATA SHEET
Register Configuration 5 4 3 2 1 0
Section
w 0
PIT3 0 0
PIT2 0 0
PIT1 0 0
PIT0 0 Res
10.2.
IRPP
Interrupt Port Prescaler Register
1F2C
w
x
x
x
x
x
x
P1INT32 P0INT4 0 0 Res
Table 27-17: Memory Banking
Mnemonic Register Name Addr. (hex) 7 ABR Alternative Banking Register 1F0F 6 Register Configuration 5 4 3 2 1 0 5.2.2.
0 0 1 Res
Section
r/w 0 0 0
Alternative Bank Address 0 0
Table 27-18: Multiplier
Mnemonic Register Name Addr. (hex) 7 MULCAND Multiplicand 1EA0 6 Register Configuration 5 4 3 2 1 0 7.2.
x x x Res
Section
r/w x x x
multiplicand x x
MULPLIER
Multiplier
1EA1
r/w x x x
multiplier x x x x x Res
MULPROD
Multiplication Product
1EA3 1EA2
r r
Product high byte Product low byte x
1 0 Res
Table 27-19: Patch Module
Mnemonic Register Name Addr. (hex) 7 PAR0 Patch Address Register 0 1E64 6 Register Configuration 5 4 3 2 1 0 9.2.
Res
Section
w
PA7 1
PA6 1
PA5 1
PA4 1
PA3 1
PA2 1
PA1 1
PA0 1
194
May 25, 2004; 6251-606-1PD
Micronas
PRELIMINARY DATA SHEET
CDC16xxF-E
Table 27-19: Patch Module, continued
Mnemonic Register Name Addr. (hex) 7 PAR1 Patch Address Register 1 1E65 6 Register Configuration 5 4 3 2 1 0 9.2.
Res
Section
w
PA15 1
PA14 1
PA13 1
PA12 1
PA11 1
PA10 1
PA9 1
PA8 1
PAR2
Patch Address Register 2
1E66
w
PA23 1
PA22 1
PA21 1
PA20 1
PA19 1
PA18 1
PA17 1
PA16 1 Res
PDR
Patch Data Register
1E67
w
PD7 0
PD6 0
PD5 0
PD4 0
PD3 0
PD2 0
PD1 0
PD0 0 Res
PER0
Patch Enable Register 0
1E68
w
PSEL6 0
PSEL5 0
PSEL4 0
PSEL3 0
PSEL2 0
PSEL1 0
PSEL0 0
PMEN 0 Res
PER1
Patch Enable Register 1
1E69
w
x x
x x
x x
x x
x x
PSEL9 0
PSEL8 0
PSEL7 0 Res
Table 27-20: Port 0
Mnemonic Register Name Addr. (hex) 7 P0PIN Port 0 Data Register 1F7E 6 Register Configuration 5 4 3 2 1 0 11.1.
Res
Section
r
x x
x x
P5 x
P4 x
P3 x
P2 x
P1 x
x x
Table 27-21: Power Saving Module
Mnemonic Register Name Addr. (hex) 7 WUS Wake-Up Source Register 1E71 1E70 6 Register Configuration 5 4 3 2 1 0 8.2. Section
r/w r/w
RTC WP7
x WP6
x WP5
x WP4
x WP3
x WP2
WP9 WP1
WP8 WP0
1 0 Res
No HW reset
Micronas
May 25, 2004; 6251-606-1PD
195
CDC16xxF-E
Table 27-21: Power Saving Module, continued
Mnemonic Register Name Addr. (hex) 7 SSR Sub Second Reload Register 1E77 1E76 1E75 1E74 6
PRELIMINARY DATA SHEET
Register Configuration 5 4 3 2 1 0
Section
r/w r/w r/w r/w
x x
x x
x x
x x
x
x
x
x
3 2 1 0 Res
8.2.
Bit 19 to 16
Bit 15 to 8 Bit 7 to 0 No HW reset
SSC
Sub Second Counter
1E7B 1E7A 1E79 1E78
r r r r
x x
x x
x x
x x
x
x
x
x
3 2 1 0 Res
Bit 19 to 16
Bit 15 to 8 Bit 7 to 0 No HW reset
RTC
Real Time Counter
1E7F 1E7E 1E7D 1E7C
r/w r/w r/w r/w
x x x x
x x x x
x x
x
x
x HR MIN SEC
x
x
3 2 1 0 Res
No HW reset
WPM0 WPM2 WPM4 WPM6 WPM8 WSC
Wake Port Mode Register
1E80 1E81 1E82 1E83 1E84
r/w
x
MOD1
x No HW reset
MOD0
0 Res
Wake Source Control
1E88
r/w
x
x
x
x
x
AST
RTC
P
0 Res
0x00 after VDD power on
OSC
Oscillator Source Register
1E90
r/w
RC 1
XK 0
XM 1
x
LD
PRE No HW reset
SRC
0 Res
RTCC
RTC Control Register
1E94
r/w
x
x
x No HW reset
SEL
0 Res
POL
Polling Register
1E99 1E98
r/w r/w
x ENA OE
CLK x
x DEL 0x00
PER
1 0 Res
196
May 25, 2004; 6251-606-1PD
Micronas
PRELIMINARY DATA SHEET
CDC16xxF-E
Table 27-21: Power Saving Module, continued
Mnemonic Register Name Addr. (hex) 7 SMX Signal Multiplexer Register 1E9C 6 Register Configuration 5 4 3 2 1 0 8.2. Section
r/w
BYP
x
x
x 0x00
x
MUX
0 Res
Table 27-22: Pulse Width Modulator
Mnemonic Register Name Addr. (hex) 7 PWM0 PWM1 PWM2 PWM3 PWM4 PWM 0 Register PWM 1 Register PWM 2 Register PWM 3 Register PWM 4 Register 1F50 1F51 1F52 1F5E 1F5F 6 Register Configuration 5 4 3 2 1 0 14.2.
0 0 0 Res
Section
w 0 0 0
Pulse width value 0 0
Table 27-23: Serial Synchronous Peripheral Interface
Mnemonic Register Name Addr. (hex) 7 SPI0D SPI 0 Data Register 1F10 6 Register Configuration 5 4 3 2 1 0 19.2.
0 0 0 Res
Section
r/w 0 0 0
Bit 7 to 0 of Rx/Tx Data 0 0
SPI0M
SPI 0 Mode Register
1F11
r/w
BIT8 0
LEN9 0
RXSEL INTERN NEDGE 0 0 0
x 0 0
CSF 0 Res
SPI1D
SPI 1 Data Register
1F12
r/w 0 0 0
Bit 7 to 0 of Rx/Tx Data 0 0 0 0 0 Res
SPI1M
SPI 1 Mode Register
1F13
r/w
BIT8 0
LEN9 0
RXSEL INTERN NEDGE 0 0 0
x 0 0
CSF 0 Res
Table 27-24: Stepper Motor Module
Mnemonic Register Name Addr. (hex) 7 SMVC SMM Control Register 1F5A 6 Register Configuration 5 4 3 2 1 0 16.2.
0 Res
Section
w
x x
x x 0
SEL 0 0
x x 0
QUAD
Micronas
May 25, 2004; 6251-606-1PD
197
CDC16xxF-E
Table 27-24: Stepper Motor Module, continued
Mnemonic Register Name Addr. (hex) 7 SMVSIN SMM Sine Register 1F5B 6
PRELIMINARY DATA SHEET
Register Configuration 5 4 3 2 1 0
Section
r w
x
x
x
x
x
x
x
BUSY
16.2.
8bit Sine Value 0 0 0 0 0 0 0 0 Res
SMVCOS
SMM Cosine Register
1F5C
w 0 0 0
8bit Cosine Value 0 0 0 0 0 Res
SMVCMP
SMM Comparator Register
1F5D
r/w
x x
x x
ACRD 0
ACRB 0
x x
ACRE 0
ACRC 0
ACRA 0 Res
Table 27-25: Test Registers
Mnemonic Register Name Addr. (hex) 7 TST3 Test Register 3 1FFD 6 Register Configuration 5 4 3 2 1 0 6.4.
0 0 0 Res
Section
w 0 0 0
For testing purposes only 0 0
TST1
Test Register 1
1FFE
w 0 0 0
For testing purposes only 0 0 0 0 0 Res
TST2
Test Register 2
1FFF
w 0 0 0
For testing purposes only 0 0 0 0 0 Res
Table 27-26: Timers
Mnemonic Register Name Addr. (hex) 7 TIM0L Timer 0 low byte 1F4E 6 Register Configuration 5 4 3 2 1 0 13. Section
r w 1
Read low byte of down-counter and latch high byte Write low byte of reload value and reload down-counter 1 1 1 1 1 1 1 Res
TIM0H
Timer 0 high byte
1F4F
r w 1 1
Latched high byte of down-counter High byte of reload value 1 1 1 1 1 1 Res
198
May 25, 2004; 6251-606-1PD
Micronas
PRELIMINARY DATA SHEET
CDC16xxF-E
Table 27-26: Timers, continued
Mnemonic Register Name Addr. (hex) 7 TIM1 TIM2 Timer 1 Register Timer 2 Register 1F54 1F55 6 Register Configuration 5 4 3 2 1 0 13.
0 0 0 Res
Section
w 0 0 0
Reload value 0 0
Table 27-27: Universal Asynchronous Receiver Transmitter 0
Mnemonic Register Name Addr. (hex) 7 UA0D UART 0 Data Register 1FA0 6 Register Configuration 5 4 3 2 1 0 20.3. Section
r w x x x
Receive register Transmit register x x x x x Res
UA0C
UART 0 Control and Status Register
1FA1
r RBUSY 0 w x x
BRKD x x x
FRER x x x
OVRR 0 x x
PAER x STPB 0
EMPTY 1 ODD 0
FULL 0 PAR 0
TBUSY 0 LEN 0 Res Res
UA0BR0
UART 0 Baudrate Register low byte
1FA2
w 0 0 0
Bit 7 to 0 of Baud Rate 0 0 0 0 0 Res
UA0BR1
UART 0 Baudrate Register high byte
1FA3
w
x -
x -
x 0
Bit 12 to 8 of Baud Rate 0 0 0 0 Res
UA0IM
UART 0 Interrupt Mask Register
1FA4
w
x -
x -
x -
x -
x -
ADR 0
BRK 0
RCVD 0 Res
UA0CA
UART 0 Compare Address Register
1FA5
w 0 0 0
Bit 7 to 0 of address 0 0 0 0 0 Res
UA0IF
UART 0 Interrupt Flag Register
1FA6
r
Test -
Test -
Test -
Test -
Test -
ADR x
BRK 0
RCVD 0 Res
Micronas
May 25, 2004; 6251-606-1PD
199
CDC16xxF-E
PRELIMINARY DATA SHEET
Table 27-28: Universal Asynchronous Receiver Transmitter 1
Mnemonic Register Name Addr. (hex) 7 UA1D UART 1 Data Register 1F18 6 Register Configuration 5 4 3 2 1 0 20.3. Section
r w x x x
Receive register Transmit register x x x x x Res
UA1C
UART 1 Control and Status Register
1F19
r RBUSY 0 w x x
BRKD x x x
FRER x x x
OVRR 0 x x
PAER x STPB 0
EMPTY 1 ODD 0
FULL 0 PAR 0
TBUSY 0 LEN 0 Res Res
UA1BR0
UART 1 Baudrate Register low byte
1F1A
w 0 0 0
Bit 7 to 0 of Baud Rate 0 0 0 0 0 Res
UA1BR1
UART 1 Baudrate Register high byte
1F1B
w
x -
x -
x 0
Bit 12 to 8 of Baud Rate 0 0 0 0 Res
UA1IM
UART 1 Interrupt Mask Register
1F1C
w
x -
x -
x -
x -
x -
ADR 0
BRK 0
RCVD 0 Res
UA1CA
UART 1 Compare Address Register
1F1D
w 0 0 0
Bit 7 to 0 of address 0 0 0 0 0 Res
UA1IF
UART 1 Interrupt Flag Register
1F1E
r
Test -
Test -
Test -
Test -
Test -
ADR x
BRK 0
RCVD 0 Res
Table 27-29: Universal Asynchronous Receiver Transmitter 2
Mnemonic Register Name Addr. (hex) 7 UA2D UART 2 Data Register 1F64 6 Register Configuration 5 4 3 2 1 0 20.3. Section
r w x x x
Receive register Transmit register x x x x x Res
UA2C
UART 2 Control and Status Register
1F65
r RBUSY 0 w x x
BRKD x x x
FRER x x x
OVRR 0 x x
PAER x STPB 0
EMPTY 1 ODD 0
FULL 0 PAR 0
TBUSY 0 LEN 0 Res Res
200
May 25, 2004; 6251-606-1PD
Micronas
PRELIMINARY DATA SHEET
CDC16xxF-E
Table 27-29: Universal Asynchronous Receiver Transmitter 2, continued
Mnemonic Register Name Addr. (hex) 7 UA2BR0 UART 2 Baud rate Register low byte 1F66 6 Register Configuration 5 4 3 2 1 0 20.3.
0 0 0 Res
Section
w 0 0 0
Bit 7 to 0 of Baud Rate 0 0
UA2BR1
UART 2 Baud rate Register high byte
1F67
w
x -
x -
x 0
Bit 12 to 8 of Baud Rate 0 0 0 0 Res
UA2IM
UART 2 Interrupt Mask Register
1F68
w
x -
x -
x -
x -
x -
ADR 0
BRK 0
RCVD 0 Res
UA2CA
UART 2 Compare Address Register
1F69
w 0 0 0
Bit 7 to 0 of address 0 0 0 0 0 Res
UA2IF
UART 2 Interrupt Flag Register
1F6A
r
Test -
Test -
Test -
Test -
Test -
ADR x
BRK 0
RCVD 0 Res
Table 27-30: Universal Port 1
Mnemonic Register Name Addr. (hex) 7 U1D Universal Port 1 Data Register 1F98 6 Register Configuration 5 4 3 2 1 0 11.3.
Res
Section
r/w
D7 0
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
U1SEG10
Universal Port 1 Segments of U1.0, U1.1
1F99
w
x
S1
T1
x
x
S0
T0
x
Port LCD
w LCDSLV 0 0 1 0 0 0 1 0
Res
U1SEG32
Universal Port 1 Segments of U1.2, U1.3
1F9A
w
x 0
S3 0
T3 1
x 0
x 0
S2 0
T2 1
x 0
Port Res
U1M30
Universal Port 1 Mode of U1.0 to U1.3
1F9B
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
U1SEG54
Universal Port 1 Segments of U1.4, U1.5
1F9C
w
x
S5
T5
x
x
S4
T4
x
Port
w SEG5.3 SEG5.2 SEG5.1 SEG5.0 SEG4.3 SEG4.2 SEG4.1 SEG4.0 LCD 0 0 1 0 0 0 1 0 Res
Micronas
May 25, 2004; 6251-606-1PD
201
CDC16xxF-E
Table 27-30: Universal Port 1, continued
Mnemonic Register Name Addr. (hex) 7 U1M54 Universal Port 1 Mode of U1.4, U1.5 1F9D 6
PRELIMINARY DATA SHEET
Register Configuration 5 4 3 2 1 0
Section
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
11.3.
U1SEG76
Universal Port 1 Segments of U1.6, U1.7
1F9E
w
x
S7
T7
x
x
S6
T6
x
Port
w SEG7.3 SEG7.2 SEG7.1 SEG7.0 SEG6.3 SEG6.2 SEG6.1 SEG6.0 LCD 0 0 1 0 0 0 1 0 Res
U1M76
Universal Port 1 Mode of U1.6, U1.7
1F9F
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
Table 27-31: Universal Port 2
Mnemonic Register Name Addr. (hex) 7 U2D Universal Port 2 Data Register 1F30 6 Register Configuration 5 4 3 2 1 0 11.3.
Res
Section
r/w
D7 0
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
U2SEG10
Universal Port 2 Segments of U2.0, U2.1
1F32
w
x
S1
T1
x
x
S0
T0
x
Port
w SEG1.3 SEG1.2 SEG1.1 SEG1.0 SEG0.3 SEG0.2 SEG0.1 SEG0.0 LCD 0 0 1 0 0 0 1 0 Res
U2M10
Universal Port 2 Mode of U2.0, U2.1
1F33
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
U2SEG32
Universal Port 2 Segments of U2.2, U2.3
1F34
w
x
S3
T3
x
x
S2
T2
x
Port
w SEG3.3 SEG3.2 SEG3.1 SEG3.0 SEG2.3 SEG2.2 SEG2.1 SEG2.0 LCD 0 0 1 0 0 0 1 0 Res
U2M32
Universal Port 2 Mode of U2.2, U2.3
1F35
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
U2SEG54
Universal Port 2 Segments of U2.4, U2.5
1F36
w
x
S5
T5
x
x
S4
T4
x
Port
w SEG5.3 SEG5.2 SEG5.1 SEG5.0 SEG4.3 SEG4.2 SEG4.1 SEG4.0 LCD 0 0 1 0 0 0 1 0 Res
202
May 25, 2004; 6251-606-1PD
Micronas
PRELIMINARY DATA SHEET
CDC16xxF-E
Table 27-31: Universal Port 2, continued
Mnemonic Register Name Addr. (hex) 7 U2M54 Universal Port 2 Mode of U2.4, U2.5 1F37 6 Register Configuration 5 4 3 2 1 0 11.3.
Res
Section
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1
U2SEG76
Universal Port 2 Segments of U2.6, U2.7
1F38
w
x
S7
T7
x
x
S6
T6
x
Port
w SEG7.3 SEG7.2 SEG7.1 SEG7.0 SEG6.3 SEG6.2 SEG6.1 SEG6.0 LCD 0 0 1 0 0 0 1 0 Res
U2M76
Universal Port 2 Mode of U2.6, U2.7
1F39
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
Table 27-32: Universal Port 3
Mnemonic Register Name Addr. (hex) 7 U3D Universal Port 3 Data Register 1FAC 6 Register Configuration 5 4 3 2 1 0 11.3.
Res
Section
r/w
D7 0
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
U3SEG10
Universal Port 3 Segments of U3.0, U3.1
1FAE
w
x
S1
T1
x
x
S0
T0
x
Port
w SEG1.3 SEG1.2 SEG1.1 SEG1.0 SEG0.3 SEG0.2 SEG0.1 SEG0.0 LCD 0 0 1 0 0 0 1 0 Res
U3M10
Universal Port 3 Mode of U3.0, U3.1
1FAF
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
U3SEG32
Universal Port 3 Segments of U3.2, U3.3
1FB0
w
x
S3
T3
x
DPM2
S2
T2
x
Port
w SEG3.3 SEG3.2 SEG3.1 SEG3.0 SEG2.3 SEG2.2 SEG2.1 SEG2.0 LCD 0 0 1 0 0 0 1 0 Res
U3M32
Universal Port 3 Mode of U3.2, U3.3
1FB1
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
U3SEG54
Universal Port 3 Segments of U3.4, U3.5
1FB2
w
x
S5
T5
x
x
S4
T4
x
Port
w SEG5.3 SEG5.2 SEG5.1 SEG5.0 SEG4.3 SEG4.2 SEG4.1 SEG4.0 LCD 0 0 1 0 0 0 1 0 Res
Micronas
May 25, 2004; 6251-606-1PD
203
CDC16xxF-E
Table 27-32: Universal Port 3, continued
Mnemonic Register Name Addr. (hex) 7 U3M54 Universal Port 3 Mode of U3.4, U3.5 1FB3 6
PRELIMINARY DATA SHEET
Register Configuration 5 4 3 2 1 0
Section
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
11.3.
U3SEG76
Universal Port 3 Segments of U3.6, U3.7
1FB4
w
x
S7
T7
x
x
S6
T6
x
Port
w SEG7.3 SEG7.2 SEG7.1 SEG7.0 SEG6.3 SEG6.2 SEG6.1 SEG6.0 LCD 0 0 1 0 0 0 1 0 Res
U3M76
Universal Port 3 Mode of U3.6, U3.7
1FB5
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
Table 27-33: Universal Port 4
Mnemonic Register Name Addr. (hex) 7 U4D Universal Port 4 Data Register 1FB8 6 Register Configuration 5 4 3 2 1 0 11.3.
Res
Section
r/w
D7 0
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
U4SEG10
Universal Port 4 Segments of U4.0, U4.1
1FBA
w
x
S1
T1
x
x
S0
T0
x
Port
w SEG1.3 SEG1.2 SEG1.1 SEG1.0 SEG0.3 SEG0.2 SEG0.1 SEG0.0 LCD 0 0 1 0 0 0 1 0 Res
U4M10
Universal Port 4 Mode of U4.0, U4.1
1FBB
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
U4SEG32
Universal Port 4 Segments of U4.2, U4.3
1FBC
w
x
S3
T3
x
x
S2
T2
x
Port
w SEG3.3 SEG3.2 SEG3.1 SEG3.0 SEG2.3 SEG2.2 SEG2.1 SEG2.0 LCD 0 0 1 0 0 0 1 0 Res
U4M32
Universal Port 4 Mode of U4.2, U4.3
1FBD
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
U4SEG54
Universal Port 4 Segments of U4.4, U4.5
1FBE
w
x
S5
T5
x
x
S4
T4
x
Port
w SEG5.3 SEG5.2 SEG5.1 SEG5.0 SEG4.3 SEG4.2 SEG4.1 SEG4.0 LCD 0 0 1 0 0 0 1 0 Res
204
May 25, 2004; 6251-606-1PD
Micronas
PRELIMINARY DATA SHEET
CDC16xxF-E
Table 27-33: Universal Port 4, continued
Mnemonic Register Name Addr. (hex) 7 U4M54 Universal Port 4 Mode of U4.4, U4.5 1FBF 6 Register Configuration 5 4 3 2 1 0 11.3.
Res
Section
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1
U4SEG76
Universal Port 4 Segments of U4.6, U4.7
1FC0
w
x
S7
T7
x
x
S6
T6
x
Port
w SEG7.3 SEG7.2 SEG7.1 SEG7.0 SEG6.3 SEG6.2 SEG6.1 SEG6.0 LCD 0 0 1 0 0 0 1 0 Res
U4M76
Universal Port 4 Mode of U4.6, U4.7
1FC1
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
Table 27-34: Universal Port 5
Mnemonic Register Name Addr. (hex) 7 U5D Universal Port 5 Data Register 1FC4 6 Register Configuration 5 4 3 2 1 0 11.3.
Res
Section
r/w
D7 0
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
U5SEG10
Universal Port 5 Segments of U5.0, U5.1
1FC6
w
x
S1
T1
x
x
S0
T0
x
Port
w SEG1.3 SEG1.2 SEG1.1 SEG1.0 SEG0.3 SEG0.2 SEG0.1 SEG0.0 LCD 0 0 1 0 0 0 1 0 Res
U5M10
Universal Port 5 Mode of U5.0, U5.1
1FC7
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
U5SEG32
Universal Port 5 Segments of U5.2, U5.3
1FC8
w
x
S3
T3
x
x
S2
T2
x
Port
w SEG3.3 SEG3.2 SEG3.1 SEG3.0 SEG2.3 SEG2.2 SEG2.1 SEG2.0 LCD 0 0 1 0 0 0 1 0 Res
U5M32
Universal Port 5 Mode of U5.2, U5.3
1FC9
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
U5SEG54
Universal Port 5 Segments of U5.4, U5.5
1FCA
w
x
S5
T5
x
x
S4
T4
x
Port
w SEG5.3 SEG5.2 SEG5.1 SEG5.0 SEG4.3 SEG4.2 SEG4.1 SEG4.0 LCD 0 0 1 0 0 0 1 0 Res
Micronas
May 25, 2004; 6251-606-1PD
205
CDC16xxF-E
Table 27-34: Universal Port 5, continued
Mnemonic Register Name Addr. (hex) 7 U5M54 Universal Port 5 Mode of U5.4, U5.5 1FCB 6
PRELIMINARY DATA SHEET
Register Configuration 5 4 3 2 1 0
Section
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
11.3.
U5SEG76
Universal Port 5 Segments of U5.6, U5.7
1FCC
w
x
S7
T7
x
x
S6
T6
x
Port
w SEG7.3 SEG7.2 SEG7.1 SEG7.0 SEG6.3 SEG6.2 SEG6.1 SEG6.0 LCD 0 0 1 0 0 0 1 0 Res
U5M76
Universal Port 5 Mode of U5.6, U5.7
1FCD
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
Table 27-35: Universal Port 6
Mnemonic Register Name Addr. (hex) 7 U6D Universal Port 6 Data Register 1FD0 6 Register Configuration 5 4 3 2 1 0 11.3.
Res
Section
r/w
D7 0
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
U6SEG10
Universal Port 6 Segments of U6.0, U6.1
1FD2
w
x
S1
T1
x
x
S0
T0
x
Port
w SEG1.3 SEG1.2 SEG1.1 SEG1.0 SEG0.3 SEG0.2 SEG0.1 SEG0.0 LCD 0 0 1 0 0 0 1 0 Res
U6M10
Universal Port 6 Mode of U6.0, U6.1
1FD3
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
U6SEG32
Universal Port 6 Segments of U6.2, U6.3
1FD4
w
x
S3
T3
x
x
S2
T2
x
Port
w SEG3.3 SEG3.2 SEG3.1 SEG3.0 SEG2.3 SEG2.2 SEG2.1 SEG2.0 LCD 0 0 1 0 0 0 1 0 Res
U6M32
Universal Port 6 Mode of U6.2, U6.3
1FD5
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
U6SEG54
Universal Port 6 Segments of U6.4, U6.5
1FD6
w
x
S5
T5
x
x
S4
T4
x
Port
w SEG5.3 SEG5.2 SEG5.1 SEG5.0 SEG4.3 SEG4.2 SEG4.1 SEG4.0 LCD 0 0 1 0 0 0 1 0 Res
206
May 25, 2004; 6251-606-1PD
Micronas
PRELIMINARY DATA SHEET
CDC16xxF-E
Table 27-35: Universal Port 6, continued
Mnemonic Register Name Addr. (hex) 7 U6M54 Universal Port 6 Mode of U6.4, U6.5 1FD7 6 Register Configuration 5 4 3 2 1 0 11.3.
Res
Section
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1
U6SEG76
Universal Port 6 Segments of U6.6, U6.7
1FD8
w
x
S7
T7
x
x
S6
T6
x
Port
w SEG7.3 SEG7.2 SEG7.1 SEG7.0 SEG6.3 SEG6.2 SEG6.1 SEG6.0 LCD 0 0 1 0 0 0 1 0 Res
U6M76
Universal Port 6 Mode of U6.6, U6.7
1FD9
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
Table 27-36: Universal Port 7
Mnemonic Register Name Addr. (hex) 7 U7D Universal Port 7 Data Register 1FDC 6 Register Configuration 5 4 3 2 1 0 11.3.
Res
Section
r/w
x 0
x 0
x 0
x 0
D3 0
D2 0
D1 0
D0 0
U7SEG10
Universal Port 7 Segments of U7.0, U7.1
1FDE
w
x
S1
T1
x
x
S0
T0
x
Port
w SEG1.3 SEG1.2 SEG1.1 SEG1.0 SEG0.3 SEG0.2 SEG0.1 SEG0.0 LCD 0 0 1 0 0 0 1 0 Res
U7M10
Universal Port 7 Mode of U7.0, U7.1
1FDF
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
U7SEG32
Universal Port 7 Segments of U7.2, U7.3
1FE0
w
x
S3
T3
x
x
S2
T2
x
Port
w SEG3.3 SEG3.2 SEG3.1 SEG3.0 SEG2.3 SEG2.2 SEG2.1 SEG2.0 LCD 0 0 1 0 0 0 1 0 Res
U7M32
Universal Port 7 Mode of U7.2, U7.3
1FE1
w
x 0
x 0
x 0
x 0
x 0
x 0
x 0
PMODE 1 Res
Micronas
May 25, 2004; 6251-606-1PD
207
CDC16xxF-E
28. Differences
This chapter describes differences of this document to predecessor document "CDC16xxF-E Automotive Controller # 1 Section 1. Introduction Description
PRELIMINARY DATA SHEET
Family User Manual", March 31, 2003, 6251-606-2AI.
1.1. Features, Table 1-1: CDC16xxF Family Feature List, page 6: Interrupt Controller expanding NMI: "16 priority levels" changed into "15 priority levels" and no. of "Port WakeUp Inputs including Slope / Level Selection" added. 1.1. Features, Table 1-1: CDC16xxF Family Feature List, page 8: Temperature Range, CDC1605F-E EMU: "Tcase: -40 C to +105 C" changed into "Tcase: 0 to +70 C".
2 3
2. Package and Pins 3. Electrical Data
Fig. 2-9 removed, Table 2-2 corrected. 3.1. Absolute Maximum Ratings: Revised Introduction. 3.2. Recommended Operating Conditions: Revised Introduction; Tj removed. 3.3. Characteristics, Table 3-3: Temperature Range "TCASE: -40 C to +105 C" changed into "TCASE: 0 to +70 C", values for RC Oscillator and Clock Supervision added, some values and footnotes revised, AIDDa: Test Conditions changed. 3.4. Recommended Crystal Characteristics, Table 3-4: Temperature Range "TCASE: -40 C to +105 C" changed into "TCASE: 0 to +70 C". 3.5. Flash/EMU Port Characteristics, Table 3-5: Temperature Range "TCASE: -40 C to 85 C" changed into "TCASE: 0 to +70 C".
4
5. Memory and Boot System
5.1.1. Address Map: "Emulation mode: E=1, Native mode: E=0" changed into a footnote of Table 5-1: Reserved (physical) Addresses. "5.3.4. Used RAM" changed into "5.3.4. Used Resources" and enlarged.
5
6. Core Logic
6.1. Control Register CR: Description of RESLNG corrected. Fig. 6-1: Analog core logic block diagram renamed, Signals and logic for TST.MIX, TEST, MOSPOR and RESBP removed, Power supplies revised. Fig. 6-2: Reset Logic Block Diagram revised: Signals MOSPOR, COMPRES and other internal signal names removed, shown logic minimized, CSW2.FHR logic corrected. 6.2.2.5. Forced Hardware Reset: added. 6.2.2.6. Wake-Up Reset: added. 6.2.5. Reset Registers: CSW2: description revised. 6.3. Standby Registers: Text of RESET cause for SR3.WAID modified and added as Footnote.
6 7
7. Multiplier 8. Power-Saving Module (PSM)
Added: "It is fully supported by the WDC C-compiler WDC816CC." Some phrases corrected and clarified. Fig. 8-3, Fig. 8-4 and Fig. 8-5: Signals MOSPOR, COMPRES, WKX and RESINT removed. 8.2. Registers: Text of RESET cause for reg. WSC modified.
8
10. Interrupt Controller (IR)
Fig. 10-1: "Block Diagram": corrected: A0 ... A15 are unidirectional. Fig. 10-5: "Port Interrupts": corrected: U5.7, U6.6 are not influenced by IRPM0. 10.2. Registers: Reset pattern of IRRET and IRP corrected.
208
May 25, 2004; 6251-606-1PD
Micronas
PRELIMINARY DATA SHEET
CDC16xxF-E
# 9
Section 11. Ports
Description P0D.Dn renamed to P0PIN.Pn. Normal/Special Flags of registers HxNS and UxSEG renamed from N/Sn to Sn. Tristate Flags of registers HxTRI renamed from TRIy to Ty. Tristate Flags of registers UxSEG renamed from TRIy to Ty.
10 11 12 13 14 15 16 17 18 19
13. Timers (TIMER) 15. Capture Compare Module (CAPCOM) 16. Stepper Motor Module (SMM) 18. DMA 19. Serial Synchronous Peripheral Interface (SPI) 23. DIGITbus Master Module 24. Audio Module (AM) 25. Hardware Options 26. Register Cross Reference Table V2.1 27. Register Quick Reference
Corrected and clarified. Fig. 15-1: CAPCOM Module Block Diagram and 15.2. Registers: Flags CCxM.MSK devided into CCxM.MCAP, CCxM.MCMP and CCxM.MOFL. 16.1. Functional Description, Fig. 16-2: Block Diagram of Output Generation Circuit: "fSM / 2E8" changed into "fSM / 256". Fig. 18-1: Block Diagram: Arrow for interface between U2 and GDB changed form unidirectional to bidirectional. 19.2. Registers: SPIxM: description revised. 23.4. Registers: Flag "DGRTMD.EOF" renamed into "DGRTMD.EOFLD". 24.1.2. Initialization: Corrected and clarified. 25.2. Listing of Dedicated Addresses and Corresponding Hardware Options: Some register descriptions clarified. 26.1. CAN RAM, memory pages 19 ... 1B: added. Table 27-7: Core Logic: SR3 Footnote added. Table 27-16: Interrupt Controller: Addr. of IRE added. Table 27-23: Serial Synchronous Peripheral Interface: SPI0 added. Other corrections according to the changes in the accessory sections.
20
28. Differences
Updated
Micronas
May 25, 2004; 6251-606-1PD
209
CDC16xxF-E
29. Data Sheet History
1. Advance Information: "CDC16xxF-E Automotive Controller Family User Manual", Feb. 17, 2003, 6251-606-1AI. First release of the advance information. Originally created for the HW version CDC16xxF-E1. 2. Advance Information: "CDC16xxF-E Automotive Controller Family User Manual", March 31, 2003, 6251-606-2AI. Second release of the advance information. Originally created for the HW version CDC16xxF-E2. 3. Preliminary Datasheet: "CDC16xxF-E Automotive Controller Family User Manual", May 25, 2004, 6251-606-1PD. First release of the preliminary datasheet. Originally created for the HW version CDC16xxF-E2.
PRELIMINARY DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-606-1PD
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
210
May 25, 2004; 6251-606-1PD
Micronas

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