 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| C51 Family C51 Family Programmer's Guide and Instruction Set Summary 1. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.2 1.1. Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2. Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3. Indirect Address Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4. Direct And Indirect Address Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5. Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.2 I.3.3 I.3.3 I.3.3 I.3.4 2. SFR Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.6 2.1. What do the SFRs Contain just after Power-on or a Reset ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.6 2.2. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.8 2.3. Assigning Higher Priority to one More Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.9 2.4. Priority Within Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.9 2.5. Timer Set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.11 2.6. Timer/Counter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.11 2.7. Timer/Counter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.12 2.8. Timer/Counter 2 Set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.12 2.9. Serial Port Set-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.14 2.10. Generating Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.14 2.11. Using Timer/Counter 1 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.14 2.12. Using Timer/Counter 2 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.14 2.13. Serial Port in Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.14 2.14. Serial Port in Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.14 3. Instruction Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.19 MATRA MHS Rev. E (14 Jan. 97) 1 C51 Family 1. Memory Organization 1.1. Program Memory The TEMIC C51 Microcontroller Family has separate address spaces for program Memory and Data Memory. The program memory can be up to 64 K bytes long. The lower 4 K for the 80C51 (8 K for the 80C52, 16 K for the 83 C154 and 32 K for the 83C154D) may reside on chip. Figure 1 to 4 show a map of 80C51, 80C52, 83C154 and 83C154D program memory. Figure 1. The 80C51 Program Memory. 3FFF FFFF FFFF 0000 16K BYTES INTERNAL 0000 Figure 3. The 83C154 Program Memory. FFFF FFFF 48K BYTES EXTERNAL 64K BYTES EXTERNAL 4000 or 60K BYTES EXTERNAL 64K BYTES EXTERNAL Figure 4. The 83C154D Program Memory. FFFF FFFF 1000 or 0FFF 4K BYTES INTERNAL 0000 0000 8000 32K BYTES EXTERNAL 64K BYTES EXTERNAL Figure 2. The 80C52 Program Memory. FFFF FFFF or 7FFF 32K BYTES INTERNAL 0000 0000 56K BYTES EXTERNAL 64K BYTES EXTERNAL 2000 or 1FFF 8K BYTES INTERNAL 0000 0000 2 MATRA MHS Rev. E (14 Jan. 97) C51 Family 1.2. Data Memory The C51 Microcontroller Family can address up to 64 K bytes of Data Memory to the chip. The "MOVX" instruction is used to access the external data memory (refer to the C51 instruction set, in this chapter, for detailed description of instructions). The 80C51 has 128 bytes of on-chip-RAM (256 bytes in the 80C52, 83C154 and 83C154D) plus a number of Special Function Registers (SFR). The lower 128 bytes of RAM can be accessed either by direct addressing (MOV data addr). or by indirect addressing (MOV @Ri). Figure 5 and 6 show the 80C51, 80C52, 83C154 and 83C154D Data Memory organization. Figure 6. The 80C52, 83C154 and 83C154D Data Memory Organisation. INTERNAL INDIRECT ADDRESSING ONLY 80H TO FFH FF FF SFRs DIRECT ADDRESSING ONLY DIRECT & INDIRECT ADDRESSING 00 0000 64K BYTES EXTERNAL AND FFFF 80 7F Figure 5. The 80C51 Data Memory Organisation. 0FFF INTERNAL FF SFRs DIRECT ADDRESSING ONLY AND DIRECT & INDIRECT ADDRESSING 00 0000 64K BYTES EXTERNAL 80 7F 1.3. Indirect Address Area Note that in Figure 6 - the SFRs and the indirect address RAM have the same addresses (80H-OFFH). Nevertheless, they are two separate areas and are accessed in two different ways. For example the instruction MOV 80H, #0AAH writes 0AAH to Port 0 which is one of the SFRs and the instruction MOV R0, # 80H MOV @ R0, # 0BBH writes 0BBH in location 80H of the data RAM. Thus, after execution of both of the above instructions Port 0 will contain 0AAH and location 80 of the RAM will contain 0BBH. Note that the stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space in those devices which implement 256 bytes of internal RAM. 1.4. Direct And Indirect Address Area The 128 bytes of RAM which can be accessed by both direct and indirect addressing can be divided into 3 segments as listed below and shown in figure 7. 1. Register Banks 0.3 : Locations 0 through 1FH (32 bytes). ASM-51 and the device after reset default to register bank 0. To use the other register banks the user must select them in the software. Each register bank contains 8 one-byte registers, 0 through 7. Reset initializes the Stack Pointer to location 07H and it is incremented once to start from location 08H which is the first register (R0) of the second register bank. Thus, in order to use more than one register bank, the SP should be initialized to a different location of the RAM where it is not used for data storage (ie, higher part of the RAM). 2. Bit Addressable Area : 16 bytes have been assigned for this segment, 20H-2FH. Each one of the 128 bits of this segment can be directly addressed (0-7FH). The bits can be referred to in two ways both of which are MATRA MHS Rev. E (14 Jan. 97) 3 C51 Family acceptable by the ASM-51. One way is to refer to their addresses, ie, 0 to 7FH. The other way is with reference to bytes 20H to 2FH. Thus, bits 0-7 can also be referred to as bits 20.0-20.7, and bits 8-FH are the same as 21.0-21.7 and so on. Each of the 16 bytes in this segment can also be addresses as a byte. 3. Scratch Pad Area : Bytes 30H through 7FH are available to user as data RAM. However, if the stack pointer has been initialized to this area, enough number of bytes should be left aside to prevent SP data destruction. Figure 7. 128 Bytes of RAM Direct and Indirect Addressable. 8 Bytes 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 0 ... 3 2 1 0 ... 7F 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 BIT ADDRESSABLE SEGMENT SCRATCH PAD AREA REGISTER BANKS 1.5. Special Function Registers Table 1 contains a list of all the SFRs and their addresses. Comparing table 1 and figure 8 shows that all of the SFRs that are byte and bit addressable are located on the first column of the diagram in figure 8. 4 MATRA MHS Rev. E (14 Jan. 97) C51 Family Table 1. SYMBOL *ACC *B *PSW SP DPTR DPL DPH *P0 *P1 *P2 *P3 *IP *IE TMOD *TCON *+T2CON TH0 TL0 TH1 TL1 +TH2 +TL2 +RCAP2H +RCAP2L *SCON SBUF PCON *IOCON (1) + 80C52, 83C154 and 83C154D only (1) 83C154 and 83C154D only Accumulator B Register Program Status Word Stack Pointer Data Pointer 2 Bytes Low Byte High Byte Port 0 Port 1 Port 2 Port 3 Interrupt Priority Control Interrupt Enable Control Timer/Counter Mode Control Timer/Counter Control Timer/Counter 2 Control Timer/Counter 0 High Byte Timer/Counter 0 Low Byte Timer/Counter 1 High Byte Timer/Counter 1 Low Byte Timer/Counter 1 High Byte Timer/Counter 2 Low Byte T/C 2 Capture Reg. High Byte T/C 2 Capture Reg. Low Byte Serial Control Serial Data Buffer Power Control IO Control * bit addressable 82H 83H 80H 90H 0A0H 0B0H 0B8H 0A8H 89H 88H 0C8H 8CH 8AH 8DH 8BH 0CDH 0CCH 0CBH 0CAH 98H 99H 87H F8H NAME ADDRESS 0E0H 0F0H 0D0H 81H MATRA MHS Rev. E (14 Jan. 97) 5 C51 Family 2. SFR Memory Map Figure 8. 8 Bytes F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 IP P3 IE P2 SCON P1 TCON P0 TMOD SP bit addressable TL0 DPL TL1 DPH TH0 TH1 PCON SBUF PSW T2CON RCAP2L RCAP2H TL2 TH2 ACC IOCON B FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87 2.1. What do the SFRs Contain just after Power-on or a Reset ? Table 2 lists the contents of each SFR after a power-on reset or a hardware reset. Table 2. Contents of the SRFs after reset. REGISTER *ACC *B *PSW SP DPTR *P0 *P1 *P2 *P3 *IP VALUE IN BINARY 0000 0000 0000 0000 0000 0000 0000 0111 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 XXX0 0000 80C51 XXX0 0000 80C52 0X00 0000 83C154/C154D 0XX0 0000 80C51 0X000 0000 83C154/C154D and 80C52 0000 0000 *IE TMOD * : bit addressable. + : 80C52, 83C154 and 83C154D only. - : 83C154 and 83C154D only. X : Undefined. 6 MATRA MHS Rev. E (14 Jan. 97) C51 Family REGISTER *TCON +*T2CON TH0 TL0 TH1 TL1 + TH2 + TL2 + RCAP2L + RCAP2H *SCON SBUF PCON -*IOCON VALUE IN BINARY 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Indeterminate 0XXX 0000 80C51 and 80C52 000X 0000 83C154 and 83C154D 0000 0000 These SFRs that have their bits assigned for various functions are listed in this section. A brief description of each bit is provided for quick reference. For more detailed information refer to the Architecture chapter of this book. PSW : Program Status Word (Bit Addressable) CY AC F0 RS1 RS0 OV F1 P CY AC F0 RS1 RS0 OV F1 P PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0 Carry Flag. Auxiliary Carry Flag. Flag 0 available to the user for general purpose. Register Bank selector bit 1 (SEE NOTE). Register Bank selector bit 0 (SEE NOTE). Overflow Flag. Flag F1 available to the user for general purpose. Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of "1" bits in the accumulator. * User software should not write 1s to reserved bits. These bits may be used in future TEMIC C51 products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. Note : The value presented by RS0 and RS1 selects the corresponding register bank. RS1 0 0 1 1 RS0 0 1 0 1 REGISTER BANK 0 1 2 3 ADDRESS 00H-07H 08H-0FH 10H-17H 18H-1FH MATRA MHS Rev. E (14 Jan. 97) 7 C51 Family PCON : Power Control Register (Not Bit Addressable) SMOD HPD RPD - GF1 GF0 PD IDL SMOD PCON.7 Double baud rate bit. If SMOD = 1, the baud rate is doubled when the serial part is used in mode 1, 2 and 3. HPD PCON.6 Hard Power Down. (83C154 and 83C154D only). The falling/rising edge of a signal connected on pin P3.5 Starts/Stops the Power-Down mode. A reset can also stop this mode. RPD PCON.5 Recover Power Down bit. (83C154 and 83C154D only). It's used to cancel a Power-Down/IDLE mode. If it's set, an interrupt (enable or disable) can cancel this mode. A reset can also stop this mode (see Note 1). PCON.4 Not implemented, reserved for futur used* GF1 PCON.3 General purpose bit. GF0 PCON.2 General purpose bit. PD PCON.1 Power Down bit. If set, the oscillator is stopped. A reset or an interrupt (83C154 and 83C154D only) can cancel this mode (Note 1). IDL PCON.0 IDLE bit. If set the activity CPU is stopped. A reset or an interrupt can cancel this mode (See Note 1). * User software should not write 1s to reserved bits. These 2.2. Interrupts bits may be used in future TEMIC C51 products to invoke new features. In that case, the reset or inactive value of the In order to use any of the interrupts in the C51, the following three steps must be taken. new bit will be 0, and its active value will be 1. 1. Set the EA (enable all) bit in the IE register to 1. 2. Set the corresponding individual interrupt enable bit in Note 1 (83C154 and 83C154D only) : the IE register to 1. - if RPD = 0 and if an interrupt cancels the mode 3. Begin the Interrupt service routine at the corresponding Power-Down/IDLE, the next instruction to execute is a Vector Address of that interrupt. See Table below. LCALL at the interrupt routine. - RPD = 1 - if interrupt request is enable the next instruction to execute is a LCALL at the interrupt routine. - if interrupt request is disable, the program continue with the instruction immediately after the Power-Down/Idle instruction. INTERRUPT SOURCE IE0 TF0 IE1 TF1 RI & TI TF2 & EXF2 VECTOR ADDRESS 0003H 000BH 0013H 001BH 0023H 002BH In addition, for external interrupts, pins INT0 and INT1 (P3.2 and P3.3) must be set to 1, and depending on whether the interrupt is to be level or transition activated, bits IT0 or IT1 in the TCON register may need to be set to 1. ITX = 0 level activated ITX = 1 transition activated 8 MATRA MHS Rev. E (14 Jan. 97) C51 Family IE : Interrupt Enable Register (Bit Addressable) If the bit is 0, the corresponding interrupt is disabled. If the bit is 1, the corresponding interrupt is enabled. EA - ET2 ES ET1 EX1 ET0 EX0 EA Disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1, interrupt source is individually enable or disabled by setting or clearing its enable bit. IE.6 Not implemented, reserved for future use*. ET2 IE.5 Enable or disable the Timer 2 overflow or capture interrupt (80C52, 83C154 and 83C154D only). ES IE.4 Enable or disable the Serial port interrupt. ET1 IE.3 Enable or disable the Timer 1 overflow interrupt. EX1 IE.2 Enable or disable External interrupt 1. ET0 IE.1 Enable or disable the Timer 0 overflow interrupt. EX0 IE.0 Enable or disable External Interrupt 0. * User software should not write 1s to reserved bits. These 2.4. Priority Within Level bits may be used in future TEMIC C51 products to invoke new features. In that case, the reset or inactive value of the Priority within level is only to resolve simultaneous requests of the same priority level. From high to low, new bit will be 0, and its active value will be 1. interrupt sources are listed below : IE.7 2.3. Assigning Higher Priority to one More Interrupts In order to assign higher priority to an interrupt the corresponding bit in the IP register must be set to 1. Remember that while an interrupt service is in progress, it cannot be interrupted by a lower or same level interrupt. IE0 TF0 IE1 TF1 RI or TI TF2 or EXF2 IP : Interrupt Priority Register (Bit Addressable) If the bit is 0, the corresponding interrupt has a lower priority and if the bit is the corresponding interrupt has a higher priority. PCT - PT2 PS PT1 PX1 PT0 PX0 PCT IP.7 Defines the same priority level for all the source interrupt (83C154 and 83C154D only). IP.6 Not implemented, reserved for future use*. PT2 IP.5 Defines the Timer 2 interrupt priority level (80C52, 83C154 and 83C154D only). PS IP.4 Defines the Serial Port interrupt priority level. PT1 IP.3 Defines the Timer 1 Interrupt priority level. PX1 IP.2 Defines External Interrupt priority level. PT0 IP.1 Defines the Timer 0 interrupt priority level. PX0 IP.0 Defines the External Interrupt 0 priority level. * User software should not write 1s to reserved bits. These bits may be used in future TEMIC C51 products to invoke new features. In that case, the reset or inactive value of the now bit will be 0, and its active value will be 1. MATRA MHS Rev. E (14 Jan. 97) 9 C51 Family IOCON : Input/Output Control Register (83C154 and 83C154D only) WDT T32 SERR IZC P3HZ P2HZ P1HZ ALF WDT T32 SERR IZC P3HZ P2HZ P1HZ ALF IOCON.7 Watch Dog Timer bit. Set when Timer 1 is overflow (TF = 1). The CPU is reset and the program is executed from address 0. IOCON.6 Timer 32 bits. The Timer 1 and Timer 0 are connected together to form a 32 bits Timer/Counter. If C/TO = 0, it's a Timer. If C/TO = 1, it's a counter. IOCON.5 Serial Port Reception Error flag. Set when an overrun on frame error is received. IOCON.4 Set/Cleared by software to select 100/10 K pull up resistance for Port 1, 2 and 3. IOCON.3 When Set, Port 3 becomes a tri-state input. When cleared, the pull-up resistance value is selected by IZC. IOCON.2 When Set, Port 2 becomes a tri-state input. When cleared, the pull-up resistance value is selected by IZC. IOCON.1 When Set, Port 1 becomes a tri-state input. When cleared, the pull-up resistance value is selected by IZC. IOCON.0 All Port tri-state. When Set and CPU in Power-Down mode, port 1, 2 and 3 are tri-state. TCON : Timer/Counter Control Register (Bit Addressable) TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TCON.7 TCON.6 TCON.5 TCON.4 TCON.3 TCON.2 TCON.1 TCON.0 Timer 1 overflow flag. Set by hardware when the Timer/Counter 1 overflows. Cleared by hardware as processor vectors to the interrupt service routine. Timer 1 run control bit. Set/cleared by software to turn Timer/Counter ON/OFF. Timer 0 overflow flag. Set by hardware when the Timer/Counter 0 overflows. Cleared by hardware as processor vectors to the service routine. Timer 0 run control bit. Set/cleared by software to turn Timer/Counter 0 ON/OFF. External Interrupt 1 edge flag. Set by hardware when External interrupt edge is detected. Cleared by hardware when interrupt is processed. Interrupt 1 type control bit. Set/cleared by software to specify falling edge/flow level triggered External Interrupt. External Interrupt 0 edge flag. Set by hardware when External Interrupt edge detected. Cleared by hardware when interrupt is processed. Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered External Interrupt. TMOD : Timer/Counter Mode Control Register (Not Bit Addressable) GATE C/T M1 M0 GATE C/T M1 M0 TIMER 1 TIMER 0 GATE C/T M1 M0 10 When TRx (in TCON) is set and GATE = 1, TIMER/COUNTERx will run only while INTx pin is high (hardware control). When GATE = 0, TIMER/COUNTERx will run only while TRx = 1 (software control). Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for Counter operation (input from Tx input pin). Mode selector bit (NOTE 1). Mode selector bit (NOTE 1). MATRA MHS Rev. E (14 Jan. 97) C51 Family Note 1 : M1 0 0 1 1 1 M0 0 1 0 1 1 OPERATING MODE 0 1 2 3 3 13 bit Timer 13-bit 16-bit Timer/Counter 8 bit Auto Reload Timer/Counter 8-bit Auto-Reload (Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits, TH0 is an 8-bit Timer and is controlled by Timer 1 control bits. (Timer 1) Ti Timer/Counter 1 stopped. (Ti /C t t d 2.5. Timer Set-up Tables 3 through 6 give some values for TMOD which can be used to set up Timer 0 in different modes. It is assumed that only one timer is being used at a time. It is desired to run Timers 0 and 1 simultaneously, in any mode, the value that in TMOD for Timer 0 must be ORed with the value shown for Timer 1 (Tables 5 and 6). For example, if it is desired to run Timer 0 in mode 1 GATE (external control) and Timer 1 in mode 2 COUNTER, then the value must be loaded into TMOD is 69H (09H from Table 3 ORed with 60H from Table 6). Moreover, it is assumed that the user, at this point, is not ready to turn the timers on and will do that a different point in the program by setting bit TRx (in TCON) to 1. Table 4. As a Counter TMOD MODE TIMER 0 FUNCTION INTERNAL EXTERNAL CONTROL CONTROL (NOTE 1) (NOTE 2) 04H 05H 06H 07H 0CH 0DH 0EH 0FH 0 1 2 3 13-bit Timer 16-bit Timer 8-bit Auto-Reload one 8-bit Timers 2.6. Timer/Counter 0 Table 3. As a Timer TMOD MODE TIMER 0 FUNCTION INTERNAL EXTERNAL CONTROL CONTROL (NOTE 1) (NOTE 2) 00H 01H 02H 03H 08H 09H 0AH 0BH 0 1 2 3 13-bit Timer 16-bit Timer 8-bit Auto-Reload Two 8-bit Timers Notes : 1. The Timer is turned ON/OFF by setting/clearing bit TR0 in the software. 2. The Timer is turned ON/OFF by the 1 to 0 transition on INT0 (P3.2) when TR0 = 1 (hardware control). MATRA MHS Rev. E (14 Jan. 97) 11 C51 Family 2.7. Timer/Counter 1 Table 5. As a Timer MODE TMOD MODE TIMER 0 FUNCTION 13-bit Timer 16-bit Timer 8-bit Auto-Reload does not run Table 6. As a Counter TMOD TIMER 0 FUNCTION 13-bit Timer 16-bit Timer 8-bit Auto-Reload not available INTERNAL EXTERNAL CONTROL CONTROL (NOTE 1) (NOTE 2) 00H 10H 20H 30H 80H 90H A0H B0H INTERNAL EXTERNAL CONTROL CONTROL (NOTE 1) (NOTE 2) 40H 50H 60H - C0H D0H E0H - 0 1 2 3 0 1 2 3 Notes : 1. The Timer is turned ON/OFF by setting/clearing bit TR1 in the software. 2. The Timer is turned ON/OFF by the 1 to 0 transition on INT1 (P3.2) when TR1 = 1 (hardware control). T2CON : Timer/Counter 2 Control register (Bit Addressable) (80C52, 83C154 and 83C154D only) TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 T2CON.7 Timer 2 overflow flag set by hardware and cleared by software. TF2 cannot be set when either RCLK = 1 or CLK = 1 EXF2 T2CON.6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX, and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. RCLK T2CON.5 Receive clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its receive clock in modes 1 & 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. TCLK T2CON.4 Transmit clock flag. When set, causes the Serial Port use Timer 2 overflow pulses for its transmit clock in modes 1 & 3, TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. EXEN2 T2CON.3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of negative transition on T2EX if Timer 2 is not being used to clock the Serial Port. EXEN2 = 0 causes Timer 2 to ignore events as T2EX. TR2 T2CON.2 Software START/STOP control for Timer 2. A logic 1 starts the Timer. T2CON.1 Timer or Counter select. C/T2 CP/RL2 T2CON.0 Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When cleared, Auto-Reloads will occur either with Timer2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the Timer is forced to Auto-Reload on Timer 2 overflow. TF2 2.8. Timer/Counter 2 Set-up Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set, separately, to turn the Timer on. 12 MATRA MHS Rev. E (14 Jan. 97) C51 Family Table 7. As a Timer T2CON MODE INTERNAL CONTROL (NOTE 1) 00H 01H Table 8. As a Counter T2CON MODE INTERNAL CONTROL (NOTE 1) 02H 03H EXTERNAL CONTROL (NOTE 2) 08H 09H EXTERNAL CONTROL (NOTE 2) 0AH 0BH 16-bit Auto-Reload 16-bit Capture BAUD rate generator receive & t a s t sa e ece ve transmit same baud rate receive only i l t it l transmit only 16-bit Auto-Reload 16-bit Capture 34H 24H 24 14H 36H 26H 26 16H Notes : 1. Capture/Reload occurs only Timer/Counter overflow. 2. Capture/Reload occurs on Timer/Counter overflow and a 1 to 0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generating mode. SCON : Serial Port Control Register (Bit Addressable) SM0 SM1 SM2 REN TN8 RB8 TI RI SM0 SM1 SM2 SCON.7 SCON.6 SCON.5 REN TB8 RB8 TI RI SCON.4 SCON.3 SCON.2 SCON.1 SCON.0 Serial Port mode specifier (NOTE 1). Serial Port mode specifier (NOTE 1). Enables the multiprocessor communication feature in mode 2 & 3. In mode 2 or 3, if SM2 is set to 1 then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be 0 (See table 9). Set/Cleared by software to Enable/Disable reception. The 9th bit that will be transmitted in modes 2 & 3. Set/Cleared by software. In modes 2 & 3, is the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In mode 0, RB8 is not used. Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes. Must be cleared by software. Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or half way through the stop bit time in the other modes (except see SM2). Must be cleared by software. Note 1 : SM0 0 0 1 1 SM1 0 1 0 1 MODE 0 1 2 3 DESCRIPTION SHIFT REGISTER 8 bit UART 8 bit UART 8 bit UART BAUD RATE Fosc./12 Variable Fosc./64 OR Fosc./32 Variable MATRA MHS Rev. E (14 Jan. 97) 13 C51 Family 2.9. Serial Port Set-Up Table 9. MODE 0 1 2 3 0 1 2 3 TH1 + 256 - K Oscillator freq. 384 baud rate SCON 10H 50H 90H D0H NA 70H B0H FOH SM2 VARIATION Single Processor Environment (SM2 = 0) TH1 must be integer value. Rounding off TH1 to the nearest integer may not produce the desired baud rate. In this case, the user may have to choose another crystal frequency. Since the PCON register is not bit addressable, one way to set the bit is logical ORing the PCON register (ie, ORL PCON, #80H). The address of PCON is 87H. Multiprocessor Environment (SM2 = 1) 2.12. Using Timer/Counter 2 to Generate Baud Rates For this purpose, Timer 2 must be used in the baud rate generating mode. Refer to Timer 2 Setup Table in this chapter. If Timer 2 is being clocked through pin T2 (P1.0) the baud rate is : Baud Rate + Timer 2 Overflow Rate 16 And if it being clocked internally the baud rate is : Baud Rate + 32 Osc. Freq [65536 - (RCAP2H, RCAP2L)] 2.10. Generating Baud Rates Serial Port in Mode 0 : Mode 0 has a fixed baud rate which is 1/12 of oscillator frequency. To run serial port in this mode none of the Timer/Counters need to be set up. Only the SCON register needs to be defined. Baud Rate + Osc Freq 12 To obtain the reload value for RCAP2H and RCAP2L the above equation can be written as : RCAP2H, RCAP2L + 65536 - 32 Osc. Freq Baud rate Serial Port in Mode 1 : Mode 1 has a variable baud rate. The baud rate can be generated by either Timer 1 or Timer 2 (80C52, 83C154 and 83C154D only). 2.13. Serial Port in Mode 2 The baud rate is fixed in this mode and 1/32 or 1/64 of the oscillator frequency depending on the value of the SMOD bit in the PCON register. In this mode none of the Timers are used and the clock comes from the internal phase 2 clock. SMOD = 1, Baud Rate = 1/32 Osc Freq. SMOD = 0, Baud Rate = 1/64 Osc Freq. To set the SMOD bit : ORL PCON, #80H. The address of PCON is 87H. 2.11. Using Timer/Counter 1 to Generate Baud Rates For this purpose, Timer 1 is used in mode 2 (Auto-Reload). Refer to Timer Setup section of this chapter. K Oscillator freq. Baud Rate + 32 12 [256-(TH1)] if SMOD = 0, then K = 1. If SMOD = 1, then K = 2. (SMOD is the PCON register). Most of the time the user knows the baud rate and needs to know the reload value for TH1. Therefore, the equation to calculate TH1 can be written as : 2.14. Serial Port in Mode 3 The baud rate in mode 3 is variable and sets up exactly the same as in mode 1. 14 MATRA MHS Rev. E (14 Jan. 97) C51 Family Table 10. TEMIC C51 Instruction Set Interrupt Response time : Refer to Hardware Description Chapter. Instructions that Affect Flag Settings (1) INSTRUC. C ADD ADDC SUBB MUL DIV DA RRC RLC SETB C X X X 0 0 X X X 1 FLAG OV X X X X X AC X X X INSTRUC. C CLRC CPL C ANL C, bit ANL C,/ bit ORL C, bit ORL C, bit MOV C, bit CJNE O X X X FLAG OV AC X X X X (1) note that operations on SFR byte address 208 or bit addresses 209-215 (i.e., the PSW or bits in the PSW) will also affect flag settings. Note on instruction set and addressing modes : Rn direct @Ri # data # data 16 addr 16 addr 11 rel bit - Register R7-R0 of the currently selected Register Bank - 8-bit internal data location's address. This could be an Internal Data RAM location (0-127) or a SFR (i.e., I/O port, control register, status register, etc. (128-255)). - 8-bit internal data RAM location (0-255) addresses indirectly through register R1 or R0. - 8-bit constant included in instruction. - 16-bit constant included in instruction. - 16-bit destination address. Used by LCALL & LJMP. Abranch can be anywhere within the 64K-byte Program memory address space - 11-bit destination address. Used by ACALL & AJMP. The branch will be within the same 2K-byte page of program memory as the first byte of the following instruction - Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditionnal jumps. Range is -128 to + 127 bytes relative to first byte of the following instruction. - Direct Addressed bit in internal Data RAM or special Function Register. MATRA MHS Rev. E (14 Jan. 97) 15 C51 Family MNEMONIC DESCRIPTION BYTE OSCIL. PERIOD MNEMONIC DESCRIPTION BYTE OSCIL. PERIOD ARITHMETIC OPERATIONS ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDCA, Rn ADDCA, direct ADDCA, @Ri ADDCA, #data SUBB A, Rn SUBB A, direct SUBB A, @Ri SUBB A, #data INC A INC Rn INC direct INC @Ri DEC A DEC Rn DEC direct DEC @Ri INC DPTR MUL AB DIV AB DA A Add register to Accumulator Add direct byte to Accumulator Add indirect RAM to Accumulator Add immediate data to Accumulator Add register to Accumulator with Carry Add direct byte to Accumulator with Carry Add indirect RAM to Accumulator with Carry Add immediate data to Acc with Carry Subtract Register from Acc with borrow Subtract direct byte from Acc with borrow Subtract indirect RAM from ACC with borrow Subtract immediate data from Acc with borrow Increment Accumulator Increment register Increment direct byte Increment direct RAM Decrement Accumulator Decrement Register Decrement direct byte Decrement indirect RAM Increment Data Pointer Multiply A & B Divide A by B Decimal Adjust Accumulator 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 12 12 12 12 12 12 ORL A, Rn 12 ORL A, direct 12 ORL A, @Ri 12 ORL A, #data 12 ORL direct, A 12 12 12 12 12 12 12 12 12 12 24 48 48 12 CLR A CPL A RL A RLC A RR A RRC A SWAP A XRL direct, #data XRL direct, A XRL A, @Ri XRL A, #data ORL direct, #data XRL A, Rn XRL A, direct LOGICAL OPERATIONS ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data AND Register to Accumulator AND direct byte to Accumulator AND indirect RAM to Accumulator AND immediate data to Accumulator AND Accumulator to direct byte AND immediate data to direct byte OR register to Accumulator OR direct byte to Accumulator OR indirect RAM to Accumulator OR immediate data to Accumulator OR Accumulator to direct byte OR immediate data to direct byte Exclusive-OR register to Accumulator Exclusive-OR direct byte to accumulator Exclusive-OR indirect RAM to Accumulator Exclusive-OR immediate data to Accumulator Exclusive-OR Accumulator to direct byte Exclusive-OR immediate data to direct byte Clear Accumulator Complement Accumulator Rotate Accumulator Left Rotate Accumulator Left through the Carry Rotate Accumulator Right Rotate Accumulator Right through the Carry Swap nibbles within the Accumulator 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 12 12 12 12 12 24 12 12 12 12 12 24 12 12 12 12 2 12 3 24 1 1 1 1 1 1 1 12 12 12 12 12 12 12 16 MATRA MHS Rev. E (14 Jan. 97) C51 Family MNEMONIC DATA TRANSFERT MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data MOV DPTR, #data16 MOVCA @A+DPTR MOVCA @A+PC MOVXA, @Ri MOVXA, @DPTR MOVX@Ri, A MOVX@DPTR, A PUSH direct POP direct Move Register to Accumulator Move direct byte to Accumulator Move indirect RAM to Accumulator Move immediate data to Accumulator Move Accumulator to register Move direct byte to register Move immediate data to register Move Accumulator to direct byte Move register to direct byte Move direct byte to direct Move indirect RAM to direct byte Move immediate data to direct byte Move Accumulator to indirect RAM Move direct by to indirect RAM Move immediate data to indirect RAM Load Data Pointer with a 16-bit constant Move Code byte relative to DPTR to Acc Move Code byte relative to PC to Acc Move External RAM (8-bit addr) to Acc Move External RAM (16-bit addr) to Acc Move Acc to External RAM (8-bit addr) Move Acc to External RAM (16-bit addr) Push direct byte only stack Pop direct byte from stack 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 12 12 12 12 12 24 CLR bit 12 12 24 24 24 ORL C, bit 24 12 24 12 24 24 24 24 24 24 24 24 24 ORL C, /bit MOV C, bit MOV bit, C JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, /bit Clear direct bit Set Carry Set direct bit Complement Carry Complement direct bit AND direct bit to Carry AND complement of direct bit to Carry OR direct bit to Carry OR complement of direct bit to Carry Move direct bit to Carry Move Carry to direct bit Jump if Carry is set Jump if Carry not set Jump if direct Bit is set Jump if direct Bit is Not set Jump if direct Bit is set & clear bit 2 1 2 1 2 2 2 2 2 2 2 2 2 3 3 3 12 12 12 12 12 24 24 24 24 12 24 24 24 24 24 24 DESCRIPTION BYTE OSCIL. PERIOD MNEMONIC DESCRIPTION BYTE OSCIL. PERIOD DATA TRANSFERT (continued) XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri Exchange register with Accumulator Exchange direct byte with Accumulator Exchange indirect RAM with Accumulator Exchange loworder Digit indirect RAM with Acc 1 2 1 1 12 12 12 12 BOOLEAN VARIABLE MANIPULATION CLR C Clear Carry 1 12 MATRA MHS Rev. E (14 Jan. 97) 17 C51 Family MNEMONIC DESCRIPTION BYTE OSCIL. PERIOD CNJE A, direct, rel Compare direct byte to Acc and Jump if Not Equal Compare immediate to Acc and Jump if Not Equal 3 24 PROGRAM BRANCHING ACALLK addr11 LCALL addr16 RET RETI AJMPaddr11 LJMPaddr16 SJMP rel JMP @A+DPTR JZ rel JNZ rel Absolute Subroutine Call Long Subroutine Call Return from Subroutine Return from interrupt Absolute Jump Long Jump Short Jump (relative addr) Jump direct relative to the DPTR Jump if Accumulator is zero Jump if Accumulator is not Zero 2 3 1 1 2 3 2 1 2 2 24 24 24 24 24 24 24 24 24 24 DJNZ Rn, rel DJNZ direct, rel NOP CJNE Rn, #data, rel Compare immediate to register and Jump if Not Equal CJNE @Ri, #data, rel Compare immediate to indirect and Jump if Not Equal Decrement register and Jump if Not Zero Decrement direct byte and Jump if Not Zero No Operation 3 24 CJNE A, #data, rel 3 24 3 24 2 3 1 24 24 12 18 MATRA MHS Rev. E (14 Jan. 97) C51 Family 3. Instruction Definitions ACALL addr 11 Function : Description : Absolute Call ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the Stack Pointer twice. The destination address is obtained by successively concatenating the five high-order bits of the incremented PC, opcode bits 7-5, and the second byte of the instruction. The subroutine called must therefore start within the same 2 K block of the program memory as the first byte of the instruction following ACALL. No flags are affected. Initially SP equals 07H. The labs " SUBRTN " is at program memory location 0345 H. After executing the instruction, ACALL SUBRTN at location 0123H, SP will contain 09H, internal RAM locations 08H and 09H will contain 25H and 01H, respectively, and the PC will contain 0345H. 2 2 a10 a9 a8 1 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0 Example : Bytes : Cycles : Encoding : Operation : ACALL (PC) (PC) + 2 (SP) (SP) + 1 [(SP)] (PC7-0) (SP) (SP) + 1 [(SP)] (PC15-8) (PC10-0) page address MATRA MHS Rev. E (14 Jan. 97) 19 C51 Family ADD a, Function : Description : Add ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occured. OV is set there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6 ; otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands. Four source operand addressing modes are allowed : register, direct, register-indirect, or immediate. The Accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B). The instruction, ADD A, R0 will leave 6DH (01101101B) in the Accumulator with the AC flag cleared and both the carry flag and OV set to 1. 1 1 0 0 1 0 1 r r r Example : ADD A, Rn Byte : Cycle : Encoding : Operation : ADD A, direct Bytes : Cycle : Encoding : Operation : ADD A, @RI Byte : Cycle : Encoding : Operation : ADD A, # data Bytes : Cycle : Encoding : Operation : ADD (A) (A) + (Rn) 2 1 0 0 1 0 0 1 0 1 direct address ADD (A) (A) + (direct) 1 1 0 0 1 0 1 1 1 i ADD (A) (A) + ((RI)) 2 1 0 0 1 0 0 1 0 0 Immediate data ADD (A) (A) + # data 20 MATRA MHS Rev. E (14 Jan. 97) C51 Family ADDC A, Function : Description : Add with Carry ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator contents, leaving the result in the Accumulator. The carry and auxiliary-carry or bit flags are set, respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occured. OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of bit 6 ; otherwise OV is cleared. When adding signed intergers, OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands. Four source operand addressing mode are allowed ; register, direct, register-indirect, or immediate. The Accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B) with the carry flag set. The instruction, ADDC A, R0 will leave 6EH (01101110B) in the Accumulator with AC cleared and both the Carry flag and OV set to 1. 1 1 0 0 1 1 1 r r r Example : ADDC A, RN Byte : Cycle : Encoding : Operation : ADDC (A) (A) + (C) + (Rn) ADDC A, direct Bytes : 2 Cycle : 1 Encoding : Operation : 0 0 1 1 0 1 0 1 direct address ADDC (A) (A) + (C) + (direct) ADDC A, @ RI Byte : 1 Cycle : 1 Encoding : Operation : 0 0 1 1 0 1 1 i ADDC (A) (A) + (C) + ((Ri)) ADDC A, #data Bytes : 2 Cycle : 1 Encoding : Operation : 0 0 1 1 0 1 0 0 immediate data ADDC (A) (A) + (C) + # data MATRA MHS Rev. E (14 Jan. 97) 21 C51 Family AJMP addr11 Function : Description : Absolute Jump AJMP transfers program execution to the indicated address, which is formed at run-time by concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits 7-5, and the second byte of the instruction. The destination must therefore be within the same 2 K block of program memory as the first byte of the instruction following AJMP. The label " JMPADR " is at program memory location 0123H. The instruction, AJMP JMPADR is a location 0345H and will load the PC with 0123H. Example : ADD A, direct Bytes : 2 Cycles : 2 Encoding : Operation : a10 a9 a8 0 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0 AJMP (PC) (PC) + 2 (PC10-0) page address ANL Function : Description : Logical-AND for byte variables ANL performs the bitwise logical-AND operation between the variables indicated and stores the results in the destination variable. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing ; when the destination is a direct address, the source can be the Accumulator or immediate data. Note : When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. If the Accumulator holds 0C3H (11000011B) and register 0 holds 55H (01010101B) then the instruction, ANL A, R0 will leave 41H (01000001B) in the Accumulator. When the destination is a directly addressed byte, this instruction will clear combinations of bits in any RAM location or hardware register. The mask byte determining the pattern of bits to be cleared would either be a constant contained in the instruction or a value computed in the Accumulator at run-time. The instruction, ANL P1, #01110011B will clear bits 7, 3, and 2 of output port 1. 1 1 0 1 0 1 1 r r r Example : ANL A, Rn Bytes : Cycles : Encoding : Operation : ANL A, direct Bytes : Cycles : Encoding : Operation : ANL (A) (A) (Rn) 2 1 0 1 0 1 0 1 0 1 direct address ANL (A) (A) (direct) MATRA MHS Rev. E (14 Jan. 97) 22 C51 Family ANL A, @ RI Byte : Cycle : Encoding : Operation : 1 1 0 1 0 1 0 1 1 i ANL (A) (A) ((Ri)) ANL A, #DATA Bytes : 2 Cycle : 1 Encoding : Operation : ANL direct, A Bytes : Cycle : Encoding : Operation : 0 1 0 1 0 1 0 0 immediate data ANL (A) (A) # data 2 1 0 1 0 1 0 0 1 0 direct address ANL (direct) (direct) (A) ANL direct, # data Bytes : 3 Cycles : 2 Encoding : Operation : 0 1 0 1 0 0 1 1 direct address immediate data ANL (direct) (direct) # data MATRA MHS Rev. E (14 Jan. 97) 23 C51 Family ANL C, Function : Description : Logical-AND for bit variables If the Boolean value of the source bit is logical 0 then clear the carry flag ; otherwise leave the carry flag in its current state. A slash (" / ") preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected. Only direct addressing is allowed for the source operand. Set the carry flag if, P1.0 = 1, ACC.7 = 1, and OV = 0 : MOV C, P1.0 ; LOAD CARRY WITH INPUT PIN STATE ANL C, ACC.7 ; AND CARRY WITH ACCUM. BIT 7 ANL C,/OV ; AND WITH INVERSE OF OVERFLOW FLAG 2 2 1 0 0 0 0 0 1 0 bit address Example : ANL C, bit Bytes : Cycles : Encoding : Operation : ANL C, /bit Bytes : Cycles : Encoding : Operation : ANL (C) (C) (bit) 2 2 1 0 1 1 0 0 0 0 bit address ANL (C) (C) (bit) CJNE Function : Description : Compare and Jump if Not Equal CJNE compares the magnitudes of the first two operands, and branches if their values are not equal. The branch destination is computed by adding the signed relative-displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction. The carry flag is set if the unsigned integer value of Example : 24 C51 Family CJNE A, direct, rel Bytes : 3 Cycles : 2 (PC) (PC) + 3 IF (A) <> (direct) THEN (PC) (PC) + relative offset IF (A) < (direct) THEN (C) 1 ELSE (C) 0 CJNE A, # data, rel Bytes : 3 Cycles : 2 (PC) (PC) + 3 IF (A) <> (data) THEN (PC) (PC) + relative offset IF (A) < data THEN (C) 1 ELSE (C) 0 CJNE Rn, # data, rel Bytes : 3 Cycles : 2 Encoding : Operation : 1 0 1 1 1 r r r immediate data rel. address Encoding : Operation : 1 0 1 1 0 1 0 1 direct address rel. address Encoding : Operation : 1 0 1 1 0 1 0 0 immediate data rel. address (PC) (PC) + 3 IF (Rn) <> data THEN (PC) (PC) + relative offset IF (Rn) < data THEN (C) 1 ELSE (C) 0 CJNE @Ri, # data, rel Bytes : 3 Cycles : 2 Encoding : Operation : 1 0 1 1 0 1 1 i immediate data rel. address (PC) (PC) + 3 IF (Ri) <> data THEN (PC) (PC) + relative offset IF ((Ri)) < data THEN (C) 1 ELSE (C) 0 25 MATRA MHS Rev. E (14 Jan. 97) C51 Family CLR A Function : Description : Example : Clear Accumulator The Accumulator is cleared (all bits set on zero). No flags are affected. The Accumulator contains 5CH (01011100B). The instruction, CLRA Will leave the Accumulator set to 00H (00000000B). 1 1 1 1 1 1 0 1 0 0 Bytes : Cycles : Encoding : Operation : CLR (A) 0 CLR bit Function : Description : Example : Clear bit The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on the carry flag or any directly addressable bit. Port 1 has previously been written with 5DH (01011101B). The instruction, CLR P1.2 will leave the port set to 59H (01011001B). 1 1 1 1 0 0 0 0 1 1 CLR C Bytes : Cycles : Encoding : Operation : CLR bit Bytes : Cycles : Encoding : Operation : CLR (C) 0 2 1 1 1 0 0 0 0 1 0 bit address CLR (bit) 0 CPLA Function : Descritpion : Example : Complement Accumulator Each bit of the Accumulator is logically complemented (one's complement). Bits which previously contained a one are changed to a zero and vice-versa. No flags are affected. The accumulator contains 5CH (01011100B). The instruction, CPLA will leave the Accumulator set to 0A3H (10100011B). 1 1 1 1 1 1 0 1 0 0 Bytes : Cycles : Encoding : Operation : CPL (A) (A) MATRA MHS Rev. E (14 Jan. 97) 26 C51 Family CPL bit Function : Description : Complement bit The bit variable specified is complemented. A bit which had been a one is changed to zero and vice-versa. No other flags are affected. CLR can operate on the carry or any directly addressable bit. Note : When this instruction is used to modify an output pin, the value used as the original data will be read from the output data latch, not the input pin. Port 1 has previously been written with 5BH (01011101B). The instruction sequence. CPL P1.1 CPL P1.2 will leave the port set to 5BH (01011011B). Example : CPL C Bytes : Cycles : Encoding : Operation : CPL bit Bytes : Cycles : Encoding : Operation : 1 1 1 0 1 1 0 0 1 1 CPL (C) (C) 2 1 1 0 1 1 0 0 1 0 bit address CPL (bit) (bit) MATRA MHS Rev. E (14 Jan. 97) 27 C51 Family DA A Function : Description : Decimal-adjust Accumulator for Addition DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two variables (each in packed-BCD format), producing two four-bit digits, Any ADD or ADDC instruction may have been used to perform the addition. If Accumulator bits 3-0 are greater than nine (xxxx1010-xxxx1111), or if the AC flag is one, six is added to the Accumulator producing the proper BCD digit in the low-order nibble. This internal addition would set the carry flag if a carry-out of the low-order four-bit field propagated through all high-order bits, but it would not clear the carry flag otherwise. If the carry flag is now set, or if the four high-order bits now exceed nine (1010xxxx -111xxxx), these high-order bits are incremented by six, producing the proper BCD digit in the high-order nibble. Again, this would set the carry flag if there was a carry-out of the high-order bits, but wouldn't clear the carry. The carry flag thus indicates if the sum of the original two BCD variables is greater than 100, allowing multiple precision decimal. OV is not affected. All of this occurs during the one instruction cycle. Essentially, this instruction performs the decimal conversion by adding 00H, 06H, 60H, or 66H to the Accumulator, depending on initial Accumulator and PSW conditions. Note : DA A cannot simply convert a hexadecimal number in the Accumulator to BCD notation, nor does DA A apply to decimal substraction. The Accumulator holds the value 56H (01010110B) representing the packed BCD digits of the decimal number 56. Register 3 contains the value 67H (01100111B) representing the packed BCD digits of the decimal number 67. The carry flag is set. The instruction sequence. ADDCA, R3 DA A will first perform a standard twos-complement binary addition, resulting in the value 0BEH (10111110), in the Accumulator. The carry and auxillary carry flags will be cleared. The decimal Adjust instruction will then after the Accumulator to the value 24H (00100100B) indicating the packed BCD digits of the decimal number 24, the low-order two digits of the decimal sum of 56,67, and the carry-in. The carry flag will set by the Decimal Adjust instruction, indicating that a decimal overflow occured. The true sum 56,67, and 1 is 124. BCD variables can be incremented or decremented by adding 01H or 99H. If the Accumulator initially holds 30H (representing the digits of 30 decimal), then the instruction sequence, ADD A, #99H DA A will leave the carry set and 29H in the Accumulator, since 30 + 99 = 129. The low-order byte of the sum can be interpreted to mean 30 -1 = 29. 1 1 1 1 0 1 0 1 0 0 Example : Bytes : Cycles : Encoding : Operation : DA - contents of Accumulator are BCD IF [[(A3 - 0) > 9] V [(AC) = 1]] THEN (A3 - 0) (A3 - 0) + 6 AND IF [[(A7 - 4) > 9] V [(C) = 1]] THEN (A7 - 4) (A7 - 4) + 6 28 MATRA MHS Rev. E (14 Jan. 97) C51 Family DEC byte Function : Description : Decrement The variable indicated is decremented by 1. An original value of 00H will underflow to 0FFH. No flags are affected. Four operand addressing modes are allowed : accumulator, register, direct, or register-indirect. Note : When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Register 0 contains 7FH (01111111B). Internal RAM locations 7 EH and 7FH contain 00H and 40H, respectively. The instruction sequence. DEC @ R0 DEC R0 DEC @ R0 will leave register 0 set to 7EH internal RAM locations 7EH and 7FH to 0FFH and 3FH. Example : DEC A Bytes : Cycles : Encoding : Operation : DEC Rn Bytes : Cycles : Encoding : Operation : DEC direct Bytes : Cycles : Encoding : Operation : DEC @ RI Bytes : Cycles : Encoding : Operation : 1 1 0 0 0 1 0 1 0 0 DEC (A) (A) - 1 1 1 0 0 0 1 1 r r r DEC (Rn) (Rn) - 1 2 1 0 0 0 1 0 1 0 1 direct address DEC (direct) (direct) - 1 1 1 0 0 0 1 0 1 1 i DEC ((Ri)) ((Ri)) - 1 MATRA MHS Rev. E (14 Jan. 97) 29 C51 Family DIV AB Function : Description : Divide DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit integer in register B. The Accumulator receives the integer part of the quotient ; register B receives the integer remainder. The carry and OV flags will be cleared. Exception : If B had originally contained 00H ; the values returned in the Accumulator and B-register will be undefined and the overflow flag will be set. The carry flag is cleared in any case. The Accumulator contains 251 (0FBH or 11111011B) and B contains 18 (12H or 00010010B). The instruction, DIV AB will leave 13 in the Accumulator (0DH or 00001101B) and the value 17 (11H or 00010001B) in B, since 251 = (13 x 18) + 17. Carry and OV will both be cleared. 1 4 1 0 0 0 0 1 0 0 Example : Bytes : Cycles : Encoding : Operation : DIV (A)15 - 8 (A)/(B) (B)7 - 0 DJNZ Function : Description : Decrement and Jump if Not Zero DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original value of 00H will underflow to 0FFH. No flags are affected. The branch destination would be computed by adding the signed relative-displacement value in the last instruction byte to the PC, after incrementing the PC to the first byte of the following instruction. The location decremented may be a register or directly addressed byte. Note : When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Internal RAM locations 40H, 50H, and 60H contain the values 01H, 70H, and 15H, respectively. the instruction sequence, DJNZ 40H, LABEL_1 DJNZ 50H, LABEL_2 DJNZ 60H, LABEL_3 will cause a jump to the instruction at label LABEL2 with the values 00H, 6FH, and 15H in the three RAM locations. The first jump was not taken because the result was zero. This instruction provides a simple way of executing a program loop a given number of times, or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction. The instruction sequence, MOV R2, #8 TOGGLE : CPL P1.7 DJNZ R2, TOGGLE will toggle P1.7 eight times, causing four output pulses to appear at bit 7 of output Port 1. Each pulse will last three machine cycles ; two for DJNZ and one to after the pin. Example : 30 MATRA MHS Rev. E (14 Jan. 97) C51 Family DJNZ Rn, rel Bytes : Cycles : Encoding : Operation : 2 2 1 1 0 1 1 r r r rel. address DJNZ (PC) (PC) + 2 (Rn) (Rn) - 1 IF (RN) > 0 or (Rn) < 0 THEN (PC) (PC) + rel DJNZ direct, rel Bytes : 3 Cycles : 2 Encoding : Operation : 1 1 0 1 0 1 0 1 direct address rel. address DJNZ (PC) (PC) + 2 (direct) (direct) - 1 IF (direct) > 0 or (direct) < 0 THEN (PC) (PC) + rel INC Function : Description : Increment INC increments the indicated variable by 1. An original value of 0FFH will overflow to 00H. No flags are affected. There addressing modes are allowed : register, direct, or register-indirect. Note : When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Register 0 contains 7EH (011111110B). Internal locations 7EH and 7FH contain 0FFH and 40H, respectively. The instruction sequence, INC @R0 INC R0 INC @R0 will leave register 0 set to 7FH and internal RAM locations 7EH and 7FH holding (respectively) 00H and 41H. 1 1 0 0 0 0 0 1 0 0 Example : INC A Bytes : Cycles : Encoding : Operation : INC Rn Bytes : Cycles : Encoding : Operation : INC (A) (A) + 1 1 1 0 0 0 0 1 r r r INC (Rn) (Rn) + 1 31 MATRA MHS Rev. E (14 Jan. 97) C51 Family INC direct Bytes : Cycles : Encoding : Operation : INC @ RI Bytes : Cycles : Encoding : Operation : 2 1 0 0 0 0 0 1 0 1 direct address INC (direct) (direct) + 1 1 1 0 0 0 0 0 1 1 i INC ((Ri)) ((Ri)) + 1 INC DPTR Function : Description : Increment Data Pointer Increment the 16-bit data pointer by 1.A 16-bit increment (modulo 216) is performed ; an overflow of the low-order byte of the data pointer (DPL) from 0FFH to 00H will increment the high-order byte (DPH). No flags are affected. This is the only 16-bit register which can be incremented. Registers DPH and DPL contain 12H and 0FEH, respectively. The instruction sequence, INC DPTR INC DPTR INC DPTR will change DPH and DPL to 13H and 01H. 1 2 1 0 1 0 0 0 1 1 Example : Bytes : Cycles : Encoding : Operation : INC (DPTR) (DPTR) + 1 JB bit, rel Function : Descritpion : Jump if Bit set If the indicated bit is a one, jump to the address indicated ; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected. Note : When this instruction is used to test an output pin, the value used as the original data will be read from the output data latch, not the input pin. The data present at input port 1 is 11001010B. The Accumulator holds 56 (01010110B). The instruction sequence. JB P1.2, LABEL 1 JB ACC.2, LABEL 2 will cause program execution to branch to the instruction at label LABEL 2. Example : 32 MATRA MHS Rev. E (14 Jan. 97) C51 Family Bytes : Cycles : Encoding : Operation : 3 2 0 0 1 0 0 0 0 0 bit address rel. address JB (PC) (PC) + 3 IF (bit) = 1 THEN (PC) (PC) + rel Jump if Bit is set and Clear bit If the indicated bit is a one, branch to the address indicated ; otherwise proceed with the next instruction. The bit will not be cleared if it is already a zero. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. No flags are affected. Note : When this instruction is used to test an output pin, the value used as the original data will be read from the output data latch, not the input pin. The Accumulator holds 56H (01010110B). The instruction sequence, JBC ACC.3, LABEL 1 JBC ACC.2, LABEL 2 will cause program execution to continue at the instruction identified by the label LABEL2, with the Accumulator modified to 52H (01010010B). 3 2 0 0 0 1 0 0 0 0 bit address rel. address JBC bit, rel Function : Description : Example : Bytes : Cycles : Encoding : Operation : JBC (PC) (PC) + 3 IF (bit) = 1 THEN (bit) 0 (PC) (PC) + rel Jump if Carry is set If the carry flag is set, branch to the address indicated ; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. No flags are affected. The carry flag is cleared. The instruction sequence, JC LABEL 1 CPL C JC LABEL 2 will set the carry and cause program execution to continue at the instruction identified by the label LABEL2. 2 2 0 1 0 0 0 0 0 0 rel. address JC rel Function : Description : Example : Bytes : Cycles : Encoding : Operation : JC (PC) (PC) + 2 IF (C) = 1 THEN (PC) (PC) + rel 33 MATRA MHS Rev. E (14 Jan. 97) C51 Family JMP @A + DPTR Function : Description : Jump indirect Add the eight-bit unsigned contents of the Accumulator with the sixteen-bit data pointer, and load the resulting sum to the program counter. This will be the address for subsequent instruction fetches. Sixteen-bit addition is performed (modulo 216) : a carry-out from the low-order eight bits propagates through the higher-order bits. Neither the Accumulator nor the Data Pointer is altered. No flags are affected. An even number from 0 to 6 is in the Accumulator. The following sequence of instructions will branch to one of four AJMP instructions in a jump table starting at JMP-TBL : MOV DPTR, #JMP_TBL JMP @ A + DPTR JMP_TBL : AJMP LABEL0 AJMP LABEL1 AJMP LABEL2 AJMP LABEL3 If the Accumulator equals 04H when starting this sequence, execution will jump to label LABEL2. Remembers that AJMP is a two-byte instruction, so the jump instructions start at every other address. 1 2 0 1 1 1 0 0 1 1 Example : Bytes : Cycles : Encoding : Operation : JMP (PC) (A) + (DPTR) JNB bit, rel Function : Description : Jump if Bit not set If the indicated bit is a zero, branch to the indicated address ; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected. The data present at input port 1 is 11001010B. The Accumulator holds 56H (01010110B). The instruction sequence, JNB P1.3, LABEL1 JNB ACC3, LABEL2 will cause program execution to continue at the instruction at label LABEL2. 3 2 0 0 1 1 0 0 0 0 bit address rel. address Example : Bytes : Cycles : Encoding : Operation : JNB (PC) (PC) + 3 IF (bit) = 0 THEN (PC) (PC) + rel 34 MATRA MHS Rev. E (14 Jan. 97) C51 Family JNC rel Function : Description : Jump if Carry not set If the carry flag is a zero, branch to the address indicated ; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice to point to the next instruction. The carry flag is not modified. The carry flag is set. The instruction sequence, JNC LABEL1 CPLC JNC LABEL2 will clear the carry and cause program execution to continue at the instruction identified by the label LABEL2. 2 2 0 1 0 1 0 0 0 0 rel. address Example : Bytes : Cycles : Encoding : Operation : JNC (PC) (PC) + 2 IF (C) = 0 THEN (PC) (PC) + rel JNZ rel Function : Description : Jump if Accumulator Not Zero If any bit of the Accumulator is a one, branch to the indicated address ; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are affected. The Accumulator originally holds 00H. The instruction sequence, JNZ LABEL1 INC A JNZ LABEL2 will set the Accumulator to 01H and continue at label LABEL2. 2 2 0 1 1 1 0 0 0 0 rel. address Example : Bytes : Cycles : Encoding : Operation : JNZ (PC) (PC) + 2 IF (A) 0 THEN (PC) (PC) + rel MATRA MHS Rev. E (14 Jan. 97) 35 C51 Family JZ rel Function : Description : Jump if Accumulator Zero If all bits of the Accumulator are zero, branch to the address indicated ; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are affected. The Accumulator originally contains 01H. The instruction sequence. JZ LABEL1 DEC A JZ LABEL2 will change the Accumulator to 00H and cause program execution at the instruction identified by the label LABEL2. 2 2 0 1 1 0 0 0 0 0 rel. address Example : Bytes : Cycles : Encoding : Operation : JZ (PC) (PC) + 2 IF (A) = 0 THEN (PC) (PC) + rel LCALL addr16 Function : Description : Long call LCALL calls a subroutine located at the indicated address. The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing the Stack Pointer by two. The high-order and low-order bytes of the PC are then loaded, respectively, with the second and third bytes of the LCALL instruction. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 64K-byte program memory address space. No flags are affected. Initially the Stack Pointer equals 07H. The label " SUBRTN " is assigned to program memory location 1234H. After executing the instruction, LCALL SUBRTN at location 0123H, the Stack Pointer will contain 09H, internal RAM locations 08H and 09H will contain 26H and 01H, and the PC will contain 1235H. 3 2 0 0 0 1 0 0 1 0 addr15-addr8 addr7-addr0 Example : Bytes : Cycles : Encoding : Operation : LCALL (PC) (PC) + 3 (SP) (SP) + 1 ((SP)) (PC7-0) (SP) (SP) + 1 ((SP)) (SP15 - 8) (PC) addr15 - 0 36 MATRA MHS Rev. E (14 Jan. 97) C51 Family LJMP addr16 Function : Description : Long Jump LJMP causes an unconditional branch to the indicated address, by loading the high-order and low-order bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore be anywhere in the full 64K program memory address space. No flags are affected. The label " JMPADR " is assigned to the instruction at program memory location 1234H. The instruction, LJMP JMPADR at location 0123H will load the program counter with 1234H. 3 2 0 0 0 0 0 0 1 0 addr15-addr8 addr7-addr0 Example : Bytes : Cycles : Encoding : Operation : LJMP (PC) addr15-0 MOV Function : Description : Move byte variable The byte variable indicated the second operand is copied into the location specified by the first operand. The source byte is not affected. No other register or flag is affected. This is by far the most flexible operation. Fifteen combinaisons of source and destination addressing modes are allowed. Internal RAM location 30H holds 40H. The value of RAM location 40H is 10H. The data present at input port 1 is 11001010B (0CAH). MOV R0, #30H ; R0 <= 30h MOV A, @ R0 ; A <= 40H MOV R1, A ; R1 <= 40h MOV R, @ R1 ; B <= 10h MOV @ R1, P1 ; RAM (40H) <= OCAH MOV P2, P1 ; P2 # 0CAH leaves the value 30H in register 0,40H in both the Accumulator and register 1,10H in register B, and 0CAH (11001010B) both in RAM location 40H and output on port 2. 1 1 1 1 1 0 1 r r r Example : MOV A, Rn Bytes : Cycles : Encoding : Operation : MOV (A) (Rn) *MOV A,direct Bytes : 2 Cycles : 1 Encoding : Operation : 1 1 1 0 0 1 0 1 direct address MOV (A) (direct) *MOV A, ACC is not valid instruction. MATRA MHS Rev. E (14 Jan. 97) 37 C51 Family MOV A,@ RI Bytes : Cycles : Encoding : Operation : 1 1 1 1 1 0 0 1 1 i MOV (A) (Ri) MOV A, # data Bytes : 2 Cycles : 1 Encoding : Operation : MOV Rn, A Bytes : Cycles : Encoding : Operation : 0 1 1 1 0 1 0 0 immediate data MOV (A) # data 1 1 1 1 1 1 1 r r r MOV (Rn) (A) MOV Rn, direct Bytes : 2 Cycles : 2 Encoding : Operation : 1 0 1 0 1 r r r direct addr. MOV (Rn) (direct) MOV Rn, # data Bytes : 2 Cycles : 1 Encoding : Operation : 0 1 1 1 1 r r r immediate data MOV (Rn) # data MOV direct, A Bytes : 2 Cycles : 1 Encoding : Operation : 1 1 1 1 0 1 0 1 direct address MOV (direct) (A) MOV direct, Rn Bytes : 2 Cycles : 2 Encoding : Operation : 1 0 0 0 1 r r r direct address MOV (direct) (Rn) 38 MATRA MHS Rev. E (14 Jan. 97) C51 Family MOV direct, direct Bytes : 3 Cycles : 2 Encoding : Operation : 1 0 0 0 0 1 0 1 dir. addr. (src) dir. addr. (dest) MOV (direct) (direct) MOV direct, @ Ri Bytes : 2 Cycles : 2 Encoding : Operation : 1 0 0 0 0 1 1 i direct addr. MOV (direct) (Ri) MOV direct, # data Bytes : 3 Cycles : 2 Encoding : Operation : MOV @ Ri, A Bytes : Cycles : Encoding : Operation : 0 1 1 1 0 1 0 1 direct address immediate data MOV (direct) # data 1 1 1 1 1 1 0 1 1 i MOV ((Ri)) (A) MOV @ Ri, direct Bytes : 2 Cycles : 2 Encoding : Operation : 1 0 1 0 0 1 1 i direct addr. MOV ((Ri)) (direct) MOV @ Ri*, data Bytes : 2 Cycles : 1 Encoding : Operation : 0 1 1 1 0 1 1 i immediate data MOV ((Ri)) # data MATRA MHS Rev. E (14 Jan. 97) 39 C51 Family MOV Function : Description : More bit data The Boolean variable indicated by the second operand is copied into the location specified by the first operand. One of the operands must be the carry flag ; the other may be any directly addressable bit. No other register or flag is affected. The carry flag is originally set. The data present at input Port 3 is 11000101B. The data previously written to output Port 1 is 35H (00110101B). MOV P1.3, C MOV C, P3.3 MOV P1.2, C will leave the carry cleared and change Port 1 to 39H (00111001B). 2 1 1 0 1 0 0 0 1 0 bit address Example : MOV C, bit Bytes : Cycles : Encoding : Operation : MOV bit, C Bytes : Cycles : Encoding : Operation : MOV (C) (bit) 2 2 1 0 0 1 0 0 1 0 bit address MOV (bit) (C) MOV DPTR, # data 16 Function : Description : Load Data Pointer with a 16-bit constant The Data Pointer is loaded with the 16-bit constant indicated. the 16-bit constant is loaded into the second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the third byte (DPL) holds the low-order byte. No flags are affected. This is the only instruction which moves 16-bits of data at once. The instruction, MOV DPTR, 1234H will load the value 1234H into the Data Pointer : DPH will hold 12H and DPL will hold 34H. 3 2 1 0 0 1 0 0 0 0 immed. data 15-8 immed. data 7-0 Example : Bytes : Cycles : Encoding : Operation : MOV (DPTR) # data15-0 DPH DPL # data15-8 # data7-0 40 MATRA MHS Rev. E (14 Jan. 97) C51 Family MOVC A, @ A + Function : Description : Move Code byte The MOVC instructions load the Accumulator with a code byte, or constant from program memory. The address of the byte fetched is the sum of the original unsigned eight-bit. Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data Pointer or the PC. In the latter case, PC is incremented to the address of the following instruction before being added with the Accumulator ; otherwise the base register is not altered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may propagate through higher-order bits. No flags are affected. A value between 0 and 3 is in the Accumulator. The following instructions will translate the value in the Accumulator to one of four values defined by the DB (define byte) directive. REL PC : INC A MOVC A, @ A + PC RET DB 66H CB 77H CB 88H DB 99H If the subroutine is called with the Accumulator equal to 01H, it will return with 77H in the Accumulator. The INC A before the MOVC instruction is needed to " get around " the RET instruction above the table. If several bytes of code separated the MOVC from the table, the corresponding number would be added to the Accumulator instead. Example : MOVC A, @ A + DPTR Bytes : 1 Cycles : 2 Encoding : Operation : 1 0 0 1 0 0 1 1 MOVC (A) ((A) + (DPTR)) MOVC A, @ A + PC Bytes : 1 Cycles : 2 Encoding : Operation : 1 0 0 0 0 0 1 1 MOVC (PC) (PC) + 1 (A) ((A) + (PC)) MATRA MHS Rev. E (14 Jan. 97) 41 C51 Family MOVX Function : Description : Move External The MOVX instructions transfer data between the Accumulator and a byte of external data memory, hence the "X" appended to MOV. There are two types of instructions, differing in whether they provide an eight-bit or sixteen-bit indirect address to the external data RAM. In the first type, the contents of R0 or R1 in the current register bank provide an eight-bit address multiplexed with data on P0. Eight bits are sufficient for external I/O expansion decoding or for a relatively small RAM array. For somewhat larger arrays, any output port pins can be used to output higher-order address bits. These pins would be controlled by an output instruction preceding the MOVX. In the second type of MOVX instruction, the Data Pointer generates a sixteen-bit address. P2 outputs the high-order eight address bits (the contents of DPH) while P0 multiplexes the low-order eight bits (DPL) with data. The P2 Special Function Register retains its previous contents while the P2 output buffers are emitting the contents of DPH. This form is faster and more efficient when accessing very large data arrays (up to 64K bytes), since no additional instructions are needed to set up the output ports. It is possible in some situation to mix the two MOVX types. A large RAM array with its high-order address lines driven by P2 can be addressed via the Data Pointer, or with code to output high-order address bits to P2 followed by a MOVX instruction using R0 or R1. An external 256 byte RAM using multiplexed address/data lines is connected to the 80C51 Port 0. Port 3 provides control lines for the external RAM. Ports 0 and 2 are used for normal I/O. Registers 0 and 1 contain 12H and 34H. Location 34H of the external RAM holds the value 56H. The instruction sequence MOVX A, @ R1 MOVX @ R0, A copies the value 56H into both the Accumulator and external RAM location 12H. Example : MOVX A, @ Ri Bytes : 1 Cycles : 2 Encoding : Operation : 1 1 1 0 0 0 1 i MOVX (A) ((Ri)) MOVX @ Ri, A Bytes : 1 Cycles : 2 MOVX ((Ri)) (A) MOVX A, @ DPTR Bytes : 1 Cycles : 2 MOVX (A) ((DPTR)) MOVX @ DPTR, A Bytes : 1 Cycles : 2 Encoding : Operation : 1 1 1 1 0 0 0 0 Encoding : Operation : 1 1 1 1 0 0 1 i Encoding : Operation : 1 1 1 0 0 0 0 0 MOVX (DPTR) (A) MATRA MHS Rev. E (14 Jan. 97) 42 C51 Family MUL AB Function : Description : Multiply MUL AB multiplies the unsigned eight-bit integers in the Accumulator and register B. The low-order byte of the sixteen-bit product is left in the Accumulator, and the high-order byte in B. If the product is greater than 255 (OFFH) the overflow flag is set ; otherwise it is cleared. The carry flag is always cleared. Originally the Accumulator holds the value 80 (50H). Register B holds the value 160 (OAOH). The instruction, MUL AB will give the product 12,800 (3200H), so B is changed to 32H (00110010B) and the Accumulator is cleared. The overflow flag is set, carry is cleared. 1 4 1 0 1 0 0 1 0 0 Example : Bytes : Cycles : Encoding : Operation : MUL (A)7 - 0 (A) x (B) (B)15 - 8 NOP Function : Description : Example : No Operation Execution continue at the following instruction. Other than the PC, no registers or flags are effected. It is desired to produce a low-going output pulse on bit 7 of Port 2 lasting exactly 5 cycles. A simple SETB/CLR sequence would generate a one-cycle pulse, so four additional cycles must be inserted. This may be done (assuming no interrupts are enable) with the instruction sequence. CLR P2.7 NOP NOP NOP NOP SETP P2.7 1 1 0 0 0 0 0 0 0 0 Bytes : Cycles : Encoding : Operation : NOP (PC) (PC) + 1 MATRA MHS Rev. E (14 Jan. 97) 43 C51 Family ORL Function : Description : Logical-OR for byte variables ORL performs the bitwise logical-OR operation between the indicated variables, storing the results in the destination byte, No flags are affected. The two operands allow six addressing mode combinaisons. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing ; when the destination is a direct address, the source can be the Accumulator or immediate data. Note : When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. If the Accumulator holds 0C3H (11000011B) and R0 holds 55H (01010101B) then the instruction, ORL A, R0 will leave the Accumulator holding the value 0D7H (11010111B). When the destination is a directly addressed byte, the instruction can set combinations of bits in any RAM location or hardware register. The pattern of bits to be set is determined by a mask byte, which may be either a constant data value in the instruction or a variable computed in the Accumulator at run-time. The instruction., ORL P1, # 00110010b will set bits 5, 4, and 1 of output Port 1. 1 1 0 1 0 0 1 r r r Example : ORL A, Rn Bytes : Cycles : Encoding : Operation ORL (A) (A) V (Rn) ORL A, direct Bytes : 2 Cycles : 1 Encoding : Operation : ORL A, @ Ri Bytes : Cycles : Encoding : Operation : 0 1 0 0 0 1 0 1 direct address ORL (A) (A) V (direct) 1 1 0 1 0 0 0 1 1 i ORL (A) (A) V ((Ri)) ORL A, # data Bytes : 2 Cycles : 1 Encoding : Operation : 0 1 0 0 0 1 0 0 immediate data ORL (A) (A) V # data ORL direct, A Bytes : 2 Cycles : 1 Encoding : Operation : 0 1 0 0 0 0 1 0 direct address ORL (direct) (direct) V (A) 44 MATRA MHS Rev. E (14 Jan. 97) C51 Family ORL direct, # data Bytes : 3 Cycles : 2 Encoding : Operation : 0 1 0 0 0 0 1 1 direct address immediate data ORL (direct) (direct) V # data ORL C, Function : Description : Logical-OR for bit variable Set the carry flag if the Boolean value is a logical 1 ; leave the carry in its current state otherwise. A slash (" / ") preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit it self is not affected. No other flags are affected. Set the carry flag if and only if P1.0 = 1, ACC. 7 = 1, or OV = 0 : MOV C, P1.0 ; LOAD CARRY WITH INPUT PIN P10 ORL C, ACC.7 ; OR CARRY WITH THE ACC. BIT7 ORL C,/OV ; OR CARRY WITH THE INVERSE OF OV 2 2 0 1 1 1 0 0 1 0 bit address Example : ORL C, bit Bytes : Cycles : Encoding : Operation : ORL C, /bit Bytes : Cycles : Encoding : Operation : ORL (C) (C) V (bit) 2 2 1 0 1 0 0 0 0 0 bit address ORL (C) (C) V (bit) POP direct Function : Description : Pop from stack. The contents of internal RAM location addressed by the Stack Pointer is read, and the Stack Pointer is decremented by one. The value read is then transferred to the directly addressed byte indicated. No flags are affected. The Stack Pointer originally contains the value 32H, and internal RAM locations 30H through 32H contain the values 20H, 23H, and 01H, respectively. The instruction sequence, POP DPH POP DPL will leave the Stack Pointer equal to the value 30H and the Data Pointer set to 0123H. At this point the instruction, POP SP will leave the Stack Pointer set to 20H. Note that in this special case the Stack Pointer was decremented to 2FH before being loaded with the value popped (20H) 2 2 1 1 0 1 0 0 0 0 direct address Example : Bytes : Cycles : Encoding : Operation : POP (direct) ((SP)) (SP) (SP) - 1 45 MATRA MHS Rev. E (14 Jan. 97) C51 Family PUSH direct Function : Description : Example : push onto stack. The Stack Pointer is incremented by one. The contents fo the indicated variable is then copied into the internal RAM location addressed by the Stack Pointer. Otherwise no flags are affected. On entering interrupt routine the Stack Pointer contains 09H. The Data Pointer holds the value 0123H. The instruction sequence, PUSH DPL PUSH DPH will leave the Stack Pointer set to 0BH and store 23H and 01H in internal RAM location 0AH and 0BH, respectively. 2 2 1 1 0 0 0 0 0 0 direct address Bytes : Cycles : Encoding : Operation : PUSH (SP) (SP) + 1 ((SP)) (direct) RET Function : Description : Return from subroutine RET pops the high-and low-order bytes of the PC successively from the stack, decrementing the Stack Pointer by two. Program execution continues at the resulting address, generally the instruction immediately following en ACALL or LCALL. No flags are affected. The Stack Pointer originally contains the value 0BH. Internal RAM locations 0AH and 0BH contain the values 23H, and 01H, respectively. The instruction, RET will leave the Stack Pointer equal to the value 09H. Program execution will continue at location 0123H. 1 2 0 0 1 0 0 0 1 0 Example : Bytes : Cycles : Encoding : Operation : RET (PC15 - 8) ((SP)) (SP) (SP) - 1 (PC7-0) ((SP)) (SP) (SP) - 1 RETI Function : Description : Return from interrupt RETI pops the high-and low-order bytes of the PC successively from the stack, and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. The Stack Pointer is left decremented by two. No other registers are affected ;the PSW is not automatically restored to its pre-interrupt status. Program execution continues at the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. If a lower-or-same-level interrupt had been pending when the RETI instruction is executed, that one instruction will be executed before the pending interrupt is processed. The Stack Pointer originally contains the value 0BH. An interrupt was detected during the instruction ending at location 0122H. Internal RAM locations 0AH and 0BH contain the values 23H and 01H, respectively. The instruction, RETI will leave the Stack Pointer equal to 09H and return program execution to location 0123H. MATRA MHS Rev. E (14 Jan. 97) Example : 46 C51 Family Bytes : Cycles : Encoding : Operation : 1 2 0 0 1 1 0 0 1 0 RETI (PC15 - 8) ((SP)) (SP) (SP) - 1 (PC7 - 0) ((SP)) (SP) (SP) - 1 RL A Function : Description : Example : Rotate Accumulator Left The eight bits in the Accumulator are rotated one bit to the left. Bit 7 rotated into the bit 0 position. No flags are affected. The Accumulator holds the value 0C5H (11000101B). The instruction, RL A leaves the Accumulator holding the value 8BH (100001011B) with the carry unaffected. 1 1 0 0 1 0 0 0 1 1 Bytes : Cycles : Encoding : Operation : RL (An + 1) (An) n = 0 - 6 (A0) (A7) RLC A Function : Description : Rotate Accumulator Left through the Carry flag The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into the carry flag ; the original state of the carry flag moves into the bit 0 position. No other flags are affected. The Accumulator holds the value 0C5H (11000101B), and the carry is zero. The instruction, RCL A leaves the Accumulator holding the value 8BH (10001010B) with the carry set. 1 1 0 0 1 1 0 0 1 1 Example : Bytes : Cycles : Encoding : Operation : RLC (An + 1) (An) n = 0 - 6 (A0) (C) (C) (A7) MATRA MHS Rev. E (14 Jan. 97) 47 C51 Family RR A Function : Description : Example : Rotate Accumulator Right The eight bits in the Accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 position. No flags are affected. The Accumulator holds the value 0C5H (11000101B). The instruction, RR A leaves the Accumulator holding the value 0E2H (11100010B) with the carry unaffected. 1 1 0 0 0 0 0 0 1 1 Bytes : Cycles : Encoding : Operation : RR (An) (An + 1) n = 0 - 6 (A7) (A0) RRC A Function : Description : Rotate Accumulator Right through Carry flag The eight bits in the Accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag ; the original value of the carry flag moves into the bit 7 position. No other flags are affected. The Accumulator holds the value 0C5H (11000101B), and the carry is zero. The instruction, RRC A leaves the Accumulator holding the value 62 (01100010B) with the carry set. 1 1 0 0 0 1 0 0 1 1 Example : Bytes : Cycles : Encoding : Operation : RRC (An) (An + 1)n = 0 - 6 (A7) (C) (C) (A0) 48 MATRA MHS Rev. E (14 Jan. 97) C51 Family SETB Function : Description : Example : Set bit SETB sets the indicated bit to one. SETB can operate on the carry flag or any direct addressable bit. No other flags are affected. The carry flag is cleared. Output Port 1 has been written with the value 34H (00110100B). The instructions, SETB C SETB P1.0 will leave the carry flag set to 1 and change the data output on Port 1 to 35H (00110101B). 1 1 1 1 0 1 0 0 1 1 SETB C Bytes : Cycles : Encoding : Operation : SETB bit Bytes : Cycles : Encoding : Operation : SETB (C) 1 2 1 1 1 0 1 0 0 1 0 bit address SETB (bit) 1 SJMP rel Function : Description : Short Jump Program control branches unconditionally to the address indicated. The branch destination is computed by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it. The label "RELADR" is assigned to an instruction at program memory location 0123H. The instruction, SJMP RELADR will assemble into location 0100H. After the instruction is executed, the PC will contain the value 0123H. (Note : Under the above conditions the instruction following SJMP will be at 102H. therefore, the displacement byte of the instruction will be the relative offset (0123H - 0102H) = 21H. Put another way, an SJMP with a displacement of 0FEH would be an one-instruction infinite loop). 2 2 1 0 0 0 0 0 0 0 rel. address Example : Bytes : Cycles : Encoding : Operation : SJMP (PC) (PC) + 2 (PC) (PC) + rel MATRA MHS Rev. E (14 Jan. 97) 49 C51 Family SETB Function : Description : Subtract with borrow SUBB subtracts the indicated variable and the carry flag together from the Accumulator, leaving the result in the Accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7, and clears C otherwise. (If C was set before executing a SUBB instruction, this indicates that a borrow was needed for the previous step in a multiple precision substraction so the carry is subtracted from the Accumulator along with the source operand). AC is set if a borrow is needed for bit 3, and cleared otherwise. OV is set if a borrow is needed into bit 6, but not into bit 7, or into bit 7, but not bit 6. When subtracting signed integers OV indicates a negative number produced when a negative value is subtracted from a positive value, or a positive result when a positive number is subtracted from a negative number. The source operand allows four addressing modes : register, direct, register-indirect, or immediate. The Accumulator holds 0C9H (11001001B), register 2 holds 54H (01010100B), and the carry flag is set. the instruction, SUBB A, R2 will leave the value 74H (01110100B) in the accumulator, with the carry flag and AC cleared but OV set. Notice that 0C9H minus 54H is 75H. The difference between this and the above result is due to the carry (borrow) flag being set before the operation. If the state of the carry is not known before starting a single or multiple-precision substraction, it should not be explicity cleared by a CLRC instruction. 1 1 1 0 0 1 1 r r r Example : SUBB A, Rn Bytes : Cycles : Encoding : Operation : SUBB (A) (A) - (C) - (Rn) SUBB A, direct Bytes : 2 Cycles : 1 Encoding : Operation : 1 0 0 1 0 1 0 1 direct address SUBB (A) (A) - (C) - (direct) SUBB A, @ Ri Bytes : 1 Cycles : 1 Encoding : Operation : 1 0 0 1 0 1 1 i SUBB (A) (A) - (C) - (Ri) SUBB A, # data Bytes : 2 Cycles : 1 Encoding : Operation : 1 0 0 1 0 1 0 0 immediate data SUBB (A) (A) - (C) - # data 50 MATRA MHS Rev. E (14 Jan. 97) C51 Family SWAP A Function : Description : Example : Swap nibbles within the Accumulator SWAP A interchanges the low-and high-order nibbles (four-bit fields) of the Accumulator (bits 3 - 0 and bits 7 - 4). The operation can also be thought of a four-bit rotate instruction. No flag are affected. The Accumulator holds the value 0C5H (11000101B). The instruction, SWAP A leave the Accumulator holding the value 5CH (01011100B). 1 1 1 1 0 0 0 1 0 0 Bytes : Cycles : Encoding : Operation : SWAP (A 3 - 0) + (A 7 - 4) XCH A, Function : Description : Exchange Accumulator with byte variable XCH loads the Accumulator with the contents of the indicated variable, at the same time writing the original Accumulator contents to the indicated variable. The source/destination operand can use register, direct, or register-indirect addressing. R0 contains the addres 20H. The Accumulator holds the value 3FH (00111111B). Internal RAM location 20H holds the value 75H (01110101B). The instruction, XCH A, @R0 will leave RAM location 20H holding the values 3FH (00111111B) and 75H (01110101B) in the Accumulator. 1 1 1 1 0 0 1 r r r Example : XCH A, Rn Bytes : Cycles : Encoding : Operation : XCH (A) + (Rn) XCH A, direct Bytes : 2 Cycles : 1 Encoding : Operation : XCH A, @Ri Bytes : Cycles : 1 1 0 0 0 1 0 1 direct address XCH (A) + (direct) 1 1 MATRA MHS Rev. E (14 Jan. 97) 51 |
Price & Availability of C51PG
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |