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Features
* * * * *
Available in Gate Array, Embedded Array or Standard Cell High-speed, 75 ps Gate Delay, 2-input NAND, FO = 2 (nominal) Up to 13.7 Million Used Gates and 1516 Pins 0.18 Geometry in up to Six-level Metal System-level Integration Technology - Cores: ARM7TDMITM, ARM920TTM and ARM946E-STM and MIPS64TM 5KfTM RISC Microprocessors; AVR (R) RISC Microcontroller; Teak(R) and PalmDSPCore(R) Digital Signal Processors; 10/100 Ethernet MAC, USB, 1394, 1284, CAN and other Assorted Processor Peripherals - Analog Functions: DACs, ADCs, OPAMPs, Comparators, PLLs and PORs - Soft Macro Memory: Gate Array SRAM -- ROM -- DPSRAM -- FIFO - Hard Macro Memory: Embedded Array or Standard Cell SRAM -- ROM -- DPSRAM -- FIFO -- Stacked E2 -- Stacked Flash - I/O Interfaces: CMOS, LVTTL, LVDS, PCI, USB; Output Currents up to 24 mA at 1.8V; 1.8V Native I/O, 2.5V Tolerant/Compliant I/O, 3.3V Tolerant/Compliant I/O, 5.0V Tolerant I/O
ASIC ATL18 Series
Description
The ATL18 Series ASIC family is fabricated on a 0.18 CMOS process with up to six levels of metal. This family features layouts with up to 13.7 million routable gates and 1516 pins. The high density and high pin count capabilities of the ATL18 family, coupled with the ability to embed microprocessor cores, DSP engines and memory on the same silicon, make the ATL18 series of ASICs an ideal choice for system-level integration. Figure 1. ATL18 Technology
ATL18 Gate Array ASIC ATL18 Embedded Array ASIC
Standard Gate Array Architecture
Standard Gate Array Architecture
Analog
ATL18 Standard Cell ASIC
CustomerSpecified Logic
Analog
Rev. 2005A-ASIC-06/02
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Table 1. ATL18 Array Organization
Device Number ATL18/44 ATL18/68 ATL18/84 ATL18/100 ATL18/120 ATL18/132 ATL18/144 ATL18/160 ATL18/184 ATL18/208 ATL18/228 ATL18/256 ATL18/304 ATL18/352 ATL18/388 ATL18/432 ATL18/484 ATL18/540 ATL18/600 ATL18/700 ATL18/800 ATL18/900 ATL18/976 ATL18/1132 ATL18/1156 ATL18/1312 ATL18/1444 ATL18/1516 Notes: 6LM Routable Gates(1) 21,902 54,572 84,303 120,474 164,735 200,388 238,297 296,171 367,923 471,598 371,057 475,669 637,427 867,442 1,062,530 1,328,670 1,564,492 1,960,378 2,434,175 3,337,788 4,061,100 5,163,302 6,090,447 7,597,266 7,919,768 10,235,584 12,430,118 13,715,871 Available Routing Sites(2) 29,202 72,762 112,404 160,632 219,646 267,184 317,729 394,894 490,564 628,797 494,742 634,225 849,902 1,156,589 1,416,706 1,771,560 2,085,989 2,613,837 3,245,566 4,450,384 5,414,800 6,884,402 8,120,596 10,129,688 10,559,690 13,647,445 16,573,490 18,287,828 Max Pad Count 44 68 84 100 120 132 144 160 184 208 228 256 304 352 388 432 484 540 600 700 800 900 976 1132 1156 1312 1444 1516 Max I/O Count 36 60 76 92 112 124 136 152 176 200 220 248 296 344 380 424 476 532 592 692 792 892 968 1124 1148 1304 1436 1508 Gate Speed(3) 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps 75 ps
1. One gate = NAND2 2. Routing site = 4 transistors 3. Nominal 2-input NAND gate, Fanout = 2 at 1.8V
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ATL18 Series ASIC
Design
Atmel supports several major software systems for design with complete cell libraries, as well as utilities for netlist verification, test vector verification and accurate delay simulations. Table 2. Design Systems Supported
System Cadence(R) Design Systems, Inc. Tools OpusTM - Schematic and Layout NC VerilogTM - Verilog Simulator PearlTM - Static Path Verilog-XLTM - Verilog Simulator BuildGatesTM - Synthesis (Ambit) ModelSim(R) - Verilog and VHDL (VITAL) Simulator Leonardo SpectrumTM - Logic Synthesis Design CompilerTM - Synthesis DFT Compiler - 1-Pass Test Synthesis BSD Compiler - Boundary Scan Synthesis TetraMax(R) - Automatic Test Pattern Generation PrimeTimeTM - Static Path VCSTM - Verilog Simulator Floorplan ManagerTM Debussy(R) First Encounter(R) Version 4.46 3.3-s008 4.3-s095 3.3-s006 4.0-p003 5.5e 2001.1d 01.01-SP1 01.08-SP1 01.08-SP1 01.08 01.08-SP1 5.2 01.08-SP1 5.1 v2001.2.3
Mentor Graphics(R) SynopsysTM
Novas Software, Inc. Silicon PerspectiveTM
Atmel's ASIC design flow is structured to allow the designer to consolidate the greatest number of system components onto the same silicon chip, using widely available thirdparty design tools. Atmel's cell library reflects silicon performance over extremes of temperature, voltage and process, and includes the effects of metal loading, interlevel capacitance, and edge rise and fall times. The design flow includes clock tree synthesis to customer-specified skew and latency goals. RC extraction is performed on the final design database and incorporated into the timing analysis. The ASIC design flow, shown on page 4, provides a pictorial description of the typical interaction between Atmel's design staff and the customer. Atmel will deliver design kits to support the customer's synthesis, verification, floorplanning and scan insertion activities. Leading-edge tools from vendors such as Synopsys and Cadence are fully supported in the Atmel design flow. In the case of an embedded array design, Atmel will conduct a design review with the customer to define the partition of the embedded array ASIC and to define the location of the memory blocks and/or cores so an underlayer layout model can be created. In the case of a standard cell design, Atmel will conduct a design review with the customer to define the partition of the standard cell ASIC and to define the location of the standard cell components so a full mask set layout can be created. Following database acceptance, automated test pattern generation (ATPG) is performed, if required, on scan paths using Synopsys tools; the design is routed; and postroute RC data is extracted. After post-route verification and a final design review, the design is taped out for fabrication.
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Figure 2. Design Flow
Deliver Design Kit
Kickoff Meeting
If Embedded Array
Define Underlayer
Synthesis/ Design Entry
Scan/JTAG
Simulation/ Static Path
Floorplan
If Embedded Array (Preliminary Netlist)
Create Underlayer
Database Handoff
Tape Out Underlayer
Database Acceptance
Fabricate Underlayer
Place and Route/ Clock Tree
Verification/ Resimulation
Final Design Review If Standard Cell If Embedded/Gate Array
Tape Out Full Mask Set
Tape Out Metal Masks
Fabricate
Fabricate Personality
Customer Atmel Joint
Proto Assembly and Test Rev. 2.2-03/02
Proto Shipment
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ATL18 Series ASIC
Pin Definition Requirements
The corner pads are reserved for Power and Ground only. All other pads are fully programmable as Input, Output, Bidirectional, Power or Ground. When implementing a design with 3.3V or 2.5V compliant or 5.0V tolerant buffers, an appropriate number of pad sites must be reserved for the VDD3 or VDD2 pins, which are used to distribute 3.3V or 2.5V power to the compliant buffers.
Design Options
Logic Synthesis ASIC Design Translation
Atmel can accept RTL designs in Verilog or VHDL formats. Atmel fully supports Synopsys for Verilog or VHDL simulation as well as synthesis. Atmel has successfully translated existing designs from most major ASIC vendors into Atmel ASICs. These designs have been optimized for speed and gate count and modified to add logic or memory, or replicated as a pin-for-pin compatible, drop-in replacement. Atmel has successfully translated existing FPGA/PLD designs from most major vendors into Atmel ASICs. There are four primary reasons to convert from an FPGA/PLD to an ASIC: * * * * Conversion of high-volume devices for a single or combined design is cost effective. Performance can often be optimized for speed or low power consumption. Several FPGA/PLDs can be combined onto a single chip to minimize cost while reducing on-board space requirements. In situations where an FPGA/PLD was used for fast cycle time prototyping, an ASIC may provide a lower cost answer for long-term volume production.
FPGA and PLD Conversions
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Macro Cores
AVR 8-bit RISC Microcontroller Core
The AVR RISC microcontroller is a true 8-bit RISC architecture, ideally suited for embedded control applications. The AVR is offered as a gate level, synthesizable macro core in the ATL18 family. The AVR supports a powerful set of 120 instructions. The AVR prefetches an instruction during a prior instruction execution, enabling the execution of one instruction per clock cycle. The Fast Access RISC register file consists of 32 general-purpose working registers. These 32 registers eliminate the data transfer delay in the traditional program code intensive accumulator architectures. The AVR can incorporate up to 64K x 16 program memory (ROM) and 64K x 8 data memory (SRAM). Among the peripheral options offered are: UART, 8-bit timer/counter, 16-bit timer/counter, programmable watchdog timer and SPI. Support for JTAG on-chip debugging has recently been added. Figure 3. AVR 8-bit RISC Microcontroller Core
16-bit
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8-bit Data Bus
ATL18 Series ASIC
ARM7TDMI 32-bit RISC Microprocessor Core
The ARM7TDMI is a powerful 32-bit processor offered as a hard macro core in the ATL18 family. The ARM7TDMI is a member of the ARM family of general purpose 32-bit microprocessors, which offer high performance with very low power consumption. Additionally, the ARM7T offers users a "thumb" mode (for higher code density using 16-bit instructions). The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers (CISC). This simplicity results in a high instruction throughput and an impressive real-time interrupt response from a small and cost-effective chip. Pipelining is employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM memory interface has been designed to allow the performance potential to be realized without incurring high costs in the memory system. Speed-critical control signals are pipelined to allow system control functions to be implemented in standard lowpower logic, and these control signals facilitate the exploitation of the fast local access modes offered by industry standard SRAMs. The ARM7TDMI core interfaces to several optional peripheral macros. Among the peripheral options offered are real-time clock, peripheral data controller, USART, external bus interface, interrupt controller, timer counter and watchdog timer. Figure 4. ARM7TDMI 32-bit RISC Microprocessor Core
Address Incrementor Register Bank (31 X 32-bit Registers) (6 Status Registers)
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ARM920T 32-bit RISC Microprocessor Core
The ARM920T extends the capabilities of the popular ARM7TDMI, while maintaining code compatibility and Thumb instruction compression. Enhancements include Harvard architecture and a memory management unit with virtual addressing support (allowing the use of advanced platform operating systems such as Windows CETM, LinuxTM, Symbian OSTM and VxWorksTM). 16 Kbyte data and instruction caches are included. The ARM946E-S is a synthesizable version of the ARM9E-S core, with similar features to the ARM920T. The ARM9E-S instruction set adds saturation logic to enhance DSP implementation, as well as double-word data moves. Additional DSP features include a single cycle 16 x 32 Multiply Accumulate (MAC) Unit. A memory protection unit is provided, but without full virtual memory support. As a result, the ARM946E-S is more suited to deeply embedded tasks that do not require extended-platform OS support. Cache sizes can be tailored to the application, resulting in a (potentially) smaller die size compared to the ARM920T. The MIPS64 5Kf is a synthesizable MIPS64 5K family core that provides 64-bit address and data paths along with an onboard IEEE 754-compliant Floating Point Unit. A built-in memory management unit with virtual addressing support allows the use of platform operating systems such as Windows CE and others. Also provided are configurable instruction and data caches, as well as a multiply divide unit capable of single cycle 32 x 16 Multiply Accumulate (MAC) operations. The Teak and Palm are synthesizable dual-MAC DSP cores from DSP Group, Inc. The Teak is a fixed-point 16-bit DSP, whereas the Palm can be configured for 16-bit, 20-bit or 24-bit fixed-point math. Both cores are optimized for high MIPs per mW, with performance targeted to handling filtering, voice compression/decompression and modem functions for portable and wireless applications such as 3G digital cellular. Hardware support is also provided for implementing Viterbi forward error correction. The Teak and Palm cores both have a comprehensive suite of development tools that are easy to learn and are intended to support rapid code development. A C compiler that supports in-line assembly language and provides language extensions to enhance C code optimization is provided. An assembler and linker are also provided. Both emulation (using test silicon) and source-level simulation of C and assembly language enhance software verification.
ARM946E-S 32-bit RISC Microprocessor Core
MIPS64 5Kf 64-bit RISC Microprocessor Core
Teak(R) and PalmDSPCore(R) Digital Signal Processing Cores
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ATL18 Series ASIC
ATL18 Series Cell Library
Atmel's ATL18 Series ASICs make use of an extensive library of cell structures, including logic cells, buffers and inverters, multiplexers, decoders and I/O options. Soft macros are also available. These cells are characterized by use of SPICE modeling at the transistor level, with performance verified on manufactured test silicon. Characterization is performed over the rated temperature and voltage ranges to ensure simulation accuracy. Absolute Maximum Ratings*
Parameter Operating Ambient Temperature Storage Temperature Maximum Input Voltage base L25V L25, L33 L33V Category Rating -55C to +125C -65C to +150C VDD + 0.5V 3.6V VHV + 0.5V 5.5V 2.0V L25, L25V L33, L33V 2.7V 3.6V
Maximum Operating Voltage (VDD) Maximum Operating Voltage (VHV) Note:
* Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 3. DC Characteristics
Symbol TA VDD VHV Parameter Operating Temperature VDD Supply Voltage VHV Supply Voltage Category All All L25, L25V L33, L33V Base L25V IIH High-level Input Current L25, L33 L33V IIL Low-level Input Current All Base L25V IOZ High-impedance Output Current L25, L33 L33V All CMOS All All All All All CMOS VIN = V DD (max) VIN = 3.6V VIN = V HV (max) VIN = 5.5V VIN = V SS VOUT = VDD (max) VOUT = 3.6V VOUT = VHV (max) VOUT = 5.5V VOUT = VSS -5 - - - - -5 - - - 5 5 5 5 - A A - - 5 A Buffer Test Condition Min -55 1.6 2.3 3.0 Typ - 1.8 2.5 3.3 Max 125 2.0 2.7 V 3.6 Units C V
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Table 3. DC Characteristics (Continued)
Symbol Parameter Category Buffer Test Condition VOUT = VDD, VDD = VDD (max) VOUT = VSS, VDD = VDD (max) L25, L25V, L33, L33V Base VOH High-level Output Voltage L25, L25V L33, L33V Base VOL Low-Level Output Voltage L25, L25V L33, L33V Base VIH High-level Input Voltage PCI L25, L25V, L33, L33V Base VIL Low-level Input Voltage PCI L25, L25V, L33, L33V Base VHYS Hysteresis L25, L25V L33, L33V C Note: Capacitance Input or Output Schmitt VDD = 1.8V VHV = 2.5V VHV = 3.3V 3.3V - - 0.31 0.44 0.46 6.6 - pF - V CMOS - - CMOS VOUT = VHV (max), VDD = VHV (max) VOUT = VSS, VDD = VHV (max) PO11* PO11L25* PO11L33* PO11* PO11L25* PO11L33* IOH = 2 mA IOH = 2 mA IOH = 2 mA IOL = 2 mA IOL = 2 mA IOL = 2 mA Min - - - - 0.75 VDD 0.75 VHV 0.75 VHV - - - 0.65VDD 0.475VHV (3.3.) 0.65VHV 0.35VDD 0.325VHV (3.3) 0.35VHV V - - V Typ 12 -11 10 -9 - - - - - - Max - mA - - mA - - - - 0.25VDD 0.25VHV 0.25VHV V V Units
Base IOS Output Short-circuit Current
PO11*
PO11L25V*
* Named buffer is given as an example only. All buffers in the category have these ratings.
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ATL18 Series ASIC
I/O Buffer Cell Library
Buffer Interface Categories
ATL18 I/O buffers are designed to operate in specific interface environments. Buffers are assigned to one of several "interface categories" that define this environment with a specific supply voltage and interface voltage level. Tables 4 and 5 define all supported interface categories. When selecting an I/O buffer for use in combination (as a bidirectional buffer), note that the input and output buffers selected must conform to the compatibility rules defined in Tables 4 and 5. Table 4. Input Buffer Categories
Interface Category Base L25 L25V L33 L33V Example Name PIC PICKL25 PICL25V PICKL33 PICL33V VHV - 2.5 2.5 3.3 3.3 VOUT (Keeper/Pullup) 1.8 2.5 2.5 3.3 - VIN(H) Nominal 1.8 2.5 2.5 3.3 3.3 VIN(H) Max 1.8 2.5 3.3 3.3 5.0 PO Compatibility Base L25 L25V L33 L33V Char. Groups 1818_io 1825_iox 1825_iox 1833_iox 1833_iox
Table 5. Output Buffer Categories
Interface Category Base L25 L25V L33 L33V Example Name PO44 PO44L25 PO44L25V PO44L33 PO44L33V VHV - 2.5 2.5 3.3 3.3 VOUT(H) 1.8 2.5 2.5 3.3 3.3 VTOL (max) 1.8 2.5 3.3 3.3 5.0 PI Compatibility Base L25 L25V L33 L33V Char. Groups 1818_io 1825_iox 1825_iox 1833_iox 1833_iox Max Available Drive 24 mA 24 mA 24 mA 24 mA 24 mA
I/O Buffers
* * *
Programmable output drive (2 mA-24 mA) Programmable slew rate control Programmable Pullup/Pulldown/Keeper
Timing and Derating Factors
Timings are generated from comprehensive transistor-level circuit simulation over temperature, voltage, process, loading and input slew rate. The library section includes pinto-pin timings. Delays are represented as mx + b form, where b is the intrinsic delay through the cell (zero load), x is the output load and m is the load factor. All delays are expressed in nanoseconds. Load factors are in nanoseconds per picofarad for output buffers and in nanoseconds per load for all internal cells. Timing values listed are for nominal conditions (VDD = 1.8 Volt, temperature = 25C, nominal process). Setup and hold times are worst case numbers for a military environment (1.6 Volts, 125C, and worst case process). Timings are measured from the rising or falling edge of the data pin (50% of VDD) to the rising edge of the clock (50% of VDD). If setup or hold times are negative, the value is set to zero. Simulation libraries contain individual derating for each cell, providing the most accurate delay numbers possible. Timing numbers in the cell library section can be used for estimation and comparison purposes under nominal conditions. 11
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Note that timing numbers in the cell library should be used for rough approximation and relative comparison only. Atmel's simulation tools contain more sophisticated timing models.
Source of CMOS Power Dissipation
There are two primary components in standard CMOS power consumption: * The major portion of the power dissipation is related to charging and discharging of gate and interconnect capacitance during switching. It directly varies with capacitance load, square of supply voltage, and frequency (P = C x V**2 x F). Quiescent or stand-by power dissipation comes primarily from two parasitic leakage paths. One is through the reverse bias P/N junctions inherent in CMOS, and the second is the subthreshold source to drain current of MOS transistors in their off state.
*
Peak current is calculated from the number of simultaneously switching registers in the device and may determine the minimum number of power and ground pins needed on a device. Another factor is the maximum amount of current drawn by I/O buffers between any two power or ground pads, which also influences the physical placement of power and ground pads. Atmel provides a methodology for calculating both components separately. Refer to the Atmel ASIC Power Estimation Worksheet and the individual data sheets.
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ATL18 Series ASIC
Testability Techniques
For complex designs involving blocks of memory and/or cores, careful attention must be given to design-for-test techniques. The sheer size of complex designs requires the use of more efficient testability techniques. Combinations of SCAN paths, multiplexed access to memory and/or core blocks, and built-in self-test (in addition to functional test patterns) must be employed to effectively test the product. An example of a highly complex design could include analog blocks; a microprocessor or DSP engine or both; SRAM to support the microprocessor or DSP engine; and random logic to support customization and interconnectivity between blocks. Combinations of parametric, functional and structural tests, defined for digital testers, should be employed to create a suite of manufacturing tests. Access to analog, microprocessor, DSP and SRAM blocks must be provided so that controllability and observability of the inputs and outputs to the blocks are achieved with minimum preconditioning. The ARM and MIPS microprocessors, AVR microcontroller, and TeakDSPCore/PalmDSPCore digital signal processors all support SCAN testing. SRAM blocks need to provide access to both address and data ports so that comprehensive memory tests can be performed. Multiplexing I/O pins is one method for providing this accessibility. BIST can also be used to perform SRAM testing. The random logic can be designed using full SCAN techniques for testability.
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Advanced Packaging
The ATL18 Series ASICs are offered in a wide variety of standard packages, including plastic and ceramic quad flatpacks, thin quad flatpacks, ceramic pin grid arrays and ball grid arrays. High-volume onshore and offshore contractors provide assembly and test for commercial product, with prototype capability in Colorado Springs. Custom package designs are also available as required to meet a customer's specific needs, and are supported through Atmel's package design center. If a standard package cannot meet a customer's needs, a package can be designed to precisely fit the customer-specific application and to maintain the performance obtained in silicon. Atmel has delivered custom-designed packages in a wide variety of configurations.
Table 6. Packaging Options
Package Type PQFP Power Quad L/TQFP PLCC CPGA CQFP PBGA Super BGA Low-profile Mini BGA Chip-scale BGA Flex-tape BGA FCBGA(2) Notes:
(1)
Pin Count 44, 52, 64, 80, 100, 120, 128, 132, 144, 160, 184, 208, 240, 304 144, 160, 208, 240, 304 32, 44, 48, 64, 80, 100, 120, 128, 144, 160, 176, 216 20, 28, 32, 44, 52, 68, 84 64, 68, 84, 100, 124, 144, 155, 180, 223, 224, 299, 391 64, 68, 84, 100, 120, 132, 144, 160, 224, 340 121, 169, 208, 217, 225, 240, 256, 272, 300, 304, 313, 316, 329, 352, 388, 420, 456 168, 204, 240, 256, 304, 352, 432, 560, 600 40, 48, 49, 56, 60, 64, 80, 81, 84, 96, 100, 108, 128, 132, 144, 160, 176, 192, 208, 224, 228 32, 36, 40, 48, 49, 56, 64, 81, 84, 100, 108, 121, 128, 144, 160, 169, 176, 192, 208, 224, 256, 288, 324 48, 49, 64, 80, 81, 84, 96, 100, 112, 132, 144, 156, 160, 180, 192, 196, 204, 208, 220, 225, 228, 256, 280 416, 480, 564, 672, 788, 896, 960, 1032, 1152, 1157, 1292, 1357, 1413, 1500, 1517, 1557, 1677, 1728, 1932
1. Partial list 2. Require custom design substrate
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Atmel Headquarters
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Atmel(R) and AVR (R) are registered trademarks of Atmel. ARM7TDMI TM, ARM920T TM and ARM946E-S TM are trademarks of ARM Limited; MIPS64 TM5KfTM are trademarks of MIPS Technologies, Inc.; Teak (R) and PalmDSPCore (R) are registered trademarks of DSP Group; Cadence (R) is a registered trademark and Opus TM, NC Verilog TM, PearlTM , Verilog-XLTM and BuildGatesTM are trademarks of Cadence Design Systems, Inc.; Mentor Graphics (R) and ModelSim (R) are registered trademarks and Leonardo Spectrum TM is a trademark of Mentor Graphics; Design Compiler TM , PrimeTimeTM, VCS TM and Floorplan Manager TM are trademarks and Synopsys (R) and TetraMax (R) are registered trademarks of Synopsys; Debussy (R) is a registered trademark of Novas Software, Inc.; Silicon Perspective(R) and First Encounter (R) are registered tradePrinted on recycled paper. marks of Silicon Perspective; Windows CE TM is a trademark of Microsoft Corp.; LinusTM is a trademark of William R. Della Croce, Jr.; Symbian OSTM is a trademark of Symbian Limited; VxWorks TM is a trademark of Wind 2005A-ASIC-06/02 River Systems, Inc. Other terms and product names may be the trademarks of others.

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