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| PRELIMINARY AM55DL128C8G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Two Am29DL640G 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memories and 64 Mbit (4 M x 16-Bit) Fast Cycle RAM and 8 Mbit (512K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage of 2.7 to 3.1 volt High performance -- Access time as fast as 70 ns Package -- 93-Ball FBGA Operating Temperature -- -40C to +85C -- AMD-supplied software manages data programming, enabling EEPROM emulation -- Eases historical sector erase flash limitations Supports Common Flash Memory Interface (CFI) Program/Erase Suspend/Erase Resume -- Suspends program/erase operations to allow programming/erasing in same bank Data# Polling and Toggle Bits -- Provides a software method of detecting the status of program or erase cycles Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences Flash Memory Features ARCHITECTURAL ADVANTAGES Simultaneous Read/Write operations -- Data can be continuously read from one bank while executing erase/program functions in another bank. -- Zero latency between read and write operations Flexible Bank architecture -- Read may occur in any of the three banks not being written or erased. -- Four banks may be grouped by customer to achieve desired bank divisions. Manufactured on 0.17 m process technology SecSiTM (Secured Silicon) Sector: Extra 256 Byte sector -- Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data -- Customer lockable: Sector is one-time programmable. Once sector is locked, data cannot be changed. Zero Power Operation -- Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero. Boot sectors -- Top and bottom boot sectors in the same device Compatible with JEDEC standards -- Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS High performance -- Access time as fast as 70 ns -- Program time: 4 s/word typical utilizing Accelerate function Ultra low power consumption (typical values) -- 2 mA active read current at 1 MHz -- 10 mA active read current at 5 MHz -- 200 nA in standby or automatic sleep mode Minimum 1 million erase cycles guaranteed per sector 20 year data retention at 125C -- Reliable operation for the life of the system HARDWARE FEATURES Any combination of sectors can be erased Ready/Busy# output (RY/BY#) -- Hardware method for detecting program or erase cycle completion Hardware reset pin (RESET#) -- Hardware method of resetting the internal state machine to the read mode WP#/ACC input pin -- Write protect (WP#) function protects sectors 0, 1, 140, and 141, regardless of sector protect status -- Acceleration (ACC) function accelerates program timing Sector protection -- Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector -- Temporary Sector Unprotect allows changing data in protected sectors in-system Power dissipation -- Operating: 25 mA maximum -- Standby: 150 A maximum -- Deep power-down standby: 10 A CE1s# and CE2s Chip Select Power down features using CE1s# and CE2s Data retention supply voltage: 2.7 to 3.1 volt Byte data control: LB#s (DQ7-DQ0), UB#s (DQ15-DQ8) FCRAM Features SRAM Features Power dissipation -- Operating: 30 mA maximum -- Standby: 15A maximum CE1s# and CE2s Chip Select Power down features using CE1s# and CE2s Data retention supply voltage: 1.5 to 3.1 volt Byte data control: LB#s (DQ7-DQ0), UB#s (DQ15-DQ8) SOFTWARE FEATURES Data Management Software (DMS) This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 26829 Rev: A Amendment/0 Issue Date: October 25, 2002 Refer to AMD's Website (www.amd.com) for the latest information. PRELIMINARY GENERAL DESCRIPTION Am29DL640G Features The Am29DL640G is a 64 megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. Word mode data appears on DQ15-DQ0; byte mode data appears on DQ7-DQ0. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 70 or 85 ns and is offered in a 93-ball FBGA package. Standard control pins--chip enable (CE#f), write enable (WE#), and output enable (OE#)--control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (programmed through AMD's ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi Sector as a one-time programmable area. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This i s an a d v a nt a g e c o m p a r e d to s y s t e m s w h e r e user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory devices), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD provides this software to simplify system design and software integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device status bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks, two 8 Mb banks with small and large sectors, and two 24 Mb banks of large sectors only. Sector addresses are fixed, system software can be used to form user-defined bank groups. During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. The device can improve overall system performance by allowing a host sy stem to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The Am29DL640G can be organized as both a top and bottom boot sector configuration. Bank Bank 1 Bank 2 Bank 3 Bank 4 Megabits 8 Mb 24 Mb 24 Mb 8 Mb Sector Sizes Eight 8 Kbyte/4 Kword, Fifteen 64 Kbyte/32 Kword Forty-eight 64 Kbyte/32 Kword Forty-eight 64 Kbyte/32 Kword Eight 8 Kbyte/4 Kword, Fifteen 64 Kbyte/32 Kword The SecSiTM (Secured Silicon) Sector is an extra 256 byte sector capable of being permanently locked by AMD or customers. The SecSi Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. 2 AM55DL128C8G October 25, 2002 PRELIMINARY TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5 Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7 Special Package Handling Instructions .................................... 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 MCP Device Bus Operations . . . . . . . . . . . . . . . . 10 FCRAM Power Down Program . . . . . . . . . . . . . . . 12 Table 2. Basic Key Table ................................................................12 Table 3. Available Key Table ..........................................................12 Reading Toggle Bits DQ6/DQ2 ............................................... 34 DQ5: Exceeded Timing Limits ................................................ 34 DQ3: Sector Erase Timer ....................................................... 34 Table 14. Write Operation Status ................................................... 35 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 36 Figure 8. Maximum Negative Overshoot Waveform ...................... 36 Figure 9. Maximum Positive Overshoot Waveform........................ 36 Flash DC Characteristics . . . . . . . . . . . . . . . . . . 37 CMOS Compatible .................................................................. 37 Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ............................................................. 40 Figure 11. Typical ICC1 vs. Frequency ............................................ 40 Flash Device Bus Operations . . . . . . . . . . . . . . . 13 Requirements for Reading Array Data ................................... 13 Writing Commands/Command Sequences ............................ 13 Accelerated Program Operation .......................................... 13 Autoselect Functions ........................................................... 13 Simultaneous Read/Write Operations with Zero Latency ....... 13 Automatic Sleep Mode ........................................................... 14 RESET#: Hardware Reset Pin ............................................... 14 Output Disable Mode .............................................................. 14 Table 4. Am29DL640G Sector Architecture ....................................15 Table 5. Bank Address ....................................................................18 Table 6. SecSi Sector Addresses ...............................................18 Table 7. Am29DL640G Boot Sector/Sector Block Addresses for Protection/Unprotection ........................................................................19 MCP Test Conditions . . . . . . . . . . . . . . . . . . . . . . 41 Figure 12. Test Setup.................................................................... 41 Figure 13. Input Waveforms and Measurement Levels ................. 41 MCP AC Characteristics . . . . . . . . . . . . . . . . . . . 42 CE#s Timing ........................................................................... 42 Figure 14. Timing Diagram for Alternating Between SRAM to Flash or FCRAM ............................................................. 42 Flash AC Characteristics . . . . . . . . . . . . . . . . . . 43 Flash Read-Only Operations ................................................. 43 Figure 15. Read Operation Timings ............................................... 43 Hardware Reset (RESET#) .................................................... 44 Figure 16. Reset Timings ............................................................... 44 Write Protect (WP#) ................................................................ 19 Table 8. WP#/ACC Modes ..............................................................20 Erase and Program Operations .............................................. 45 Figure 17. Program Operation Timings.......................................... Figure 18. Accelerated Program Timing Diagram.......................... Figure 19. Chip/Sector Erase Operation Timings .......................... Figure 20. Back-to-back Read/Write Cycle Timings ...................... Figure 21. Data# Polling Timings (During Embedded Algorithms). Figure 22. Toggle Bit Timings (During Embedded Algorithms)...... Figure 23. DQ2 vs. DQ6................................................................. 46 46 47 48 48 49 49 Temporary Sector Unprotect .................................................. 20 Figure 1. Temporary Sector Unprotect Operation........................... 20 Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 21 SecSiTM (Secured Silicon) Sector Flash Memory Region ............................................................ 22 Figure 3. SecSi Sector Protect Verify.............................................. 23 Hardware Data Protection ...................................................... 23 Low VCC Write Inhibit ........................................................... 23 Write Pulse "Glitch" Protection ............................................ 23 Logical Inhibit ...................................................................... 23 Power-Up Write Inhibit ......................................................... 23 Common Flash Memory Interface (CFI) . . . . . . . 23 Flash Command Definitions . . . . . . . . . . . . . . . . 27 Reading Array Data ................................................................ 27 Reset Command ..................................................................... 27 Autoselect Command Sequence ............................................ 27 Enter SecSiTM Sector/Exit SecSi Sector Command Sequence .............................................................. 27 Word Program Command Sequence ..................................... 28 Unlock Bypass Command Sequence .................................. 28 Figure 4. Program Operation .......................................................... 29 Temporary Sector Unprotect .................................................. 50 Figure 24. Temporary Sector Unprotect Timing Diagram .............. 50 Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram ............................................................. 51 Alternate CE#f Controlled Erase and Program Operations .... 52 Figure 26. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings.......................................................................... 53 Read Cycle ............................................................................. 54 Figure 27. SRAM Read Cycle--Address Controlled...................... 54 Figure 28. SRAM Read Cycle ........................................................ 55 Write Cycle ............................................................................. 56 Figure 29. SRAM Write Cycle--WE# Control ................................ 56 Figure 30. SRAM Write Cycle--CE#1s Control ............................. 57 Figure 31. SRAM Write Cycle--UB#s and LB#s Control ............... 58 Chip Erase Command Sequence ........................................... 29 Sector Erase Command Sequence ........................................ 29 Erase Suspend/Erase Resume Commands ........................... 30 Figure 5. Erase Operation............................................................... 30 Flash Write Operation Status . . . . . . . . . . . . . . . . 32 Figure 6. Data# Polling Algorithm ................................................... 32 FCRAM AC CHaracteristics . . . . . . . . . . . . . . . . 59 Read Operation ...................................................................... 59 Write Operation ....................................................................... 60 Power Down and Power Down Program Parameters ............. 61 Other Timing Parameters ....................................................... 61 AC Test Conditions ................................................................. 62 Read Timing ........................................................................... 62 Figure 32. OE# Control Access...................................................... 62 DQ7: Data# Polling ................................................................. 32 DQ6: Toggle Bit I .................................................................... 33 Figure 7. Toggle Bit Algorithm......................................................... 33 FCRAM AC Characteristics .................................................... 63 Figure 33. CE#1 Control Access.................................................... Figure 34. Address after OE# Control Access ............................... Figure 35. Address Access after CE#1 Control Access................. Figure 36. CE#1 Control ................................................................ 63 63 64 64 DQ2: Toggle Bit II ................................................................... 34 October 25, 2002 AM55DL128C8G 3 PRELIMINARY Figure 37. WE# Control Single Write Operation ............................. 65 Figure 38. WE# Control Continuous Write Operation ..................... 65 Figure 39. Read/Write Timing CE#1 Control, Read Cycle First.............................................................................. 66 Figure 40. Read/Write Timing CE#1 Control, Write Cycle First.............................................................................. 66 Figure 41. Read (OE# Control)/Write (WE# Control) Timing, Read Cycle First.............................................................................. 67 Figure 42. Read (OE# Control)/Write (WE# Control) Timing, Write Cycle First.............................................................................. 67 Figure 43. Power Down Program Timing ........................................ 68 Figure 44. Power Down Program Timing ........................................ 68 Figure 45. Power Down Entry and Exit Timing ............................... 68 Figure 46. Power Up Timing #1 ...................................................... 69 Figure 47. Power Up Timing #2 ...................................................... 69 Figure 48. Standby Entry Timing after Read or Write ..................... 69 FCRAM Data Retention . . . . . . . . . . . . . . . . . . . . 70 Low VDD Characteristics ........................................................ 70 Figure 49. Data Retention Timing .................................................. 70 Flash Erase And Programming Performance . . Latchup Characteristics . . . . . . . . . . . . . . . . . . . . BGA Package Pin Capacitance . . . . . . . . . . . . . . Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 71 71 71 71 72 Figure 50. CE#1s Controlled Data Retention Mode....................... 72 Figure 51. CE2s Controlled Data Retention Mode......................... 72 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 73 FNA093--93-Ball Fine-Pitch Grid Array 10 x 10 mm ............. 73 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 74 4 AM55DL128C8G October 25, 2002 PRELIMINARY PRODUCT SELECTOR GUIDE Part Number Speed Options Standard Voltage Range: VCC = 2.7-3.1 V Flash Memory 70 70 70 30 85 85 85 40 70 70 70 40 AM55DL128C8G Pseudo SRAM 85 85 85 40 Max Access Time, ns CE#f Access, ns OE# Access, ns MCP BLOCK DIAGRAM VCCf A21 to A0 CE#f1 RESET #1 64 MBit Flash Memory #1 VSS RY/BY#1 DQ15 to DQ0 VCCf VSS A21 to A0 WP#/ACC RESET#2 CE#f2 RY/BY#2 64 MBit Flash Memory #2 DQ15 to DQ0 DQ15 to DQ0 VCCs/VCCQ VSS/VSSQ A21 to A0 PE# LB#s UB#s WE# OE# CE1#fc CE2fc 64 MBit Fast Cycle RAM DQ15 to DQ0 A18 to A0 8 MBit SRAM CE1#s CE2s DQ15 to DQ0 October 25, 2002 AM55DL128C8G 5 PRELIMINARY FLASH MEMORY BLOCK DIAGRAM VCC VSS OE# BYTE# Mux A21-A0 Bank 1 Address Bank 1 Y-gate X-Decoder A21-A0 RY/BY# Bank 2 Address Bank 2 X-Decoder DQ15-DQ0 A21-A0 RESET# WE# CE# BYTE# WP#/ACC DQ15-DQ0 A0-A21 STATE CONTROL & COMMAND REGISTER Status DQ15-DQ0 Control DQ15-DQ0 DQ15-DQ0 Mux X-Decoder Bank 3 Address Bank 3 Y-gate X-Decoder A21-A0 Mux Bank 4 Address Bank 4 6 AM55DL128C8G DQ15-DQ0 October 25, 2002 PRELIMINARY CONNECTION DIAGRAM 93-Ball FBGA Top View Flash 1 only A1 NC A10 NC Flash 2 only B1 NC B2 NC B3 VSS B4 C4 D4 E4 F4 A17 B5 C5 D5 E5 F5 CE#1s B6 NC B7 NC B8 NC B9 NC B10 NC FCRAM only Flash 1 and 2 shared Shared FCRAM & SRAM Shared RY/BY#2 CE#f2 C1 NC C2 NC C3 A7 C6 D6 E6 F6 NC C7 A8 C8 A11 C9 NC LB#s WP#/ACC WE# D2 A3 D3 A6 D7 A19 D8 A12 D9 A15 UB#s RESET#1 CE2FC E2 A2 E3 A5 E7 A9 E8 A13 E9 A21 A18 RY/BY#1 A20 F1 NC F2 A1 F3 A4 F7 A10 F8 A14 F9 NC F10 NC 2nd SRAM only G1 NC G2 A0 G3 VSS G4 DQ1 G5 VCCs G6 CE2s G7 DQ6 G8 PE#FC G9 A16 G10 NC H2 CE#f1 H3 OE# H4 DQ9 H5 DQ3 H6 DQ4 H7 DQ13 H8 DQ15 H9 VCCf J2 K2 NC J3 K3 DQ8 J4 DQ10 J5 VCCf J6 VCCFC J7 DQ12 J8 DQ7 J9 VSS CE1#FC DQ0 K4 DQ2 K5 DQ11 K6 NC K7 DQ5 K8 DQ14 K9 NC L1 NC L2 L3 L4 L5 VCCf L6 NC L7 NC L8 NC L9 NC L10 NC NC RESET#2 VSS M1 NC M10 NC Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. October 25, 2002 AM55DL128C8G 7 PRELIMINARY PIN DESCRIPTION A18-A0 A21-A19 DQ15-DQ0 CE#f1 CE#f2 OE# WE# RY/BY#1 RY/BY#2 UB#s LB#s RESET#1 RESET#2 WP#/ACC VCCf = 19 Address Inputs (Common) = 2 Address Inputs (Flash + FCRAM) = 16 Data Inputs/Outputs (Common) = Chip Enable 1 (Flash) = Chip Enable 2 (Flash) = Output Enable (Common) = Write Enable (Common) = Ready/Busy Output 1 (Flash 1) = Ready/Busy Output 2 (Flash 2) = Upper Byte Control (FCRAM + SRAM) = Lower Byte Control (FCRAM + SRAM) = Hardware Reset Pin, Active Low (Flash 1) = Hardware Reset Pin, Active Low (Flash 2) = Hardware Write Protect/ Acceleration Pin (Flash) = Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) = SRAM Power Supply = Device Ground (Common) = Pin Not Connected Internally = Chip Enabled #1 (FCRAM) = Chip Enable #2 (FCRAM) = Chip Enable #1 (SRAM) = Chip Enable #2 (SRAM) = FCRAM power supply = FCRAM power down enable LOGIC SYMBOL 19 A18-A0 A21-A19 CE#f1 CE#f2 CE#1FC CE2FC PE#FC CE#1s CE2s OE# WE# WP#/ACC RESET#1 RESET#2 UB#s LB#s RY/BY# DQ15-DQ0 16 or 8 VCCs VSS NC CE#1FC CE2FC CE#1s CE2s VCCFC PE#FC 8 AM55DL128C8G October 25, 2002 PRELIMINARY ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am55DL128 C 8 G 70 L T TAPE AND REEL T = 7 inches S = 13 inches TEMPERATURE RANGE L = Light Industrial (-30C to +85C) SPEED OPTION See "Product Selector Guide" on page 5 PROCESS TECHNOLOGY G = 0.17 m SRAM Device Density 8 = 8 Mbits FAST CYCLE RAM DEVICE DENSITY C = 64 Mbits AMD DEVICE NUMBER/DESCRIPTION AM55DL128C8G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Two Am29DL640G 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) FastCycle RAM and 8 Mbit (512K x 16 bit) SRAM Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Valid Combinations Order Number AM55DL128C8G70L AM55DL128C8G85L T, S T, S Package Marking M550000000 M550000001 October 25, 2002 AM55DL128C8G 9 PRELIMINARY MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1-2 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. 10 AM55DL128C8G October 25, 2002 PRELIMINARY Table 1. Operation Read from Active Flash Write to Active Flash Standby Deep Power-down Standby Output Disable Flash Hardware Reset Sector Protect 11 9 10 7, 9, 11 7, 10, 11 7, 9, 11 7, 10, 11 9 10 X CE#f CE#f Active Inactive (Note 3) L L H H Notes Device Bus Operations--Flash Word Mode, (Notes 1, 2, 3) Addr. AIN AIN X X X X X SADD, A6 = L, A1 = H, A0 = L SADD, A6 = H, A1 = H, A0 = L X LB#s UB#s X X X X X X X X X X X X X X RESET# H H VCC 0.3 V VCC 0.3 V H L WP#/ACC (Note 6) L/H 6 H H L/H L/H DQ7- DQ0 DOUT DIN High-Z High-Z High-Z High-Z DQ15- DQ8 DOUT DIN High-Z High-Z High-Z High-Z CE#1s CE2s CE#1FC CE2FC PE#FC OE# WE# H X H X H X NA L H X H X L X L H L NA H X L X H X H L X H X H L X L H H H X X H H H L H H H L H H H X X H H H X L H H H L H H H H X H L H X X H H H L X X H H 9 10 9 10 VCC 0.3 V VCC 0.3 V L H L H X X VID L/H DIN X Sector Unprotect Temporary Sector Unprotect L H X X VID 8 DIN X X X X L X L L H L L H L L H L L H X VID 8 DIN DOUT High-Z DOUT DOUT High-Z DIN DIN High-Z DOUT DOUT High-Z DOUT DOUT High-Z High-Z Read from SRAM H H L H H H H L H AIN H L L H X High-Z DOUT DIN High-Z DIN DOUT High-Z DOUT DOUT High-Z DOUT High-Z Write to SRAM H H L H H H H X L AIN H L L H X Read from FCRAM H H H X X L X L X L L H H L H AIN H L L H X Write to FCRAM H H H X H X L H H H L AIN Key (12) H L H VCC 0.3 V X Power Down Program 13 VCC 0.3 V H H L X X X H Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 9.0 0.5 V, X = Don't Care, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. 3. Do not apply CE#f1 or 2 = VIL, CE#1s = VIL and CE2s = VIH at the same time. All operations assume FCRAM is in standby. To put in Power Down program PE must be Low. To put in Power Down CE2 must be Low. Active flash is device being addressed. Don't care or open LB#s or UB#s. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the "Sector/Sector Block Protection and Unprotection" section. 8. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". If WP#/ACC = VHH, all sectors will be unprotected. Data will be retained in FCRAM. 9. 4. 5. 6. 10. Data will be lost in FCRAM. 11. CE# inputs on both flash devices may be held low for this operation. 12. See "Power Down Program Key Table" on p. 13 13. Valid for FCRAM only. 7. October 25, 2002 AM55DL128C8G 11 PRELIMINARY FCRAM POWER DOWN PROGRAM Definition KEY A0 Mode Select A8 A21 Area Select A20 A18 L L H H A21 L H L H A0 L L H H A20 L X X H A8 L H L H AREA BOTTOM (2) RESERVED RESERVED TOP (3) Mode NAP (4) RESERVED 16M Partial SLEEP (4, 5) Table 2. Mode NAP 16M Partial SLEEP A0 A8 Mode Select L L H L H L H H Basic Key Table A18 X L H X A21 Area Select X L H X A20 X L H X Data Retention Area None Bottom 16M only Top 16M only None Table 3. Notes: 1. Available Key Table The Power Down Program can be performed one time after compliance of Power-up timings and it should not be re-programmed after regular Read or Write. Unspecified addresses, A1 to A7, A9 to A17 and A19, can be either High or Low during the programming. The RESERVED key should not be used. 2. 3. 4. 5. BOTTOM area is from the lowest address location. TOP area is from the highest address location. NAP and SLEEP do not retain the data and Area Select is ignored. Default state. Power Down Program to this SLEEP mode can be omitted. 12 AM55DL128C8G October 25, 2002 PRELIMINARY FLASH DEVICE BUS OPERATIONS Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE#f and OE# pins to VIL. CE#f is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to the Flash Read-Only Operations table for timing specifications and to Figure 15 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. See "Write Protect (WP#)" on page 19 for related information. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15-DQ0. Standard read cycle timings apply in this mode. Refer to the Sector/Sector Block Protection and Unprotection and Autoselect Command Sequence sections for more information. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f to VIL, and OE# to VIH. For program operations, the CIOf pin determines whether the device accepts program data in bytes or words. Refer to "Flash Device Bus Operations" for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The "Word Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 4 indicates the address space that each sector occupies. Similarly, a "sector address" is the address bits required to uniquely select a sector. The "Flash Command Definitions" section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. The device address space is divided into four banks. A "bank address" is the address bits required to uniquely select a bank. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The Flash AC Characteristics section contains timing specification tables and timing diagrams for write operations. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 20 shows how read and write cycles may be initiated for simultaneous operation with zero latency. ICC6f and ICC7f in the table represent the current specifications for read-while-program and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE#f and RESET# pins are both held at VCC 0.3 V. (Note that this is a more restricted voltage range than V IH .) If CE#f and RESET# are held at V IH , but not October 25, 2002 AM55DL128C8G 13 PRELIMINARY within VCC 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3f in the table represents the standby current specification. ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.3 V, the device draws CMOS standby current (ICC4 f). If RESET# is held at VIL but not within VSS0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the MCP AC Characteristics tables for RESET# parameters and to Figure 16 for the timing diagram. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#f, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC5f in the table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. 14 AM55DL128C8G October 25, 2002 PRELIMINARY Table 4. Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 Bank 1 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 Am29DL640G Sector Architecture Sector Size (Kbytes/Kwords) 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x16) Address Range 00000h-00FFFh 01000h-01FFFh 02000h-02FFFh 03000h-03FFFh 04000h-04FFFh 05000h-05FFFh 06000h-06FFFh 07000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7FFFFh Sector Address A21-A12 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001xxx 0000010xxx 0000011xxx 0000100xxx 0000101xxx 0000110xxx 0000111xxx 0001000xxx 0001001xxx 0001010xxx 0001011xxx 0001100xxx 0001101xxx 0001101xxx 0001111xxx October 25, 2002 AM55DL128C8G 15 PRELIMINARY Table 4. Bank Sector SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 Bank 2 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Am29DL640G Sector Architecture (Continued) Sector Address A21-A12 0010000xxx 0010001xxx 0010010xxx 0010011xxx 0010100xxx 0010101xxx 0010110xxx 0010111xxx 0011000xxx 0011001xxx 0011010xxx 0011011xxx 0011000xxx 0011101xxx 0011110xxx 0011111xxx 0100000xxx 0100001xxx 0100010xxx 0101011xxx 0100100xxx 0100101xxx 0100110xxx 0100111xxx 0101000xxx 0101001xxx 0101010xxx 0101011xxx 0101100xxx 0101101xxx 0101110xxx 0101111xxx 0110000xxx 0110001xxx 0110010xxx 0110011xxx 0100100xxx 0110101xxx 0110110xxx 0110111xxx 0111000xxx 0111001xxx 0111010xxx 0111011xxx 0111100xxx 0111101xxx 0111110xxx 0111111xxx Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x16) Address Range 80000h-87FFFh 88000h-8FFFFh 90000h-97FFFh 98000h-9FFFFh A0000h-A7FFFh A8000h-AFFFFh B0000h-B7FFFh B8000h-BFFFFh C0000h-C7FFFh C8000h-CFFFFh D0000h-D7FFFh D8000h-DFFFFh E0000h-E7FFFh E8000h-EFFFFh F0000h-F7FFFh F8000h-FFFFFh F9000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 16 AM55DL128C8G October 25, 2002 PRELIMINARY Table 4. Bank Sector SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 Bank 3 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 Am29DL640G Sector Architecture (Continued) Sector Address A21-A12 1000000xxx 1000001xxx 1000010xxx 1000011xxx 1000100xxx 1000101xxx 1000110xxx 1000111xxx 1001000xxx 1001001xxx 1001010xxx 1001011xxx 1001100xxx 1001101xxx 1001110xxx 1001111xxx 1010000xxx 1010001xxx 1010010xxx 1010011xxx 1010100xxx 1010101xxx 1010110xxx 1010111xxx 1011000xxx 1011001xxx 1011010xxx 1011011xxx 1011100xxx 1011101xxx 1011110xxx 1011111xxx 1100000xxx 1100001xxx 1100010xxx 1100011xxx 1100100xxx 1100101xxx 1100110xxx 1100111xxx 1101000xxx 1101001xxx 1101010xxx 1101011xxx 1101100xxx 1101101xxx 1101110xxx 1101111xxx Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x16) Address Range 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-28FFFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2FFFFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh October 25, 2002 AM55DL128C8G 17 PRELIMINARY Table 4. Bank Sector SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 Bank 4 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 Note:A21:A0 in word mode. Am29DL640G Sector Architecture (Continued) Sector Address A21-A12 1110000xxx 1110001xxx 1110010xxx 1110011xxx 1110100xxx 1110101xxx 1110110xxx 1110111xxx 1111000xxx 1111001xxx 1111010xxx 1111011xxx 1111100xxx 1111101xxx 1111110xxx 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111 Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 (x16) Address Range 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3F8FFFh 3F9000h-3F9FFFh 3FA000h-3FAFFFh 3FB000h-3FBFFFh 3FC000h-3FCFFFh 3FD000h-3FDFFFh 3FE000h-3FEFFFh 3FF000h-3FFFFFh Table 5. Bank 1 2 3 4 Bank Address A21-A19 000 001, 010, 011 100, 101, 110 111 Table 6. Device Am29DL640G SecSi Sector Addresses Sector Size 256 bytes (x16) Address Range 00000h-0007Fh 18 AM55DL128C8G October 25, 2002 PRELIMINARY Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term "sector" applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table 7). The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented via two methods. Table 7. Am29DL640G Boot Sector/Sector Block Addresses for Protection/Unprotection Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8-SA10 SA11-SA14 SA15-SA18 SA19-SA22 SA23-SA26 SA27-SA30 SA31-SA34 SA35-SA38 SA39-SA42 SA43-SA46 SA47-SA50 SA51-SA54 SA55-SA58 SA59-SA62 SA63-SA66 SA67-SA70 SA71-SA74 SA75-SA78 SA79-SA82 SA83-SA86 SA87-SA90 SA91-SA94 SA95-SA98 A21-A12 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX, 0000010XXX, 0000011XXX, 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX Sector/ Sector Block Size 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 192 (3x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes Sector SA99-SA102 SA103-SA106 SA107-SA110 SA111-SA114 SA115-SA118 SA119-SA122 SA123-SA126 SA127-SA130 SA131-SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 A21-A12 10111XXXXX 11000XXXXX 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX 11101XXXXX 11110XXXXX 1111100XXX, 1111101XXX, 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111101 1111111111 Sector/ Sector Block Size 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 192 (3x64) Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes Sector Protect/Sector Unprotect requires V ID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 25 shows the timing diagram. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. Note that the sector unprotect algorithm unprotects all sectors in parallel. All previously protected sectors must be individually re-protected. To change data in protected sectors efficiently, the temporary sector unprotect function is available. See "Temporary Sector Unprotect". The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD's ExpressFlashTM Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See the Sector/Sector Block Protection and Unprotection section for details. Write Protect (WP#) The Write Protect function provides a hardware method of protecting without using VID. This function is one of two provided by the WP#/ACC pin. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in sectors 0, 1, 140, and 141, independently of whether those sectors were protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". October 25, 2002 AM55DL128C8G 19 PRELIMINARY If the system asserts VIH on the WP#/ACC pin, the device reverts to whether sectors 0, 1, 140, and 141 were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Table 8. WP# Input Voltage Temporary Sector Unprotect (Note: For the following discussion, the term "sector" applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table 7). This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 24 shows the timing diagrams, for this feature. If the WP#/ACC pin is at VIL , sectors 0, 1, 140, and 141 will remain protected during the Temporary sector Unprotect mode. WP#/ACC Modes Device Mode VIL VIH VHH Disables programming and erasing in SA0, SA1, SA140, and SA141 Enables programming and erasing in SA0, SA1, SA140, and SA141 Enables accelerated programming (ACC). See "Accelerated Program Operation" on page 13. START RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected (If WP#/ACC = VIL, sectors 0, 1, 140, and 141 will remain protected). 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation 20 AM55DL128C8G October 25, 2002 PRELIMINARY START PLSCNT = 1 RESET# = VID Wait 1 s Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address START PLSCNT = 1 RESET# = VID Wait 1 s Temporary Sector Unprotect Mode No First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Wait 150 s Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Read from sector address with A6 = 0, A1 = 1, A0 = 0 No No First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Temporary Sector Unprotect Mode Increment PLSCNT Reset PLSCNT = 1 Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 No No PLSCNT = 25? Yes Data = 01h? Increment PLSCNT Yes No Yes No Read from sector address with A6 = 1, A1 = 1, A0 = 0 Set up next sector address Device failed Protect another sector? No Remove VID from RESET# PLSCNT = 1000? Yes Data = 00h? Yes Device failed Write reset command Last sector verified? Yes No Sector Protect Algorithm Sector Protect complete Sector Unprotect Algorithm Remove VID from RESET# Write reset command Sector Unprotect complete Figure 2. In-System Sector Protect/Unprotect Algorithms October 25, 2002 AM55DL128C8G 21 PRELIMINARY SecSiTM (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. AMD offers the device with the SecSi Sector either factor y locked o r custom er locka ble . Th e factory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a "1." The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to utilize the that sector in any manner they choose. The customer-lockable version has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a "0." Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the SecSi Sector Secure through a command sequence (see "Enter SecSiTM Sector/Exit SecSi Sector Command Sequence"). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. On power-up, or following a hardware reset, the device reverts to sending commands to the first 256 bytes of Sector 0. Factory Locked: SecSi Sector Programmed and Protected At the Factory In a factory locked device, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is preprogrammed with both a random number and a secure ESN. The 8-word random number will at addresses 000000h-000007h in word mode (or 000000h-00000Fh in byte mode). The secure ESN will be programmed in the next 8 words at addresses 000008h-00000Fh (or 000010h-000020h in byte mode). The device is available preprogrammed with one of the following: A random, secure ESN only Customer code through the ExpressFlash service Both a random, secure ESN and customer code through the ExpressFlash service. Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer's code, with or without the random ESN. The devices are then shipped from AMD's factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD's ExpressFlash service. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The SecSi Sector area can be protected using one of the following procedures: Write the three-cycle Enter SecSi Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, except that RESET# may be at either V IH or V ID . This allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. 22 AM55DL128C8G October 25, 2002 PRELIMINARY . Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE#f = VIH or WE# = VIH. To initiate a write cycle, CE#f and WE# must be a logical zero while OE# is a logical one. If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. START RESET# = VIH or VID Wait 1 s Write 60h to any address Power-Up Write Inhibit If WE# = CE#f = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. Remove VIH or VID from RESET# Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 9-12. To terminate reading CFI data, the system must write the reset command.The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 9-12. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies of these documents. Write reset command SecSi Sector Protect Verify complete Figure 3. SecSi Sector Protect Verify Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 13 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than V LKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE#f or WE# do not initiate a write cycle. October 25, 2002 AM55DL128C8G 23 PRELIMINARY Table 9. Addresses (Word Mode) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Query Unique ASCII string "QRY" CFI Query Identification String Description Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Table 10. Addresses (Word Mode) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h System Interface String Description VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) 24 AM55DL128C8G October 25, 2002 PRELIMINARY Table 11. Addresses (Word Mode) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 0017h 0002h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 007Dh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h Device Size = 2 byte Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) N Device Geometry Definition Description Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100) October 25, 2002 AM55DL128C8G 25 PRELIMINARY Table 12. Addresses (Word Mode) 40h 41h 42h 43h 44h 45h Data 0050h 0052h 0049h 0031h 0033h 0004h Query-unique ASCII string "PRI" Major version number, ASCII (reflects modifications to the silicon) Minor version number, ASCII (reflects modifications to the CFI table) Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 0002h 0001h 0001h 0004h 0077h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode Simultaneous Operation 00 = Not Supported, X = Number of Sectors (excluding Bank 1) Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 4Fh 0001h 00h = Uniform device, 01h = 8 x 8 Kbyte Sectors, Top And Bottom Boot with Write Protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom Program Suspend 0 = Not supported, 1 = Supported Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks Bank 1 Region Information X = Number of Sectors in Bank 1 Bank 2 Region Information X = Number of Sectors in Bank 2 Bank 3 Region Information X = Number of Sectors in Bank 3 Bank 4 Region Information X = Number of Sectors in Bank 4 Primary Vendor-Specific Extended Query Description 0000h 0000h 0085h 4Eh 0095h 50h 0001h 57h 0004h 58h 0017h 59h 0030h 5Ah 0030h 5Bh 0017h 26 AM55DL128C8G October 25, 2002 PRELIMINARY FLASH COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 13 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#f, whichever happens later. All data is latched on the rising edge of WE# or CE#f, whichever happens first. Refer to the MCP AC Characteristics section for timing diagrams. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset co m m an d re tur n s th at b a nk t o t he e ra se- suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the eras e-sus pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the section for more information. The Flash Read-Only Operations table provides the read parameters, and Figure 15 shows the timing diagram. Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of autoselect codes without reinitiating the command sequence. Table 13 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SADD). Table 4 shows the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. Enter SecSiTM Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi October 25, 2002 AM55DL128C8G 27 PRELIMINARY Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 13 shows the address and data requirements for both command sequences. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. See also "SecSiTM (Secured Silicon) Sector Flash Memory Region" for further information. cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1." Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 13 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (See Table 13). The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH any operation other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 4 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 17 for timing diagrams. Word Program Command Sequence The system may program the device by word. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 13 shows the address and data requirements for the byte program command sequence. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Flash Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from "0" back to a "1." Attempting to do so may 28 AM55DL128C8G October 25, 2002 PRELIMINARY Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 5 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams. START Write Program Command Sequence Embedded Program algorithm in progress Data Poll from System Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 13 shows the address and data requirements for the sector erase comm a n d s e q u e n c e . N o te t h a t th e S e c S i S e c to r, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 80 s occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 80 s, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than S e ct o r E ra se o r E ra s e S u s p en d d u r i n g th e time-out period resets that bank to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read Verify Data? No Yes No Increment Address Last Address? Yes Programming Completed Note: See Table 13 for program command sequence. Figure 4. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 13 shows the address and data requirements for the chip erase command sequence. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Flash Write Operation Status section for information on these status bits. October 25, 2002 AM55DL128C8G 29 PRELIMINARY data from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Flash Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 5 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams. just as in the standard Byte Program operation. Refer to the Flash Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. Refer to the Sector/Sector Block Protection and Unprotection and Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command (address bits are don't care). The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 80 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. Addresses are "don't-cares" when writing the Erase suspend command. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Flash Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, START Write Erase Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed Notes: 1. See Table 13 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 5. Erase Operation 30 AM55DL128C8G October 25, 2002 PRELIMINARY Table 13. Command Sequence 1 Read 6 Reset 7 Manufacturer ID Autoselect 8 Device ID 9 SecSi Sector Factory Protect 10 Sector/Sector Block Protect Verify 11 Word Word Word Word Word Word Word Word Cycles Am29DL640G Command Definitions Second Addr Data Bus Cycles (Notes 2-5) Third Fourth Addr Data Addr Data Fifth Addr Data Sixth Addr Data 1 1 4 6 4 4 3 4 4 3 2 2 6 6 1 1 1 First Addr Data RA RD XXX F0 555 555 555 555 555 555 555 555 XXX XXX 555 555 BA BA 55 AA AA AA AA AA AA AA AA A0 90 AA AA B0 30 98 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA PA XXX 2AA 2AA 55 55 55 55 55 55 55 55 PD 00 55 55 (BA)555 (BA)555 (BA)555 (BA)555 555 555 555 555 90 90 90 90 88 90 A0 20 (BA)X00 (BA)X01 01 7E (BA)X0E 02 (BA)X0F 01 (BA)X03 80/00 (SADD) 00/01 X02 Enter SecSi Sector Region Exit SecSi Sector Region Program Unlock Bypass Unlock Bypass Program 12 Unlock Bypass Reset 13 Chip Erase Sector Erase Erase Suspend 14 Erase Resume 15 CFI Query 16 XXX PA 00 PD Word Word 555 555 80 80 555 555 AA AA 2AA 2AA 55 55 555 SADD 10 30 Word Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE#f pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE#f pulse, whichever happens first. SADD = Address of the sector to be verified (in autoselect mode) or erased. Address bits A21-A12 uniquely select any sector. Refer to Table 4 for information on sector addresses. BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. Address bits A21-A19 select a bank. Refer to Table 5 for information on sector addresses. Notes: 1. See Tables 1-2 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15-DQ8 are don't care in command sequences, except for RD and PD. 5. Unless otherwise noted, address bits A21-A12 are don't cares for unlock and command cycles, unless SADD or PA is required. 6. No unlock or command cycles required when bank is reading array data. 7. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information). 8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or SecSi Sector factory protect information. Data bits DQ15-DQ8 are don't care. See the Autoselect Command Sequence section for more information. 9. 10. 11. 12. 13. 14. 15. 16. The device ID must be read across the fourth, fifth, and sixth cycles. The data is 80h for factory locked and 00h for not factory locked. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. The Unlock Bypass command is required prior to the Unlock Bypass Program command. The Unlock Bypass Reset command is required to return to the read mode when the bank is in the unlock bypass mode. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. Command is valid when device is ready to read array data or when device is in autoselect mode. October 25, 2002 AM55DL128C8G 31 PRELIMINARY FLASH WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 14 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ15-DQ0 (or DQ7-DQ0 for byte mode) on the following read cycles. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ15-DQ8 (DQ7-DQ0 in byte mode) while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ15-DQ0 may be still invalid. Valid data on DQ15-DQ0 (or DQ7-DQ0 for byte mode) will appear on successive read cycles. Table 14 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm. Figure 21 in the MCP AC Characteristics section shows the Data# Polling timing diagram. START Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5. Figure 6. Data# Polling Algorithm 32 AM55DL128C8G October 25, 2002 PRELIMINARY RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode. Table 14 shows the outputs for RY/BY#. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 14 shows the outputs for Toggle Bit I on DQ6. Figure 7 shows the toggle bit algorithm. Figure 22 in the "Flash AC Characteristics" section shows the toggle bit timing diagrams. Figure 23 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II. START DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE#f to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. Read Byte (DQ7-DQ0) Address =VA Read Byte (DQ7-DQ0) Address =VA Toggle Bit = Toggle? Yes No No DQ5 = 1? Yes Read Byte Twice (DQ7-DQ0) Address = VA Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Note: The system should recheck the toggle bit even if DQ5 = "1" because the toggle bit may stop toggling as DQ5 changes to "1." See the subsections on DQ6 and DQ2 for more information. Figure 7. Toggle Bit Algorithm October 25, 2002 AM55DL128C8G 33 PRELIMINARY DQ2: Toggle Bit II The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE#f to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 14 to compare outputs for DQ2 and DQ6. Figure 7 shows the toggle bit algorithm in flowchart form, and the section "DQ2: Toggle Bit II" explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 22 shows the toggle bit timing diagram. Figure 23 shows the differences between DQ2 and DQ6 in graphical form. not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 7). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1," indicating that the program or erase cycle was not successfully completed. The device may output a "1" on DQ5 if the system tries to program a "1" to a location that was previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a "1." Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a "0" to a "1." If the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is "1," the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0," the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 14 shows the status of DQ3 relative to the other status bits. Reading Toggle Bits DQ6/DQ2 Refer to Figure 7 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ15-DQ0 (or DQ7-DQ0 for byte mode) at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ15-DQ0 (or DQ7-DQ0 for byte mode) on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has 34 AM55DL128C8G October 25, 2002 PRELIMINARY Table 14. Status Embedded Program Algorithm Embedded Erase Algorithm Erase Erase-Suspend- Suspended Sector Read Non-Erase Suspended Sector Erase-Suspend-Program Write Operation Status DQ7 2 DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No toggle Data Toggle DQ5 1 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 2 No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0 Standard Mode Erase Suspend Mode Notes: 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. October 25, 2002 AM55DL128C8G 35 PRELIMINARY ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -55C to +125C Ambient Temperature with Power Applied . . . . . . . . . . . . . . -30C to +85C Voltage with Respect to Ground VCCf, VCCs (Note 1) . . . . . . . . . . . . -0.5 V to +4.0 V RESET# (Note 2) . . . . . . . . . . . .-0.5 V to +12.5 V WP#/ACC . . . . . . . . . . . . . . . . . .-0.5 V to +10.5 V All other pins (Note 1) . . . . . . -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot V SS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 8. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 9. 2. Minimum DC input voltage on pins RESET#, and WP#/ACC is -0.5 V. During volta ge tran sitions, WP#/ACC, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on pin RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. +0.8 V -0.5 V -2.0 V 20 ns 20 ns 20 ns Figure 8. Maximum Negative Overshoot Waveform 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns Figure 9. Maximum Positive Overshoot Waveform OPERATING RANGES Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . -30C to +85C VCCf/VCCs Supply Voltages VCCf/VCCs for standard voltage range . . 2.7 V to 3.1 V Operating ranges define those limits between which the functionality of the device is guaranteed. 36 AM55DL128C8G October 25, 2002 PRELIMINARY FLASH DC CHARACTERISTICS CMOS Compatible Parameter Symbol ILI ILIT ILO ILR ILIA Parameter Description Input Load Current RESET# Input Load Current Output Leakage Current Reset Leakage Current ACC Input Leakage Current Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; RESET# = 12.5 V VOUT = VSS to VCC, VCC = VCC max VCC = VCC max= 12.5 V VCC = VCC max, WP#/ACC = VACC max CE#f = VIL, OE# = VIH, Byte Mode CE#f = VIL, OE# = VIH, Word Mode 5 MHz 1 MHz 5 MHz 1 MHz 10 2 10 2 15 0.2 0.2 0.2 21 21 21 21 17 -0.2 2.4 8.5 Min Typ Max 1.0 35 1.0 35 35 16 4 16 4 30 5 5 5 45 45 45 45 35 0.8 VCC + 0.2 9.5 mA A A A mA mA mA Unit A A A A A ICC1f Flash VCC Active Read Current (Notes 1, 2) ICC2f ICC3f ICC4f ICC5f ICC6f ICC7f Flash VCC Active Write Current (Notes 2, 3) Flash VCC Standby Current 2 (Note 6) Flash VCC Reset Current 2 (Note 6) Flash VCC Current Automatic Sleep Mode (Notes 2, 4, 6) Flash VCC Active Read-While-Program Current (Notes 1, 2) Flash VCC Active Read-While-Erase Current (Notes 1, 2) Flash VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) Input Low Voltage Input High Voltage Voltage for WP#/ACC Program Acceleration and Sector Protection/Unprotection Voltage for Sector Protection, Autoselect and Temporary Sector Unprotect Output Low Voltage Output High Voltage Flash Low VCC Lock-Out Voltage 5 CE#f = VIL, OE# = VIH, WE# = VIL VCCf = VCC max, CE#f, RESET#, WP#/ACC = VCCf 0.3 V VCCf = VCC max, RESET# = VSS 0.3 V, WP#/ACC = VCCf 0.3 V VCCf = VCC max, VIH = VCC 0.3 V; VIL = VSS 0.3 V CE#f = VIL, OE# = VIH CE#f = VIL, OE# = VIH Byte Word Byte Word ICC8f VIL VIH VHH VID VOL VOH1 VOH2 VLKO CE#f = VIL, OE#f = VIH mA V V V 11.5 IOL = 4.0 mA, VCCf = VCCs = VCC min IOH = -2.0 mA, VCCf = VCCs = VCC min IOH = -100 A, VCC = VCC min 0.85 x VCC VCC-0.4 2.3 12.5 0.45 V V V 2.5 V Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. 6. Typical and maximum specification are double for MCP because there are 2 flash components. October 25, 2002 AM55DL128C8G 37 PRELIMINARY SRAM DC AND OPERATING CHARACTERISTICS Parameter Symbol ILI ILO ICC Parameter Description Input Leakage Current Output Leakage Current Operating Power Supply Current Test Conditions VIN = VSS to VCC CE#1s = VIH, CE2s = VIL or OE# = VIH or WE# = VIL, VIO= VSS to VCC IIO = 0 mA, CE#1s = VIL, CE2s = WE# = VIH, VIN = VIH or VIL Cycle time = 1 s, 100% duty, IIO = 0 mA, CE#1s 0.2 V, CE2 VCC - 0.2 V, VIN 0.2 V or VIN VCC - 0.2 V Cycle time = Min., IIO = 0 mA, 100% duty, CE#1s = VIL, CE2s = VIH, VIN = VIL = or VIH IOL = 2.1 mA IOH = -1.0 mA CE#1s = VIH, CE2 = VIL, Other inputs = VIH or VIL CE#1s VCC - 0.2 V, CE2 VCC - 0.2 V (CE#1s controlled) or CE2 0.2 V (CE2s controlled), CIOs = VSS or VCC, Other input = 0 ~ VCC -0.2 (Note 1) 2.2 2.4 0.3 Min -1.0 -1.0 Typ Max 1.0 1.0 3 Unit A A mA ICC1s Average Operating Current 3 mA ICC2s VOL VOH ISB Average Operating Current Output Low Voltage Output High Voltage Standby Current (TTL) 30 0.4 mA V V mA ISB1 Standby Current (CMOS) 15 A VIL VIH Input Low Voltage Input High Voltage 0.6 VCC+0.2 (Note 2) Notes: 1. Undershoot: -1.0 V in case of pulse width 20 ns. 2. VCC+1.0 V in case of pulse width 20 ns. 3. Undershoot and overshoot are samples and not 100% tested. 38 AM55DL128C8G October 25, 2002 PRELIMINARY FCRAM DC CHARACTERISTICS Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level Symbol ILI ILO VOH VOL IDDPS VCC Power Down Current IDDPN IDDP16 VCC= VCC max, IDDS VCC Standby Current IDDS1 IDDA1 VCC Active Current IDDA2 Input Low Voltage (Note 4) Input High Voltage (Note 5) Note: 1. All voltages are referenced to VSS. Test Conditions VIN = VSS to VDD VOUT= VSS to VCC, Output Disable VCC= VCC, IOH= -0.5mA IOL= 1mA SLEEP VCC= VCC max, VIN= VIH or VIL, CE2 0.2V NAP 16M Partial VIN= VIH or VIL CE1= CE2= VIH VIN 0.2V or VIN VCC-0.2V, CE1= CE2 VDD-0.2V VIN = VIH or VIL CE1= VIL and CE2= VIH, IOUT= 0mA TRC/TWC= minimum TRC/TWC= 1 A Min -1.0 -1.0 2.2 - - - - - Max +1.0 +1.0 - 0.4 10 65 85 1.5 Unit A A V V A A A mA - - - -0.3 2.2 150 25 3 0.5 A mA mA V V VIL VIH 2. 3. 4. 5. DC Characteristics are measured after the following POWER-UP timing. IOUT depends on the output load conditions. Minimum DC voltage on input or I/O pin are -0.3 V. During voltage transitions, inputs may negative overshoot VSS to -1.0 V for periods of up to 5 ns. Maximum DC voltage or Input and I/O pin are VDD+0.3 V. During voltage transitions, input may positive overshoot to VDD+1.0 V for periods of up to 5 ns. October 25, 2002 AM55DL128C8G 39 PRELIMINARY DC CHARACTERISTICS Zero-Power Flash 25 Supply Current in mA 20 15 10 5 0 0 500 1000 1500 2000 Time in ns 2500 3000 3500 4000 Note: Addresses are switching at 1 MHz Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) 12 3.3 V 10 2.7 V 8 Supply Current in mA 6 4 2 0 1 Note: T = 25 C 2 3 Frequency in MHz Figure 11. Typical ICC1 vs. Frequency 4 5 40 AM55DL128C8G October 25, 2002 PRELIMINARY MCP TEST CONDITIONS Table 15. 3.3 V Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) CL 6.2 k Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Test Specifications 70, 85 1 TTL gate 30 5 0.0-3.0 1.5 1.5 pF ns V V V Unit Device Under Test 2.7 k Note: Diodes are IN3064 or equivalent Figure 12. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS KS000010-PAL 3.0 V 0.0 V Input 1.5 V Measurement Level 1.5 V Output Figure 13. Input Waveforms and Measurement Levels October 25, 2002 AM55DL128C8G 41 PRELIMINARY MCP AC CHARACTERISTICS CE#s Timing Parameter Test Setup JEDEC -- Std tCCR Description CE#s Recover Time -- Min 0 ns All Speeds Unit CE#f tCCR CE1#s tCCR tCCR CE2s tCCR Figure 14. Timing Diagram for Alternating Between SRAM to Flash or FCRAM 42 AM55DL128C8G October 25, 2002 PRELIMINARY FLASH AC CHARACTERISTICS Flash Read-Only Operations Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Std. tRC tACC tCE tOE tDF tDF tOH Description Read Cycle Time 1 Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Notes 1, 3) Output Enable to Output High Z (Notes 1, 3) Output Hold Time From Addresses, CE#f or OE#, Whichever Occurs First Read tOEH Output Enable Hold Time 1 Toggle and Data# Polling CE#f, OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Min Min Min Speed 70 70 70 70 30 16 16 0 0 10 85 85 85 85 40 Unit ns ns ns ns ns ns ns ns ns Notes: 1. Not 100% tested. 2. See Figure 12 and Table 15 for test specifications 3. Measurements performed by placing a 50 termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF . tRC Addresses CE#f tRH tRH OE# tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tOE tDF Addresses Stable tACC 0V Figure 15. Read Operation Timings October 25, 2002 AM55DL128C8G 43 PRELIMINARY FLASH AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std tReady tReady tRP tRH tRPD tRB Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Max Max Min Min Min Min All Speed Options 20 500 500 50 20 0 Unit s ns ns ns s ns Note: Not 100% tested. RY/BY# CE#f, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#f, OE# RESET# tRP Figure 16. Reset Timings 44 AM55DL128C8G October 25, 2002 PRELIMINARY FLASH AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC tAVAV tAVWL Std tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tOEPH tGHWL tWLEL tELWL tEHWH tWHEH tWLWH tWHDL tGHWL tWS tCS tWH tCH tWP tWPH tSR/W tWHWH1 tWHWH1 Description Write Cycle Time 1 Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE#f or OE# high during toggle bit polling Data Setup Time Data Hold Time Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time (CE#f to WE#) CE#f Setup Time WE# Hold Time (CE#f to WE#) CE#f Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Byte Programming Operation 2 Word Accelerated Programming Operation, Word or Byte 2 Sector Erase Operation 2 VCC Setup Time 1 Write Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Typ Typ Typ Min Min Max 7 4 0.4 50 0 90 s sec s ns ns Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ 30 30 0 5 s 40 0 20 0 0 0 0 0 35 40 0 45 70 70 0 15 45 Speed 85 85 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tWHWH1 tWHWH2 tWHWH1 tWHWH2 tVCS tRB tBUSY Notes: 1. Not 100% tested. 2. See the "Flash Erase And Programming Performance" section for more information. October 25, 2002 AM55DL128C8G 45 PRELIMINARY FLASH AC CHARACTERISTICS Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE#f tGHWL OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# Status DOUT tRB tWPH tWHWH1 PA PA Read Status Data (last two cycles) tCH A0h VCCf tVCS Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode. Figure 17. Program Operation Timings VHH WP#/ACC VIL or VIH tVHH tVHH VIL or VIH Figure 18. Accelerated Program Timing Diagram 46 AM55DL128C8G October 25, 2002 PRELIMINARY FLASH AC CHARACTERISTICS Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SADD 555h for chip erase Read Status Data VA tAH VA CE#f tGHWL OE# tWP WE# tCS tDS tDH Data 55h 30h 10 for Chip Erase In Progress Complete tCH tWPH tWHWH2 tBUSY RY/BY# tVCS VCCf tRB Notes: 1. SADD = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Flash Write Operation Status". 2. These waveforms are for the word mode. Figure 19. Chip/Sector Erase Operation Timings October 25, 2002 AM55DL128C8G 47 PRELIMINARY FLASH AC CHARACTERISTICS tWC Addresses Valid PA tRC Valid RA tWC Valid PA tWC Valid PA tAH tACC CE#f tCPH tCE tOE tCP OE# tOEH tWP WE# tWPH tDS tDH Data Valid In tGHWL tDF tOH Valid Out Valid In Valid In tSR/W WE# Controlled Write Cycle Read Cycle CE#f Controlled Write Cycles Figure 20. Back-to-back Read/Write Cycle Timings tRC Addresses VA tACC tCE CE#f tCH OE# tOEH WE# tOH DQ7 High Z VA VA tOE tDF Complement Complement True Valid Data High Z DQ0-DQ6 tBUSY RY/BY# Status Data Status Data True Valid Data Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 21. Data# Polling Timings (During Embedded Algorithms) 48 AM55DL128C8G October 25, 2002 PRELIMINARY FLASH AC CHARACTERISTICS tAHT Addresses tAHT tASO CE#f tOEH WE# tOEPH OE# tDH DQ6/DQ2 Valid Data Valid Status tAS tCEPH tOE Valid Status Valid Status Valid Data (first read) RY/BY# (second read) (stops toggling) Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Figure 22. Toggle Bit Timings (During Embedded Algorithms) Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete Erase Suspend Read DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f to toggle DQ2 and DQ6. Figure 23. DQ2 vs. DQ6 October 25, 2002 AM55DL128C8G 49 PRELIMINARY FLASH AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std tVIDR tVHH tRSP tRRB Description VID Rise and Fall Time (See Note) VHH Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min Min Min Min All Speed Options 500 250 4 4 Unit ns ns s s Note: Not 100% tested. VID RESET# VSS, VIL, or VIH tVIDR Program or Erase Command Sequence CE#f tVIDR VID VSS, VIL, or VIH WE# tRSP RY/BY# tRRB Figure 24. Temporary Sector Unprotect Timing Diagram 50 AM55DL128C8G October 25, 2002 PRELIMINARY FLASH AC CHARACTERISTICS VID VIH RESET# SADD, A6, A1, A0 Valid* Sector/Sector Block Protect or Unprotect Valid* Verify 40h Sector/Sector Block Protect: 150 s, Sector/Sector Block Unprotect: 15 ms Valid* Data 60h 60h Status 1 s CE#f WE# OE# * For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0, SADD = Sector Address. Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram October 25, 2002 AM55DL128C8G 51 PRELIMINARY FLASH AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 Std tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tWHWH1 Description Write Cycle Time 1 Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE#f Pulse Width CE#f Pulse Width High Programming Operation 2 Accelerated Programming Operation, Word or Byte 2 Sector Erase Operation 2 Byte Word Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ 40 30 5 s 7 4 0.4 s sec 40 40 0 0 0 0 45 Speed 70 70 0 45 45 85 85 Unit ns ns ns ns ns ns ns ns ns ns tWHWH1 tWHWH2 tWHWH1 tWHWH2 Notes: 1. Not 100% tested. 2. See the "Flash Erase And Programming Performance" section for more information. 52 AM55DL128C8G October 25, 2002 PRELIMINARY FLASH AC CHARACTERISTICS 555 for program 2AA for erase PA for program SADD for sector erase 555 for chip erase Data# Polling PA Addresses tWC tWH WE# tGHEL OE# tCP CE#f tWS tCPH tDS tDH Data tRH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase tAS tAH tWHWH1 or 2 tBUSY DQ7# DOUT RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SADD = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode. Figure 26. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings October 25, 2002 AM55DL128C8G 53 PRELIMINARY SRAM AC CHARACTERISTICS Read Cycle Parameter Symbol tRC tAA tCO1, tCO2 tOE tBA tLZ1, tLZ2 tBLZ tOLZ tHZ1, tHZ2 tBHZ tOHZ tOH Speed Description 70 Read Cycle Time Address Access Time Chip Enable to Output Output Enable Access Time LB#s, UB#s to Access Time Chip Enable (CE#1s Low and CE2s High) to Low-Z Output UB#, LB# Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB#s, LB#s Disable to High-Z Output Output Disable to High-Z Output Output Data Hold from Address Change Min Max Max Max Max Min Min Min Max Max Max Min 70 70 70 35 70 10 10 5 25 25 25 10 85 85 85 85 45 85 ns ns ns ns ns ns ns ns ns ns ns ns Unit tRC Address tOH Data Out Previous Data Valid tAA Data Valid Note: CE#1s = OE# = VIL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL Figure 27. SRAM Read Cycle--Address Controlled 54 AM55DL128C8G October 25, 2002 PRELIMINARY SRAM AC CHARACTERISTICS tRC Address tAA tCO1 tOH CE#1s CE2s tCO2 tOE tOLZ tBLZ tLZ tHZ OE# tOHZ Data Valid Data Out High-Z Figure 28. Notes: 1. WE# = VIH, if CIOs is low, ignore UB#s/LB#s timing. SRAM Read Cycle 2. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 3. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device interconnection. October 25, 2002 AM55DL128C8G 55 PRELIMINARY SRAM AC CHARACTERISTICS Write Cycle Parameter Symbol tWC tCw tAS tAW tBW tWP tWR tWHZ tDW tDH tOW Speed Description 70 Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write UB#s, LB#s to End of Write Write Pulse Time Write Recovery Time Write to Output High-Z Max Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Min Min min 20 30 0 5 25 35 ns ns ns Min Min Min Min Min Min Min Min 60 60 50 0 0 ns 70 60 0 70 70 60 85 85 70 ns ns ns ns ns ns ns Unit tWC Address tCW (See Note 1) tAW CE2s tCW (See Note 1) tWP (See Note 4) tAS (See Note 3) High-Z tWHZ Data Out Data Undefined tDW Data Valid tWR CE#1s WE# tDH High-Z tOW Data In Notes: 1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing. 2. tCW is measured from CE#1s going low to the end of write. 3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE#1s or WE# going high. 4. tAS is measured from the address valid to the beginning of write. 5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE#1s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE#1s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 29. SRAM Write Cycle--WE# Control 56 AM55DL128C8G October 25, 2002 PRELIMINARY SRAM AC CHARACTERISTICS tWC Address tAS (See Note 2 ) tCW (See Note 3) CE#1s tAW CE2s tBW tWP (See Note 5) WE# tDW Data In tDH tWR (See Note 4) UB#s, LB#s Data Valid Data Out High-Z High-Z Notes: 1. CE#1s controlled, if CIOs is low, ignore UB#s and LB#s timing. 2. tCW is measured from CE#1s going low to the end of write. 3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE#1s or WE# going high. 4. tAS is measured from the address valid to the beginning of write. 5. A write occurs during the overlap (tWP) of low CE#1s and low WE#. A write begins when CE#1s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE#1s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 30. SRAM Write Cycle--CE#1s Control October 25, 2002 AM55DL128C8G 57 PRELIMINARY SRAM AC CHARACTERISTICS tWC Address tCW (See Note 2) tAW CE2s UB#s, LB#s tCW (See Note 2) tBW tAS (See Note 4) tWP (See Note 5) tDW Data In tDH tWR (See Note 3) CE#1s WE# Data Valid Data Out High-Z High-Z Notes: 1. UB#s and LB#s controlled, CIOs must be high. 2. tCW is measured from CE#1s going low to the end of write. 3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE#1s or WE# going high. 4. tAS is measured from the address valid to the beginning of write. 5. A write occurs during the overlap (tWP) of low CE#1s and low WE#. A write begins when CE#1s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE#1s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 31. SRAM Write Cycle--UB#s and LB#s Control 58 AM55DL128C8G October 25, 2002 PRELIMINARY FCRAM AC CHARACTERISTICS Read Operation Parameter tRC tCE tOE tAA tOH tCLZ tOLZ tCLZ tOHZ tASC tASO tASO[ABS] tBSC tBSO tAX tCLAH tOHAH tCHAH tOHAH tCHBH tOHBH tCLOL tOLCH tCP tOP tOP[ABS] Notes: 1. The output load is 50pF. Description (Notes) Read Cycle Time Chip Enable Access Time (1, 3) Output Enable Time (1) Address Access Time (1, 4) Output Data Hold Time (1) CE#1FC Low to Output Low-Z (2) OE Low to Output Low-Z (2) CE#1FC High to Output High-Z (2) OE High to Output High-Z (2) Address Setup Time to CE#1FC Low (5) Address Setup Time to OE Low (3, 6, 7) LB#s/UB#s Setup Time to CE#1FC Low (5) LB#s/UB#s Setup Time to OE Low Address Invalid Time (4, 8) Address Hold Time from CE#1FC Low (4) Address Hold Time from OE Low (4, 9) Address Hold Time from CE#1FC High Address Hold Time from OE High LB#s/UB#s Hold Time from CE#1FC High LB#s/UB#s Hold Time from OE High CE#1FC Low to OE Low Delay Time (3, 6, 9, 10) OE Low to CE#1FC High Delay Time (9) CE#1FC High Pulse Width OE High Pulse Width (6, 7, 9, 10) Min Max Max Max Min Min Min Max Max Min Min Min Min Min Max Min Min Min Min Min Min Min Max Min Min Min Max Min Speed 70 70 65 40 65 5 5 0 20 20 -5 25 10 -5 10 5 70 45 -5 -5 -5 -5 1000 25 45 12 1000 25 12 85 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2. 3. The output load is 5pF. The tCE is applicable if OE is brought to Low before CE#1FC goes Low and is also applicable if actual value of both or either tASO or TCLOL is shorter than specified value. Applicable only to A14, A15 and A16 when both CE#1FC and OE are kept at Low for the address access. Applicable if OE is brought to Low before CE#1FC goes Low. The tASO, tCLOL (min) and tOP (min) are reference values when the access time is determined to tOE. If actual value of each parameter is shorter that specified minimum value, tOE become longer by the amount of subtracting actual value from specified 9. minimum value. For example, if actual tASO, tASO (actual), is shorter than specified minimum value, tASO (min), during OE control access (i.e., CE#1FC stays Low), the tOE become tOE (max) + tASO (min)-tASO (actual). 7. 8. The tASO[ABS] and tOP[ABS] is the absolute minimum value during OE control access. The tAX is applicable when all of two addresses among A14 to A16 are switched from previous state. If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC (min)- tCLOL (actual). 4. 5. 6. 10. Maximum value is applicable if CE#1FC is kept at Low. October 25, 2002 AM55DL128C8G 59 PRELIMINARY FCRAM AC CHARACTERISTICS Write Operation Parameter tWC tAS tAH tCS tCH tWS tWH tBS tBH tOES tOEH tOEH[ABS] tOHCL tOHAH tCW tWP tWRC tWR tDS tDH tCP Notes: 1. 2. 3. Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR). New write address is valid from either CE#1 or WE is bought to High. The tOEH is specified from end of tWC(min). The tOEH (min) is a reference value when the access time is determined by tOE. If actual value, tOEH (actual) is shorter than specified minimum value, tOE become longer by the amount of subtracting actual value from specified minimum value. The tOEH (max) is applicable if CE#1 is kept at Low and both WE and OE# are kept at High. The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE#1 stays Low 7. 8. 9. 6. tOHCL (min) must be satisfied if read operation is not performed prior to write operation. In case OE# is disabled after tOHCL (min), WE Low must be asserted after tRC (min) from CE#1 Low. In other words, read operation is initiated if tOHCL (min) is not satisfied. Applicable if CE#1 stays Low after read operation. tCW and tWP is applicable if write operation is initiated by CE#1 and WE, respectively. tWRC and tWR is applicable if write operation is terminated by CE#1 and WE, respectively. The tWR (min) can be ignored if CE#1 is brought to High together or after WE is brought to High. In such case, the tCP (min) must be satisfied. Description (Notes) Write Cycle Time (1) Address Setup Time (2) Address Hold Time (2) Address Access Time CE#1FC Write Setup Time CE#1FC Write Hold Time WE# Setup Time WE# Hold Time LB#s and UB#s Setup Time LB#s and US Hold Time (3) OE# Hold Time (3, 4, 5) OE# High to CE#1FC Low Setup Time (6) OE# High to Address Hold Time (7) CE#1FC Write Pulse Width (1, 8) WE# Write Pulse Width (1, 8) CE#1FC Write Recovery Time (1, 9) WE# Write Recovery Time (1, 3 ,9) Data Setup Time Data Hold Time CE#1FC High Pulse (9) Min Min Max Min Max Min Max Min Min Min Min Max Min Max Min Min Min Min Min Min Max Min Min Min Min Min Min Speed 70 70 0 65 35 40 0 65 0 0 0 0 20 -5 20 -5 25 12 -5 -5 45 5 45 10 10 15 0 12 85 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4. 5. 60 AM55DL128C8G October 25, 2002 PRELIMINARY FCRAM AC CHARACTERISTICS Power Down and Power Down Program Parameters Parameter tCSP tC2LP tCHH tCHHN tCHS tEPS tEP tEPH tEAS tEAH Note: 1. Applicable to Power Down Program Description (Notes) CE2 Low Setup for Power Down Entry CE2 Low Hold Time after Power Down Entry CE#1FC High Hold Time following CE2 High after Power Down Exit [SLEEP mode only] CE#1FC High Hold Time following CE2 High after Power Down Exit [Except for SLEEP mode] CE#1FC High Setup Time following CE2 High after Power Down Exit CE#1FC High to PE Low Setup Time (1) PE Pulse Width (1) PE High to CE#1FC Low Hold Time (1) Address Setup Time to PE High (1) Address Hold Time from PE High (1) Min Min Min Min Min Min Min Min Min Min Speed 70 10 70 350 1 10 70 70 70 15 0 85 Unit ns ns s s ns ns ns ns ns ns Other Timing Parameters Parameter tCHOX tCHWX tC2LH tC2HL tCHH tT Notes: 1. Description (Notes) CE#1FC High to OE# Invalid Time for Standby Entry CE#1FC High to WE# Invalid Time for Standby Entry (1) CE2 Low Hold Time after Power-up (2) CE2 High Hold Time after Power-up (3) CE#1FC High Hold Time following CE2 High after Power-up (2) Input Transition Time (4) Min Min Min Min Min Min Max Speed 70 7 7 50 50 350 1 25 85 Unit ns ns s s s ns 2. 3. 4. Some data might be written into any address location if tCHWX (min) is not satisfied. Must satisfy tCHH (min) after tC2LH (min). Requires Power Down mode entry and exit after tC2LH. The Input Transition Time (tT) at AC testing is 5n as shown in below. If actual tT is longer than 5 ns, it may violate AC specification of some timing parameters. October 25, 2002 AM55DL128C8G 61 PRELIMINARY FCRAM AC CHARACTERISTICS AC Test Conditions Symbol VIH VIL VREF tT Description Input High Level Input Low Level Input Timing Measurement Level Input Transition Time Test Setup Value 2.3 0.4 1.3 5 Unit V V V ns Between VIL and VIH Read Timing tRC tRC Addresses Valid Address tASO Valid Address tCE tOHAH tOHAH CE#1 tOLCH tCLOL OE# tASO tBSO tOE tOP tOE tOHBH tBSO tOHBH LB#/UB# tOLZ tOHZ tOH Output Valid tOLZ tOHZ tOH Output Valid DQ Figure 32. Notes: 1. 2. CE2, PE# and WE# must be High for entire read cycle. OE# Control Access Either or both LB# and UB# must be Low when both CE#1 and OE# are Low. 62 AM55DL128C8G October 25, 2002 PRELIMINARY FCRAM AC Characteristics tRC ADDRESS tASC CE#1 tCP Address Valid tCE tCHAH tASC tRC Address Valid tCE tCHAH OE# tBSC UB#, LB# tCHZ tCLZ DQ15-0 Valid Data Output Valid Data Output tOH tCLZ tCHZ tOH tCHBH tBSC tCHBH Figure 33. Notes: 1. 2. CE2, PE# and WE# must be High for entire read cycle. CE#1 Control Access Either or both LB# and UB# must be Low when both CE#1 and OE# are Low. tRC tRC Address Valid Address tRC Address tASO Valid Address tOLAH tAX Valid Address tAA tOHAH CE#1 OE# tBSO tOE tOHBH tOHZ LB#/UB# tOLZ tOH Output Valid tOH DQ Output Valid Figure 34. Notes: 1. 2. Address after OE# Control Access CE2, PE# and WE# must be High for entire read cycle. Either or both LB# and UB# must be Low when both CE#1 and OE# are Low. October 25, 2002 AM55DL128C8G 63 PRELIMINARY FCRAM AC CHARACTERISTICS tRC tRC Address Valid Address tRC Address tASC Valid Address tCLAH tAX Valid Address tAA tCHAH tCHZ CE#1 OE# tBSC tCE tOHBH LB#/UB# tCLZ tOH Output Valid tOH DQ Output Valid Figure 35. Notes: 1. Address Access after CE#1 Control Access CE2, PE# and WE# must be High for entire read cycle. 2. Either or both LB# and UB# must be Low when both CE#1 and OE# are Low. tWC Addresses Valid Address tAH tAS tAS CE#1 tWS tCW tWH tWRC tWS WE# tBS tBH tBS UB#, LB# tOHCL OE# tDS tDH DQ Input Valid Figure 36. Notes: 1. CE2 and PE# must be High for write cycle. CE#1 Control 64 AM55DL128C8G October 25, 2002 PRELIMINARY FCRAM AC CHARACTERISTICS tWC ADDRESS tOHAH tAS Address Valid tAH tCH CE#1 tOHCL WE# tBH tBS tBH tCS tWP tWR tCP tAS UB#, LB# tOES OE# tOHZ DQ15-0 tDS tDH Figure 37. Note:CE2 and PE# must be High for write cycle. WE# Control Single Write Operation tWC ADDRESS tOHAH tAS tAH tAS CE#1 tOHCL WE# tOHBH UB#, LB# tOES OE# tOHZ DQ15-0 tDS tDH tBS tBH tBS tCS tWP tWR Valid Data Input Figure 38. Note:CE2 and PE# must be High for write cycle. WE# Control Continuous Write Operation October 25, 2002 AM55DL128C8G 65 PRELIMINARY FCRAM AC CHARACTERISTICS tWC ADDRESS tCHAH tAS Write Address tAH tASC Read Address CE#1 tWH WE# tCHBH tCP tWS tCW tWH tWRC tWS tCLOL tBS tBH tBSO UB#, LB# tOHCL OE# tCHZ tOH DQ15-0 Read Data Input tDS tDH tOLZ Write Data Input Figure 39. Read/Write Timing CE#1 Control, Read Cycle First Note:Write address is valid from either CE#1 or WE# of last falling edge. tRC ADDRESS tASO CE#1 Low Read Address Valid tOHAH tAS Write Address tWR WE# tBH UB#, LB# tOEH tBSO tOHBH tBS tOE OE# tDH DQ15-0 Write Data Input tOLZ tOES tOHZ tOH Read Data Output Figure 40. Read/Write Timing CE#1 Control, Write Cycle First Note:The tOEH is specified from the time satisfied both tWRC and tWR (min). 66 AM55DL128C8G October 25, 2002 PRELIMINARY FCRAM AC CHARACTERISTICS tWC ADDRESS tOHAH CE#1 tAS Write Address tAH tASO Read Address Low tWP WE# tOHBH tBS tWR tOEH tBH tBSO UB#, LB# tOES OE# tOHZ tOH DQ15-0 Read Data Output tDS tDH tOLZ Write Data Input Figure 41. Notes: 1. 2. Read (OE# Control)/Write (WE# Control) Timing, Read Cycle First CE#1 can be tied to Low for WE# and OE# controlled operation. When CE#1 is tied to Low, output is exclusively controlled by OE# tRC ADDRESS tASO CE#1 Low Read Address Valid tOHAH tAS Write Address tWR WE# tBH UB#, LB# tOEH tBSO tOHBH tBS tOE OE# tDH DQ15-0 Write Data Input tOLZ tOES tOHZ tOH Read Data Output Figure 42. Notes: 1. 2. Read (OE# Control)/Write (WE# Control) Timing, Write Cycle First CE#1 can be tied to Low for WE# and OE# controlled operation. When CE#1 is tied to Low, output is exclusively controlled by OE# October 25, 2002 AM55DL128C8G 67 PRELIMINARY FCRAM AC CHARACTERISTICS CE#1 tEPS PE# tEAS Address A21-A16 Key tEAH tEP tEPH Figure 43. Notes: 1. 2. CE2 must be High for Power Down Program operation. Power Down Program Timing Any other inputs not specified above can be either High or Low. CE#1 tEPS PE# tEAS Address A21-A16 Key tEAH tEP tEPH Figure 44. Notes: 1. 2. CE2 must be High for Power Down Program operation. Power Down Program Timing Any other inputs not specified above can be either High or Low. CE#1 tCHS CE2 tCSP tC2LP High-Z tCHH (tCHHN ) DQ15 -DQ0 Power Down Entry Power Down Mode Power Down Exit Figure 45. Note: 1. Power Down Entry and Exit Timing This Power Down mode can be also used for Power up #2 below except that tCHHN can not be used at Power up timing. 68 AM55DL128C8G October 25, 2002 PRELIMINARY FCRAM AC CHARACTERISTICS CE#1 tCHS tC2LH CE2 tCHH VDD 0V VDD min Figure 46. Power Up Timing #1 Notes: 1. The tC2LH specifies after VDD reaches specified minimum level. CE#1 tCHS tC2HL CE2 tC2HL VDD 0V tCSP tC2LP tCHH VDD min Figure 47. Notes: 1. 2. Power Up Timing #2 The tC2LH specifies from CE2 Low to High transition after VDD reaches specified minimum level. CE#1 must be brought to High prior to or together with CE2 Low to High transition. CE#1 tCHOX tCHWX OE# WE# Active (Read) Standby Active (Write) Standby Figure 48. Standby Entry Timing after Read or Write Note:Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (min) period from either last address transition of A0, A1, and A2, or CE#1 Low to High transition. October 25, 2002 AM55DL128C8G 69 PRELIMINARY FCRAM DATA RETENTION Low VDD Characteristics Parameter VDR IDR Test Conditions CE#1 = CE2 VDD - 0.2V or, VDD Data Retention Supply Voltage CE#1 = CE2 = VIH VDD = VDR, VIN = VDD - 0.2 to VIH or VIL, CE#1 = CE2 = VIH, IOUT = 0 mA VDD Data Retention Supply Current VDD = VDR, VIN 0.2 or VIN VDD - 0.2, CE#1 = CE2 = VDD - 0.2, IOUT = 0 mA Data Retention Setup Time VDD = VDD at data retention entry Data Retention Recovery Time VDD = VDD after data retention VDD Voltage Transition Time Description Min. 2.5 - Max. 3.1 1.5 Unit V mA IDR1 tDRS tDRR v/t - 0 200 0.2 150 - - 0.2 A ns ns V/s tDRS 3.1V VDD 2.7V CE2 2.5V CE#1 > VDD-0.2V or V IH tDRR V/t V/t min 0.4V VSS Data Retention Mode Data bits must be in High-Z at data retention entry. Figure 49. Data Retention Timing 70 AM55DL128C8G October 25, 2002 PRELIMINARY FLASH ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Program Time Accelerated Byte/Word Program Time Word Program Time Chip Program Time (Note 3) Byte Mode Word Mode Typ 1 0.4 56 5 4 7 42 28 150 120 210 126 sec 84 Max 2 5 Unit sec sec s s s Excludes system level overhead (Note 5) Comments Excludes 00h programming prior to erasure (Note 4) Notes: 1. Typical program and erase times assume the following conditions: 25C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 13 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Description Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Min -1.0 V -1.0 V -100 mA Max 12.5 V VCC + 1.0 V +100 mA Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. BGA PACKAGE PIN CAPACITANCE Parameter Symbol CIN COUT CIN2 CIN3 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance WP#/ACC Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Typ TBA TBA TBA TBA Max TBA TBA TBA TBA Unit pF pF pF pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz. DATA RETENTION Parameter Description Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years October 25, 2002 AM55DL128C8G 71 PRELIMINARY SRAM DATA RETENTION Parameter Symbol VDR IDR tSDR tRDR Parameter Description VCC for Data Retention Data Retention Current Data Retention Set-Up Time Recovery Time Test Setup CS1#s VCC - 0.2 V 1 VCC = 3.0 V, CE#1s VCC - 0.2 V 1 See data retention waveforms 0 tRC Min 1.5 1.0 2 Typ Max 3.3 15 Unit V A ns ns Notes: 1. CE#1s VCC - 0.2 V, CE2s VCC - 0.2 V (CE#1s controlled) or CE2s 0.2 V (CE2s controlled), CIOs = VSS or VCC. 2. Typical values are not 100% tested. VCC 2.7V tSDR Data Retention Mode tRDR 2.2V VDR CE1#s GND Figure 50. CE1#s VCC - 0.2 V CE#1s Controlled Data Retention Mode Data Retention Mode VCC 2.7 V CE2s tSDR tRDR VDR 0.4 V GND Figure 51. CE2s < 0.2 V CE2s Controlled Data Retention Mode 72 AM55DL128C8G October 25, 2002 PRELIMINARY PHYSICAL DIMENSIONS FNA093--93-Ball Fine-Pitch Grid Array 10 x 10 mm PRELIMINARY October 25, 2002 AM55DL128C8G 73 PRELIMINARY REVISION SUMMARY Revision A (October 25, 2002) Initial release. Trademarks Copyright (c) 2002 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 74 AM55DL128C8G October 25, 2002 |
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