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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003
14-BIT, 48-KSPS, DATA ACQUISITION SYSTEM WITH ANALOG-TO-DIGITAL CONVERTER, MUX, PGA, AND REFERENCE
FEATURES D PGA Gains: 1, 2, 4, 5, 8, 10, 16, 20 V/V D Programmable Input (Up to 4-Channel D D D D D D D D D
Differential/Up to 8-Channel Single-Ended or Some Combination) 1.15-V, 2.048-V, or 2.5-V Internal Reference SPI/DSP Compatible Serial Interface (20 MHz) Throughput Rate: 48 kSamples/s Error Overload Indicator Programmable Output 2's Complement/Binary 2.7-V to 5.5-V Single Supply Operation 4-Bit Digital I/O Via Serial Interface Pin Compatible With ADS7870 SSOP-28 Package
APPLICATIONS D Portable Battery Powered Systems D Low Power Instrumentation D Low Power Control Systems D Smart Sensor Applications
The programmable-gain amplifier provides high input impedance, excellent gain accuracy, good commonmode rejection, and low noise. For many low-level signals, no external amplification or impedance buffering is needed between the signal source and the A/D input. The offset voltage of the PGA is auto zeroed. Gains of 1, 2, 4, 5, 8, 10, 16, and 20 V/V allow signals as low as 125 mV to produce full-scale digital outputs. The ADS7871 contains an internal reference, which is trimmed for high initial accuracy and stability vs temperature. Drift is typically 10 ppm/C. An external reference can be used in situations where multiple ADS7871s share a common reference. The serial interface allows the use of SPI, QSPI, Microwire, and 8051-family protocols, without glue logic.
BUFOUT/REFIN Oscillator CCLK OSC ENABLE
DESCRIPTION
The ADS7871 (US patents 6140872, 6060874) is a complete low-power data acquisition system on a single chip. It consists of a 4-channel differential/8-channel single-ended multiplexer, precision programmable gain amplifier, 14-bit successive approximation analog-todigital converter and a precision voltage reference.
VREF LN0 LN1 LN2 LN3 LN4 LN5 LN6 LN7
REF
BUFIN
MUX
+ PGA _
14-BIT A/D
BUSY CONVERT RESET RISE/FALL CS
I/O0 I/O1 I/O2 I/O3
Digital I/O
Registers
Serial Interface
SCLK DIN DOUT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002-2003, Texas Instruments Incorporated
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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003
SPECIFICATIONS
For the Total System (see Note 1), -40C TA 85C, VDD = 5 V, BUFIN = 2.5 V (using external reference), 2.5-MHz CCLK and 2.5-MHz SCLK (unless otherwise noted) PARAMETER Analog Input Input voltage (LNx inputs) Input capacitance (see Note 2) Input im edance (see In ut impedance Note 2) Common mode Differential VI = 2 Vpp, 60 Hz (see Note 3) Linear operation -0.2 4 to 9.7 6 7 100 100 14 G = 1 to 20 V/V G = 1 to 20 V/V G = 1 to 20 V/V G = 1 to 20 V/V Ratiometric configuration or external reference (see Note 4) Internal reference DC common-mode rejection ratio, RTI Power supply rejection ratio, RTI Dynamic Characteristics Continuous mode Throughput rate Address mode External clock, CCLK (see Note 5) Internal oscillator frequency Serial interface clock, SCLK Data setup time Data hold time Digital Inputs Low-level input voltage, VIL Logic levels High level input voltage VIH High-level voltage, Low-level input current, IIL High-level input current, IIH VDD 3.6 V VDD > 3.6 V 2 3 1 1 0.8 V V V A A 10 10 One channel Different channels 0.1 2.5 20 48 48 20 ksample/s MHz MHz MHz ns ns G = 1 to 10 V/V G = 16 and 20 V/V G = 1 to 10 V/V G = 16 and 20 V/V VI = -0.2 V to 5.2 V, G = 20 V/V VDD = 5 V 10%, G = 20 V/V 13 -4 -2 -24 -0.2 -0.25 -0.35 -0.4 80 88 2 0.5 1 4 4 24 0.2 0.25 0.35 0.4 M dB pA Bits Bits LSB LSB LSB %FSR %FSR %FSR %FSR dB dB VDD + 0.2 V pF TEST CONDITIONS MIN TYP MAX UNIT
Channel-to-channel crosstalk Maximum leakage current Static Accuracy Resolution No missing codes Integral linearity Differential linearity Offset error
Full-scale gain error
NOTES: 1. The specifications for the total system are overall analog input to digital output specifications. The specifications for internal functions indicate the performance of the individual functions in the ADS7871. 2. The ADS7871 uses switched capacitor techniques for the programmable gain amplifier and A/D converter. A characteristic of such circuits is that the input capacitance at any selected LNx pin changes during the conversion cycle. 3. One channel ON with its inputs grounded. All other channels OFF with sinewave voltage applied to their inputs. 4. Ratiometric configuration exists when the input source is configured such that changes in the reference cause corresponding changes in the input voltage. The same accuracy applies when a perfect external reference is used. 5. The CCLK is divided by the DF value specified by the contents of register 3, A/D Control register, bits D0 and D1 to produce DCLK. The maximum value of DCLK is 2.5 MHz.
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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003
SPECIFICATIONS
For the Total System (see Note 1), -40C TA 85C, VDD = 5 V, BUFIN = 2.5 V (using external reference), 2.5-MHz CCLK and 2.5-MHz SCLK (unless otherwise noted) PARAMETER Digital Outputs Data coding Low-level Low level output voltage VOL voltage, Logic levels High-level High level output voltage VOH voltage, Leakage current Output capacitance Voltage Reference Bandga Bandgap voltage reference Output drive Reference Buffer Input voltage, BUFIN Input impedance, BUFIN Input offset Out ut Output voltage accuracy vs temperature, tem erature, BUFOUT/REFIN (see Notes 6 and 7) Output drive, BUFOUT/REFIN Power Supply Requirements Supply voltage 1-kHz Sample rate Power supply current (see Note 6) 48-kHz Sample rate Power down 1-kHz Sample rate Power dissipation (see Note 6) 48-kHz Sample rate Power down Temperature Range Operating free-air Storage range -40 -65 85 150 C C REF and BUF on, Internal oscillator on REF and BUF on, External CCLK REF, BUF, and internal oscillator off REF and BUF on, Internal oscillator on REF and BUF on, External CCLK REF and BUF off -6 8.5 11 5 2.7 1.2 1.7 2 1 5.5 V mA mA A mW mW W Pin 28 used as out ut, output, Vref = 2.048 V and 2.5 V At pin 27 -10 -0.25 0.9 1000||3 1 0.05 10 20 10 0.25 50 VDD - 0.2 V G||pF mV %FSR ppm/C mA Vref = 2.048 V, 2.5 V Vref = 1.15 V Pin 26 used as output, Use internal OSC or external CCLK as conversion clock -0.25 0.05 1.15 0.6 0.25 %FSR V A Binary two's complement Isink = 5 mA Isink = 16 mA Isource = 0.5 mA Isource = 5 mA Hi-Z state, VO = 0 V to VDD 5 VDD - 0.4 4.6 1 0.4 0.8 V V A pF TEST CONDITIONS MIN TYP MAX UNIT
65 Thermal resistance, QJA C/W NOTES: 1. The specifications for the total system are overall analog input to digital output specifications. The specifications for internal functions indicate the performance of the individual functions in the ADS7871. 6. REF and BUF contribute 190 mA and 150 mA (950 mW and 750 mW) respectively. At initial power up the default condition for both REF and BUF functions is power off. They can be turned on under software control by writing a 1 to D3 and D2 of register 7, REF/OSCILLATOR CONTROL register. 7. For VDD < 3 V, Vref = 2.5 V is not usable.
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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003
SPECIFICATIONS
For Internal Functions (see Note 1), -40C TA 85C, VDD = 5 V, BUFIN = 2.5 V (using external reference), 2.5-MHz CCLK and 2.5-MHz SCLK (unless otherwise noted) PARAMETER Multiplexer On resistance Off resistance Off channel leakage current On channel = 5.2 V, Off channel = 0 V On channel = 0 V, Off channel = 5.2 V On channel = 5.2 V, Off channel = 0 V On channel = 0 V, Off channel = 5.2 V VLNx = 5.2 V 100 1 100 100 100 100 G pA pA pA pA TEST CONDITIONS MIN TYP MAX UNIT
On channel leakage current PGA Amplifier
Input capacitance (see Note 2) In ut impedance Input im edance (see Note 2) Offset voltage Small signal bandwidth G=1 Settling time Analog-To-Digital Converter DC Characteristics Resolution Integral linearity error Differential linearity error No missing codes Offset error Full-scale (gain) error Common mode rejection, RTI of A/D Power supply rejection, RTI of ADS7871 PGA Plus A/D Converter Sampling Dynamics Throughput rate Conversion time Acquisition time Auto zero time Aperture delay Small signal bandwidth Step response External reference, VDD = 5 V 10% fCCLK = 2.5 MHz, DF = 1 50 CCLK cycles 14 CCLK cycles 28 CCLK cycles 8 CCLK cycles 36 CCLK cycles REFIN = 2.5 V G = 20 Common mode Differential
4 to 9.7 6 7 100 5/Gain 0.3 6.4 14 2 0.5 14 2 0.02 60 60 50 5.6 9.6 3.2 12.8 5 1 Complete Conversion Cycle
pF M M V MHz s s LSB LSB LSB Bits LSB % dB dB kHz s s s s MHz
NOTES: 1. The specifications for the total system are overall analog input to digital output specifications. The specifications for internal functions indicate the performance of the individual functions in the ADS7871. 2. The ADS7871 uses switched capacitor techniques for the programmable gain amplifier and A/D converter. A characteristic of such circuits is that the input capacitance at any selected LNx pin changes during the conversion cycle.
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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
MODEL ADS7871IDB ADS7871IDB PACKAGE TYPE SSOP-28 Surface mount SSOP-28 Surface mount PACKAGE DRAWING NUMBER 324 324 TEMPERATURE RANGE -40C to 85C -40C to 85C PACKAGE MARKING ADS7871 ADS7871 ORDERING NUMBER ADS7871IDB ADS7871IDBR TRANSPORT MEDIA Rails (48) Tape and reel (1000)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Analog inputs: Input current, momentary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.5 V to GND - 0.5 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Junction temperature (TJ max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Lead temperature, soldering: (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PIN ASSIGNMENTS
SSOP-28 PACKAGE (TOP VIEW)
LN0 LN1 LN2 LN3 LN4 LN5 LN6 LN7 RESET RISE/FALL I/O0 I/O1 I/O2 I/O3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
BUFOUT/REFIN BUFIN VREF GND VDD CS DOUT DIN SCLK CCLK OSC ENABLE BUSY CONVERT GND
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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003
Terminal Functions
TERMINAL NO. 1-8 9 10 11-14 15 16 17 18 19 20 21 22 23 NAME LN0-LN7 RESET RISE/FALL I/O0-I/O3 GND CONVERT BUSY OSC ENABLE CCLK SCLK DIN DOUT CS I/O AI DI DI DIO - DI DO DI DIO DI DIO DO DI MUX input lines 0-7 Master reset, zeros all registers Sets the active edge for SCLK. 0 sets SCLK active on falling edge. 1 sets SCLK active on rising edge. Digital input or output signal Connect to ground. (this pin is grounded internally on the ADS7871. It has a weak pulldown on the ADS7870). 0 to 1 transition starts a conversion cycle. 1 indicates converter is busy 0 sets CCLK as an input, 1 sets CCLK as an output and turns the oscillator on. If OSC ENABLE = 1, then the internal oscillator is output to this pin. If OSC ENABLE = 0, then this is the input pin for an external conversion clock. Serial data input/output transfer clock. Active edge set by the RISE/FALL pin. If RISE/FALL is low, SCLK is active on the falling edge. Serial data input. In the 3-wire mode, this pin is used for serial data input. In the 2-wire mode, serial data output appears on this pin as well as the DOUT pin. Serial data output. This pin is driven when CS is low and is high impedance when CS is high. This pin behaves the same in both 3-wire and 2-wire modes. Chip select. When CS is low, the serial interface is enabled. When CS is high, the serial interface is disabled, the DOUT pin is high impedance, and the DIN pin is an input. The CS pin only affects the operation of the serial interface. It does not directly enable/disable the operation of the signal conversion process. Power supply voltage, 2.7 V to 5.5 V Power supply ground 2.048-/2.5-V On-chip voltage reference Input to reference buffer amplifier Output from reference buffer amplifier and reference input to ADC DESCRIPTION
24 25 26 27 28
VDD GND VREF BUFIN BUFOUT/REFIN
- - AO AI AIO
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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003
TYPICAL PERFORMANCE CURVES
GAIN ERROR vs FREE-AIR TEMPERATURE
16 12 8 4 0 -4 -8 -12 -16 -50 Offset Error - LSB Gain Error - LSB VDD = 5 V, CCLK = 2.5 MHz, REFIN = 2.5 V (ext) 16 12 8 Gain = 20 4 Gain = 1 0 -4 Gain = 8 Gain = 20 -8 -12 -16 -50 Gain = 1 Gain = 8 VDD = 5 V, CCLK = 2.5 MHz, REFIN = 2.5 V (ext)
OFFSET ERROR vs FREE-AIR TEMPERATURE
-25
0
25
50
75
100
125
TA - Free-Air Temperature - C
-25 0 25 50 75 TA - Free-Air Temperature - C
100
125
Figure 1
Figure 2
VOLTAGE REFERENCE ERROR vs FREE-AIR TEMPERATURE
0.0025 VDD = 5 V, CCLK = 2.5 MHz 0.0015 Voltage Reference Error - V Vbg 1.15 V 0.0005 0 -0.0005 BufVref 2.048 V Vref 2.048 V BufVref 2.5 V Vref 2.5 V -0.0025 -50 -25 0 25 50 75 100 TA - Free-Air Temperature - C 125 BufVbg 1.15 V Internal Oscillator Frequency - MHz 2.70 2.65 2.60 2.55 2.50
INTERNAL OSCILLATOR FREQUENCY vs FREE-AIR TEMPERATURE
VDD = 5 V
+3 sigma
Oscillator 2.45 2.40 2.35 2.30 -50 -3 sigma
-0.0015
-25
0 25 50 75 TA - Free-Air Temperature - C
100
125
Figure 3
Figure 4
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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003
TYPICAL PERFORMANCE CURVES
OUTPUT OFFSET ERROR vs COMMON-MODE VOLTAGE
24 VDD = 5 V, TA = 25C, CCLK = 2.5 MHz 8 6 Gain = 20 Gain = 8 Output Offset Error - LSB 4 2 0 -2 -4 -6 -8 0 1 2 3 Common-Mode Voltage - V 4 5 2.5 3 3.5 4 4.5 Power Supply Voltage - V 5 5.5 Vref = 2.048 V Vref = 2.5 V Gain = 20, TA = 25C, CCLK = 2.5 MHz
OUTPUT OFFSET ERROR vs POWER SUPPLY VOLTAGE
16 Output Offset Error - LSB
8
0
Gain = 1
-8
-16
-24
Figure 5
Figure 6
BUFFER OUTPUT CHARACTERISTIC
2.65 2.625 2.6 2.575 2.55 2.525 2.5 2.475 0.5 2.45 -20 -18 -16 -14 -12 -10 -8 -6 -4 IO - Output Current - mA -2 0 0 -2 ZO = 2 Sourcing Current, VDD = 5 V, REFIN = 2.5 V, TA = 25C 5.5 5 4.5 VO - Output Voltage - V 4 3.5 3 2.5 2 1.5 1
REFERENCE OUTPUT CHARACTERISTIC
VDD = 5 V, CCLK = 2.5 MHz, TA = 25C
VO - Output Voltage - V
-1.5
-1 -0.5 0 0.5 1 IO - Output Current - A
1.5
2
Figure 7
Figure 8
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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003
TYPICAL PERFORMANCE CURVES
TYPICAL INPUT RANGE
6 VI x GAIN PGA OUTPUT
4 Level-Shift Error 3 Input to A/D 2 Valid Bit = 1
-1 -6 -5 -4 -3 -2 -1 0
Differential Input Voltage - V
Figure 9
QUIESCENT CURRENT vs SAMPLING RATE
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 5 10 15 20 25 30 35 40 Sampling Rate - ks/s 45 50 0 0 5 SCLK = CCLK = 52 x Sampling Rate, VDD = 5 V, Vref and Buf on, OSC off, TA = 25C Peak-To-Peak Output Code Range IQ- Quiescent Current - mA 15 20
Figure 10
NOISE AND EFFECTIVE NUMBER OF BITS vs PGA GAIN
15 CCLK = 2.5 MHz, VDD = 5 V, TA = 25C 14 Effective Number of Bits 9
10
13
5 Vref = 2.5 V, Internal Ref + Buf, DC Input 10 PGA Gain 15
12
11 20
Figure 11
Figure 12
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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003
TYPICAL PERFORMANCE CURVES
INL
INL - Integral Nonlinearity - LSB
3 2 1 0 -1 -2 -3 0
1 F Cap on, BUFOUT/REFIN, VDD = 5 V, REFIN = 2.5 V, CCLK = 2.5 MHz, TA = 25C
2048
4096
6144
8192 Code
10240
12288
14336
16384
Figure 13
DNL - Differential Nonlinearity - LSB DNL 4 3 2 1 0 -1 -2 0 2048 4096 6144 8192 Code 10240 12288 14336 16384 VDD = 5 V, CCLK = 2.5 MHz, Vref = 2.5 V, TA = 25C
Figure 14
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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003
OVERVIEW
The ADS7871 is a complete data acquisition device composed of an input analog multiplexer (MUX), a programmable gain amplifier (PGA) and an analog-to-digital converter (A/D). Four lines of digital input/output (I/O) are also provided. Additional circuitry provides support functions including conversion clock, voltage reference, and serial interface for control and data retrieval. The ADS7871 is based on the ADS7870 and shares the same interface, functionality, and pinout. The exceptions are: pin 15 is now hard-wired to ground; the SAR conversion cycle takes 14 clocks rather than 12; and the output data has only one defined zero at bit 14 as opposed to three defined zeroes at bits 12, 13, and 14 in the ADS7870. Control and configuration of the ADS7871 is accomplished by command bytes written to internal registers through the serial port. Command Register device control includes MUX channel selection, PGA gain, A/D start conversion command, and I/O line control. Command register configuration control includes internal voltage reference setting and oscillator control. Operational modes and selected functions can be activated by digital inputs at corresponding pins. Pin settable configuration options include SCLK active-edge selection, master reset, and internal oscillator clock enable. The ADS7871 has eight analog signal input pins, LN0 through LN7. These pins are connected to a network of analog switches (the MUX block in Figure 15). The inputs can be configured as 8 single-ended or 4 differential inputs, or some combination. The four general-purpose digital I/O pins (I/O3 through I/O0) can be made to function individually as either digital inputs or digital outputs. These pins give the user access to four digital I/O pins through the serial interface without having to run additional wires to the host controller. The programmable gain amplifier (PGA) provides gains of 1, 2, 4, 5, 8, 10, 16, and 20 V/V. The 14-bit A/D converter in the ADS7871 is a successive approximation type. The default output of the converter is 2's complement format and can be read in a variety of ways depending on the program configuration. The ADS7871's internal voltage reference can be software configured for output voltages of 1.15 V, 2.048 V or 2.5 V. The reference circuit is trimmed for high initial accuracy and low temperature drift. A separate buffer amplifier is provided to buffer the high impedance Vref output. The voltage reference, PGA, and A/D converter use the conversion clock (CCLK) and signals derived from it. CCLK can be either an input or output signal. The ADS7871 can divide the CCLK signal by a constant before it is applied to the A/D converter and PGA. This allows a higher frequency system clock to be used to control the A/D converter operation. Division factors (DF) of 1, 2, 4 and 8 are available. The signal that is actually applied to the PGA and A/D converter is DCLK, where DCLK = CCLK/DF. The ADS7871 is designed so that its serial interface can be conveniently used with a wide variety of microcontrollers. It has four conventional serial interface pins: SCLK (serial data clock), DOUT (serial data out), DIN (serial data in, which may be set bidirectional in some applications), and CS (chip select function). The ADS7871 has ten internal user accessible registers which are used in normal operation to configure and control the device (summarized in Figure 18).
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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003
FUNCTIONAL DESCRIPTION
Multiplexer The ADS7871 has eight analog signal input pins, LN0 through LN7. These pins are connected to a network of analog switches (the MUX block in the block diagram). The switches are controlled by four bits in the Gain/Mux register. LN0 through LN7 can be configured as 8 single-ended inputs or 4 differential inputs or some other combination. Some mux combination examples are shown in Figure 23. The differential polarity of the input pins can be changed with the M2 bit in the MUX address. This feature allows reversing the polarity of the conversion result without having to physically reverse the input connections to the ADS7871. For linear operation, the input signal at any of the LN0 through LN7 pins can range between GND - 0.2 V and VDD + 0.2 V. The polarity of the differential signal can be changed through commands written to Gain/Mux register, but each line must remain within the linear input common mode voltage range. Inputs LN0 through LN7 have ESD protection circuitry as the first active elements on the chip. These contain protection diodes connected to Vdd and GND that remain reverse biased under normal operation. If input voltages are expected beyond the absolute maximum voltage range it is necessary to add resistance in series with the input to limit the current to 10 mA or less. Conversion Clock The conversion clock (CCLK) and signals derived from it are used by the voltage reference, the PGA, and the A/D converter. The CCLK pin can be made either an input or an output. For example, one ADS7871 can be made to be the conversion clock master (CCLK is an output), while the others are slaved to it with their CCLK pins all being inputs (by default). This can reduce A/D conversion errors caused by multiple clocks and other systems noise. When the OSC ENABLE pin is low or zero, the CCLK pin is an input and the ADS7871 relies on an applied external clock for the conversion process. When OSC ENABLE is high or if the OSCE bit D4 in register 7 is set to a one, the internal oscillator and an internal buffer is enabled, making pin 19 an output. Either way the CCLK is sensed internally at the pin so all ADS7871s would see the same clock delays. Capacitive loading on the CCLK pin can draw significant current compared with the supply current to the ADS7871 (Iload = fCCLK * VDD*Cload). The internal reference requires a continuous clock and may be supplied by the internal oscillator independently of the system clock driving the CCLK pin. Setting OSCR (bit D5 in register 7), and REFE (bit D3 in register 7) both to one will accomplish this. Figure 11 illustrates all of theses relationships. The ADS7871 utilizes the power saving technique of turning on and off the biasing for the PGA and A/D as needed. This does not apply to the oscillator, reference, and buffer, these will run continuously when enabled. The buffer output is high impedance when disabled, so for a low power data logging application the filter capacitor will not be discharged when the buffer is turned off, and won't require as much settling time when turned on. The serial interface clock is independent of the conversion clock and can run faster or slower. If it's desirable to use a faster system clock than the 2.5 MHz nominal rate that the ADS7871 uses then this clock may be divided to a slower rate ( 1/2, 1/4, 1/8) by setting the appropriate bits in register 3. This clock divider applies equally to external as well as internal clock to create the internal DCLK for the PGA and A/D conversion cycle. The ADS7871 has both maximum and minimum DCLK frequency constraints (DCLK = CCLK/DF). The maximum DCLK is 2.5 MHz. The minimum DCLK frequency applied to the PGA, reference and A/D is 100 kHz.
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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003 Pin 26 VREF Pin 27 BUFIN Pin 28 BUFOUT/REFIN
REF BUF Enabled by Reg.7 D2, BUFE To ADC
Internal Oscillator (2.5 MHz) Enabled by Reg.7 D4, OSCE or Reg.7D5, OSCR or Pin 18, OSC Enable
OSC CLK Reg.7 D5 OSCR = 1 Internal Reference Enabled by Reg.7D3, REFE 1/4 Reg.7 D5 OSCR = 0 1/N Divider N Set by Reg.3 D[1:0], CFD[1:0] Enabled by Pin 18 OSC Enable Reg.7 D4, OSCE DCLK Pin 18 OSC Enable
Pin 19 CCLK
Internal Control Logic ADS7871
Figure 15. Block Diagram With Internal and External Clocks and References Voltage Reference and Buffer Amplifier The ADS7871 uses a patented switched capacitor implementation of a band-gap reference. The circuit has curvature correction for drift, and can be software configured for output voltages of 1.15 V, 2.048 V or 2.5 V (default). The internal reference output (Vref) is not designed to drive a typical load; a separate buffer amplifier must be used to supply any load current. The internal reference buffer (REFBUF) can source many tens of milliamps to quickly charge a filter cap tied to it's output, but it can only typically sink 200 A. If there is any significant noise on the REFIN pin then a resistor to ground ( 250 ) would improve the buffers ability to recover from a positive going noise spike. This would, of course, be at the expense of power dissipation. The temperature compensation of the onboard reference is adjusted with the reference buffer in the circuit. Performance is specified in this configuration. Programmable Gain Amplifier The programmable gain amplifier (PGA) provides gains of 1, 2, 4, 5, 8, 10, 16, and 20 V/V. The PGA is a single supply, rail-to-rail input, auto-zeroed, capacitor based instrumentation amplifier. PGA gain is set by bits G2 through G0 of Register 4. The ability to detect when the PGA outputs are driven to clipping, or nonlinear operation, is provided by the least significant bit of the output data (register 0), being set to one. This result is the logical OR of fault detecting comparators within the ADS7871 monitoring the outputs of the PGA. The inputs are also monitored, for problems, often due to ac common mode or low supply operation, and ORed to this OVL bit. Register 2 can be read to determine what fault conditions existed during the conversion. An illustration of how the OVL bit could be set without having reached the maximum output code of the A/D converter is shown in Fig. 10. The OVL bit also facilitates a quick test to allow for an auto-ranging application, indicating to the system controller it should try reducing the PGA gain.
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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003
A/D Converter The 14-bit A/D converter in the ADS7871 is a successive approximation type. The output of the converter is 2's complement format and can be read through the serial interface MSB first or LSB first. A plot of Output Codes vs Input Voltage is shown in Figure 23. With the input multiplexer configured for differential input the A/D transfer function is: * 8192 v Code v 8191 for * V ref G v V IN v V ref * 1 LSB G (1)
With the input multiplexer configured for single-ended inputs the A/D transfer function is: 0 v Code v 8191 for 0 v V IN v V ref * 1 LSB G (2)
01 1111 1111 1111 (8191) 01 1111 1111 1110 (8190)
Positive Full Scale Transition
Output Code is 2's Complement
OUTPUT CODE
-V REF
00 0000 0000 0010 (2) 00 0000 0000 0001 (1) 00 0000 0000 0000 (0)
Zero Transition 11 1111 1111 1111 (-1) 11 1111 1111 1110 (-2) +V REF
10 0000 0000 0001 (-8191) 10 0000 0000 0000 (-8192) Negative Full Scale Transition INPUT VOLTAGE
Figure 16. Output Codes Versus Input Voltage
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ADS7871
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Conversion Cycle A conversion cycle requires 50 DCLKs, where DCLK = CCLK/DF, the divided-down clock. Operation of the PGA requires 36 DCLKS: capture the input signal, auto-zero the PGA, level-shift and amplify the input signal. The period of this cycle makes certain the settling time is sufficient for gain = 20 and (source impedance of 2k or less) even if the gain is less than 20. The SAR converter takes the last 14 DCLKs. For maximum sampling rate the input command and output data must be communicated during this cycle, although this is not recommended for best performance. During the conversion cycle the internal capacitive load at the selected MUX input changes between 6pF and 9.7pF. When the ADS7871 is not converting the MUX inputs have a nominal 4pF load capacitance. The source impedance of the input will cause the voltage to vary on the DCLK transitions as the internal capacitors are switched in and out. A 10 nF to 100 nF capacitor across the differential inputs will help filter these glitches, and act as an anti-alias filter in combination with the source impedance. Source impedance greater than 2k will require longer settling times and so the CCLK should be reduced accordingly. For minimum power dissipation, the bias needed for each function is turned on, allowed to settle, and run only for the duration required for each conversion. Low rate data logging applications can capitalize on this by utilizing the internal oscillator as needed rather than running a slow system clock. Starting an A/D Conversion Cycle There are four ways to cause the ADS7871 to perform a conversion: 1. Send a Direct Mode instruction. 2. Write to Register 4 with the CNV bit = 1 3. Write to Register 5 with the CNV bit = 1
4. Assert the CONVERT pin (logic high) -- Then a new conversion cycle will start at the second active edge of CCLK Serial Interface The ADS7871 communicates with microprocessors and other external circuitry through a digital serial port interface. It is compatible with a wide variety of popular micro-controllers and digital signal processors (DSP). These include TI's TMS320, MSC1210 and MSP430 product families. Other vendors products such as Motorola 68HC11, Intel 80C51, and MicroChip PIC Series are also supported. The serial interface consists of four primary pins, SCLK (serial bit clock), DIN (serial data input), DOUT (serial data output) and CS (chip select). SCLK synchronizes the data transfer with each bit being transmitted on the falling or rising SCLK edge as determined by the RISE/FALL pin. SDIN may also be used as a serial data output line. Additional pins expand the versatility of the basic serial interface and allow it to be used with different micro-controllers. The BUSY pin indicates when a conversion is in progress and may be used to generate interrupts for the micro-controller. The CONVERT pin can be used as a hardware means of causing the ADS7871 to start a conversion cycle. The RESET pin can be toggled in order to reset the ADS7871 to the power-on state. Communication through the serial interface is dependent on the micro-controller providing an instruction byte followed by either additional data (for a write operation) or just additional SCLKs to allow the ADS7871 to provide data (for a read operation). Special operating modes for reducing the instruction byte overhead for retrieving conversion results are available. Reset of device (RESET), start of conversion (CONVERT), and oscillator enable (OSC ENABLE) can be done by signals to external pins or entries to internal registers. The actual execution of each of these commands is a logical OR function; either pin or register signal TRUE cause the function to execute. The CONVERT pin signal is an edge-triggered event, with a hold time of two CCLK periods for debounce.
}
The next conversion will queue up, waiting for the current conversion to complete
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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003
Operating Modes The ADS7871 serial interface operates based on an instruction byte followed by an action commanded by the contents of that instruction. The 8-bit instruction word is clocked into the DIN input. There are two types of instruction bytes that may be written to the ADS7871 as determined by bit D7 of the instruction word (see Figure 23). These two instructions represent two different operating modes. In direct mode (bit D7 = 1), a conversion is started. A register mode (bit D7 = 0) instruction is followed by a Read or Write Operation to the specified register.
INSTRUCTION BYTE D7 (MSB) Start Conversion (Direct Mode) Read/Write (Register Mode) 1 D6 G2 D5 G1 D4 G0 OR 0 R/W 16/8 A4 A3 A2 A1 A0 D3 M3 D2 M2 D1 M1 D0 M0
START CONVERSION INSTRUCTION BYTE (Direct Mode)(1) BIT D7 D6-D4 G2-G0 SYMBOL NAME Mode select PGA gain select VALUE 1 000 001 010 011 100 101 110 111 See Figure 27 FUNCTION Starts a conversion cycle (direct mode) PGA Gain = 1 (power up default condition) PGA Gain = 2 PGA Gain = 4 PGA Gain = 5 PGA Gain = 8 PGA Gain = 10 PGA Gain = 16 PGA Gain = 20 Determines input channel selection for the requested conversion, differential or single-ended configuration.
D3-D0
M3-M0
Input channel select
NOTE 1: The seven lower bits of this byte are also written to register 4, the Gain/Mux register. READ/WRITE INSTRUCTION BYTE (Register Mode) BIT D7 D6 D5 D4-D0 R/W 16/8 AS4-AS0 SYMBOL NAME Mode Select Read/Write Select Word Length Register Address VALUE 0 0 1 0 1 See Figure 21 Write Operation Read Operation 8-Bit Word 16-Bit Word (2 8-bit bytes) Determines the address of the register that is to be read from or written to FUNCTION Initiates a read or write operation (Register Mode)
Figure 17. Instruction Byte Addressing Direct Mode In the direct mode a conversion is initiated by writing a single 8-bit instruction byte to the ADS7871 (bit D7 is set to 1). Writing the direct mode command sets the configuration of the multiplexer, selects the gain of the PGA, and starts a conversion cycle. After the last bit of the instruction byte is received, the ADS7871 performs a conversion on the selected input channel with the PGA gain set as indicated in the instruction byte. The conversion cycle will begin on the second falling edge of DCLK after the eighth active edge of SCLK of the instruction byte. When the conversion is complete the conversion result will be stored in the A/D Output registers and is available to be clocked out of the serial interface by the controlling device using the READ operation in the Register Mode.
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ADS7871
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The structure of the instruction byte for direct mode is shown in Figure 17.
D D7: This bit is set to 1 for direct mode operation D D6 through D4 (G2 - G0): These bits control the gain of the programmable gain amplifier. PGA gains of 1,
2, 4, 5, 8, 10,16 and 20 are available. The coding is shown in Figure 17.
D D3 through D0 (M3 - M0): These bits configure the switches that determine the input channel selection.
The input channels may be placed in either differential or single-ended configurations. In the case of differential configuration, the polarity of the input signal is reversible. The coding is shown in Figure 24. Note that the seven lower bits of this byte are written to register 4, the Gain/Mux register. All other controllable ADS7871 parameters are values previously stored in their respective registers. These values are either the power-up default values (0) or values that were previously written to one of the control registers in a Register mode operation. No additional data is required for a direct mode instruction. Register Mode In register mode (Bit D7 of the Instruction Byte is 0) a read or write instruction to one of the ADS7871's registers is initiated. All of the user determinable functions and features of the ADS7871 can be controlled by writing information to these registers (see Figure 18). Conversion results can be read from the A/D Output registers.
REGISTER ADDRESS A4 0 0 0 0 0 0 0 0 1 1 A3 0 0 0 0 0 0 0 0 1 1 A2 0 0 0 0 1 1 1 1 0 1 A1 0 0 1 1 0 0 1 1 0 1 A0 0 1 0 1 0 1 0 1 0 1 ADDR NO. 0 1 2 3 4 5 6 7 24 31 READ/ WRITE Read Read Read R/W R/W R/W R/W R/W R/W Read REGISTER CONTENT D7(MSB) ADC5 ADC13 0 0 CNV/ BSY CNV/ BSY 0 0 LSB 0 D6 ADC4 ADC12 0 0 G2 0 0 0 2W/3 0 D5 ADC3 ADC11 VLD5 BIN G1 0 0 OSCR 8051 0 D4 ADC2 ADC10 VLD4 0 G0 0 0 OSCE 0 0 D3 ADC1 ADC9 VLD3 RMB1 M3 IO3 OE3 REFE 0 0 D2 ADC0 ADC8 VLD2 RBM0 M2 IO2 OE2 BUFE 8501 0 D1 0 ADC7 VLD1 CFD1 M1 IO1 OE1 R2V 2W/3 0 D0 OVR ADC6 VLD0 CFD0 M0 IO0 OE0 RBG LSB 1 REGISTER NAME A/D Output Data, LS Byte A/D Output Data, MS Byte PGA Valid Register A/D Control Register Gain/Mux Register Digital I/O State Register Digital I/O Control Register Ref/Oscillator Control Register Serial Interface Control Register ID Register
Figure 18. Register Address Map The Instruction Byte (see Figure 17) contains the address of the register for the next read/write operation, determines whether the serial communication is to be done in 8-bit or 16-bit word length, and determines whether next operation will read-from or write-to the addressed register. The structure of the instruction byte for register mode is shown in Figure 17.
D D7: This bit is set to 0 for register mode operation. D D6 (R/W): Bit 6 of the Instruction Byte determines whether a read or write operation is performed, 1 for a read
or 0 for a write.
D D5 (16/8): This bit determines the word length of the read or write operation that follows, 1 for sixteen bits
(two eight-bit bytes) or 0 for eight bits.
D D4 through D0 (A4 - A0): These bits determine the address of the register that is to be read from or written
to. Register address coding and other information are tabulated in Figure 18.
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ADS7871
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For sixteen-bit operations, the first eight bits will be written-to/read-from the address encoded by the instruction byte, bits A4 through A0 (Register Address). The address of the next eight bits depends upon whether the Register Address for the first byte is odd or even. If it is even, then the address for the second byte will be Register Address + 1. If the Register Address is odd, then the address for the second byte is the Register Address - 1. This arrangement allows transfer of conversion results from the two A/D Output Data registers either MS byte first or LS byte first (see Serial Interface Control Register text). Register Summary A summary of information about the addressable registers is shown in Figure 18. Their descriptions follow, and more detailed information is provided later in the section called Internal User-accessible Registers. Registers 0 and 1, the A/D Output Data Registers, contain the least significant and most significant bits of the A/D conversion result (ADC0 through ADC13). Register 0 also has one fixed zero (D1), and a bit to indicate if the internal voltage limits of the PGA have been over ranged (OVR). This is a read only register. Write an 8-bit word to register 0 and the ADS7871 will reset. Register 2, the PGA Valid Register, contains information that describes the nature of the problem in the event that the allowable input voltage to the PGA has been exceeded. Register 3, the A/D Control Register, has two test bits (best left set to zero), a bit to convert the output format to straight binary (BIN), an unused bit, two bits to configure an automatic read back mode of the A/D results (RBM1, RBM0), and two bits that program the frequency divider for the CCLK (CDF1, CDF0). Register 4, the Gain/Mux Register, contains the input channel selection information (M0 through M3) and the programmable gain amplifier gain set bits (G0 through G2). Register 5, the Digital I/O State Register, contains the state of each of the digital I/O pins (I/O3 through I/O0). In addition, registers 4 and 5 contain a convert/busy bit (CNV/BSY) that can be used to start a conversion via a write instruction or sense when the converter is busy with a read instruction. Register 6, the Digital I/O Control Register, contains the information that determines whether each of the four digital I/O pins is to be an input or an output function (OE3 through OE0). This sets the mode of each I/O pin. Register 7, the Ref/Oscillator Control Register, controls whether the internal oscillator used for the conversion clock is on or off (OSCE), whether the internal voltage reference and buffer are on or off (REFE, BUFE), and whether the reference provides 2.5 V, 2.048 V, or 1.15 V. Register 24, the Serial Interface Control Register, controls whether data is presented MSB or LSB first (LSB bit), whether the serial interface is configured for 2-wire or 3-wire operation (2W bit), and determines proper timing control for 8051-type microprocessor interfaces (8051 bit). Register 31, the ID Register, is read only. Reset There are three ways to reset. All register contents, and the Serial Interface will be reset on: 1. Cycle power. The power down time must be long enough to allow internal nodes to discharge. 2. Toggle the RESET pin. Minimum pulse width to reset is 50 ns. 3. Write an 8-bit byte to register 0. The ADS7871 will not wait for the data which would normally follow this instruction. All of these actions set all internal registers to zero, turns off the oscillator, reference, and buffer. Recovery time for the reference is dependent on capacitance on the reference and buffer outputs.
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ADS7871
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Only the serial interface is reset (and disabled) when CS signal is brought high. If CS is continuously held low, and the ADS7871 is reset by an 8-bit write to register 0 (even if inadvertently) then the next 1 input to DIN is the synchronizing bit for the Serial Interface. The next active edge of SCLK following this 1 will latch in the first bit of the new instruction byte. For applications where CS cannot be cycled, and system synchronization is lost, the ADS7871 must be reset by writing 39 zeros and a one. The Serial Interface will then be ready to accept the next command byte. This string length is based on the worst case conditions to ensure that the device is synchronized.
NOTE: A noisy SCLK, with excessive ringing, can lead to inadvertently resetting the ADS7871. Sufficient capacitance to correct this problem may be provided just by a scope probe which would mask this issue during debugging. 100 in series with the SCLK pin is usually sufficient to correct this problem. Since the data is changed on the opposite edge of the SCLK it is usually settled before the active edge of SCLK and wouldn't need its own 100 resistor, though it wouldn't hurt.
Write Operation To perform a write operation an instruction byte must first be written to the ADS7871 as described previously (see Figure 17). This instruction will determine the target register as well as the word length (8 bits or 16 bits). The CS pin must be asserted (0) prior to the first active SCLK edge (rising or falling depending on the state of the RISE/FALL pin) that will latch the first bit of the instruction byte. The first active edge after CS must have the first bit of the instruction byte. The remaining seven bits of the instruction byte will be latched on the next seven active edges of SCLK. CS must remain low for the entire sequence. Setting CS high will reset the serial interface. When starting a conversion by setting the CNV/BSY bit in the Gain/Mux register and/or the Digital I/O register, the conversion will start on the second falling edge of DCLK after the last active SCLK edge of the write operation. Figure 19 shows an example of an eight-bit write operation with LSB first and SCLK active on the rising edge. The double arrows indicate the SCLK transition when data is latched into its destination register.
Instruction Latched Register is updated
SCLK
DIN
DOUT
CS
Figure 20 shows an example of the timing for a 16-bit write to an even address with LSB first and SCLK active on the rising edge. Notice that both bytes are updated to their respective registers simultaneously. Also shown is that the address (ADDR) for the write of the second byte is incremented by one since the ADDR in the instruction byte was even. For an odd ADDR, the address for the second byte would be ADDR-1.
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A0 A1 A2 A3 A4 0 0 0 D0 D1 D2 D3 D4 D5 D6 D7
Figure 19. Timing Diagram for an 8-Bit Write Operation
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Instruction Latched Both Bytes Updated
SCLK
DIN
DOUT
CS
Read Operation A read operation is similar to a write operation except that data flow (after the instruction byte) is from the ADS7871 to the host controller. After the instruction byte has been latched (on the eighth active edge of SCLK) the DOUT pin (and the DIN pin if in two-wire mode) will begin driving data on the next nonactive edge of SCLK. This allows the host controller to have valid data on the next active edge of SCLK. The data on DOUT (or DIN) will transition on nonactive edges of SCLK. The DIN pin (two-wire mode) will cease driving data (return to high impedance) on the nonactive edge of SCLK following the eighth (or sixteenth) active edge of the read data. DOUT is only high impedance when CS is not asserted. With CS high (1), DOUT (or DIN) is forced to high impedance mode. In general, the ADS7871 is insensitive to the idle state of the clock except that the state of SCLK may determine if the DIN is driving data or not. Upon completion of the read operation, the ADS7871 will be ready to receive the next instruction byte. Read operations will reflect the state of the ADS7871 on the first active edge of SCLK of the data byte transferred. Figure 21 shows an example of an eight-bit read operation with LSB first and SCLK active on the rising edge. The double rising arrows indicate when the instruction is latched.
SCLK
Figure 22 provides an example of a 16-bit read operation from an odd address with LSB first and SCLK active on the rising edge. The address (ADDR) for the second byte is decremented by one since the ADDR in the instruction byte is odd. For an even ADDR, the address for the second byte would be incremented by one.
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0 A1 A2 A3 A4 1 0 0 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Data for ADDR Data for ADDR + 1
Figure 20. Timing Diagram of a 16-Bit Write Operation to an Even Address
DIN
DOUT
CS
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A0 A1 A2 A3 A4 0 1 0 D0 D1 D2 D3 D4 D5 D6 D7
Figure 21. Timing Diagram for an 8-Bit Read Operation
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ADS7871
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SCLK
DIN
DOUT
CS
Multiplexer Addressing The last four bits in the Instruction Byte (during a start conversion instruction) or the Gain/Mux Register (ADDR = 4) assign the multiplexer configuration for the requested conversion. The input channels may be placed in either differential or single-ended configurations. For differential configurations, the polarity of the input signal is reversible by the state of M2 (Bit D2). In single-ended mode, all input channels are measured with respect to system ground (pin 25). Figure 23 shows some examples of multiplexer assignments and Figure 24 provides the coding for the input channel selection.
EXAMPLES OF MULTIPLEXER OPTIONS Differential and Single-Ended Channel + + + + + + + + LN0, LN1 LN2, LN3 LN4 LN5 LN6 LN7 + - - + + + + +
CODING FOR DIFFERENTIAL INPUT CHANNEL SELECT
SELECTION BITS M3 0 0 0 0 0 0 0 0 M2 0 0 0 0 1 1 1 1 M1 1 0 1 0 1 0 1 1 M0 0 1 0 1 0 1 0 1 - + - + - + - + LN0 + LN1 - + - + - + - LN2 INPUT LINES LN3 LN4 LN5 LN6 LN7
NOTE: Bit M3 selects either differential or single-ended mode. If differential mode is selected, BIt M2 determines the polarity of the input channels. Bold items are power-up default conditions.
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1 A1 A2 A3 A4 1 1 0 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Data from ADDR Data from ADDR-1
Figure 22. Timing Diagram for a 16-Bit Read Operation to an Odd Address
4 Differential Channel LN0, LN1 LN2, LN3 LN4, LN5 LN6, LN7 + - + - - + - + Channel LN0 LN1 LN2 LN3 LN4 LN5 LN6 LN7
8 Single-Ended
Figure 23. Examples of Multiplexer Options
CODING FOR SINGLE-ENDED INPUT CHANNEL SELECT (negative input is ground)
SELECTION BITS M3 1 1 1 1 1 1 1 1 M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 LN0 + + + + + + + + NL1 LN2 INPUT LINES LN3 LN4 LN5 LN6 LN7
Figure 24. Multiplexer Addressing
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INTERNAL USER-ACCESSIBLE REGISTERS
The registers in the ADS7871 are eight bits wide. Most of the registers are reserved, the ten user-accessible registers are summarized in the Register Address Map (see Figure 18). Detailed information for each register follows. The default power-on/reset state of all bits in the registers is 0. ADC Output Registers The A/D Output registers are read only registers located at ADDR = 0 and ADDR = 1 that contain the results of the A/D conversion, ADC13 through ADC0 (see Figure 25). The conversion result is in 2's complement format. The bits can be taken out of the registers MSB (D7) first or LSB (D0) first, as determined by the state of the LSB bits (D7 or D0) in the Serial Interface Control register. The ADDR = 0 register also contains the OVR bit which indicates if the internal voltage limits to the PGA have been exceeded.
ADC OUTPUT REGISTERS ADDR 0 1 D7 (MSB) ADC5 ADC13 D6 ADC4 ADC12 D5 ADC3 ADC11 D4 ADC2 ADC10 D3 ADC1 ADC9 D2 ADC0 ADC8 D1 0 ADC7 D0 OVR ADC6
ADDR = 0 (LS Byte) BIT D7-D2 D1 D0 SYMBOL ADC5- ADC0 -- OVR NAME A/D Output -- PGA Over-Range VALUE (1) 0 0 1 FUNCTION Six least significant bits of conversion result This bit is not used and is always 0. Valid conversion result An analog over-range problem has occurred in the PGA. Conversion result may be invalid. Details of the type of problem are stored in Register 2, the PGA Valid register.
ADDR = 1 (MS Byte) BIT D7-D0 SYMBOL ADC13- ADC6 NAME ADC Output VALUE (1) FUNCTION Eight most significant bits of conversion result
NOTE 1: Value depends on conversion result.
Figure 25. ADC Output Registers (ADDR = 0 and ADDR = 1)
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PGA Valid Register The PGA Valid register (ADDR = 2) is a read only register that contains the individual results of each of the six comparators for the PGA, VLD5 through VLD0, as shown in Figure 26.
PGA VALID REGISTER ADDR 2 ADDR = 2 BIT D7-D6 D5 D4 D3 D2 D1 D0 SYMBOL -- VLD5 VLD4 VLD3 VLD2 VLD1 VLD0 NAME -- PGA Valid 5 PGA Valid 4 PGA Valid 3 PGA Valid 2 PGA Valid 1 PGA Valid 0 VALUE 0 0 1 0 1 0 1 0 1 0 1 0 1 FUNCTION These bits are not used and are always 0. Voltage at minus (-) output from the PGA has exceeded its minimum value. Voltage at minus (-) output from the PGA has exceeded its maximum value. Voltage at minus (-) input to the PGA has exceeded its maximum value. Voltage at plus (+) output from the PGA has exceeded its minimum value. Voltage at plus (+) output from the PGA has exceeded its maximum value. Voltage at plus (+) input to the PGA has exceeded its maximum value. D7 (MSB) 0 D6 0 D5 VLD5 D4 VLD4 D3 VLD3 D2 VLD2 D1 VLD1 D0 VLD0
Figure 26. PGA Valid Register (ADDR = 2) A/D Control Register The A/D Control register (ADDR = 3) configures the CCLK divider and read back mode option as shown in Figure 27.
ADC CONTROL REGISTER ADDR 3 ADDR = 3 BIT D7-D6 D5 D4 D3-D2 SYMBOL -- BIN -- RBM1-RBM0 NAME -- Output Data Format -- Automatic Read Back Mode VALUE 0 0 1 0 00 01 10 11 00 01 10 11 FUNCTION These bits are reserved and must always be written 0. Mode 0 - Twos complement Mode 1 - Binary output data format This is a reserve bit and must always be written 0 Mode 0 - Read instruction required to access ADC conversion result. Mode 1 - Most significant byte returned first Mode 2 - Least significant byte returned first Mode 3 - Only most significant byte returned Division factor for CCLK = 1 (DCLK = CCLK) Division factor for CCLK = 2 (DCLK = CCLK/2) Division factor for CCLK = 4 (DCLK = CCLK/4) Division factor for CCLK = 8 (DCLK = CCLK/8) D7 (MSB) 0 D6 0 D5 BIN D4 0 D3 RBM1 D2 RBM0 D1 CFD1 D0 CFD0
D1-D0
CFD1-CFD0
CCLK Divide
Bold items are power-up default conditions.
Figure 27. ADC Control Register (ADDR = 3)
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Read Back Modes RBM1 and RBM0 determine which of four possible modes is used to read the A/D conversion result from the A/D Output registers.
D Mode 0 (default mode) requires a separate read instruction to be performed in order to read the output of
the A/D Output registers
D Mode 1, 2, and 3: Provide for different types of automatic read-back options of the conversion results from
the A/D Output registers without having to use separate read instructions: Mode 1: Provides data MS byte first Mode 2: provides data LS byte first Mode 3: Output only the MS byte For more information refer to the READ BACK MODE section. Clock Divider CFD1 and CFD0 set the CCLK divisor constant which determines the DCLK applied to the A/D, PGA and reference. The A/D and PGA operate with a maximum clock of 2.5 MHz. In situations where an external clock is used to pace the conversion process it may be desirable to reduce the external clock frequency before it is actually applied to the PGA and A/D. The signal that is actually applied to the A/D and PGA is called DCLK, where DCLK = CCLK/DF (DF is the division factor determined by the CFD1 and CFD0 bits). For example, if the external clock applied to CCLK is 10 MHz and DF = 4 (CFD1 = 1, CFD0 = 0), DCLK equals 2.5 MHz. Gain/Mux Register The Gain/Mux register (ADDR = 4) contains the bits that configure the PGA gain (G2 - G0) and the input channel selection (M3 - M0) as shown in Figure 24. This register is also updated when direct mode is used to start a conversion so its bit definition is compatible with the instruction byte.
GAIN/MUX REGISTER ADDR 4 ADDR = 4 BIT D7 D6-D4 SYMBOL CNV/BSY G2-G0 NAME Convert/Busy PGA Gain Select VALUE 0 1 000 001 010 011 100 101 110 111 Figure 27 FUNCTION Idle Mode Busy Mode; write = start conversion PGA Gain = 1 PGA Gain = 2 PGA Gain = 4 PGA Gain = 5 PGA Gain = 8 PGA Gain = 10 PGA Gain = 16 PGA Gain = 20 Determines input channel selection for the requested conversion, differential or single-ended configuration. D7 (MSB) CNV/BSY D6 G2 D5 G1 D4 G0 D3 M3 D2 M2 D1 M1 D0 M0
D3-D0
M3-M0
Input Channel Select
Bold items are power-up default conditions.
Figure 28. Gain/Mux Register (ADDR = 4)
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Input Channel Selection Bits M3 through M0 configure the switches that determine the input channel selection. The input channels may replaced in either differential or single-ended configurations. In the case of differential configuration, the polarity of the input pins is reversible by the state of the M2 bit. The coding for input channels is given in Figure 24 and examples of different input configurations are shown in Figure 23. Convert/Busy If the CNV/BSY bit is set to a 1 during a write operation, a conversion will start on the second falling edge of DCLK after the active edge of SCLK that latched the data into the Gain/Mux register. The CNV/BSY bit may be read with a read instruction. The CNV/BSY bit will bet set to 1 in a read operation if the ADS7871 is performing a conversion at the time the register is sampled in the read operation. Gain Select Bits G2 through G0 control the gain of the programmable gain amplifier. PGA gains of 1, 2, 4, 5, 8, 10, 16 and 20 are available. The coding is shown in Figure 28. Digital Input/Output State Register The Digital I/O State register (ADDR = 5) contains the state of each of the four digital I/O pins. Each pin can function as a digital input (the state of the pin is set by an external signal connected to it) or a digital output (the state of the pin is set by data from a serial input to the ADS7871). The input/output functional control is established by the digital I/O mode control bits (OE3 - OE0) in the Digital I/O Control register. In addition, the convert/busy bit (CNV/BSY) can be used to start a conversion via a write instruction or determine if the converter is busy by executing a read instruction. Digital I/O State Bits Bits D3 through D0 (I/O3 - I/O0) of the Digital I/O State register are the state bits. If the corresponding mode bit makes the pin a digital input, the state bit indicates whether the external signal connected to the pin is a 1 or a 0, and it is not possible to control the state of the corresponding bit with a write operation. The state of the bit is only controlled by the external signal connected to the digital I/O pin. Coding is shown in Figure 29.
DIGITAL I/O STATE REGISTER ADDR 5 ADDR = 5 BIT D7 D6-D4 D3 D2 D1 D0 SYMBOL CNV/BSY -- IO3 IO2 IO1 IO0 NAME Convert/Busy -- State for I/O3 State for I/O2 State for I/O1 State for I/O0 VALUE 0 1 0 0 1 0 1 0 1 0 1 FUNCTION Idle Mode Busy Mode; write = start conversion These bits are not used and are always 0. Input or Output State = 0 Input or Output State = 1 Input or Output State = 0 Input or Output State = 1 Input or Output State = 0 Input or Output State = 1 Input or Output State = 0 Input or Output State = 1 D7 (MSB) CNV/BSY D6 0 D5 0 D4 0 D3 IO3 D2 IO2 D1 IO1 D0 IO0
Bold items are power-up default conditions. NOTE: When the Mode Control makes a pin a digital input, it is not possible to control the state of the corresponding bit in the digital I/O state register with a write operation. The state of the bit is only controlled by the external signal connected to the digital I/O pin.
Figure 29. Digital I/O State Register (ADDR = 5)
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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003
The four digital I/O pins allow control of external circuitry, such as a multiplexer, or allow the digital status lines from other devices to be read without using any additional micro-controller pins. Reads from this register always reflect the state of the pin, not the state of the latch inside the ADS7871. Convert/Busy If CNV/BSY is set to a 1 during a write operation, a conversion will start on the second falling edge of DCLK after the active edge of SCLK that latched the data into the Digital I/O register. The CNV/BSY bit may be read with a read instruction. The CNV/BSY will be set to 1 in a read operation if the ADS7871 is performing a conversion at the time the register is sampled in the read operation. Digital I/O Control Register The Digital I/O Control register (ADDR = 6) contains the information that determines whether each of the four digital I/O lines is configured as an input or output. Setting the appropriate OE bit to 1 enables the corresponding I/O pin as an output. Setting the appropriate OE bit to 0 enables the corresponding I/O pin as an input (see Figure 30).
DIGITAL I/O CONTROL REGISTER ADDR 6 ADDR = 6 BIT D7-D4 D3 D2 D1 D0 SYMBOL -- OE3 OE2 OE1 OE0 NAME -- State for I/O3 State for I/O2 State for I/O1 State for I/O0 VALUE 0 0 1 0 1 0 1 0 1 Digital I/O 1 - digital input Digital I/O 1 = digital output Digital I/O 2- digital input Digital I/O 2 - digital output Digital I/O 3- digital input Digital I/O 3 - digital output Digital I/O 4- digital input Digital I/O 4 - digital output FUNCTION These bits are reserved and must always be set to 0. D7 (MSB) 0 D6 0 D5 0 D4 0 D3 OE3 D2 OE2 D1 OE1 D0 OE0
Bold items are power-up default conditions.
Figure 30. Digital I/O Control Register (ADDR = 6)
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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003
Reference/Oscillator Configuration Register The Reference/Oscillator Configuration register (ADDR = 7) determines whether the internal oscillator is used (OSCE and OSCR), whether the internal voltage reference and buffer are on or off (REFE and BUFE), and whether the reference is 2.5 V, 2.048 V, or 1.15 V as shown in Figure 31.
REFERENCE/OSCILLATOR REGISTER ADDR 7 ADDR = 7 BIT D7-D6 D5 D4 D3 D2 D1 D0 SYMBOL -- OSCR OSCE REFE BUFE R2V RBG NAME -- Oscillator Control Oscillator Enable Reference Enable Buffer Enable 2V Reference Bandgap Reference VALUE 0 0 1 0 1 0 1 0 1 0 1 0 1 FUNCTION These bits are reserved and must always be set to 0. Source of clock for internal VREF is CCLK pin. Clocking signal comes from the internal oscillator. CCLK is configured as an input. CCLK outputs a 2.5 MHz signal (70 A). Reference is powered down. Reference is powered up. Buffer is powered down and draws no current. Buffer is powered up and draws 150 A of current. VREF = 2.5 V (RBG bit = 0) VREF = 2.048 V (RBG bit = 0) Bit R2V determines the value of the reference voltage. VREF = 1.15 V D7 (MSB) 0 D6 0 D5 OSCR D4 OSCE D3 REFE D2 BUFE D1 R2V D0 RBG
Bold items are power-up default conditions.
Figure 31. Reference/Oscillator Configuration Register (ADDR = 7) Oscillator Control The internal voltage reference uses a switched capacitor technique which requires a clocking signal input. When OSCR = 1, the clocking signal for the reference comes from the internal oscillator. When OSCR = 0, the clocking signal for the reference is derived from the signal on the CCLK pin and affected by the frequency divider controlled by the CFD0 and CFD1 bits in the A/D Control register. The OSCE bit is the internal oscillator enable bit. When it is set to 1 power is applied to the internal oscillator causing it to produce a 2.5-MHz output and causing the signal to appear at the CCLK pin. The internal oscillator is also enabled when the OSCR bit and the REFE bit are set to 1, but does not make CCLK an output pin.. The internal oscillator is also enabled when the OSC ENABLE pin is set to 1. The power-up default condition is 0 for OSCE and OSCR. If either the OSC ENABLE pin is held high, or either of these control register bits are 1, then the oscillator will be turned on. Voltage Reference and Buffer Enable When the REFE bit = 0 (power-up default condition), the reference is powered down and draws no current. When REFE is set to 1, the reference is powered up and draws approximately 190 A of current. When the BUFE bit = 0 (power-up default condition) the buffer amplifier is powered down and draws no current. When the buffer amplifier is set to 1, it is powered up and draws approximately 150 A of current. Selecting the Reference Voltage When the RBG bit is set to 1, the voltage on the Vref pin is 1.15 V and the R2V bit has no effect. When this bit is set to 0 (power-up default condition), the R2V bit determines the value of the reference voltage. When R2V = 0 and RBG = 0 (power-up default condition), the voltage at the Vref pin is 2.5 V. When R2V = 1 and RBG =0, the reference voltage is 2.048 V.
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ADS7871
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A 14-bit bipolar input A/D converter has 16384 states and each state corresponds to 305 V mV with the 2.5-V reference. With a 2.048-V reference, each A/D bit corresponds to 250 V. Serial Interface Control Register The Serial Interface Control register (ADDR = 24), see Figure 32, allows certain aspects of the serial interface to be controlled by the user. It controls whether data is presented MSB or LSB first, whether the serial interface is configured for 2-wire or 3-wire operation and determines proper timing control for 8051-type microprocessor interfaces. The information in this register is formatted with the information symmetric about its center. This is done so that it may be read or written either LSB (bit D7) or MSB (bit D0) first. Each control bit has two locations in the register. If either of the two is set, the function is activated. This arrangement can potentially simplify micro-controller communication code. The instruction byte to write this configuration data to Register 24 is itself symmetric. From Figure 17, a register mode write instruction of 8 bits to address 24 is 0001 1000 in binary form. Therefore, this command to write to this register will be valid under all conditions.
SERIAL INTERFACE CONTROL REGISTER ADDR 24 ADDR = 7 BIT D7 D6 D5 SYMBOL LSB 2W 8051 NAME LSB or MSB first 2 Wire or 3 Wire Serial Interface VALUE 0 1 0 1 0 1 0 0 1 0 1 0 1 FUNCTION Serial interface receives and transmits MSB first. Serial interface receives and transmits LSB first. 3-Wire mode 2-Wire mode DIN high impedance on the next inactive edge or when CS goes inactive. DIN pin is high impedance on last active SCLK edge of the bye of data transfer These bits are reserved and must always be set 0. DIN high impedance on the next inactive edge or when CS goes inactive. DIN pin is high impedance on last active SCLK edge of the bye of data transfer 3-Wire mode 2-Wire mode Serial interface receives and transmits MSB first. Serial interface receives and transmits LSB first. D7 (MSB) LSB D6 2W D5 8051 D4 0 D3 0 D2 8051 D1 2W D0 LSB
D4-D3 D2
-- 8051
-- Serial Interface
D1 D0
2W LSB
2 Wire or 3 Wire LSB or MSB first
Bold items are power-up default conditions.
Figure 32. Serial Interface Control Register (ADDR = 24) LSB or MSB The LSB bit determines whether the serial interface receives and transmits either LSB or MSB first. Setting the LSB bit (1) configures the interface to expect all bytes LSB first as opposed to the default MSB first (LSB = 0). 2-Wire or 3-Wire Operation The 2W bit configures the ADS7871 for two-wire or three-wire mode. In two-wire mode (2W = 1), the DIN pin is enabled as an output during the data output portion of a read instruction. The DIN pin accepts data when the ADS7871 is receiving and it outputs data when the ADS7871 is transmitting. When data is being sent out of the DIN pin, it also appears on the DOUT pin as well. In three-wire mode (2W = 0), data to the ADS7871 is received on the DIN pin and is transmitted on the DOUT pin. The power-up default condition is three-wire mode.
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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003
Serial Interface Timing (8051 Bit) The 8051 bit will change the timing of when the DIN pin will go to high impedance at the end of an operation. When the bit is a 1, the pin goes to high impedance on the last active SCLK edge of the last byte of data transfer instead of waiting for the next inactive edge, or CS to go inactive. This allows the ADS7871 to disconnect from the data lines soon enough to avoid contention with an 80C51-type interface. The 80C51 drives data four CPU cycles before an inactive SCLK edge and for two CPU cycles after an active SCLK edge. When the 8051 bit is a 0, the DIN pin goes high impedance on the next inactive SCLK edge or when CS goes inactive (1). Figure 33 and Figure 34 show the timing of when the ADS7871 will set the DIN pin to high impedance at the end of a read operation when the 2W bit is set. The behavior of DOUT does not depend of the state of 2W. The 8051 bit is not set for these two examples.
Micro drives DIN ADS7871 drives DIN DIN high-impedance on CS
SCLK
DIN
A0
A1
A2
A3
A4
0
1
0
D0
D1
D2
D3
D4
D5
D6
D7
DOUT
CS
Micro drives DIN
SCLK
DIN
DOUT
D0
D1
D2
D3
D4
D5
D6
D7
CS
Figure 34. Timing for High Impedance State on DIN/DOUT (Inactive SCLK Edge) Figure 35 shows the timing for entering the high impedance state when the 8051 bit is set. Notice that on the last bit of the read operation the DIN (and DOUT) pin goes to the high impedance state on the active edge of SCLK instead of waiting for the inactive edge of SCLK or CS going high as shown in Figure 33 and Figure 34. This is for compatibility with 80C51 Mode 0 type serial interfaces. An 80C51 forces DIN valid before the SCLK falling edge and holds it valid until after the SCLK rising edge. This can lead to contention but setting the 8051 bit fixes this potential problem without requiring CS to be toggled high after every read operation.
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ADS7871 drives DIN A0 A1 A2 A3 A4 0 1 0 D0
D0
D1
D2
D3
D4
D5
D6
D7
Figure 33. Timing for High Impedance State on DIN/DOUT (CS = 1)
DIN high-impedance on inactive edge
D1
D2
D3
D4
D5
D6
D7
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Micro drives DIN ADS7871 drives DIN DIN high-impedance on active SCLK edge
SCLK
DIN
A0
A1
A2
A3
A4
0
1
0
D0
D1
D2
D3
D4
D5
D6
D7
DOUT
CS
ID Register The ADS7871 has an ID Register (at ADDR = 31) to allow the user to identify which revision of the ADS7871 is installed. This is shown in Figure 36.
ID REGISTER ADDR 31 ADDR = 31 BIT D7-D0 SYMBOL -- NAME -- VALUE -- FUNCTION The contents of this register identify the revision of the ADS7871 D7 (MSB) 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1
Remaining Registers The remaining register addresses are not used in the normal operation of the ADS7871. These registers will return random values when read and nonzero writes to these registers will cause erratic behavior. Unused bits in the partially used registers must always be written low.
STARTING A CONVERSION THROUGH THE SERIAL INTERFACE
There are two methods of starting a conversion cycle through the serial interface. The first (nonaddressed or direct mode) is by using the start conversion byte as described earlier. The second (addressed mode) is by setting the CNV/BSY bit of the register 4 or register 5 by performing a write instruction. The conversion will start on the second falling edge of DCLK after the eighth active edge of SCLK (for the instruction in nonaddressed mode or the data in addressed mode). The BUSY pin will go active (1) one DCLK period (1, 2, 4, or 8 CCLK periods depending on CFD1 and CFD0) after the start of a conversion. This delay is to allow BUSY to go inactive when conversions are queued to follow in immediate succession. BUSY will go inactive at the end of the conversion. If a conversion is already in progress when the CNV/BSY bit is set on the eighth active SCLK edge, the CNV/BSY bit will be placed in queue and the current conversion will be allowed to finish. If a conversion is already queued, the new one will replace the currently queued conversion. The queue is only one conversion long. Immediately upon completion of the current conversion, the next conversion will start. This allows for maximum throughput through the A/D converter. Since BUSY is defined to be inactive for the first DCLK clock period of the conversion, the inactive (falling) edge of BUSY can be used to mark the end of a conversion (and start of the next conversion).
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D0
D1
D2
D3
D4
D5
D6
D7
Figure 35. Timing for High Impedance State on DIN/DOUT (8051 Bit = 1)
Figure 36. ID Register (ADDR = 31)
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Figure 37 shows the timing of a conversion start using the convert start instruction byte. The double rising arrow on SCLK indicates when the instruction is latched. The double falling arrow on CCLK indicates where the conversion cycle will actually start (second falling edge of CCLK after the eighth active edge of SCLK). This example is for LSB first, CCLK divider = 1, and SCLK active on rising edge. Notice that BUSY goes active one CCLK period later since CCLK divider = 1.
SCLK
DIN
M0
M1
M2
M3
G0
G1
G2
1
DOUT
CS
CCLK
BUSY
Figure 37. Timing Diagram for a Conversion Start Using Serial Interface Convert Instruction Figure 38 shows an example of a conversion start using an 8-bit write operation to the Gain/Mux Register with the CNV/BSY bit set to 1. The double rising arrow on SCLK indicates where the data is latched into the Gain/Mux register and the double arrow on CCLK indicates when the conversion will start. The example is for LSB first, CCLK divider = 1, and SCLK active on rising edge.
DOUT
CS
CCLK
BUSY
Figure 38. Timing Diagram for a Conversion Start Using 8-Bit Write to the Gain/Mux Register Figure 39 shows the timing of a conversion start using the convert start instruction byte when a conversion is already in progress (indicated by BUSY high). The double rising arrow on SCLK indicates when the instruction is latched. The second falling arrow on CCLK indicates when the conversion cycle would have started had a conversion not been in progress. The double falling arrow on CCLK indicates where the conversion cycle will actually start (immediately after completion of the previous conversion). This example is for LSB first, CCLK divider = 2, and SCLK active on rising edge. Notice that BUSY will be low for two CCLK periods because the CCLK divider = 2.
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DIN
A0
A1
A2
A3
A4
0
0
0
M0
M1
M2
M3
G0
G1
G2
1
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SCLK
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Conversion Starts
Conversion Starts
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SCLK
DIN
M0
M1
M2
M3
G0
G1
G2
1
DOUT
zy
CS
CCLK
BUSY
Figure 39. Timing Diagram of Delayed Conversion Start with Serial Interface
STARTING A CONVERSION USING THE CONVERT PIN
A conversion can also be started by an active (rising) edge on the CONVERT pin. Similar to the CNV/BSY register bit, the conversion will start on the second falling edge of CCLK after the Convert rising edge. The CONVERT pin must stay high for at least two CCLK periods. CONVERT must also be low for at least two CCLK periods before going high. BUSY will go active one DCLK period after the start of the conversion. Contrary to the CNV/BSY bit in the register, the Convert pin will abort any conversion in process and restart a new conversion. BUSY will go low at the end of the conversion. CS may be either high or low when the Convert pin starts a conversion. Figure 40 shows the timing of a conversion start using the CONVERT pin. The double falling arrow on CCLK indicates when the conversion cycle will actually start (the second active CCLK edge after CONVERT goes active). This example is for CCLK divider = 4. Notice that BUSY goes active four CCLK periods later.
Conversion Starts
CCLK
BUSY
CONV
Figure 40. Timing Diagram of Conversion Start Using Convert Pin Read Back Modes
There are four modes available to read the A/D conversion result from the A/D Output Registers. The RBM1 and RBM0 bits in the A/D Control Register (ADDR = 3) control which mode is used by ADS7871. Read Back Mode 0 (default mode) requires a separate read instruction to retrieve the conversion result Read Back Mode 1 (automatic) provides the output most significant byte first Read Back Mode 2 (automatic) provides the output least significant byte first Read Back Mode 3 (automatic) provides only the most significant byte
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Mode 3 will not short cycle the A/D. Automatic Read Back Mode is only triggered when starting a conversion using the serial interface. Conversions started using the CONVERT pin do not trigger the read back mode. The first bit of data for an automatic read back is loaded on the first active SCLK edge of the read portion of instruction. The remaining bits are loaded on the next inactive SCLK edge (the first one after the first active edge). To avoid getting one bit from one conversion and the remainder of the byte from another conversion, a conversion should not finish between the first active SCLK edge and the next inactive edge. Mode 0 Mode 0 (default operating mode) requires a read instruction to be performed to retrieve a conversion result. MS byte first format is achieved by performing a sixteen bit read from ADDR = 1. LS byte first format is achieved by performing a sixteen bit read from ADDR = 0. Reading only the most significant byte can be achieved by performing an eight bit read from ADDR = 1. To increase throughput it is possible to read the result of a conversion while a conversion is in progress. The last conversion completed prior to the first active SCLK edge of the conversion data word (not the instruction byte) is retrieved. This overlapping allows a sequence of start conversion N, read conversion N - 1, start conversion N +1, read conversion N, etc. For conversion 0, the result of conversion -1 would need to be discarded. Mode 1 In this mode, the serial interface configures itself to clockout a conversion result as soon as a conversion is started. This is useful since a read instruction is not required so eight SCLK cycles are saved. This mode operates like an implied sixteen bit read instruction byte for ADDR = 1 was sent to the ADS7871 after starting the conversion. It is not necessary to wait for the end of the conversion to start clocking out conversion results. The last completed conversion at the sampling edge of SCLK will be read back (whether a conversion is in progress or not). Mode 2 This mode is similar to Mode 1 except that the conversion result is provided LS byte first (equivalent to a sixteen bit read from ADDR = 0). Figure 41 and Figure 42 show timing examples of an automatic read back operation using Mode 2. In Figure 41, the result of the previous conversion is retrieved. This example is for LSB first, CCLK divider = 2, and SCLK active on rising edge. The data may be read back immediately after the start conversion instruction. It is not necessary to wait for the conversion to actually start (or finish).
First output bit loaded in the output register The remaining output bits loaded in the output register
SCLK
DIN
DOUT
CS
CCLK
BUSY
Figure 41. Timing Diagram for Automatic Read Back of Previous Conversion Result Using Mode 2
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M0 M1 M2 M3 G0 G1 G2 1 OVR 0 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13
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In Figure 42 the result of the just requested conversion is retrieved. The micro-controller must wait for BUSY to go inactive before clocking out the ADC Output Register. CS must stay low while waiting for BUSY. This example is for LS byte first, CCLK divider = 1, and SCLK active on falling edge. Notice that the DOUT pin is not driven with correct data until the appropriate active edge of SCLK.
SCLK
DIN
DOUT
CS
CCLK
BUSY
Figure 42. Timing Diagram for Automatic Read Back of Current Conversion Result Using Mode 2 Mode 3 This mode only returns the most significant byte of the conversion. It is equivalent to an eight bit read from ADDR = 1.
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1 G2 G1 G0 M3 M2 M1 M0 B5 B4 B3 B2 B1 B0 0 OVR B13 B12 B11 B10 B9 B8 B7 B6
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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003
APPLICATION INFORMATION REQUIRED SUPPORT ELEMENTS
As with any precision analog integrated circuit, good power supply bypassing is required. A low ESR ceramic capacitor in parallel with a large value electrolytic across the supply line will furnish the required performance. Typical values are 0.1 F and 10 F respectfully. Noise performance of the internal voltage reference circuit is improved if a ceramic capacitor of approximately 0.01 F is connected from Vref to ground. Increasing the value of this capacitor may bring slight improvement in the noise on Vref but will increase the time required to stabilize after turn on. If the internal buffer amplifier is used it must have an output filter capacitor connected to ground to ensure stability. A nominal value of 0.47 F provides the best performance. Any value between 0.1 F and 10 F is acceptable. In installations where one ADS7871 buffer is used to drive several devices an additional filter capacitor of 0.1 F should be installed at each of the slave devices. The circuit in Figure 43 shows a typical installation with all control functions under control of the host embedded controller. The SCLK is active on the falling edge. If the internal voltage reference and oscillator are used, they must be turned on by setting the corresponding control bits in the device registers. These registers must be set on power up and after any reset operation.
VDD ADS7871 RESET RISE/FALL 23 20 21 22 18 19 16 17 26 27 28 15 CS SCLK DIN DOUT OSC_CTRL CCLK CONVERT BUSY VREF BUFIN BUFOUT/REFIN GND VDD GND D100 D101 D102 D103 LN0 LN1 LN2 LN3 LN4 LN5 LN6 LN7 24 25 11 12 13 14 Digital I/O - 4 Lines 1 2 3 4 5 6 7 8 Analog In - 8 Lines
0.01 F
10 F
Serial Interface
0.01 F 0.47 F
Figure 43. Typical Operation with Recommended Capacitor Values
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ADS7871
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APPLICATION INFORMATION MICRO-CONTROLLER CONNECTIONS
The ADS7871 is quite flexible in interfacing to various micro-controllers. Connections using the hardware mode of two types of controllers (Motorola M68HC11, Intel 80C51) are described below. Motorola M68HC11 (SPI) The Motorola M68HC11 has a three-wire (four if you count the slave select) serial interface that is commonly referred to as SPI (Serial Peripheral Interface), where the data is transmitted MSB first. This interface is usually described as the micro-controller and the peripheral each having two 8-bit shift registers (one for receiving and one for transmitting). The transmit shift register of the micro-controller and the receive shift register of the peripheral are connected together and vice versa. SCK controls the shift registers. SPI is capable of full duplex operation (simultaneous read and write). The ADS7871 will not support full duplex operation. The ADS7871 can only be written to or read from. It cannot do both simultaneously. Since the M68HC11 can configure SCK to have either rising or falling edge active, the RISE/FALL pin on the ADS7871 can be in which ever state is appropriate for the desired mode of operation of the M68HC11 for compatibility with other peripherals. In the Interface Control Register (see Figure 32), the 2W bit should be cleared (default). The LSB bit should be clear (default). The 8051 bit should also be clear (default). Since the ADS7871 will default to SPI mode, the M68HC11 should not need to initialize the ADS7871 Interface Configuration Register after power-on or reset. Figure 44 shows a typical physical connection between an M68HC11 and a ADS7871. A pull-up resister on DOUT may be needed to keep DOUT from floating during write operations. CS may be permanently tied low if desired, but then the ADS7871 must be the only peripheral.
VDD 10 k typ M68HC11 MISO MOSI SCK SS ADS7871 DIN DOUT SCLK CS
Figure 44. Connection of M68HC11 to the ADS7871 Intel 80C51 The Intel 80C51 operated in serial port Mode 0 has a two-wire (three-wire if an additional I/O pin is used for CS) serial interface. The TXD pin provides the clock for the serial interface and RXD serves as the data input and output. The data is transferred LSB first. Best compatibility is achieved by connecting the RISE/FALL pin of the ADS7871 high (rising edge of SCLK active). In the Interface Configuration Register, the LSB bit and the 8051 bit should be set. The 2W bit should also be set. The first instruction after power-on or reset should be a write operation to the Interface Configuration Register. Figure 45 shows a typical physical connection between an 80C51 and an ADS7871. CS may be permanently tied low if desired, but then the ADS7871 must be the only peripheral.
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ADS7871
SLAS370A - APRIL 2002 - REVISED MARCH 2003
APPLICATION INFORMATION
VDD 10 k typ 80C51 RXD ADS7871 DIN DOUT TXD Px.x SCLK CS
Figure 45. Connection of the 80C51 to the ADS7871
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MECHANICAL DATA
DB (R-PDSO-G**)
28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M
PLASTIC SMALL-OUTLINE
0,25 0,09 5,60 5,00 8,20 7,40
Gage Plane 1 A 14 0- 8 0,25 0,95 0,55
Seating Plane 2,00 MAX 0,05 MIN 0,10
PINS ** DIM A MAX
14
16
20
24
28
30
38
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 /E 12/01
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150
38
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