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ADS 785
ADS7852
2
For most current data sheet and other product information, visit www.burr-brown.com
12-Bit, 8-Channel, Parallel Output ANALOG-TO-DIGITAL CONVERTER
FEATURES
q q q q q q q q q 2.5V INTERNAL REFERENCE 8 INPUT CHANNELS 500kHz SAMPLING RATE SINGLE 5V SUPPLY 1LSB: INL, DNL GUARANTEED NO MISSING CODES 70dB SINAD LOW POWER: 13mW 32-LEAD TQFP PACKAGE
DESCRIPTION
The ADS7852 is an 8-channel, 12-bit analog-to-digital converter complete with sample-and-hold, internal 2.5V reference and a full 12-bit parallel output interface. Typical power dissipation is 13mW at at 500kHz throughput rate. The ADS7852 features both a nap mode and a sleep mode further reducing the power consumption to 2mW. The input range is from 0V to twice the reference voltage. The reference voltage can be overdriven by an external voltage. The ADS7852 is ideal for multi-channel applications where low power and small size are critical. Medical instrumentation, high-speed data acquisition and laboratory equipment are just a few of the applications that would take advantage of the special features offered by the ADS7852. The ADS7852 is available in a 32lead TQFP package and is fully specified and guaranteed over the -40C to +85C temperature range.
APPLICATIONS
q q q q DATA ACQUISITION TEST AND MEASUREMENT INDUSTRIAL PROCESS CONTROL MEDICAL INSTRUMENTS
A0 A1 A2
ADS7852
SAR
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 CDAC 8-Channel MUX
3-State Parallel Data Bus Output Latches and 3-State Drivers CLK BUSY WR CS RD
Comparator Buffer 10k VREF Internal +2.5V Ref
International Airport Industrial Park * Mailing Address: PO Box 11400, Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 * Tel: (520) 746-1111 Twx: 910-952-1111 * Internet: http://www.burr-brown.com/ * Cable: BBRCORP * Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132
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1998 Burr-Brown Corporation
1 PDS-1509B
ADS7852 October, 1999 Printed in U.S.A.
SPECIFICATIONS
At TA = -40C to +85C, fS = 500kHz, fCLK = 16 * fS, and VSS = +5V, using internal reference, unless otherwise specified. ADS7852Y PARAMETER RESOLUTION ANALOG INPUT Input Voltage Range Input Impedance Input Capacitance Input Leakage Current DC ACCURACY No Missing Codes Integral Linearity Error Differential Linearity Error Offset Error Offset Error Drift Offset Error Match Gain Error(1) Gain Error Gain Error Drift Gain Error Match Noise Power Supply Rejection Ratio SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Multiplexer Settling Time Aperture Delay Aperture Jitter AC ACCURACY Signal-to-Noise Ratio Total Harmonic Distortion(3) Signal-to-(Noise+Distortion) Spurious Free Dynamic Range Channel-to-Channel Isolation REFERENCE OUTPUT Internal Reference Voltage Internal Reference Drift Input Impedance Source Current(4) REFERENCE INPUT Range Resistance(5) DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH VIL VOH VOL Data Format POWER SUPPLY REQUIREMENT +VSS Quiescent Current Normal Power Nap Mode Current(6) Sleep Mode Current(6) TEMPERATURE RANGE Specified Performance Storage 0 5M 15 1 12 1 2 4 Ext Ref = 2.5000V Int Ref 25 150 1.2 13.5 1.5 500 500 5 30 72 -74 70 74 95 2.50 30 5 5 T T T T -77 72 77 T T T T T T T 2 5 1 15 40 T 1 T T T T T 0.5 1 T 1 1 T T 10 25 CONDITIONS MIN TYP MAX 12 5 T T T T MIN ADS7852YB TYP MAX T T UNITS Bits V pF A Bits LSB(1) LSB LSB ppm/C LSB LSB LSB ppm/C LSB Vrms LSB Clk Cycles Clk Cycles kHz ns ns ps dB dB dB dB dB V ppm/C G G A V k
Worst-Case , +VSS = 5V 5%
VIN VIN VIN VIN
= = = =
5Vp-p 5Vp-p 5Vp-p 5Vp-p
at at at at
50kHz 50kHz 50kHz 50kHz
-72 71 78
-76
68 76
2.48 CS = GND CS = VSS Static Load 2.0 to Internal Reference Voltage
2.52
T
T
50 2.55 10 CMOS T T T +VSS + 0.3 0.8 0.4 Straight Binary T 5.25 3.5 17.5 800 30 +85 +150 T T T T T T T T T T
T T
IIH = +5A IIL = +5A IOH = 250A IOL = 250A
3 -0.3 3.5
T T T
V V V V
Specified Performance
4.75 2.6 13 600 10 -40 -65
T T T T T T T
V mA mW A A C C
NOTES: (1) LSB means Least Significant Bit, with VREF equal to +2.5V, one LSB is 1.22mV. (2) Measured relative to an ideal, full-scale input of 4.999V. Thus, gain error includes the error of the internal voltage reference. (3) Calculated on the first nine harmonics of the input frequency. (4) If the internal reference is required to source current to an external load, the reference voltage will change due to the internal 10k resistor. (5) Can vary 30%. (6) See Timing Diagrams for further detail.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
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ADS7852
2
PIN CONFIGURATION
Top View TQFP
PIN ASSIGNMENTS
PIN 1
DB0 (LSB)
NAME AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AGND VREF
DESCRIPTION Analog Input Channel 0 Analog Input Channel 1 Analog Input Channel 2 Analog Input Channel 3 Analog Input Channel 4 Analog Input Channel 5 Analog Input Channel 6 Analog Input Channel 7 Analog Ground, GND = 0V Voltage Reference Input and Output. See Specification Table for ranges. Decouple to ground with a 0.1F ceramic capacitor and a 2.2F tantalum capacitor. Digital Ground, GND = 0V Channel Address. See Channel Selection Table for details. Channel Address. See Channel Selection Table for details. Channel Address. See Channel Selection Table for details. Data Bit 11 (MSB) Data Bit 10 Data Bit 9 Data Bit 8 Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 Data Bit 0 (LSB) Write Input. Active LOW. Use to start a new conversion and to select an analog channel via address inputs A0, A1 and A2 in combination with CS. BUSY output goes LOW and stays LOW during a conversion. BUSY rises when a conversion is complete. External Clock Input. The clock speed determines the conversion rate by the equation: fCLK = 16 * fSAMPLE. Read Input. Active LOW. Use to read the data outputs in combination with CS. Also use (in conjunction with A0 or A1) to place device in power-down mode. Chip Select Input. Active LOW. The combination of CS taken LOW and WR taken LOW initiates a new conversion and places the outputs in tri-state mode. Voltage Supply Input. Nominally +5V. Decouple to ground with a 0.1F ceramic capacitor and a 10F tantalum capacitor.
2 3
DB1
BUSY
CLK
VSS
WR
RD
CS
4 5 6 7
32
31
30
29
28
27
26
25
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7
1 2 3 4 5 6 7 8
24 23 22
DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9
8 9 10
ADS7852Y
21 20 19 18 17
11 12 13 14 15 16 17 18 19 20 21 22
DGND A2 A1 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 WR
10
11
12
13
14
15 DB11 (MSB)
VREF
AGND
DGND
DB10
A2
A1
A0
16
9
ABSOLUTE MAXIMUM RATINGS(1)
Analog Inputs to AGND, Any Channel Input .............. -0.3V to (VD + 0.3V) REFIN ......................................................................... -0.3V to (VD + 0.3V) Digital Inputs to DGND .............................................. -0.3V to (VD + 0.3V) Ground Voltage Differences: AGND, DGND ..................................... 0.3V +VSS to AGND .......................................................................... -0.3V to 6V Power Dissipation .......................................................................... 325mW Maximum Junction Temperature ................................................... +150C Operating Temperature Range ......................................... -40C to +85C Storage Temperature Range .......................................... -65C to +150C Lead Temperature (soldering, 10s) ............................................... +300C NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.
23 24 25 26 27
28
BUSY
29
CLK
30
RD
ELECTROSTATIC DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications.
31
CS
32
VSS
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3
ADS7852
PACKAGE/ORDERING INFORMATION
MINIMUM RELATIVE ACCURACY (LSB) 2 MAXIMUM GAIN ERROR (LSB) 25 PACKAGE DRAWING NUMBER 351 SPECIFICATION TEMPERATURE RANGE -40C to +85C
PRODUCT ADS7852Y
PACKAGE 32-Lead TQFP
ORDERING NUMBER(1) ADS7852Y/250 ADS7852Y/2K ADS7852YB/250 ADS7852YB/2K
TRANSPORT MEDIA Tape Tape Tape Tape and and and and Reel Reel Reel Reel
"
ADS7852YB
"
1
"
40
"
32-Lead TQFP
"
351
"
-40C to +85C
"
"
"
"
"
"
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of "ADS7852Y/2K" will get a single 2000-piece Tape and Reel.
ADS7852 CHANNEL SELECTION
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 CHANNEL SELECTED Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7
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ADS7852
4
TYPICAL PERFORMANCE CURVES
At TA = +25C, VSS = +5V, fSAMPLE = 500kHz, fCLK = 16 * fSAMPLE, and internal reference, unless otherwise specified.
SPECTRAL PERFORMANCE (4096 Point FFT, fIN = 49.561kHz, -0.5dB) 0 -20 0 -20
SPECTRAL PERFORMANCE (4096 Point FFT, fIN = 100.7081kHz, -0.5dB)
Amplitude (dB)
-40 -60 -80 -100 -120 0 50 100 150 200 250 Frequency (kHz)
Amplitude (dB)
-40 -60 -80 -100 -120 0 50 100 150 200 250 Frequency (kHz)
SPECTRAL PERFORMANCE (4096 Point FFT, fIN = 199.5851kHz, -0.5dB) 0 -20 0 -20
SPECTRAL PERFORMANCE (4096 Point FFT, fIN = 247.1921kHz, -0.5dB)
Amplitude (dB)
Amplitude (dB)
0 50 100 150 200 250
-40 -60 -80 -100 -120 Frequency (kHz)
-40 -60 -80 -100 -120 0 50 100 150 200 250 Frequency (kHz)
CHANGE IN SPURIOUS FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs TEMPERATURE
SNR and SINAD Delta from +25C (dB)
CHANGE IN SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-(NOISE+DISTORTION) vs TEMPERATURE
1.0 fIN = 49.6kHz,-0.5dB
SFDR Delta from +25C (dB)
-1.0
0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -50 -25 0 25 Temperature (C) 50 75 100 SINAD fIN = 49.6kHz,-0.5dB SNR
*First nine harmonics
-0.5
THD Delta from +25C (dB)
of the input frequency 0.5 THD*
0.0 SFDR -0.5
0.0
0.5
-1.0 -50 -25 0 25 Temperature (C) 50 75 100
1.0
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5
ADS7852
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25C, VSS = +5V, fSAMPLE = 500kHz, fCLK = 16 * fSAMPLE, and internal reference, unless otherwise specified.
SIGNAL-TO-NOISE and SIGNAL-TO-(NOISE+DISTORTION) vs INPUT FREQUENCY 76 SNR 74
SPURIOUS FREE DYNAMIC RANGE and TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 90 SFDR 85 -85 THD* 80 -80 -90
SNR and SINAD (dB)
SINAD 70
68
75 *First nine harmonics of the input frequency
-75
66 1k 10k 100k 1M Input Frequency (Hz)
70 1k 10k 100k 1M
-70
INTEGRAL LINEARITY ERROR vs CODE 1.00 0.75 0.50 1.00 0.75 0.50
DIFFERENTIAL LINEARITY ERROR vs CODE
ILE (LSBs)
0.25 0.00 -0.25 -0.50 -0.75 -1.00 000H
DLE (LSBs)
0.25 0.00 -0.25 -0.50 -0.75 -1.00 000H
400H
800H Output Code
C00H
FFFH
400H
800H Output Code
C00H
FFFH
CHANGE IN INTERNAL REFERENCE VOLTAGE vs TEMPERATURE 6.0 4.0
CHANGE IN GAIN ERROR vs TEMPERATURE 8 6
Delta from +25C (LSB)
Delta from +25C (mV)
4 2 0 -2 -4 -6 -8
2.0 0.0 -2.0 -4.0 -6.0 -50 -25 0 25 Temperature (C) 50 75 100
-50
-25
0
25 Temperature (C)
50
75
100
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ADS7852
6
THD (dB)
72
SFDR (dB)
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25C, VSS = +5V, fSAMPLE = 500kHz, fCLK = 16 * fSAMPLE, and internal reference, unless otherwise specified.
CHANGE IN GAIN ERROR vs TEMPERATURE (With External 2.5V Reference) 0.5 0.4
Delta from +25C (LSB) Delta from +25C (LSB)
CHANGE IN OFFSET vs TEMPERATURE 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -50 -25 0 25 Temperature (C) 50 75 100
-50
-25
0
25 Temperature (C)
50
75
100
CHANGE IN WORST-CASE CHANNEL-TO-CHANNEL OFFSET MISMATCH vs TEMPERATURE 0.10 0.020 0.015
CHANGE IN WORST-CASE CHANNEL-TO-CHANNEL GAIN MISMATCH vs TEMPERATURE
Delta from +25C (LSB)
0.05
Delta from +25C (LSB)
-50 -25 0 25 Temperature (C) 50 75 100
0.010 0.005 0.000 -0.005 -0.010 -0.015
0.00
-0.05
-0.10
-0.020 -50 -25 0 25 Temperature (C) 50 75 100
CHANGE IN WORST-CASE INTEGRAL LINEARITY AND DIFFERENTIAL LINEARITY vs SAMPLE RATE
Delta Relative to fSAMPLE = 500kHz (LSB)
CHANGE IN WORST-CASE INTEGRAL LINEARITY AND DIFFERENTIAL LINEARITY vs TEMPERATURE 0.050
3.0 2.5
Delta from +25C (LSB)
2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 100 200 300 400 500 600 700 800 Sample Rate (kHz) Delta DL Delta IL
0.025
Delta IL
0.000
-0.025
Delta DL
-0.050 -50 -25 0 25 Temperature (C) 50 75 100
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ADS7852
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25C, VSS = +5V, fSAMPLE = 500kHz, fCLK = 16 * fSAMPLE, and internal reference, unless otherwise specified.
SUPPLY CURRENT vs TEMPERATURE 2.680 fSAMPLE = 500kHz 2.675
Supply Current (mA)
SUPPLY CURRENT vs SAMPLE RATE 2.9 2.8
Supply Current (mA)
2.7 2.6 2.5 2.4 2.3
2.670
2.665
2.660
2.655 -50 -25 0 25 Temperature (C) 50 75 100
100
200
300
400
500
600
Sample Rate (kHz)
CHANGE IN NAP CURRENT AND SLEEP CURRENT vs TEMPERATURE 25
0.25 0.20 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.20
CHANGE IN GAIN AND OFFSET vs SUPPLY VOLTAGE
15 Nap 10 5 0 -5 -10 -50 -25 0 25 50 75 100 Temperature (C)
Delta from VSS = 5.00V (LSB)
20 Delta from +25C (A)
Gain
Offset
Sleep
-0.25 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 VSS (V)
5.20 5.25
POWER SUPPLY REJECTION vs POWER SUPPLY RIPPLE FREQUENCY 30
Power Supply Rejection (mV/V)
25 20 15 10 5 0 10 100 1k 10k 100k 1M
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ADS7852
8
THEORY OF OPERATION
The ADS7852 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC) with an internal 2.5V bandgap reference. The architecture is based on capacitive redistribution which inherently includes a sample/hold function. The converter is fabricated on a 0.6micron CMOS process. See Figure 1 for the basic operating circuit for the ADS7852. The ADS7852 requires an external clock to run the conversion process. This clock can vary between 200kHz (12.5Hz throughput) and 8MHz (500kHz throughput). The duty cycle of the clock is unimportant as long as the minimum HIGH and LOW times are at least 50ns and the clock period is at least 125ns. The minimum clock frequency is governed by the parasitic leakage of the Capacitive Digital-to-Analog (CDAC) capacitors internal to the ADS7852.
The front-end input multiplexer of the ADS7852 features eight single-ended analog inputs. Channel selection is performed using the address pins A0 (pin 14), A1 (pin 13), and A2 (pin 12). When a conversion is initiated, the input voltage is sampled on the internal capacitor array. While a conversion is in progress, all channel inputs are disconnected from any internal function (see Truth Table for addressing). The range of the analog input is set by the voltage on the VREF pin. With the internal 2.5V reference, the input range is 0V to 5V. An external reference voltage can be placed on VREF, overdriving the internal voltage. The range for the external voltage is 2.0V to 2.55V, giving an input voltage range of 4.0V to 5.1V.
Busy Output BUSY 28
Chip Select
Clock Input
Read Input
+5V Analog Supply
+
10F
+
0.1F
VSS 32 CS 31 RD 30 CLK 29 WR 27 DB0 (LSB) 26 DB1 25
0V to 5V 1 2 3 4 5 6 7 8 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5
Write Input
DB2 24 DB3 23 DB4 22
ADS7852Y
DB5 21 DB6 20 DB7 19
15 DB11 (MSB)
AIN6 AIN7
11 DGND AGND 10 VREF 12 A2 13 A1 14 A0
DB8 18 DB9 17
16 DB10
9
A2 Select
A1 Select
0.1F
+
2.2F
+
FIGURE 1. Typical Circuit Configuration.
A0 Select
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9
ADS7852
ANALOG INPUTS
The ADS7852 features eight single-ended inputs. While the static current into each analog input is basically zero, the dynamic current depends on the input voltage and sample rate. Essentially, the current into the device must charge the internal hold capacitor during the sample period. After this capacitor has been fully charged, no further input current is required. For optimum performance, the source driving the analog inputs must be capable of charging the input capacitance to a 12-bit settling level within the sample period. This can be as little as 350ns in some operating modes. While the converter is in the hold mode, or after the sampling capacitor has been fully charged, the input impedance of the analog input is greater than 1G.
series 10k resistor that is connected to the 2.5V internal reference. Accounting for the maximum difference between the external reference voltage and the internal reference voltage, and the processing variations for the on-chip 10k resistor, this current can be as high as 75A. In addition, the VREF pin should still be bypassed to ground with at least a 0.1F ceramic capacitor placed as close to the ADS7852 as possible. Depending on the particular reference and ADC conversion speed, additional bypass capacitance may be required, such as the 2.2F tantalum capacitor shown in the Typical Circuit Configuration (Figure 1). Close attention should be paid to the stability of any external reference source that is driving the large bypass capacitors present at the VREF pin.
REFERENCE
The reference voltage on the VREF pin establishes the fullscale range of the analog input. The ADS7852 can operate with a reference in the range of 2.0V to 2.55V corresponding to a full-scale range of 4.0V to 5.1V. The voltage at the VREF pin is internally buffered and this buffer drives the capacitor DAC portion of the converter. This is important because the buffer greatly reduces the dynamic load placed on the reference source. Since the voltage at VREF will be unavoidably affected by noise and glitches generated during the conversion process, it is highly recommended that the VREF pin be bypassed to ground as outlined in the sections that follow. INTERNAL REFERENCE The ADS7852 contains an onboard 2.5V reference, resulting in a 0V to 5V input range on the analog input. The Specifications Table gives the various specifications for the internal reference. This reference can be used to supply a small amount of source current to an external load but the load should be static. Due to the internal 10k resistor, a dynamic load will cause variations in the reference voltage, and will dramatically affect the conversion result. Note that even a static load will reduce the internal reference voltage seen at the buffer input. The amount of reduction depends on the load and the actual value of the internal "10k" resistor. The value of this resistor can vary by 30%. The VREF pin should be bypassed with a 0.1F ceramic capacitor placed as close to the ADS7852 as possible. In addition, a 2.2F tantalum capacitor should be used in parallel with the ceramic capacitor. EXTERNAL REFERENCE The internal reference is connected to the VREF pin and to the internal buffer via an on-chip 10k series resistor. Because of this configuration, the internal reference voltage can easily be overridden by an external reference voltage. The voltage range for the external voltage is 2.00V to 2.55V, corresponding to an analog input range of 4.0V to 5.1V. While the external reference will not have to provide significant dynamic current to the VREF in, it does have to drive the
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BASIC OPERATION
Figure 1 shows the simple circuit required to operate the ADS7852 with Channel 0 selected. A conversion can be initiated by bringing the WR pin (pin 27) LOW for a minimum of 35ns. BUSY (pin 28) will output a LOW during the conversion process and rises only after the conversion is complete. The 12 bits of output data will be valid on pins 15 through 26 following the rising edge of BUSY. STARTING A CONVERSION A conversion is initiated on the falling edge of the WR input, with valid signals on A0, A1, A2, and CS. The ADS7852 will enter the conversion mode on the first rising edge of the external clock following the WR pin going LOW. The conversion process takes 13.5 clock cycles (1.5 cycles for the DB0 decision, 2 clock cycles for the DB5 decision, and 1 clock cycle for each of the other bit decisions). This allows 2.5 clock cycles for sampling. Upon initiating a conversion, the BUSY output will go LOW approximately 20ns after the falling edge of the WR pin. The BUSY output will return HIGH just after the ADS7852 has finished a conversion and the output data will be valid on pins 15 through 26. The rising edge of BUSY can be used to latch the output data into an external device. It is recommended that the data be read immediately after each conversion since the switching noise of the asynchronous data transfer can cause digital feedthrough degrading the converter's performance. See Figure 2. CHANNEL ADDRESSING The selection of the analog input channel to be converted is controlled by address pins A0, A1, and A2. This channel becomes active on the rising edge of WR with CS held LOW. The data on the address pins should be stable for at least 10ns prior to WR going HIGH. The address pins are also used to control the power-down functions of the ADS7852. Careful attention must be paid to the status of the address pins following each conversion. If the user does not want the ADS7852 to enter either of the power-down modes following a conversion, the A0 and A1 pins must be LOW when RD and CS are returned HIGH after reading the data at the end of a conversion (see the PowerDown Mode section of this data sheet for more details). 10
ADS7852
HOLD tCKH CLK
1 2 3 4 5 6 7 8 9
tCKP
10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8
tCKL t1 WR t2
t4
t4 CS t5 BUSY Conversion n tCONV RD t7 t8 Address Bus Address n + 1 t9 t10 Data Bus Hi-Z
Data Valid
t3
Conversion n + 1 tACQ t6
Address n + 2
Hi-Z
Data Valid
Hi-Z
SYMBOL tCONV tACQ tCKP tCKL tCKH t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15
DESCRIPTION Conversion Time Acquisition Time Clock Period Clock LOW Clock HIGH WR LOW Prior to Rising Edge of CLK WR LOW After Rising Edge of CLK CS LOW After Rising Edge of CLK CS and RD HIGH BUSY Delay After CS LOW RD LOW Address Hold Time Address Setup Time Bus Access Time Bus Relinquish Time CS to RD Setup Time RD to CS Hold Time CLK LOW to BUSY HIGH BUSY to RD Delay RD HIGH to CLK LOW
MIN
TYP
MAX 1.75 0.25 5000
UNITS s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
125 40 40 35 20 20 25 20 25 5 5 30 5 0 0 10 0 50
FIGURE 2. ADS7852 Write/Read Timing. READING DATA Data from the ADS7852 will appear at pins 15 through 26. The MSB will output on pin 15 while the LSB will output on pin 26. The outputs are coded in Straight Binary (with 0V = 000H and 5V = FFFH). Following a conversion, the BUSY pin will go HIGH. After BUSY has been HIGH for at least t14 seconds, the CS and RD pins may be brought LOW to enable the 12-bit output bus. CS and RD must be held LOW for at least 25ns following BUSY HIGH. Data will be valid 30ns after the falling edge of both CS and RD. The output data will remain valid for 20ns following the rising edge of both CS and RD. See Figure 2 for the read cycle timing diagram.
DIGITAL OUTPUT STRAIGHT BINARY DESCRIPTION Least Significant Bit (LSB) Full Scale Midscale Midscale -1LSB Zero Full Scale ANALOG INPUT 1.2207mV 4.99878V 2.5V 2.49878V 0V 1111 1111 1111 1000 0000 0000 0111 1111 1111 0000 0000 0000 FFF 800 7FF 000 BINARY CODE HEX CODE
Table I. Ideal Input Voltages and Output Codes.
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ADS7852
POWER-DOWN MODE The ADS7852 has two different power-down modes: the Nap mode and the Sleep mode. In the Nap mode, all analog and digital circuitry, with the exception of the voltage reference, is powered off. In the Sleep mode, everything is powered off. While the Sleep mode affords the lowest power consumption, the time to come out of Sleep mode can be considerable since it takes the internal reference voltage a finite amount of time to power up and reach a stable value. This latency can result in spurious output data for a minimum of ten conversion cycles at a 500kHz sampling rate. It should also be noted that any external load connected to the VREF pin will exacerbate this effect since a discharge path for the VREF bypass capacitor is provided during the Sleep cycle. Even the parasitic leakage of the bypass capacitor itself should be considered if the unit is left in the Sleep mode for an extended period. After power-up, this capacitor must be recharged by the internal reference voltage and the on-chip 10k series resistor. Under worst-case conditions (e.g., the bypass capacitor is completely discharged), the output data can be invalid for several hundred milliseconds.
Since the Nap mode maintains the voltage on the VREF pin by keeping the internal reference powered-up, valid conversions are available immediately after the Nap mode is terminated. The simplest way to use the power-down mode is following a conversion. After a conversion has finished and BUSY has returned HIGH, CS and RD must be brought LOW for a minimum of 25ns. When RD and CS are returned HIGH, the ADS7852 will enter the power-down mode on the rising edge of RD. If CS is always kept LOW, the power-down mode will be controlled exclusively by RD. Depending on the status of the A0 and A1 address pins, the ADS7852 will either enter the Nap mode, the Sleep mode, or be returned to normal operation in the sampling mode. See Table II and Figures 3 and 4 for further details.
RD A2 X X X X A1 0 1 0 1 A0 0 0 1 1 POWER-DOWN MODE None Sleep Nap Sleep
= Signifies rising edge of RD pin. X = Don't care
TABLE II. ADS7852 Power-Down Mode.
CS t11 t6 RD t12
CLK t13 BUSY
t14
A1
t7
t8
A0 NOTE: Rising edge of 1st RD while A0 = 1 initiates power-down immediately. A1 must be LOW to enter Nap mode.
FIGURE 3. Entering Nap Using RD and A0.
CS t11 t6 RD t15 CLK t12
A1
t7
t8
A0 NOTE: Rising edge of 2nd RD while A0 = 0 places the ADS7852 in sample mode. A1 must be LOW to initiate wake-up.
FIGURE 4. Initiating Wake-Up Using RD and A0.
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ADS7852
12
LAYOUT
Test Point VCC DOUT 3k 100pF CLOAD Load Circuit for tdis and ten tdis Waveform 2, ten tdis Waveform 1
CS/SHDN
VIH
DOUT Waveform 1(1) tdis DOUT Waveform 2(2) Voltage Waveforms for tdis
90%
10%
NOTES: (1) Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control.
FIGURE 5. Timing Diagram and Test Circuits for Parameters in Figure 2. In addition to using the address pins in conjunction with RD, the power-down mode can also be terminated implicitly by starting a new conversion (e.g., taking WR LOW while CS is LOW). If it is desired to keep the ADS7852 in a powerdown state for a period that is greater than dictated by the sampling rate, the convert signal driving the WR pin must be disabled. The typical supply current of the ADS7852, with a 5V supply and a 500kHz sampling rate, is 2.6mA. In the Nap mode, the typical supply current is 600A. In the Sleep mode, the current is typically reduced to 10A.
For optimum performance, care should be taken with the physical layout of the ADS7852 circuitry. This is particularly true if the CLK input is approaching the maximum throughput rate. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any single conversion for an n-bit SAR converter, there are n "windows" in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, or high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. Their error can change if the external event changes in times with respect to the CLK input. With this in mind, power to the ADS7852 should be clean and well bypassed. A 0.1F ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1F to 10F capacitor is recommended. If needed an even larger capacitor and a 5 or 10 series resistor may be used to low pass filter a noisy supply. The ADS7852 draws very little current from an external reference on average as the reference voltage is internally buffered. However, glitches from the conversion process appear at the VREF input and the reference source must be able to handle this. Whether the reference is internal or external, the VREF pin should be bypassed with a 0.1F capacitor. An additional larger capacitor may also be used, if desired. If the reference voltage is external and originates from an op amp, make sure it can drive the bypass capacitor or capacitors without oscillation. The GND pin should be connected to a clean ground point. In many cases, this will be the "analog" ground. Avoid connections which are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power supply entry point. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry.
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13
ADS7852

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