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ADC08100 8-Bit, 100 MSPS, 1.3 mW/MSPS A/D Converter
June 2000
ADC08100 8-Bit, 100 MSPS, 1.3 mW/MSPS A/D Converter
General Description
The ADC08100 is a low-power, 8-bit, monolithic analog-todigital converter with an on-chip track-and-hold circuit. Optimized for low cost, low power, small size and ease of use, this product operates at conversion rates of 20 MSPS to 125 MSPS with outstanding dynamic performance over its full operating range while consuming just 1.3 mW per MHz of clock frequency. That's just 130 mW of power at 100 MSPS. Raising the PD pin puts the ADC08100 into a Power Down mode where it consumes just 1 mW. The unique architecture achieves 7.4 Effective Bits with 40 MHz input frequency. The excellent DC and AC characteristics of this device, together with its low power consumption and single +3V supply operation, make it ideally suited for many imaging and communications applications, including use in portable equipment. Furthermore, the ADC08100 is resistant to latch-up and the outputs are short-circuit proof. The top and bottom of the ADC08100's reference ladder are available for connections, enabling a wide range of input possibilities. The digital outputs are TTL/CMOS compatible with a separate output power supply pin to support interfacing with 3V or 2.5V logic. The digital inputs (CLK and PD) are TTL/CMOS compatible. The ADC08100 is offered in a 24-lead plastic package (TSSOP) and is specified over the industrial temperature range of -40C to +85C.
Features
n n n n n Single-ended input Internal sample-and-hold function Low voltage (single +3V) operation Small package Power-down feature
Key Specifications
n n n n n n n Resolution 8 bits Maximum sampling frequency 100 MSPS (min) DNL 0.4 LSB (typ) ENOB 7.4 bits (typ) at fIN = 41 MHz THD -60 dB (typ) Guaranteed no missing codes Power consumption -- Operating: 1.3 mW/MSPS (typ) -- Power down: 1 mW (typ)
Applications
n n n n n n n n n Flat panel displays Projection systems Set-top boxes Battery-powered instruments Communications Medical scan converters X-ray imaging High speed viterbi decoders Astronomy
Pin Configuration
DS101371-1
(c) 2000 National Semiconductor Corporation
DS101371
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ADC08100
Ordering Information
ADC08100CIMTC ADC08100CIMTCX TSSOP TSSOP (tape and reel)
Block Diagram
DS101371-2
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Equivalent Circuit Description
6
VIN
Analog signal input. Conversion range is VRB to VRT.
3
VRT
Analog Input that is the high (top) side of the reference ladder of the ADC. Nominal range is 1.0V to 2.3V. Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See Section 2.0 for more information. Mid-point of the reference ladder. This pin should be bypassed to a clean, quiet point in the analog ground plane with a 0.1 F capacitor. Analog Input that is the low side (bottom) of the reference ladder of the ADC. Nominal range is 0.0V to (VRT - 1.0V). Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See Section 2.0 for more information.
9
VRM
10
VRB
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ADC08100
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Equivalent Circuit
(Continued) Description Power Down input. When this pin is high, the converter is in the Power Down mode and the data output pins hold the last conversion result.
23
PD
24
CLK
CMOS/TTL compatible digital clock Input. VIN is sampled on the falling edge of CLK input.
13 thru 16 and 19 thru 22
D0-D7
Conversion data digital Output pins. D0 is the LSB, D7 is the MSB. Valid data is output just after the rising edge of the CLK input.
7
VIN GND
Reference ground for the single-ended analog input, VIN. Positive analog supply pin. Connect to a clean, quiet voltage source of +3V. VA should be bypassed with a 0.1 F ceramic chip capacitor for each pin, plus one 10 F capacitor. See Section 3.0 for more information. Power supply for the output drivers. If connected to VA, decouple well from VA. The ground return for the output driver supply. The ground return for the analog supply.
1, 4, 12
VA
18 17 2, 5, 8, 11
DR VD DR GND AGND
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ADC08100
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA) Voltage on Any Input or Output Pin Reference Voltage (VRT, VRB) CLK, OE Voltage Range Digital Output Voltage (VOH, VOL) Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Dissipation at TA = 25C ESD Susceptibility (Note 5) Human Body Model Machine Model 3.8V -0.3V to VA VA to AGND -0.3V to (VA + 0.3V) DR GND to DR VD 25 mA 50 mA See (Note 4) 2500V 250V
Soldering Temperature, Infrared, 10 seconds (Note 6) Storage Temperature
235C -65C to +150C
Operating Ratings (Notes 1, 2)
Operating Temperature Range Supply Voltage (VA) Ground Difference |GND - DR GND| Upper Reference Voltage (VRT) Lower Reference Voltage (VRB) VIN Voltage Range -40C TA +85C +2.7V to +3.6V 0V to 300 mV 1.0V to (VA + 0.1V) 0V to (VRT - 1.0V) VRB to VRT
Converter Electrical Characteristics
The following specifications apply for VA = DR VD = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 100 MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25C (Notes 7, 8) Symbol DC ACCURACY INL DNL Integral Non-Linearity Differential Non-Linearity Missing Codes FSE VOFF Full Scale Error Zero Scale Offset 18 26 Parameter Conditions Typical (Note 9) Limits (Note 9) Units (Limits) LSB (max) LSB (max) LSB (min) (max) mV (max) mV (max) V (min) V (max) pF pF M MHz 2.3 1.0 VRT - 1.0 0 150 300 5.3 10.6 2.0 0.8 10 -50 3 VA = DR VD = 2.7V, IOH = -400 A VA = DR VD = 2.7V, IOL = 1.0 mA 2.6 0.4 2.4 0.5 V (max) V (min) V (max) V (min) (min) (max) mA (min) mA (max) V (min) V (max) nA nA pF V (min) V (max)
0.5 0.4
1.3
+1.0 -0.95 0
28 35
VRB VRT
ANALOG INPUT AND REFERENCE CHARACTERISTICS VIN CIN RIN BW VRT VRB RREF IREF Input Voltage VIN Input Capacitance RIN Input Resistance Full Power Bandwidth Top Reference Voltage Bottom Reference Voltage Reference Ladder Resistance Reference Ladder Current VRT to VRB VIN = 0.75V +0.5 Vrms (CLK LOW) (CLK HIGH) 1.6 3 4
>1
200 1.9 0.3 220 7.3
CLK, PD DIGITAL INPUT CHARACTERISTICS VIH VIL IIH IIL CIN VOH VOL Logical High Input Voltage Logical Low Input Voltage Logical High Input Current Logical Low Input Current Logic Input Capacitance High Level Output Voltage Low Level Output Voltage DR VD = VA = 3.3V DR VD = VA = 2.7V VIH = DR VD = VA = 3.3V VIL = 0V, DR VD = VA = 2.7V
DIGITAL OUTPUT CHARACTERISTICS
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ADC08100
Converter Electrical Characteristics
(Continued)
The following specifications apply for VA = DR VD = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 100 MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25C (Notes 7, 8) Symbol Parameter Conditions Typical (Note 9) 7.5 7.5 7.3 7.3 7.2 47 47 46 46 45 47 47 46.5 45.8 61 60 63 54 -61 -60 -60 -54 -62 -60 -63 -54 -68 -65 -64 -68 -48 44 42.8 43.9 43.3 42.7 7.0 6.9 6.8 Limits (Note 9) Units (Limits) Bits Bits (min) Bits (min) Bits (min) Bits dB dB (min) dB (min) dB (min) dB dB dB (min) dB (min) dB dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
DYNAMIC PERFORMANCE fIN = 4 MHz, VIN = FS - 0.25 dB fIN = 10 MHz, VIN = FS - 0.25 dB ENOB Effective Number of Bits fIN = 41 MHz, VIN = FS - 0.25 dB, TA= 25C fIN = 41 MHz, VIN = FS - 0.25 dB, TA = TMIN to TMAX fIN = 49.8 MHz, VIN = FS - 0.25 dB fIN = 4 MHz, VIN = FS - 0.25 dB fIN = 10 MHz, VIN = FS - 0.25 dB SINAD Signal-to-Noise & Distortion fIN = 41 MHz, VIN = FS - 0.25 dB, TA= 25C fIN = 41 MHz, VIN = FS - 0.25 dB, TA = TMIN to TMAX fIN = 49.8 MHz, VIN = FS - 0.25 dB fIN = 4 MHz, VIN = FS - 0.25 dB SNR Signal-to-Noise Ratio fIN = 10 MHz, VIN = FS - 0.25 dB fIN = 41 MHz, VIN = FS - 0.25 dB fIN = 49.8 MHz, VIN = FS - 0.25 dB fIN = 4 MHz, VIN = FS - 0.25 dB SFDR Spurious Free Dynamic Range fIN = 10 MHz, VIN = FS - 0.25 dB fIN = 41 MHz, VIN = FS - 0.25 dB fIN = 49.8 MHz, VIN = FS - 0.25 dB fIN = 4 MHz, VIN = FS - 0.25 dB THD Total Harmonic Distortion fIN = 10 MHz, VIN = FS - 0.25 dB fIN = 41 MHz, VIN = FS - 0.25 dB fIN = 49.8 MHz, VIN = FS - 0.25 dB fIN = 4 MHz, VIN = FS - 0.25 dB HD2 2nd Harmonic Distortion fIN = 10 MHz, VIN = FS - 0.25 dB fIN = 41 MHz, VIN = FS - 0.25 dB fIN = 49.8 MHz, VIN = FS - 0.25 dB fIN = 4 MHz, VIN = FS - 0.25 dB HD3 3rd Harmonic Distortion fIN = 10 MHz, VIN = FS - 0.25 dB fIN = 41 MHz, VIN = FS - 0.25 dB fIN = 49.8 MHz, VIN = FS - 0.25 dB IMD Intermodulation Distortion f1 = 9 MHz, VIN = FS - 6.25 dB f2 = 10 MHz, VIN = FS - 6.25 dB DC Input fIN = 10 MHz, VIN = FS - 3 dB DC Input fIN = 10 MHz, VIN = FS - 3 dB DC Input IA + DRID Total Operating Current fIN = 10 MHz, VIN = FS - 3 dB, PD = Low CLK Low, PD = Hi
POWER SUPPLY CHARACTERISTICS IA DR ID Analog Supply Current Output Driver Supply Current 41 41 1 8 42 49 0.2 52 mA (max) 2 50 mA (max) mA (max) mA (max) mA (max)
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ADC08100
Converter Electrical Characteristics
(Continued)
The following specifications apply for VA = DR VD = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 100 MHz at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25C (Notes 7, 8) Symbol Parameter Conditions Typical (Note 9) 126 147 0.6 54 TBD Limits (Note 9) 156 Units (Limits) mW (max) mW mW dB dB
POWER SUPPLY CHARACTERISTICS DC Input PC Power Consumption fIN = 10 MHz, VIN = FS - 3 dB, PD = Low CLK Low, PD = Hi PSRR1 PSRR2 Power Supply Rejection Ratio Power Supply Rejection Ratio FSE change with 2.7V to 3.3V change in VA SNR change with 200 mV at 1 MHz on supply
AC ELECTRICAL CHARACTERISTICS fC1 fC2 tCL tCH tOH tOD tAD tAJ Maximum Conversion Rate Minimum Conversion Rate Minimum Clock Low Time Minimum Clock High Time Output Hold Time Output Delay Pipeline Delay (Latency) Sampling (Aperture) Delay Aperture Jitter CLK Low to Acquisition of Data CLK High to Data Invalid CLK High to Data Valid 4.4 5.9 2.5 1.5 2 8.5 125 20 4.5 4.5 100 MHz (min) MHz ns (min) ns (min) ns ns (max) Clock Cycles ns ps rms
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AGND or DR GND, or greater than VA or DR VD), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150C. The maximum allowable power dissipation is dictated by TJmax, the junctionto-ambient thermal resistance (JA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax - TA) / JA. In the 24-pin TSSOP, JA is 92C/W, so PDMAX = 1,358 mW at 25C and 435 mW at the maximum operating ambient temperature of 85C. Note that the power consumption of this device under normal operation will typically be about 162 mW (126 mW quiescent power + 12 mW reference ladder power + 24 mW to drive the output bus capacitance). The values for maximum power dissipation listed above will be reached only when the ADC08100 is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k resistor. Machine model is 220 pF discharged through ZERO Ohms. Note 6: See AN-450, "Surface Mounting Methods and Their Effect on Product Reliability", or the section entitled "Surface Mount" found in any post 1986 National Semiconductor Linear Data Book, for other methods of soldering surface mount devices. Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device. However, errors in the A/D conversion can occur if the input goes above DR VD or below GND by more than 100 mV. For example, if VA is 2.7VDC the full-scale input voltage must be 2.6VDC to ensure accurate conversions.
DS101371-7
Note 8: To guarantee accuracy, it is required that VA and DR VD be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Note 9: Typical figures are at TJ = 25C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
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ADC08100
Typical Performance Characteristics
wise stated INL
VA = DR VD = 3V, fCLK = 100 MHz, fIN = 41 MHz, unless other-
INL vs Temperature
DS101371-8
DS101371-14
INL vs Supply Voltage
INL vs Sample Rate
DS101371-10 DS101371-15
DNL
DNL vs Temperature
DS101371-9
DS101371-17
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ADC08100
Typical Performance Characteristics
otherwise stated (Continued) DNL vs Supply Voltage
VA = DR VD = 3V, fCLK = 100 MHz, fIN = 41 MHz, unless
DNL vs Sample Rate
DS101371-11 DS101371-18
SNR vs Temperature
SNR vs Supply Voltage
DS101371-20 DS101371-21
SNR vs Sample Rate
SNR vs Input Frequency
DS101371-12
DS101371-23
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ADC08100
Typical Performance Characteristics
otherwise stated (Continued) SNR vs Clock Duty Cycle
VA = DR VD = 3V, fCLK = 100 MHz, fIN = 41 MHz, unless
Distortion vs Temperature
DS101371-24
DS101371-25
Distortion vs Supply Voltage
Distortion vs Sample Rate
DS101371-13 DS101371-26
Distortion vs Input Frequency
Distortion vs Clock Duty Cycle
DS101371-28
DS101371-29
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ADC08100
Typical Performance Characteristics
otherwise stated (Continued) SINAD/ENOB vs Temperature
VA = DR VD = 3V, fCLK = 100 MHz, fIN = 41 MHz, unless
SINAD/ENOB vs Supply Voltage
DS101371-30 DS101371-38
SIND/ENOB vs Sample Rate
SINAD/ENOB vs Input Frequency
DS101371-16
DS101371-39
SINAD/ENOB vs Clock Duty Cycle
Power Consumption vs Sample Rate
DS101371-40
DS101371-19
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ADC08100
Typical Performance Characteristics
otherwise stated (Continued) Spectral Response @ fIN = 10 MHz
VA = DR VD = 3V, fCLK = 100 MHz, fIN = 41 MHz, unless
Spectral Response @ fIN = 41 MHz
DS101371-44
DS101371-45
Spectral Response @ fIN = 76 MHz
DS101371-42
Specification Definitions
APERTURE (SAMPLING) DELAY is that time required after the fall of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the "hold" mode tAD after the clock goes low. APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as input noise. BOTTOM OFFSET is the difference between the input voltage that just causes the output code to transition to the first code and the negative reference voltage. Bottom Offset is defined as EOB = VZT - VRB, where VZT is the first code transition input voltage. VRB is the lower reference voltage. Note that this is different from the normal Zero Scale Error. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. Measured at 100 MSPS with a ramp input. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion Ratio, or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. ANALOG INPUT BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. The
test is performed with fIN equal to 100 kHz plus integer multiples of fCLK. The input frequency at which the output is -3 dB relative to the low frequency input signal is the full power bandwidth. FULL-SCALE ERROR is a measure of how far the last code transition is from the ideal 112 LSB below VREF and is defined as: Vmax + 1.5 LSB - VREF where Vmax is the voltage at which the transition to the maximum (full scale) code occurs. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from zero scale (12 LSB below the first code transition) through positive full scale (12 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. The end point test method is used. Measured at 100 MSPS with a ramp input. OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the output pins. OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock. PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data is pre-
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ADC08100
Specification Definitions
(Continued)
sented to the output driver stage. New data is available at every clock cycle, but the data lags the conversion by the Pipeline Delay plus the Output Delay. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or dc. SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of the
input signal at the output to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding dc. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first six harmonic components to the rms value of the input signal at the output.
Timing Diagram
DS101371-31
FIGURE 1. ADC08100 Timing Diagram
Functional Description
The ADC08100 uses a new, unique architecture that achieves over 7 effective bits at input frequencies up to and beyond 50 MHz. The analog input signal that is within the voltage range set by VRT and VRB is digitized to eight bits. Input voltages below VRB will cause the output word to consist of all zeroes. Input voltages above VRB will cause the output word to consist of all ones. Incorporating a switched capacitor bandgap, the ADC08100 exhibits a power consumption that is proportional to frequency, limiting power consumption to what is needed at the clock rate that is used. This and its excellent performance over a wide range of clock frequencies makes it an ideal choice as a single ADC for many 8-bit needs. Data is acquired at the falling edge of the clock and the digital equivalent of that data is available at the digital outputs 2.5 clock cycles plus tOD later. The ADC08100 will convert as
long as the clock signal is present. The device is in the active state when the Power Down pin (PD) is low. When the PD pin is high, the device is in the power down mode, where the output pins hold the last conversion before the PD pin went high and the device consumes just 1 mW.
Applications Information
1.0 REFERENCE INPUTS The reference inputs VRT and VRB are the top and bottom of the reference ladder, respectively. Input signals between these two voltages will be digitized to 8 bits. External voltages applied to the reference input pins should be within the range specified in the Operating Ratings table (1.0V to (VA + 0.1V) for VRT and -100 mV to (VRT - 1.0V) for VRB). Any device used to drive the reference pins should be able to source sufficient current into the VRT pin and sink sufficient current from the VRB pin.
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ADC08100
Applications Information
(Continued)
DS101371-32
FIGURE 2. Simple, low component count reference biasing. Because of the ladder and external resistor tolerances, the reference voltage can vary too much for some applications. The reference bias circuit of Figure 2 is very simple and the performance is adequate for many applications. However, circuit tolerances will lead to a wide referance voltage range. Superior performance can generally be achieved by driving the reference pins with a low impedance source. The circuit of Figure 3 will allow a more accurate setting of the reference voltages. The lower amplifier must have bipolar supplies as its output voltage must go negative to force VRB to any voltage below the VBE of the PNP transistor. Of course, the divider resistors at the amplifier input could be changed to suit your reference voltage needs, or the divider can be replaced with potentiometers for precise settings. The bottom of the ladder (VRB) may simply be returned to ground if the minimum input signal excursion is 0V. Be sure that the driving source can source sufficient current into the VRT pin and sink enough current from the VRB pin to keep these pins stable. The LMC662 amplifier shown was chosen for its low offset voltage and low cost.
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ADC08100
Applications Information
(Continued)
DS101371-33
FIGURE 3. Driving the reference to force desired values requires driving with a low impedance source. VRT should always be at least 1.0V more positive than VRB to minimize noise. The VRM pin is the center of the reference ladder and should be bypassed to a clean, quiet point in the analog ground plane with a 0.1 F capacitor. DO NOT allow this pin to float. 2.0 THE ANALOG INPUT The analog input of the ADC08100 is a switch followed by an integrator. The input capacitance changes with the clock level, appearing as 3 pF when the clock is low, and 4 pF when the clock is high. Since a dynamic capacitance is more difficult to drive than is a fixed capacitance, choose an amplifier that can drive this type of load. The CLC409 and the CLC428 have been found to be good amplifiers to drive the ADC08100.
Figure 4 shows an example of an input circuit using the CLC409. Any input amplifier should incorporate some gain as operational amplifiers exhibit better phase margin and transient response with gains above 2 or 3 than with unity gain. If an overall gain of less than 3 is required, attenuate the input and operate the amplifier at a higher gain, as shown in Figure 4.
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ADC08100
Applications Information
(Continued)
DS101371-34
FIGURE 4. The input amplifier should incorporate some gain for best performance (see text). The RC at the amplifier output filters the clock rate energy that comes out of the analog input due to the input sampling circuit. The optimum time constant for this circuit depends not only upon the amplifier and ADC, but also on the circuit layout and board material. A resistor value should be chosen between 18 and 47 and the capacitor value chose according to the formula 0.1 F ceramic chip capacitor placed within one centimeter of the converter's power supply pins. Leadless chip capacitors are preferred because they have low lead inductance. While a single voltage source is recommended for the VA and DR VD supplies of the ADC08100, these supply pins should be well isolated from each other to prevent any digital noise from being coupled into the analog portions of the ADC. A choke or 27 resistor is recommended between these supply lines with adequate bypass capacitors close to the supply pins. As is the case with all high speed converters, the ADC08100 should be assumed to have little power supply rejection. None of the supplies for the converter should be the supply that is used for other digital circuitry in any system with a lot of digital power being consumed. The ADC supplies should be the same supply used for other analog circuitry. No pin should ever have a voltage on it that is in excess of the supply voltage or below ground by more than 300 mV, not even on a transient basis. This can be a problem upon application of power and power shut-down. Be sure that the supplies to circuits driving any of the input pins, analog or digital, do not come up any faster than does the voltage at the ADC08100 power pins. 4.0 THE DIGITAL INPUT PINS The ADC08100 has two digital input pins: The PD pin and the Clock pin. 4.1 The PD Pin The Power Down (PD) pin, when high, puts the ADC08100 into a low power mode where power consumption is reduced to 1 mW. Once the clock is restored, there is a time of 2.5 clock cycles plus tOD before the output data is valid.
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This will provide optimum SNR performance. Best THD performance is realized when the capacitor and resistor values are both zero. To optimize SINAD, reduce the capacitor value until SINAD performance is optimized. That is, until SNR = -THD. This value will usually be in the range of 40% to 65% of the value calculated with the above formula. An accurate calculation is not possible because of the board material and layout dependance. The circuit of Figure 4 has both gain and offset adjustments. If you eliminate these adjustments normal circuit tolerances may cause signal clipping unless care is exercised in the worst case analysis of component tolerance and the input signal excursion is appropriately limited to account for the worst case conditions. Of course, this means that the designer will not be able to count on getting a full scale output with maximum signal input. 3.0 POWER SUPPLY CONSIDERATIONS A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A 10 F tantalum or aluminum electrolytic capacitor should be placed within an inch (2.5 cm) of the A/D power pins, with a
ADC08100
Applications Information
(Continued)
The digital output pins retain the last conversion output code when either the clock is stopped or the PD pin is high. 4.2 The ADC08100 Clock Although the ADC08100 is tested and its performance is guaranteed with a 100 MHz clock, it typically will function well with clock frequencies from 20 MHz to 125 MHz. The trace bringing the clock signal to the converter clock pin should be as short as possible. If it is longer than 1 cm, be sure that the source impedance of the driver is 100 and terminate the clock line within 1 cm of the ADC clock pin with a series combination of a 100 resistor and a 3 pF capacitor to ground. Halting the clock will provide nearly as much power saving as raising the PD pin high. Typical power consumption with a stopped clock is 3 mW, compared to 1 mW when PD is high. The digital outputs will remain in the same state as they were before the clock was halted. Once the clock is restored (or the PD pin is brought low), there is a time of 2.5 clock cycles plus tOD before the output data is valid. However, because of the linear relationship between total power consumption and clock frequency, the part requires several microseconds after the clock is restarted or substantially changed in frequency before the part returns to its specified accuracy. 5.0 LAYOUT AND GROUNDING Proper grounding and proper routing of all signals are essential to ensure accurate conversion. A combined analog and digital ground plane should be used. Since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon the logic-generated noise because of the skin effect. Total surface area is more important than is total ground plane volume. Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance that may seem impossible to isolate and remedy. The solution is to keep the analog circuitry well separated from the digital circuitry. High power digital components should not be located on or near a straight line between the ADC or any linear component and the power supply area as the resulting common return current path could cause fluctuation in the analog input "ground" return of the ADC. Generally, analog and digital lines should cross each other at 90 to avoid getting digital noise into the analog path. In high frequency systems, however, avoid crossing analog and digital lines altogether. Clock lines should be isolated from ALL other lines, analog AND digital. Even the generally accepted 90 crossing should be avoided as even a little coupling can cause problems at high frequencies. Best performance at high frequencies is obtained with a straight signal path. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter's input and ground should be connected to a very clean point in the analog ground plane.
DS101371-36
FIGURE 5. Layout Example
Figure 5 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed together away from any digital components.
6.0 DYNAMIC PERFORMANCE The ADC08100 is ac tested and its dynamic performance is guaranteed. To meet the published specifications, the clock source driving the CLK input must exhibit less than 3 ps (rms) of jitter. For best ac performance, isolating the ADC clock from any digital circuitry should be done with adequate buffers, as with a clock tree. See Figure 6. It is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal. The clock signal can also introduce noise into the analog path.
DS101371-37
FIGURE 6. Isolating the ADC Clock from Digital Circuitry 7.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should not go more than 300 mV below the ground pins or 300 mV above the supply pins. Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital circuits (e.g., 74F and 74AC devices) to exhibit undershoot that goes more than a volt below ground. A 51 resistor in series with the offending digital input will usually eliminate the problem.
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ADC08100
Applications Information
(Continued)
Care should be taken not to overdrive the inputs of the ADC08100. Such practice may lead to conversion inaccuracies and even to device damage. Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current is required from DR VD and DR GND. These large charging current spikes can couple into the analog section, degrading dynamic performance. Buffering the digital data outputs (with a 74AF541, for example) may be necessary if the data bus capacitance exceeds 10 pF. Dynamic performance can also be improved by adding 47 to 56 series resistors at each digital output, reducing the energy coupled back into the converter input pins. Using an inadequate amplifier to drive the analog input. As explained in Section 2.0, the capacitance seen at the input alternates between 3 pF and 4 pF with the clock. This dynamic capacitance is more difficult to drive than is a fixed ca-
pacitance, and should be considered when choosing a driving device. The CLC409 and the CLC428 have been found to be good devices for driving the ADC08100. Driving the VRT pin or the VRB pin with devices that can not source or sink the current required by the ladder. As mentioned in Section 1.0, care should be taken to see that any driving devices can source sufficient current into the VRT pin and sink sufficient current from the VRB pin. If these pins are not driven with devices than can handle the required current, these reference pins will not be stable, resulting in a reduction of dynamic performance. Using a clock source with excessive jitter, using an excessively long clock signal trace, or having other signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive output noise and a reduction in SNR performance. The use of simple gates with RC timing is generally inadequate as a clock source.
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ADC08100
Physical Dimensions
inches (millimeters) unless otherwise noted
NOTES: UNLESS OTHERWISE SPECIFIED REFERENCE JECED REGISTRATION mo-153, VARIATION AD, DATED 7/93. 24-Lead Package TC Order Number ADC08100CIMT NS Package Number MTC24
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ADC08100 8-Bit, 100 MSPS, 1.3 mW/MSPS A/D Converter
Notes
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Francais Tel: +33 (0) 1 41 91 8790
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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