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12-Bit, 210 MSPS TxDAC(R) D/A Converter AD9742
FEATURES
High performance member of pin-compatible TxDAC product family Excellent spurious-free dynamic range performance SNR @ 5 MHz output, 125 MSPS: 70 dB Twos complement or straight binary data format Differential current outputs: 2 mA to 20 mA Power dissipation: 135 mW @ 3.3 V Power-down mode: 15 mW @ 3.3 V On-chip 1.2 V Reference CMOS compatible digital interface 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP packages Edge-triggered latches
APPLICATIONS
Wideband communication transmit channel: Direct IF Base stations Wireless local loops Digital radio links Direct digital synthesis (DDS) Instrumentation
FUNCTIONAL BLOCK DIAGRAM
3.3V REFLO 1.2V REF REFIO FS ADJ RSET 3.3V DVDD DCOM CLOCK CLOCK SEGMENTED SWITCHES LSB SWITCHES LATCHES
150pF
AVDD CURRENT SOURCE ARRAY
ACOM
0.1F
AD9742
IOUTA IOUTB MODE
02913-B-001
DIGITAL DATA INPUTS (DB11-DB0) SLEEP
Figure 1.
GENERAL DESCRIPTION
The AD97421 is a 12-bit resolution, wideband, third generation member of the TxDAC series of high performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9742 offers exceptional ac and dc performance while supporting update rates up to 210 MSPS. The AD9742's low power dissipation makes it well suited for portable and low power applications. Its power dissipation can be further reduced to a mere 60 mW with a slight degradation in performance by lowering the full-scale current output. Also, a power-down mode reduces the standby power dissipation to approximately 15 mW. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance.
Edge-triggered input latches and a 1.2 V temperature compensated band gap reference have been integrated to provide a complete monolithic DAC solution. The digital inputs support 3 V CMOS logic families.
PRODUCT HIGHLIGHTS
1. The AD9742 is the 12-bit member of the pin-compatible TxDAC family, which offers excellent INL and DNL performance. Data input supports twos complement or straight binary data coding. High speed, single-ended CMOS clock input supports 210 MSPS conversion rate. Low power: Complete CMOS DAC function operates on 135 mW from a 2.7 V to 3.6 V single supply. The DAC fullscale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. On-chip voltage reference: The AD9742 includes a 1.2 V temperature compensated band gap voltage reference. Industry-standard 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP packages.
2. 3. 4.
5. 6.
1
Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD9742 TABLE OF CONTENTS
Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 Dynamic Specifications ............................................................... 4 Digital Specifications ................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Terminology ...................................................................................... 8 Typical Performance Characteristics ............................................. 9 Functional Description .................................................................. 12 Reference Operation .................................................................. 12 Reference Control Amplifier..................................................... 13 DAC Transfer Function ............................................................. 13 Analog Outputs........................................................................... 13 Digital Inputs .............................................................................. 14 Clock Input.................................................................................. 14 DAC Timing................................................................................ 15 Power Dissipation....................................................................... 15 Applying the AD9742 ................................................................ 16 Differential Coupling Using a Transformer................................ 16 Differential Coupling Using an Op Amp ................................ 16 Single-Ended, Unbuffered Voltage Output ............................. 17 Single-Ended, Buffered Voltage Output Configuration ........ 17 Power and Grounding Considerations, Power Supply Rejection ...................................................................................... 17 Evaluation Board ............................................................................ 19 General Description................................................................... 19 Outline Dimensions ....................................................................... 29 Ordering Guide........................................................................... 30
REVISION HISTORY
6/04--Data Sheet Changed from Rev. A to Rev. B Changes to the Title.................................................................................1 Changes to General Description............................................................1 Changes to Product Highlights..............................................................1 Changes to Dynamic Specifications......................................................4 Changes to Figures 6 and 10...................................................................9 Changes to Figures 12 to 15 .................................................................10 Changes to the Functional Description Section................................12 Changes to the Digital Inputs Section ................................................14 Changes to Figure 29.............................................................................15 Changes to Figure 30.............................................................................16 5/03--Data Sheet Changed from Rev. 0 to Rev. A Added 32-Lead LFCSP Package ........................................... Universal Edits to Features..................................................................................... 1 Edits to Product Highlights.................................................................. 1 Edits to DC Specifications.................................................................... 2 Edits to Dynamic Specifications.......................................................... 3 Edits to Digital Specifications .............................................................. 4 Edits to Absolute Maximum Ratings.................................................. 5 Edits to Thermal Characteristics......................................................... 5 Edits to Ordering Guide ....................................................................... 5 Edits to Pin Configuration ................................................................... 6 Edits to Pin Function Descriptions..................................................... 6 Edits to Figure 2 ..................................................................................... 7 Replaced TPCs 1, 4, 7, and 8 ................................................................ 8 Edits to Figure 3 ................................................................................... 10 Edits to Functional Description Section .......................................... 10 Added Clock Input Section................................................................ 12 Added Figure 7..................................................................................... 12 Edits to DAC Timing Section ............................................................ 12 Edits to Sleep Mode Operation Section............................................ 13 Edits to Power Dissipation Section................................................... 13 Renumbered Figures 8 to 26 .............................................................. 13 Added Figure 11................................................................................... 13 Added Figures 27 to 35 ....................................................................... 21 Updated Outline Dimensions............................................................ 26
5/02--Revision 0: Initial Version
Rev. B | Page 2 of 32
AD9742 SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 1.
Parameter RESOLUTION DC ACCURACY1 Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current3 REFERENCE INPUT Input Compliance Range Reference Input Resistance (Ext. Reference) Small Signal Bandwidth TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift POWER SUPPLY Supply Voltages AVDD DVDD CLKVDD Analog Supply Current (IAVDD) Digital Supply Current (IDVDD)4 Clock Supply Current (ICLKVDD) Supply Current Sleep Mode (IAVDD) Power Dissipation4 Power Dissipation5 Power Supply Rejection Ratio--AVDD6 Power Supply Rejection Ratio--DVDD6 OPERATING RANGE Min 12 -2.5 -1.3 -0.02 -0.5 -0.5 2 -1 Typ Max Unit Bits LSB LSB % of FSR % of FSR % of FSR mA V k pF V nA V M MHz ppm of FSR/C ppm of FSR/C ppm of FSR/C ppm/C
0.5 0.4
+2.5 +1.3 +0.02 +0.5 +0.5 20 +1.25
0.1 0.1
100 5 1.14 1.20 100 1.26
0.1 1 0.5 0 50 100 50
1.25
2.7 2.7 2.7
3.3 3.3 3.3 33 8 5 5 135 145
3.6 3.6 3.6 36 9 6 6 145 +1 +0.04 +85
-1 -0.04 -40
V V V mA mA mA mA mW mW % of FSR/V % of FSR/V C
1 2
Measured at IOUTA, driving a virtual ground. Nominal full-scale current, IOUTFS, is 32 times the IREF current. 3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load. 4 Measured at fCLOCK = 25 MSPS and fOUT = 1 MHz. 5 Measured as unbuffered voltage output with IOUTFS = 20 mA and 50 RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz. 6 5% power supply variation.
Rev. B | Page 3 of 32
AD9742
DYNAMIC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, differential transformer coupled output, 50 doubly terminated, unless otherwise noted. Table 2
Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) Output Settling Time (tST) (to 0.1%)1 Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%)1 Output Fall Time (10% to 90%)1 Output Noise (IOUTFS = 20 mA)2 Output Noise (IOUTFS = 2 mA)2 Noise Spectral Density3 AC LINEARITY Spurious-Free Dynamic Range to Nyquist fCLOCK = 25 MSPS; fOUT = 1.00 MHz 0 dBFS Output -6 dBFS Output -12 dBFS Output -18 dBFS Output fCLOCK = 65 MSPS; fOUT = 1.00 MHz fCLOCK = 65 MSPS; fOUT = 2.51 MHz fCLOCK = 65 MSPS; fOUT = 10 MHz fCLOCK = 65 MSPS; fOUT = 15 MHz fCLOCK = 65 MSPS; fOUT = 25 MHz fCLOCK = 165 MSPS; fOUT = 21 MHz fCLOCK = 165 MSPS; fOUT = 41 MHz fCLOCK = 210 MSPS; fOUT = 40 MHz fCLOCK = 210 MSPS; fOUT = 69 MHz Spurious-Free Dynamic Range within a Window fCLOCK = 25 MSPS; fOUT = 1.00 MHz; 2 MHz Span fCLOCK = 50 MSPS; fOUT = 5.02 MHz; 2 MHz Span fCLOCK = 65 MSPS; fOUT = 5.03 MHz; 2.5 MHz Span fCLOCK = 125 MSPS; fOUT = 5.04 MHz; 4 MHz Span Total Harmonic Distortion fCLOCK = 25 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 2.00 MHz fCLOCK = 65 MSPS; fOUT = 2.00 MHz fCLOCK = 125 MSPS; fOUT = 2.00 MHz Signal-to-Noise Ratio fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA fCLOCK = 125 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA fCLOCK = 125 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA fCLOCK = 165 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA fCLOCK = 165 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA fCLOCK = 210 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA fCLOCK = 210 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA Min 210 11 1 5 2.5 2.5 50 30 -152 Typ Max Unit MSPS ns ns pV-s ns ns pA/Hz pA/Hz dBm/Hz
74
84 85 82 76 85 83 80 75 74 72 60 67 60
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc -74 dBc dBc dBc dBc dB dB dB dB dB dB dB dB
80 90 90 90 -82 -77 -77 -77 78 86 73 78 69 71 69 66
Rev. B | Page 4 of 32
AD9742
Parameter Multitone Power Ratio (8 Tones at 400 kHz Spacing) fCLOCK = 78 MSPS; fOUT = 15.0 MHz to 18.2 MHz 0 dBFS Output -6 dBFS Output -12 dBFS Output -18 dBFS Output Min Typ Max Unit
65 67 65 63
dBc dBc dBc dBc
1 2 3
Measured single-ended into 50 load. Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only. Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 3.
Parameter DIGITAL INPUTS1 Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) Latch Pulse Width (tLPW) CLK INPUTS2 Input Voltage Range Common-Mode Voltage Differential Voltage Min 2.1 -10 -10 5 2.0 1.5 1.5 0 0.75 0.5 3 2.25 Typ 3 0 Max Unit V V A A pF ns ns ns V V V
0.9 +10 +10
1.5 1.5
1 2
Includes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode. Applicable to CLK+ and CLK- inputs when configured for differential or PECL clock input mode.
DB0-DB11
tS
CLOCK
tH tLPW tPD tST
0.1%
Figure 2. Timing Diagram
Rev. B | Page 5 of 32
02912-B-002
IOUTA OR IOUTB
0.1%
AD9742 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter AVDD DVDD CLKVDD ACOM ACOM DCOM AVDD AVDD DVDD CLOCK, SLEEP Digital Inputs, MODE IOUTA, IOUTB REFIO, REFLO, FS ADJ CLK+, CLK-, MODE Junction Temperature Storage Temperature Lead Temperature (10 sec) With Respect to ACOM DCOM CLKCOM DCOM CLKCOM CLKCOM DVDD CLKVDD CLKVDD DCOM DCOM ACOM ACOM CLKCOM Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -3.9 -3.9 -3.9 -0.3 -0.3 -1.0 -0.3 -0.3 Max +3.9 +3.9 +3.9 +0.3 +0.3 +0.3 +3.9 +3.9 +3.9 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 CLKVDD + 0.3 150 +150 300 Unit V V V V V V V V V V V V V V C C C
THERMAL CHARACTERISTICS1
Thermal Resistance 28-Lead 300-Mil SOIC JA = 55.9C/W 28-Lead TSSOP JA = 67.7C/W 32-Lead LFCSP JA = 32.5C/W
1
Thermal impedance measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7.
-65
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. B | Page 6 of 32
AD9742 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
(MSB) DB11 1 DB10 2 DB9 3 DB8 4 DB7 5 DB6 6
28 27 26 25 24
CLOCK DVDD DCOM MODE AVDD DB5 1 DB4 2 DVDD 3 DB3 4 DB2 5 DB1 6 (LSB) DB0 7 NC 8
32 DB6 31 DB7 30 DB8 29 DB9 28 DB10 27 DB11 (MSB) 26 DCOM 25 SLEEP
PIN 1 INDICATOR
RESERVED TOP VIEW DB5 7 (Not to Scale) 22 IOUTA
23
AD9742
AD9742
TOP VIEW (Not to Scale)
DB4 8 DB3 9 DB2 10 DB1 11 (LSB) DB0 12 NC 13 NC 14
21 20 19 18 17 16 15
IOUTB ACOM NC FS ADJ REFIO REFLO SLEEP
02912-B-003
24 FS ADJ 23 REFIO 22 ACOM 21 IOUTA 20 IOUTB 19 ACOM 18 AVDD 17 AVDD
NC 9 DCOM 10 CLKVDD 11 CLK+ 12 CLK- 13 CLKCOM 14 CMODE 15 MODE 16
NC = NO CONNECT
NC = NO CONNECT
Figure 3. 28-Lead SOIC and TSSOP Pin Configuration
Figure 4. 32-Lead LFCSP Pin Configuration
Table 5. Pin Function Descriptions
SOIC/TSSOP Pin No. 1 2 to 11 12 13, 14 15 16 17 LFCSP Pin No. 27 28 to 32, 1, 2, 4 to 6 7 8, 9 25 N/A 23 Mnemonic DB11 DB10 to DB1 DB0 N/C SLEEP REFLO REFIO Description Most Significant Data Bit (MSB). Data Bits 10 to 1. Least Significant Data Bit (LSB). No Internal Connection. Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left unterminated if not used. Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie REFLO to ACOM). Requires 0.1 F capacitor to ACOM when internal reference activated. Full-Scale Current Output Adjust. No Internal Connection. Analog Common. Complementary DAC Current Output. Full-scale current when all data bits are 0s. DAC Current Output. Full-scale current when all data bits are 1s. Reserved. Do not connect to common or supply. Analog Supply Voltage (3.3 V). Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement. Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float CLK-). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations on-chip). Digital Common. Digital Supply Voltage (3.3 V). Clock Input. Data latched on positive edge of clock. Differential Clock Input. Differential Clock Input. Clock Supply Voltage (3.3 V). Clock Common.
18 19 20 21 22 23 24 25 N/A
24 N/A 19, 22 20 21 N/A 17, 18 16 15
FS ADJ NC ACOM IOUTB IOUTA RESERVED AVDD MODE CMODE
26 27 28 N/A N/A N/A N/A
10, 26 3 N/A 12 13 11 14
DCOM DVDD CLOCK CLK+ CLK- CLKVDD CLKCOM
Rev. B | Page 7 of 32
02912-B-004
AD9742 TERMINOLOGY
Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (or DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error The deviation of the output current from the ideal of zero is called the offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. Gain Error The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. Output Compliance Range The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per C. For reference drift, the drift is reported in ppm per C.
3.3V
Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Settling Time The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. Spurious-Free Dynamic Range The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). Multitone Power Ratio The spurious-free dynamic range containing multiple carrier tones of equal amplitude. It is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone.
REFLO 1.2V REF 0.1F REFIO FS ADJ RSET 2k 3.3V DVDD DCOM CLOCK DVDD DCOM RETIMED CLOCK OUTPUT* LECROY 9210 PULSE GENERATOR 50 SLEEP
150pF
AVDD
ACOM
AD9742
PMOS CURRENT SOURCE ARRAY IOUTA
MINI-CIRCUITS T1-1T IOUTB MODE 50 50
02912-B-005
SEGMENTED SWITCHES FOR DB11-DB3 LATCHES
LSB SWITCHES
ROHDE & SCHWARZ FSEA30 SPECTRUM ANALYZER
CLOCK OUTPUT
DIGITAL DATA TEKTRONIX AWG-2021 WITH OPTION 4
*AWG2021 CLOCK RETIMED SO THAT THE DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK.
Figure 5. Basic AC Characterization Test Set-Up (SOIC/TSSOP Packages)
Rev. B | Page 8 of 32
AD9742 TYPICAL PERFORMANCE CHARACTERISTICS
95 90 85 80
SFDR (dBc)
95
125MSPS
210MSPS (LFCSP) 165MSPS (LFCSP)
90 85 80
0dBFS -6dBFS (LFCSP)
65MSPS
SFDR (dBc)
75 70 65 125MSPS (LFCSP) 60 55 50
02912-B-006
75 -12dBFS 70 65 -12dBFS (LFCSP) 60 -6dBFS 55 50
02912-B-007
210MSPS
165MSPS
0dBFS (LFCSP)
45 1 10 100
45 0 10 20 30 40 50 60
fOUT (MHz)
fOUT (MHz)
Figure 6. SFDR vs. fOUT @ 0 dBFS
95 90 85 80 -12dBFS
SFDR (dBc)
Figure 9. SFDR vs. fOUT @ 165 MSPS
95 90 85 0dBFS (LFCSP)
0dBFS
SFDR (dBc)
80 75 -6dBFS (LFCSP) 70 65 60 55 50
02912-B-009
75 -6dBFS 70 65 60 55 50 45 0 5 10 15 20 25
-6dBFS
-12dBFS -12dBFS (LFCSP) 0dBFS
02912-B-054 02912-B-010
45 0 10 20 30 40 50 60 70
fOUT (MHz)
fOUT (MHz)
Figure 7. SFDR vs. fOUT @ 65 MSPS
95 90 85 80
Figure 10. SFDR vs. fOUT @ 210 MSPS
95 90 85 80
SFDR (dBc)
20mA
SFDR (dBc)
75 70 65 60 55 50
02912-B-012
75 70 65 60 55 50 45 0 5 10 15 20 25 10mA 5mA
-6dBFS -12dBFS 0dBFS
45 0 5 10 15 20 25 30 35 40 45
fOUT (MHz)
fOUT (MHz)
Figure 8. SFDR vs. fOUT @ 125 MSPS
Figure 11. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS
Rev. B | Page 9 of 32
AD9742
95 90 85 65MSPS 80 125MSPS
80 95 90 85 65MSPS (8.3,10.3) 78MSPS (10.1,12.1)
SFDR (dBc)
SFDR (dBc)
75 70 65 60 55 50
02912-B-013
75 70 65 60 55 50 165MSPS (22.6, 24.6)
165MSPS
125MSPS (16.9, 18.9) 210MSPS (29, 31) 210MSPS (29, 31)
210MSPS 210MSPS (LFCSP)
-20
-15
-10
-5
0
-20
-15
-10
-5
0
AOUT (dBFS)
AOUT (dBFS)
Figure 12. Single-Tone SFDR vs. AOUT @ fOUT = fCLOCK/11
95 90 85 80 65MSPS 125MSPS (LFCSP)
1.0
Figure 15. Dual-Tone IMD vs. AOUT @ fOUT = fCLOCK/7
0.5
SFDR (dBc)
75 70 65 60 55 50 45 -25 210MSPS
02912-B-008
165MSPS (LFCSP)
ERROR (LSB)
0
125MSPS
165MSPS
-0.5
210MSPS (LFCSP)
-20
-15
-10
-5
0
0
1024
2048 CODE
3072
4096
AOUT (dBFS)
Figure 13. Single-Tone SFDR vs. AOUT @ fOUT = fCLOCK/5
80 1.0 0.8 75 20mA 0.6 0.4
Figure 16. Typical INL
70
ERROR (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8
SNR
65 5mA 60 10mA
55
25
45
65
85
105
125
145
165
185
205
02912-B-011
0
1024
2048 CODE
3072
4096
fCLOCK (MHz)
Figure 14. SNR vs. fCLOCK and IOUTFS @ fOUT = 5 MHz and 0 dBFS
Figure 17. Typical DNL
Rev. B | Page 10 of 32
02912-B-017
50
-1.0
02912-B-015
-1.0
02912-B-014
45 -25
45 -25
AD9742
90 85 4MHz 80 75 19MHz 70 65 49MHz 60 34MHz 55
02912-B-019
0 -10 -20
fCLOCK = 78MSPS fOUT1 = 15.0MHz fOUT2 = 15.4MHz
SFDR = 77dBc AMPLITUDE = 0dBFS
MAGNITUDE (dBm)
-30 -40 -50 -60 -70 -80 -90
SFDR (dBc)
-20
0
20
40
60
80
1
6
11
16
21
26
31
36
TEMPERATURE (C)
FREQUENCY (MHz)
Figure 18. SFDR vs. Temperature @ 165 MSPS, 0 dBFS
0 -10 -20 0
Figure 20. Dual-Tone SFDR
fCLOCK = 78MSPS
fCLOCK = 78MSPS fOUT = 15.0MHz
SFDR = 79dBc AMPLITUDE = 0dBFS
-10 -20
fOUT1 = 15.0MHz fOUT2 = 15.4MHz fOUT3 = 15.8MHz fOUT4 = 16.2MHz
SFDR = 75dBc AMPLITUDE = 0dBFS
MAGNITUDE (dBm)
-40 -50 -60 -70 -80 -90
02912-B-016
MAGNITUDE (dBm)
-30
-30 -40 -50 -60 -70 -80 -90
1
6
11
16
21
26
31
36
1
6
11
16
21
26
31
36
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 19. Single-Tone SFDR
Figure 21. Four-Tone SFDR
3.3V
REFLO 1.2V REF VREFIO 0.1F RSET 2k IREF 3.3V REFIO FS ADJ DVDD DCOM CLOCK CLOCK SLEEP
150pF
AVDD
ACOM
AD9742
PMOS CURRENT SOURCE ARRAY IOUTA
VDIFF = VOUTA - VOUTB IOUTA IOUTB MODE VOUTB RLOAD 50 VOUTA RLOAD 50
02912-B-021
SEGMENTED SWITCHES FOR DB11-DB3 LATCHES
LSB SWITCHES
IOUTB
DIGITAL DATA INPUTS (DB11-DB0)
Figure 22. Simplified Block Diagram (SOIC/TSSOP Packages)
Rev. B | Page 11 of 32
02912-B-020
-100
-100
02912-B-018
50 -40
-100
AD9742 FUNCTIONAL DESCRIPTION
Figure 22 shows a simplified block diagram of the AD9742. The AD9742 consists of a DAC, digital control logic, and full-scale output current control. The DAC contains a PMOS current source array capable of providing up to 20 mA of full-scale current (IOUTFS). The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16th of an MSB current source. The remaining LSBs are binary weighted fractions of the middle bits current sources. Implementing the middle and lower bits with current sources, instead of an R-2R ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the DAC's high output impedance (i.e., >100 k). All of these current sources are switched to one or the other of the two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. The switches are based on the architecture that was pioneered in the AD9764 family, with further refinements to reduce distortion contributed by the switching transient. This switch architecture also reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. The analog and digital sections of the AD9742 have separate power supply inputs (i.e., AVDD and DVDD) that can operate independently over a 2.7 V to 3.6 V range. The digital section, which is capable of operating at a rate of up to 210 MSPS, consists of edge-triggered latches and segment decoding logic circuitry. The analog section includes the PMOS current sources, the associated differential switches, a 1.2 V band gap voltage reference, and a reference control amplifier. The DAC full-scale output current is regulated by the reference control amplifier and can be set from 2 mA to 20 mA via an external resistor, RSET, connected to the full-scale adjust (FS ADJ) pin. The external resistor, in combination with both the reference control amplifier and voltage reference ,VREFIO, sets the reference current, IREF, which is replicated to the segmented current sources with the proper scaling factor. The full-scale current, IOUTFS, is 32 times IREF.
REFERENCE OPERATION
The AD9742 contains an internal 1.2 V band gap reference. The internal reference can be disabled by raising REFLO to AVDD. It can also be easily overridden by an external reference with no effect on performance. REFIO serves as either an input or an output depending on whether the internal or an external reference is used. To use the internal reference, simply decouple the REFIO pin to ACOM with a 0.1 F capacitor and connect REFLO to ACOM via a resistance less than 5 . The internal reference voltage will be present at REFIO. If the voltage at REFIO is to be used anywhere else in the circuit, an external buffer amplifier with an input bias current of less than 100 nA should be used. An example of the use of the internal reference is shown in Figure 23.
3.3V OPTIONAL EXTERNAL REF BUFFER
REFLO 1.2V REF REFIO
150pF
AVDD
ADDITIONAL LOAD
0.1F 2k
FS ADJ
CURRENT SOURCE ARRAY
02912-B-022
AD9742
Figure 23. Internal Reference Configuration
An external reference can be applied to REFIO, as shown in Figure 24. The external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Note that the 0.1 F compensation capacitor is not required since the internal reference is overridden, and the relatively high input impedance of REFIO minimizes any loading of the external reference.
3.3V
AVDD VREFIO
REFLO 1.2V REF
150pF
AVDD
EXTERNAL REF RSET
REFIO FS ADJ
CURRENT SOURCE ARRAY
02912-B-023
IREF = VREFIO/RSET
AD9742
REFERENCE CONTROL AMPLIFIER
Figure 24. External Reference Configuration
Rev. B | Page 12 of 32
AD9742
REFERENCE CONTROL AMPLIFIER
The AD9742 contains a control amplifier that is used to regulate the full-scale output current, IOUTFS. The control amplifier is configured as a V-I converter, as shown in Figure 24, so that its current output, IREF, is determined by the ratio of the VREFIO and an external resistor, RSET, as stated in Equation 4. IREF is copied to the segmented current sources with the proper scale factor to set IOUTFS, as stated in Equation 3. The control amplifier allows a wide (10:1) adjustment span of IOUTFS over a 2 mA to 20 mA range by setting IREF between 62.5 A and 625 A. The wide adjustment span of IOUTFS provides several benefits. The first relates directly to the power dissipation of the AD9742, which is proportional to IOUTFS (see the Power Dissipation section). The second relates to the 20 dB adjustment, which is useful for system gain control purposes. The small signal bandwidth of the reference control amplifier is approximately 500 kHz and can be used for low frequency small signal multiplying applications.
VOUTA = IOUTAx RLOAD VOUTB = IOUTB x RLOAD
Note that the full-scale value of VOUTA and VOUTB should not exceed the specified output compliance range to maintain specified distortion and linearity performance.
(5) (6)
VDIFF = (IOUTA - IOUTB) x RLOAD
(7)
Substituting the values of IOUTA, IOUTB, IREF, and VDIFF can be expressed as:
V DIFF = {(2 x DAC CODE - 4095)/ 4096}
(32 x RLOAD / RSET )x VREFIO
(8)
DAC TRANSFER FUNCTION
Both DACs in the AD9742 provide complementary current outputs, IOUTA and IOUTB. IOUTA provides a near full-scale current output, IOUTFS, when all bits are high (i.e., DAC CODE = 4095), while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB is a function of both the input code and IOUTFS and can be expressed as:
Equations 7 and 8 highlight some of the advantages of operating the AD9742 differentially. First, the differential operation helps cancel common-mode error sources associated with IOUTA and IOUTB, such as noise, distortion, and dc offsets. Second, the differential code-dependent current and subsequent voltage, VDIFF, is twice the value of the single-ended voltage output (i.e., VOUTA or VOUTB), thus providing twice the signal power to the load. Note that the gain drift temperature performance for a singleended (VOUTA and VOUTB) or differential output (VDIFF) of the AD9742 can be enhanced by selecting temperature tracking resistors for RLOAD and RSET due to their ratiometric relationship, as shown in Equation 8.
IOUTA = (DAC CODE / 4096 )x I OUTFS IOUTB = (4095 - DAC CODE )/4096 x I OUTFS where DAC CODE = 0 to 4095 (i.e., decimal representation).
ANALOG OUTPUTS
The complementary current outputs in each DAC, IOUTA, and IOUTB may be configured for single-ended or differential operation. IOUTA and IOUTB can be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, via a load resistor, RLOAD, as described in the DAC Transfer Function section by Equations 5 through 8. The differential voltage, VDIFF, existing between VOUTA and VOUTB, can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. The ac performance of the AD9742 is optimum and specified using a differential transformer-coupled output in which the voltage swing at IOUTA and IOUTB is limited to 0.5 V. The distortion and noise performance of the AD9742 can be enhanced when it is configured for differential operation. The common-mode error sources of both IOUTA and IOUTB can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude decreases. This is due to the first-order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise.
(1) (2)
As mentioned previously, IOUTFS is a function of the reference current IREF, which is nominally set by a reference voltage, VREFIO, and external resistor, RSET. It can be expressed as:
I OUTFS = 32 x I REF
where
(3)
I REF = VREFIO / RSET
(4)
The two current outputs will typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTA and IOUTB should be directly connected to matching resistive loads, RLOAD, that are tied to analog common, ACOM. Note that RLOAD may represent the equivalent load resistance seen by IOUTA or IOUTB as would be the case in a doubly terminated 50 or 75 cable. The single-ended voltage output appearing at the IOUTA and IOUTB nodes is simply
Rev. B | Page 13 of 32
AD9742
Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (assuming no source termination). Since the output currents of IOUTA and IOUTB are complementary, they become additive when processed differentially. A properly selected transformer will allow the AD9742 to provide the required power and voltage levels to different loads. The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100 k in parallel with 5 pF. It is also slightly dependent on the output voltage (i.e., VOUTA and VOUTB) due to the nature of a PMOS device. As a result, maintaining IOUTA and/or IOUTB at a virtual ground via an I-V op amp configuration will result in the optimum dc linearity. Note that the INL/DNL specifications for the AD9742 are measured with IOUTA maintained at a virtual ground via an op amp. IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. The negative output compliance range of -1 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9742. The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. It degrades slightly from its nominal 1.2 V for an IOUTFS = 20 mA to 1 V for an IOUTFS = 2 mA. The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUTA and IOUTB does not exceed 0.5 V. The digital interface is implemented using an edge-triggered master/slave latch. The DAC output updates on the rising edge of the clock and is designed to support a clock rate as high as 210 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulse width. The setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges may affect digital feedthrough and distortion performance. Best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock.
CLOCK INPUT
SOIC/TSSOP Packages
The 28-lead package options have a single-ended clock input (CLOCK) that must be driven to rail-to-rail CMOS levels. The quality of the DAC output is directly related to the clock quality, and jitter is a key concern. Any noise or jitter in the clock will translate directly into the DAC output. Optimal performance will be achieved if the CLOCK input has a sharp rising edge, since the DAC latches are positive edge triggered.
LFCSP Package
A configurable clock input is available in the LFCSP package, which allows for one single-ended and two differential modes. The mode selection is controlled by the CMODE input, as summarized in Table 6. Connecting CMODE to CLKCOM selects the single-ended clock input. In this mode, the CLK+ input is driven with rail-to-rail swings and the CLK- input is left floating. If CMODE is connected to CLKVDD, the differential receiver mode is selected. In this mode, both inputs are high impedance. The final mode is selected by floating CMODE. This mode is also differential, but internal terminations for positive emitter-coupled logic (PECL) are activated. There is no significant performance difference between any of the three clock input modes.
Table 6. Clock Mode Selection
CMODE Pin CLKCOM CLKVDD Float Clock Input Mode Single-Ended Differential PECL
DIGITAL INPUTS
The AD9742 digital section consists of 12 input bit channels and a clock input. The 12-bit parallel data inputs follow standard positive binary coding, where DB11 is the most significant bit (MSB) and DB0 is the least significant bit (LSB). IOUTA produces a full-scale output current when all data bits are at Logic 1. IOUTB produces a complementary output with the full-scale current split between the two outputs as a function of the input code.
DVDD
The single-ended input mode operates in the same way as the CLOCK input in the 28-lead packages, as described previously. In the differential input mode, the clock input functions as a high impedance differential pair. The common-mode level of the CLK+ and CLK- inputs can vary from 0.75 V to 2.25 V, and the differential voltage can be as low as 0.5 V p-p. This mode can be used to drive the clock with a differential sine wave since the high gain bandwidth of the differential inputs will convert the sine wave into a single-ended square wave internally.
DIGITAL INPUT
02912-B-024
Figure 25. Equivalent Digital Input
Rev. B | Page 14 of 32
AD9742
The final clock mode allows for a reduced external component count when the DAC clock is distributed on the board using PECL logic. The internal termination configuration is shown in Figure 26. These termination resistors are untrimmed and can vary up to 20%. However, matching between the resistors should generally be better than 1%.
AD9742
CLK+ CLK- 50 50
02912-B-025
active pull-down circuit that ensures that the AD9742 remains enabled if this input is left disconnected. The AD9742 takes less than 50 ns to power down and approximately 5 s to power back up.
POWER DISSIPATION
The power dissipation, PD, of the AD9742 is dependent on several factors that include:
CLOCK RECEIVER
TO DAC CORE
VTT = 1.3V NOM
* * * *
The power supply voltages (AVDD, CLKVDD, and DVDD) The full-scale current output IOUTFS The update rate fCLOCK The reconstructed digital input waveform
Figure 26. Clock Termination in PECL Mode
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the relationship between the position of the clock edges and the time at which the input data changes. The AD9742 is rising edge triggered, and so exhibits dynamic performance sensitivity when the data transition is close to this edge. In general, the goal when applying the AD9742 is to make the data transition close to the falling clock edge. This becomes more important as the sample rate increases. Figure 27 shows the relationship of SFDR to clock placement with different sample rates. Note that at the lower sample rates, more tolerance is allowed in clock placement, while at higher rates, more care must be taken.
75 70 65 60 20MHz SFDR
The power dissipation is directly proportional to the analog supply current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly proportional to IOUTFS, as shown in Figure 28, and is insensitive to fCLOCK. Conversely, IDVDD is dependent on both the digital input waveform, fCLOCK, and digital supply DVDD. Figure 29 shows IDVDD as a function of full-scale sine wave output ratios (fOUT/fCLOCK) for various update rates with DVDD = 3.3 V.
35
30
25
IAVDD (mA)
20
15
10
02912-B-027
02912-B-028
0
2
4
6
8
10 12 IOUTFS (mA)
14
16
18
20
dB
55 50MHz SFDR 50 45
Figure 28. IAVDD vs. IOUTFS
20 18 16 210MSPS
40 50MHz SFDR
02912-B-026
14 IDVDD (mA) 12 10 8 6 4 2 0 0.01 65MSPS 125MSPS 165MSPS
35 -3
-2
-1
0 ns
1
2
3
Figure 27. SFDR vs. Clock Placement @ fOUT = 20 MHz and 50 MHz
Sleep Mode Operation
The AD9742 has a power-down function that turns off the output current and reduces the supply current to less than 6 mA over the specified supply range of 2.7 V to 3.6 V and temperature range. This mode can be activated by applying a Logic Level 1 to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 AVDD. This digital input also contains an
0.1 RATIO (fOUT/fCLOCK)
1
Figure 29. IDVDD vs. Ratio @ DVDD = 3.3 V
Rev. B | Page 15 of 32
AD9742
12
for impedance matching purposes. Note that the transformer provides ac coupling only.
DIFF
MINI-CIRCUITS T1-1T IOUTA 22
10
ICLKVDD (mA)
8 PECL 6
AD9742
IOUTB 21 OPTIONAL RDIFF
RLOAD
02912-B-030
4 SE 2
02912-B-029
Figure 31. Differential Output Using a Transformer
0 0 50 100 150 200 250 fCLOCK (MSPS)
Figure 30. ICLKVDD vs. fCLOCK and Clock Mode
APPLYING THE AD9742
Output Configurations
The following sections illustrate some typical output configurations for the AD9742. Unless otherwise noted, it is assumed that IOUTFS is set to a nominal 20 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the optimum high frequency performance and is recommended for any application that allows ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain, and/or level shifting within the bandwidth of the chosen op amp. A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage will result if IOUTA and/or IOUTB are connected to an appropriately sized load resistor, RLOAD, referred to ACOM. This configuration may be more suitable for a single-supply system requiring a dc-coupled, ground-referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting IOUTA or IOUTB into a negative unipolar voltage. This configuration provides the best dc linearity since IOUTA or IOUTB is maintained at a virtual ground.
The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetrically around ACOM and should be maintained with the specified output compliance range of the AD9742. A differential resistor, RDIFF, may be inserted in applications where the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable. RDIFF is determined by the transformer's impedance ratio and provides the proper source termination that results in a low VSWR. Note that approximately half the signal power will be dissipated across RDIFF.
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used to perform a differential-to-singleended conversion, as shown in Figure 32. The AD9742 is configured with two equal load resistors, RLOAD, of 25 . The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across IOUTA and IOUTB, forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amp's distortion performance by preventing the DAC's high slewing output from overloading the op amp's input.
500
AD9742
IOUTA 22
225
225 IOUTB 21 COPT
AD8047
500 25 25
02912-B-031
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-tosingle-ended signal conversion, as shown in Figure 31. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer's pass band. An RF transformer, such as the Mini-Circuits T1-1T, provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used
Figure 32. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8047 is configured to provide some additional signal gain. The op amp must operate off a dual supply since its output is approximately 1 V. A high speed amplifier capable of preserving the differential performance of the AD9742 while meeting other system level objectives (e.g., cost or power) should be selected. The op amp's differential gain, gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit.
Rev. B | Page 16 of 32
AD9742
The differential circuit shown in Figure 33 provides the necessary level shifting required in a single-supply system. In this case, AVDD, which is the positive analog supply for both the AD9742 and the op amp, is also used to level shift the differential output of the AD9742 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application.
500
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION
Figure 35 shows a buffered single-ended output configuration in which the op amp U1 performs an I-V conversion on the AD9742 output current. U1 maintains IOUTA (or IOUTB) at a virtual ground, minimizing the nonlinear output impedance effect on the DAC's INL performance as described in the Analog Outputs section. Although this single-ended configuration typically provides the best dc linearity performance, its ac distortion performance at higher DAC update rates may be limited by U1's slew rate capabilities. U1 provides a negative unipolar output voltage, and its full-scale output voltage is simply the product of RFB and IOUTFS. The full-scale output should be set within U1's voltage output swing capabilities by scaling IOUTFS and/or RFB. An improvement in ac distortion performance may result with a reduced IOUTFS since U1 will be required to sink less signal current.
COPT RFB 200
AD9742
IOUTA 22
225
225 IOUTB 21 COPT 25 25 1k
AD8041
1k
Figure 33. Single-Supply DC Differential Coupled Circuit
SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT
Figure 34 shows the AD9742 configured to provide a unipolar output range of approximately 0 V to 0.5 V for a doubly terminated 50 cable since the nominal full-scale current, IOUTFS, of 20 mA flows through the equivalent RLOAD of 25 . In this case, RLOAD represents the equivalent load resistance seen by IOUTA or IOUTB. The unused output (IOUTA or IOUTB) can be connected to ACOM directly or via a matching RLOAD. Different values of IOUTFS and RLOAD can be selected as long as the positive compliance range is adhered to. One additional consideration in this mode is the integral nonlinearity (INL), discussed in the Analog Outputs section. For optimum INL performance, the single-ended, buffered voltage output configuration is suggested.
AD9742
IOUTA 22 50 IOUTB 21 25 50
02912-B-033
02912-B-032
AVDD
AD9742
IOUTA 22
IOUTFS = 10mA
U1
IOUTB 21 200
VOUT = IOUTFS x RFB
02912-B-034
Figure 35. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION
Many applications seek high speed and high performance under less than ideal operating conditions. In these application circuits, the implementation and construction of the printed circuit board is as important as the circuit design. Proper RF techniques must be used for device selection, placement, and routing as well as power supply bypassing and grounding to ensure optimum performance. Figure 40 to Figure 43 illustrate the recommended printed circuit board ground, power, and signal plane layouts implemented on the AD9742 evaluation board. One factor that can measurably affect system performance is the ability of the DAC output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution. This is referred to as the power supply rejection ratio (PSRR). For dc variations of the power supply, the resulting performance of the DAC directly corresponds to a gain error associated with the DAC's full-scale current, IOUTFS. AC noise on the dc supplies is common in applications where the power distribution is generated by a switching power supply. Typically, switching power supply noise will occur over the spectrum from tens of kHz to several MHz. The PSRR versus frequency of the AD9742 AVDD supply over this frequency range is shown in Figure 36.
IOUTFS = 20mA
VOUTA = 0V TO 0.5V
Figure 34. 0 V to 0.5 V Unbuffered Voltage Output
Rev. B | Page 17 of 32
AD9742
85 80 75 70
PSRR (dB)
65 60 55 50 45 40
02912-B-035
appear as current noise superimposed on the DAC's full-scale current, IOUTFS, one must determine the PSRR in dB using Figure 36 at 250 kHz. To calculate the PSRR for a given RLOAD, such that the units of PSRR are converted from A/V to V/V, adjust the curve in Figure 36 by the scaling factor 20 log (RLOAD). For instance, if RLOAD is 50 , the PSRR is reduced by 34 dB (i.e., PSRR of the DAC at 250 kHz, which is 85 dB in Figure 36, becomes 51 dB VOUT/VIN). Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9742 features separate analog and digital supplies and ground pins to optimize the management of analog and digital ground currents in a system. In general, AVDD, the analog supply, should be decoupled to ACOM, the analog common, as close to the chip as physically possible. Similarly, DVDD, the digital supply, should be decoupled to DCOM as close to the chip as physically possible. For those applications that require a single 3.3 V supply for both the analog and digital supplies, a clean analog supply may be generated using the circuit shown in Figure 37. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained by using low ESR type electrolytic and tantalum capacitors.
FERRITE BEADS TTL/CMOS LOGIC CIRCUITS AVDD 100F ELECT. 10F-22F TANT. 0.1F CER. ACOM
0
2
4
6 8 FREQUENCY (MHz)
10
12
Figure 36. Power Supply Rejection Ratio (PSRR)
An example serves to illustrate the effect of supply noise on the analog supply. Suppose a switching regulator with a switching frequency of 250 kHz produces 10 mV of noise and, for simplicity's sake (ignoring harmonics), all of this noise is concentrated at 250 kHz. To calculate how much of this undesired noise will
3.3V POWER SUPPLY
Figure 37. Differential LC Filter for Single 3.3 V Applications
Rev. B | Page 18 of 32
02912-B-036
Note that the ratio in Figure 36 is calculated as amps out/volts in. Noise on the analog power supply has the effect of modulating the internal switches, and therefore the output current. The voltage noise on AVDD, therefore, will be added in a nonlinear manner to the desired IOUT. Due to the relative different size of these switches, the PSRR is very code dependent. This can produce a mixing effect that can modulate low frequency power supply noise to higher frequencies. Worst-case PSRR for either one of the differential DAC outputs will occur when the fullscale current is directed toward that output. As a result, the PSRR measurement in Figure 36 represents a worst-case condition in which the digital inputs remain static and the full-scale output current of 20 mA is directed to the DAC output being measured.
AD9742 EVALUATION BOARD
GENERAL DESCRIPTION
The TxDAC family evaluation boards allow for easy setup and testing of any TxDAC product in the SOIC and LFCSP packages. Careful attention to layout and circuit design, combined with a prototyping area, allows the user to evaluate the AD9742 easily and effectively in any application where high resolution, high speed conversion is required. This board allows the user the flexibility to operate the AD9742 in various configurations. Possible output configurations include transformer coupled, resistor terminated, and single and differential outputs. The digital inputs are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. Provisions are also made to operate the AD9742 with either the internal or external reference or to exercise the power-down feature.
J1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 DB13X DB12X DB11X DB10X DB9X DB8X DB7X DB6X DB5X DB4X DB3X DB2X DB1X DB0X JP3 CKEXTX
DCOM R1 R2 R3 R4 R5 R6 R7 R8 R9
RP5 OPT RP3 RP3 RP3 RP3 RP3 RP3 RP3 RP3 RP4 RP4 RP4 RP4 RP4 RP4 RP4 22 16 22 15 22 14 22 13 22 12 22 11 22 10 22 9 22 16 22 15 22 14 22 13 22 12 22 11 22 10 22 9
1 DCOM 2 R1 3 R2 4 R3 5 R4 6 R5 7 R6 8 R7 9 R8 10 R9
RP1 OPT
1 2 3 4 5 6 7 8 9 10
DB13X DB12X DB11X DB10X DB9X DB8X DB7X DB6X DB5X DB4X DB3X DB2X DB1X DB0X CKEXTX
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7
DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CKEXT
RIBBON
8 RP4
DCOM 1 R1 2 R2 3 R3 4 R4 5 R5 6 R6 7 R7 8 R8 9 R9 10
L2 TB1 1 C7 0.1F TB1 2
BEAD
RED TP2 DVDD + C4 10F 25V
RP6 OPT
DCOM 1 R1 2 R2 3 R3 4 R4 5 R5 6 R6 7 R7 8 R8 9 R9 10
RP2 OPT
BLK TP4
C6 0.1F
BLK TP7
BLK TP8
L3 TB1 3 C9 0.1F TB1 4
BEAD
RED TP5 AVDD + C5 10F 25V
BLK TP6
BLK TP10
BLK TP9
Figure 38. SOIC Evaluation Board--Power Supply and Digital Inputs
Rev. B | Page 19 of 32
02912-B-037
C8 0.1F
AD9742
AVDD + C14 10F 16V C16 0.1F C17 0.1F CUT UNDER DUT JP6 DVDD + C15 10F 16V C18 0.1F C19 0.1F R5 OPT CLOCK CKEXT JP4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CLOCK TP1 WHT DVDD JP2 AVDD MODE R6 OPT 3 2 1 T1-1T REF TP3 WHT C11 0.1F C1 0.1F AVDD C2 0.1F T1 4 5 6 S3 R4 50 R2 10k S5 DVDD C13 OPT DVDD IX S2 IOUTA 1 JP10 AB 2 3
R11 50
DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CLOCK DVDD DCOM MODE AVDD RESERVED IOUTA U1 AD9742 IOUTB ACOM NC FS ADJ REFIO REFLO SLEEP
JP8 IOUT
R1 2k
C12 OPT
JP9
AVDD
2 AB 3 1 JP5 INT EXT REF
SLEEP TP11 WHT R3 10k
S1 IOUTB
R10 50
IY
1
2 AB 3 JP11
Figure 39. SOIC Evaluation Board--Output Signal Conditioning
Rev. B | Page 20 of 32
02912-B-038
AD9742
Figure 40. SOIC Evaluation Board--Primary Side
Figure 41. SOIC Evaluation Board--Secondary Side
Rev. B | Page 21 of 32
02912-B-040
02912-B-039
AD9742
Figure 42. SOIC Evaluation Board--Ground Plane
Figure 43. SOIC Evaluation Board--Power Plane
Rev. B | Page 22 of 32
02912-B-042
02912-B-041
AD9742
Figure 44. SOIC Evaluation Board Assembly--Primary Side
Figure 45. SOIC Evaluation Board Assembly--Secondary Side
Rev. B | Page 23 of 32
02912-B-044
02912-B-043
AD9742
RED TP12 CVDD C3 0.1F TB1 2 BLK TP2 C2 10F 6.3V C10 0.1F 2 4 6 8 1 3 5 7 DB13X DB12X DB11X DB10X DB9X DB8X DB7X DB6X DB5X DB4X DB3X DB2X DB1X DB0X
L1 BEAD TB1 1
HEADER STRAIGHT UP MALE NO SHROUD
10 12 L2 BEAD RED TP13 DVDD C7 0.1F BLK TP4 C4 10F 6.3V C6 0.1F 14 16 18 20 22 24 26 28 L3 BEAD RED TP5 AVDD C9 0.1F BLK TP6 C5 10F 6.3V C8 0.1F 30 32 34 36 38 40
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
TB3
1
TB3
2
TB4
1
JP3 CKEXTX
TB4
2
J1
R3 100 DB13X DB12X DB11X DB10X DB9X DB8X DB7X DB6X DB5X DB4X DB3X DB2X DB1X DB0X CKEXTX
R4 100
R15 100
R16 100
R17 100
R18 100
R19 100
R20 100 1 RP3 2 RP3 3 RP3 4 RP3 5 RP3 6 RP3 7 RP3 8 RP3 1 RP4 2 RP4 3 RP4 4 RP4 5 RP4 6 RP4 7 RP4
8 RP4
22 16 22 15 22 14 22 13 22 12 22 11 22 10 22 9 22 16 22 15 22 14 22 13 22 12 22 11 22 10
22 9
DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CKEXT
R21 100
R24 100
R25 100
R26 100
R27 100
R28 100
Figure 46. LFCSP Evaluation Board Schematic--Power Supply and Digital Inputs
Rev. B | Page 24 of 32
02912-B-045
AD9742
AVDD C17 0.1F DVDD C19 0.1 0.1F CVDD C32 0.1F
SLEEP TP11 WHT
R29 10k DB7 DB6 DVDD DB5 DB4 DB3 DB2 DB1 DB0 CVDD CLK CLKB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DB7 DB6 DVDD DB5 DB4 DB3 DB2 DB1 DB0 DCOM U1 CVDD CLK CLKB CCOM CMODE MODE DB8 DB9 DB10 DB11 DB12 DB13 DCOM1 SLEEP FS ADJ REFIO ACOM IA IB ACOM1 AVDD AVDD1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DB8 DB9 DB10 DB11 DB12 DB13 TP3 WHT TP1 WHT 3 2 1 AVDD C11 0.1F DNP C12 T1 - 1T JP9 T1 4 5 6 S3 AGND: 3, 4, 5 R11 50 DNP C13
JP8 IOUT
CMODE
AD9744LFCSP TP7 WHT R30 10k CVDD R1 2k 0.1%
R10 50
JP1 MODE
Figure 47. LFCSP Evaluation Board Schematic--Output Signal Conditioning
1 7 U4 2 AGND: 5 CVDD: 8 CVDD
CVDD
C20 10F 16V
C35 0.1F
R5 120 CLKB JP2 CKEXT CLK 3 U4 4 AGND: 5 CVDD: 8 C34 0.1F 6 S5 AGND: 3, 4, 5 R6 50
02912-B-047
R2 120
Figure 48. LFCSP Evaluation Board Schematic--Clock Input
Rev. B | Page 25 of 32
02912-B-046
AD9742
Figure 49. LFCSP Evaluation Board Layout--Primary Side
Figure 50. LFCSP Evaluation Board Layout--Secondary Side
Rev. B | Page 26 of 32
02912-B-049
02912-B-048
AD9742
Figure 51. LFCSP Evaluation Board Layout--Ground Plane
Figure 52. LFCSP Evaluation Board Layout--Power Plane
Rev. B | Page 27 of 32
02912-B-051
02912-B-050
AD9742
Figure 53. LFCSP Evaluation Board Layout Assembly--Primary Side
Figure 54. LFCSP Evaluation Board Layout Assembly--Secondary Side
Rev. B | Page 28 of 32
02912-B-053
02912-B-052
AD9742 OUTLINE DIMENSIONS
9.80 9.70 9.60
28
15
4.50 4.40 4.30 6.40 BSC
1 14
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 8 0 0.75 0.60 0.45
SEATING PLANE
0.20 0.09
COMPLIANT TO JEDEC STANDARDS MO-153AE
Figure 55. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters
18.10 (0.7126) 17.70 (0.6969)
28
15
7.60 (0.2992) 7.40 (0.2913)
1 14
10.65 (0.4193) 10.00 (0.3937)
2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 8 1.27 (0.0500) 0.51 (0.0201) SEATING 0 0.32 (0.0126) BSC 0.33 (0.0130) PLANE 0.23 (0.0091)
0.75 (0.0295) x 45 0.25 (0.0098)
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 56. 28-Lead Standard Small Outline Package [SOIC] Wide Body (R-28) Dimensions shown in millimeters and (inches)
Rev. B | Page 29 of 32
AD9742
5.00 BSC SQ 0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
BOTTOM VIEW
3.25 3.10 SQ 2.95
8
0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF
17 16
9
0.25 MIN 3.50 REF
12 MAX
1.00 0.85 0.80 SEATING PLANE
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 57. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm x 5 mm Body (CP-32-2) Dimensions shown in millimeters
ORDERING GUIDE
Models AD9742AR AD9742ARRL AD9742ARZ2 AD9742ARZRL2 AD9742ARU AD9742ARURL7 AD9742ARUZ2 AD9742ARUZRL72 AD9742ACP AD9742ACPRL7 AD9742ACPZ2 AD9742ACPZRL72 AD9742-EB AD9742ACP-PCB Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 28-Lead 300-Mil SOIC 28-Lead 300-Mil SOIC 28-Lead 300-Mil SOIC 28-Lead 300-Mil SOIC 28-Lead TSSOP 28-Lead TSSOP 28-Lead TSSOP 28-Lead TSSOP 32-Lead LFCSP 32-Lead LFCSP 32-Lead LFCSP 32-Lead LFCSP Evaluation Board (SOIC) Evaluation Board (LFCSP) Package Options 1 R-28 R-28 R-28 R-28 RU-28 RU-28 RU-28 RU-28 CP-32-2 CP-32-2 CP-32-2 CP-32-2
1 2
R = Small Outline IC; RU = Thin Shrink Small Outline Package; CP = Lead Frame Chip Scale Package. Z = Pb-free part.
Rev. B | Page 30 of 32
AD9742 NOTES
Rev. B | Page 31 of 32
AD9742 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02912-0-6/04(B)
Rev. B | Page 32 of 32

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