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8-Bit, 250 MSPS 3.3V A/D Converter
Preliminary Technical Data
FEATURES
* * * * * * * * * * * DNL = 0.25 LSB INL = 0.5 LSB Single +3.3 V supply operation (3.0 to 3.6 V) Power dissipation of 450 mW at 250 MSPS 1 Vp-p analog input range Internal 1.0 V reference Single-ended or differential analog inputs LVDS or single-ended TTL/CMOS outputs Power down mode Clock duty cycle stabilizer Pin-similar to AD9054A
AD9480
FUNCTIONAL BLOCK DIAGRAM
VREF SENSE AGND DrGND DRVDD AVDD
Reference VIN+ VINDS+ DSCLK+ CLK-
AD9480
8-Bit ADC Pipeline Core Port 8 D7A - D0A A Port 8 D7B - D0B B DCO+ DCOLogic
T&H
8
Clock Mgmt
APPLICATIONS
* Digital oscilloscopes * Instrumentation and measurement * Communications (modems)
PDWN S1 S3/ LVDSBIAS S2
Figure 1. Functional Block Diagram
PRODUCT HIGHLIGHTS
Power down mode - A power-down function may be exercised to bring total consumption down to 13mW Superior linearity - A DNL of +/- 0.25 makes the AD9480 suitable for instrumentation and measurement applications. Pin-similar to the AD9054A - Allows easy upgrades for improved linearity and ac performance LVDS outputs (ANSI-644) - simplifies timing and improves noise performance
PRODUCT DESCRIPTION
The AD9480 is an 8-bit monolithic analog-to-digital converter optimized for high speed, low power, small size, and ease of use. The product operates at a 250 MSPS conversion rate, with excellent linearity and dynamic performance over its full operating range. To minimize system cost and power dissipation, the AD9480 includes an internal reference and track-and-hold circuit. The user only provides a +3.3 V power supply and a differential encode clock. No external reference or driver components are required for many applications. A data sync input is supported for proper output data port alignment, and a data clock output is available for proper output data timing. The digital outputs are TTL/CMOS or LVDS (ANSI 644) compatible with an option of two's complement or binary output format. The CMOS dual (demultiplexed) mode pipes ADC data through two 8-bit channels at one-half the clock rate in either interleaved or parallel mode. LVDS mode provides the best output performance with all data piped at the full clock rate through a single output channel. Fabricated on an advanced BiCMOS process, the AD9480 is available in a 44-pin surface mount package (44-TQFP) specified over the industrial temperature range (-40C to +85C).
Figure 2 FFT 70MHz Analog Input at 250MSPS Rev. PrH_ 3/5/2004
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
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AD9480
TABLE OF CONTENTS
AD9480--DC Specifications ................................................................. 3 DIGITAL SPECIFICATIONS ........................................................... 4 AC SPECIFICATIONS....................................................................... 4 SWITCHING SPECIFICATIONS.................................................... 5 EXPLANATION OF TEST LEVELS................................................ 6 Absolute Maximum Ratings.............................................................. 6 Definitions................................................................................................ 7 Theory of Operation ............................................................................... 9 Clocking the AD9480 ......................................................................... 9 Driving the Analog Inputs ................................................................. 9 Voltage Reference................................................................................ 9
Preliminary Technical Data
Compatibility with the AD9054A ...................................................11 Digital Outputs ..................................................................................11 Output Coding ..................................................................................12 Data Clock Out..................................................................................12 Interleaving Two AD9480s...............................................................12 EQuivalent Circuits ...............................................................................13 Pin Function Descriptions ...................................................................14 Pin Configurations ................................................................................16 Timing Diagram ....................................................................................17 Outline Dimensions ..............................................................................18 Ordering Guide .................................................................................18
REVISION HISTORY
Revision PrA: Initial Version Revision PrB: Added timing diagram Revision PrC: Updated specifications Revision PrD: Updated pin names, pin functions, and timing diagram; added application section; formatted to new data sheet template; updated power dissipation and analog bandwidth Revision PrE: Updated timing diagram, latency numbers, PDWN labeling, Power ---> 470mW Revision PrF: Added reference, equivalent circuits, package info, DS section Revision PrG: Added Output Coding section, SFDR spec, SFDR plot, FFT plot, Timing specs, Thetaja , Power-Down Dissipation, Vcm for analog, Updated Analog Rin, THDS , Tj max , AC specs, Power specs, Corrected VREF typo Revision PrH: added Power Down Timing, Tovr placeholders, corrected ext. VREF typo (p3,10), updated power down description
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Preliminary Technical Data
AD9480--DC SPECIFICATIONS1
AD9480
AVDD = 3.3V, DRVDD = 3.3V; EXT REF; DIFFERENTIAL ANALOG AND CLOCK INPUTS, LVDS OUTPUT MODE, UNLESS OTHERWISE NOTED)
Parameter
RESOLUTION No Missing Codes Offset Error Gain Error2 ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Offset Error TEMPERATURE DRIFT Gain Error Reference Internal Reference Voltage REFERENCE Output Current Input Current Input Resistance Differential Input Voltage Range Common Mode Voltage Input Resistance Input Capacitance Analog Bandwidth, Full Power AVDD DRVDD Power Dissipation3 Power Down Dissipation Power Supply Rejection Ratio (PSRR) IAVDD4 IDRVDD4 AVDD DRVDD Power Dissipation3 Power Down Dissipation Power Supply Rejection Ratio (PSRR) I IDRVDD4
4 AVDD
Temp
Full Full 25C 25C Full 25C Full Full Full Full 25C Full Full Full Full Full Full Full Full Full Full Full 25C Full Full Full Full Full Full 25C Full Full
Table 1
Test Level
VI VI I I VI I VI V V V I V V V V V V V IV IV VI VI I VI VI IV IV VI VI I VI VI
Min
Typ
8 Guaranteed
Max
Unit
Bits mV % FS
0.25 0.35 0.5 - 1.0 0.7 110 1200 1.0 + 1.0
LSB LSB LSB LSB ppm/C ppm/C ppm/C V uA uA
ANALOG INPUTS
0.5 2 10 4 750 3.3 574 16 148 34 3.3 452 13 146 39
k Vpp V k pF MHz V V mW mW mV/V mA mA V V mW mW mV/V mA mA
3.0
3.6
POWER SUPPLY (LVDS Mode)
3.0
3.6
POWER SUPPLY (CMOS Mode)
Specifications subject to change without notice Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.0 V external reference and a 1 V p-p differential analog input). Power dissipation measured with rated encode and a dc analog input (Outputs Static). 4 IAVDD and IDRVDD measured with 19.7 MHz analog input @ 0.5dBFS at 250MSPS.
2 3
1
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AD9480
DIGITAL SPECIFICATIONS
AVDD = 3.3V, DRVDD = 3.3V
Parameter
Differential Input VIH VIL Input Resistance Input Capacitance Logic `1' Voltage Logic `0' Voltage Input Resistance Input Capacitance Logic `1' Voltage Logic `0' Voltage Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding
1
Preliminary Technical Data
Temp
Full Full Full Full 25C Full Full Full Full Full Full Full Full Full
Test Level
IV IV IV IV IV IV IV IV IV IV IV IV IV IV
Min
Typ
Max
Unit
mV V V k pF V V k PF V V mV V
DIGITAL INPUTS (CLK+, CLK-, DS+, DS-)
LOGIC INPUTS
DIGITAL OUTPUTS (CMOS Mode) DIGITAL OUTPUTS (LVDS Mode)
DRVDD - 0.05 0.05 247 454 1.125 1.375 Twos Complement or Binary
Table 2: Digital Specifications
AC SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V; INTERNAL REF; DIFFERENTIAL ANALOG AND CLOCK INPUT, LVDS OUTPUT MODE, UNLESS OTHERWISE NOTED
Parameter
fIN= 19.7 MHz SIGNAL TO NOISE RATIO (SNR) - Without Harmonics fIN= 49.7 MHz fIN= 70.1 MHz fIN= 100 MHz fIN=170 MHz fIN= 19.7 MHz SIGNAL TO NOISE RATIO (SINAD) - With Harmonics fIN= 49.7 MHz fIN= 70.1 MHz fIN= 100 MHz fIN=170 MHz fIN= 19.7 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN= 49.7 MHz fIN= 70.1 MHz fIN= 100 MHz fIN=170 MHz fIN= 19.7 MHz SECOND AND THIRD HARMONIC DISTORTION Spurious Free Dynamic Range (SFDR) fIN= 49.7 MHz fIN= 70.1 MHz fIN= 100 MHz fIN=170 MHz fIN= 19.7 MHz fIN= 49.7 MHz fIN= 70.1 MHz fIN= 100 MHz
1
Temp
25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C
Test Level
I I I V V I I I V V I I I V V I I I V V I I I V
Min
Typ
46 46 46 46 45.5 46 46 46 46 45.5
Max
Unit
dB dB dB dB dB dB dB dB dB dB Bits Bits Bits Bits Bits
-60 -60 -60 -60 -60 65 65 65 64
dBc dBc dBc dBc dBc dBc dBc dBc dBc
SNR/harmonics based on an analog input voltage of -0.5 dBFS referenced to a 1 Vpp full-scale input range. Rev. PrH Page 4 of 18 3/5/2004
Preliminary Technical Data
Parameter
fIN=170 MHz TWO TONE INTERMOD DISTORTION (IMD) fIN1= 19 MHz, fIN2= 20 MHz fIN1= 70 MHz, fIN2= 71 MHz
AD9480
Temp
25C 25C 25C
Test Level
V V V
Min
Typ
-65 -55
Max
Unit
dBc dBc dBc
Table 3: AC Specifications
SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V; DIFFERENTIAL ENCODE INPUT, UNLESS OTHERWISE NOTED
Parameter
CLOCK Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) Valid Time (tV)1 Propagation Delay (tPDR) 1 Propagation Delay (tPDF) 1 Rise Time (tR) Fall Time (tF) DCO Propagation Delay - Rising Edge (tCPDR) DCO Propagation Delay - Falling Edge (tCPDF) Data to DCO Skew (tPD - tCPD) DS+ Input Setup Time (tSDS)2 DS+ Input Hold Time (tHDS) Interleaved Mode (A, B Latency) Parallel Mode (A, B Latency) Tpwrdown Tpwrdnrecovery Tovr Power Down Delay Power Down Recovery Overvoltage Recovery Time Valid Time (tV)1 Propagation Delay (tPD) 1 Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) DCO Propagation Delay (tCPD) Data to DCO Skew (tPD - tCPD) Pipeline Latency Power Down Delay Power Down Recovery Overvoltage Recovery Time Aperture Delay (tA) Aperture Uncertainty (Jitter)
Temp
Full Full Full Full Full Full Full Full Full Full Full Full Full 25C 25C 25C 25C 25C Full Full Full Full Full Full 25C 25C 25C 25C 25C 25C
Test Level
VI IV IV VI VI VI V V VI VI IV IV IV VI VI VI VI VI VI VI V V VI IV VI VI VI VI V V
Min
250 1.2 1.2 2
Typ
2 2 3.7 3.4 1.6 1.3 3.9 3.8 -.3 0.5 0.5 8, 8 9, 8
Max
Unit
MSPS nS nS nS nS nS nS nS nS nS nS nS nS cycles cycles nS nS nS nS nS nS nS nS nS cycles nS nS nS
OUTPUT PARAMETERS IN CMOS MODE
OUTPUT PARAMETERS IN LVDS MODE
2.8 0.5 0.5 2.6 .2 8
Tpwrdown Tpwrdnrecovery Tovr APERTURE
1.5 0.25
nS pS rms
Table 4: Switching Specifications
tV and tPD are measured from the transition points of the CLK input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 10 pF or a dc current of 40 A. Rise and fall times measured from 10% to 90%. 2 DS inputs used in CMOS mode only.
1
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AD9480
EXPLANATION OF TEST LEVELS
TEST LEVEL
I II III IV V VI 100% production tested.
Preliminary Technical Data
100% production tested at +25C and guaranteed by design and characterization at specified temperatures. Sample Tested Only Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at +25C and guaranteed by design and characterization for industrial temperature range.
Absolute Maximum Ratings
Parameter
AVDD Voltage DRVDD Voltage Analog Input Voltage Analog Input Current Digital Input Voltage Digital Output Current VREF Input Voltage Operating Temperature Range (Ambient) Maximum Junction Temperature Environmental Lead Temperature (Soldering, 10 sec) Maximum Case Temperature Storage Temperature Range (Ambient)
Table 5: Absolute Maximum Ratings
Rating
4 V max 4 V max +0.5 V to AVDD - 0.5 V 0.4 mA +0.5 V to AVDD - 0.5 V 20 mA max +0.5 V to AVDD - 0.5 V -40C to +85C 150C 150C C -65C to +150C
Electrical
Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Impedance (ja) = 46.4 C/W (4 Layer PCB)
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Preliminary Technical Data
DEFINITIONS
ANALOG BANDWIDTH
The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.
AD9480
ENCODE PULSE WIDTH/DUTY CYCLE
Pulse width high is the minimum amount of time that the ENCODE pulse should be left in logic "1" state to achieve rated performance; pulse width low is the minimum time ENCODE pulse should be left in low state. See timing implications of changing tENCH in text. At a give clock rate, these specs define an acceptable Encode duty cycle.
APERTURE DELAY
The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled.
FULL SCALE INPUT POWER
Expressed in dBm. Computed using the following equation:
APERTURE UNCERTAINTY (JITTER)
The sample-to-sample variation in aperture delay.
CROSSTALK
Coupling onto one channel being driven by a low level (-40 dBFS) signal when the adjacent interfering channel is driven by a fullscale signal.
PowerFullscale
2 V Fullscalerms Z Input = 10 log .001

GAIN ERROR DIFFERENTIAL ANALOG INPUT RESISTANCE, DIFFERENTIAL ANALOG INPUT CAPACITANCE, AND DIFFERENTIAL ANALOG INPUT IMPEDANCE
The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Gain error is the difference between the measured and ideal full scale input voltage range of the ADC.
HARMONIC DISTORTION, SECOND
The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc.
DIFFERENTIAL ANALOG INPUT VOLTAGE RANGE
The peak to peak differential voltage that must be applied to the converter to generate a full scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. Peak to peak differential is computed by rotating the inputs phase 180 degrees and taking the peak measurement again. Then the difference is computed between both peak measurements.
HARMONIC DISTORTION, THIRD
The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc.
INTEGRAL NONLINEARITY
The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit.
DIFFERENTIAL NONLINEARITY
The deviation of any code width from an ideal 1 LSB step.
MINIMUM CONVERSION RATE
The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.
EFFECTIVE NUMBER OF BITS
The effective number of bits (ENOB) is calculated from the measured SNR based on the equation:
MAXIMUM CONVERSION RATE
The encode rate at which parametric testing is performed.
ENOB =
SNRMEASURED - 1.76dB 6.02
OUTPUT PROPAGATION DELAY
The delay between a differential crossing of CLK+ and CLK- and
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AD9480
the time when all output data bits are within valid logic levels.
Preliminary Technical Data
to converter full scale).
NOISE (FOR ANY RANGE WITHIN THE ADC)
TWO-TONE INTERMODULATION DISTORTION REJECTION
The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc.
Vnoise = Z * .001 * 10
FS dBm - SNRdBc - Signal dBFS 10
Where Z is the input impedance, FS is the full scale of the device for the frequency in question, SNR is the value for the particular input level and Signal is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise.
TWO-TONE SFDR
The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It also may be reported in dBc (i.e., degrades as signal level is lowered) or in dBFS (i.e., always relates back to converter full scale).
POWER SUPPLY REJECTION RATIO
The ratio of a change in input offset voltage to a change in power supply voltage.
WORST OTHER SPUR
The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dBc.
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc.
TRANSIENT RESPONSE TIME
Transient response time is defined as the time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale.
SIGNAL-TO-NOISE RATIO (WITHOUT HARMONICS)
The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
OUT-OF-RANGE RECOVERY TIME
Out of range recovery time is the time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. It also may be reported in dBc (i.e., degrades as signal level is lowered) or dBFS (i.e., always related back
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Preliminary Technical Data
THEORY OF OPERATION
The AD9480 uses a 1.5 bit per stage architecture. The analog
AD9480
Voltage Reference
A stable and accurate 0.5 V reference is built into the AD9480. Users can choose this internal reference or provide an external reference for greater accuracy and flexibility. The available reference configurations are summarized in Table 8.
inputs drive an integrated high bandwidth track-and-hold circuit that samples the signal prior to quantization by the 8-bit
core. For ease of use, the part includes an onboard reference and input logic that accepts TTL, CMOS, or LVPECL levels. The digital output logic levels are user selectable as standard 3 V CMOS or LVDS (ANSI 644-compatible) via pin 30 (S2).
S2 Voltage AVDD (Default) 2/3 AVDD AGND Digital Outputs CMOS Interleaved CMOS Parallel LVDS
Table 6: S2 Voltage Levels
Clocking the AD9480
Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock will be combined with the desired signal at the A/D output. For that reason, considerable care has been taken in the design of the CLOCK input of the AD9480, and the user is advised to give commensurate thought to the clock source. The AD9480 has an internal clock duty cycle stabilization circuit that locks to the rising edge of CLOCK (falling edge of CLOCK if driven differentially) and optimizes timing internally for sample rates between 100 and 250 MSPS. This allows for a wide range of input duty cycles at the input without degrading performance. Jitter on the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The clock duty cycle stabilizer can be disabled at pin 28 (S1).
S1 Voltage AVDD (Default) 2/3 AVDD 1/3 AVDD AGND Data Format Offset Binary Offset Binary Twos Complement Twos Complement Duty Cycle Stabilizer Disabled Enabled Enabled Disabled
Figure 3 Internal Reference Equivalent Circuit
FIXED REFERENCE
The internal reference can be configured for a differential span of 0.5 Vp-p or 1 Vp-p. Figures 4 and 5 show the two configurations.
Table 7: S1 Voltage Levels
Driving the Analog Inputs
The analog input to the AD9480 is a differential buffer. For best dynamic performance, impedances at VIN+ and VIN- should match. Optimal performance is obtained with the analog inputs are driven differentially. SNR and SINAD performance will degrade if the analog input is driven with a single-ended signal. A wideband transformer, such as the Minicircuits ADT1-1WT, can provide the differential analog inputs for applications that require a singleended-to-differential conversion. The AD9480 can be configured for a 1 Vpp or 0.5 Vpp input. See the Voltage Reference section for more information. Optimal performance is achieved with a 1 Vpp analog input.
VREF
10 uF 0.1 uF
SENSE
Figure 4 Internal Fixed Reference (0.5 Vpp)
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AD9480
Preliminary Technical Data
May require RC filter
VREF
10 uF 0.1 uF
External Reference or DAC Input
AVDD
VREF
SENSE
SENSE
Figure 5 Internal Fixed Reference (1 Vpp)
If the internal reference of the AD9480 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 5 depicts how the internal reference voltage is affected by loading.
Figure 7 External Reference
PROGRAMMABLE REFERENCE
The programmable reference can be used to set a differential input span anywhere between 0.5 Vpp and 1.1 Vpp. The resulting VREF is equal to 0.5 x (1 + R2/R1).
VREF
10 uF 0.1 uF
R2 SENSE R1
Figure 6 Internal VREF v. Load
EXTERNAL REFERENCE
An external reference can be used for greater accuracy and temperature stability when required. The gain of the AD9480 can also be varied using this configuration. A voltage output DAC can be used to set VREF, providing for a means to digitally adjust the full scale voltage. VREF can be externally set to voltages from 0.5V to 1.1V; optimum performance is obtained at VREF = 1V. ( See TPC section )
Figure 8 Programmable Reference
SENSE Voltage AVDD VREF 0.2 V to VREF AGND to 0.2 V
Resulting VREF N/A (External Reference Input) 0.5 V 0.5 x (1+R2/R1) V 1.0 V
Mode External Reference Internal Fixed Reference Programmable Reference Internal Fixed Reference
Differential Span 1 x External Reference Voltage 0.5 Vpp 1 x VREF (0.5 Vpp to 1.1 Vpp) 1 Vpp
Table 8 : Reference Configuration
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Preliminary Technical Data
Pin 15 16 17 28 29 30 33 34 42 AD9054A Pin Name VDD GND GND VDD GND VDD VREFOUT VREFIN DEMUX AD9480 Pin Name DGND DCODCO+ S1 PDWN S2 SENSE VREF S3 Connecting the AD9480 for AD9054A-Compatibility
AD9480
Pin must be changed to a GND connection A data clock out (DCO) was not available on the AD9054A. DCO can be disabled with pin 42 (S3). A data clock out (DCO) was not available on the AD9054A. DCO can be disabled with pin 42 (S3). An output data format select and a duty cycle stabilizer (DCS) were not available on the AD9054A. The AD9054A output data was in binary format. Tie HIGH for binary output data and DCS disabled. Power down was not available on the AD9054A. Tie LOW for normal operation. Tie HIGH for compatibility with the AD9054A. This sets the digital outputs to CMOS Interleaved. Operation is slightly different. See Reference Operation section for more information. Operation is slightly different. See Reference Operation section for more information. Tie to GND to put DCO+ and DCO- in a high impedance state (pins 16 and 17). DCO+ and DCO- were not available on the AD9054A. On the AD9054A, tying pin 42 to GND selected Single Channel CMOS Mode. This mode is not available on the AD9480.
Table 9: Differences between AD9054A and AD9480
Compatibility with the AD9054A
The AD9480 is pin-similar to the AD9054A, an 8-bit, 200 MSPS ADC with CMOS outputs. Every attempt has been made to keep the pin out of these two ADCs as close as possible. However, to use the AD9480 in place of the AD9054A, a few changes must be made. First, the AD9480 requires a +3.3 V supply in place of a +5 V supply. The AD9480 also includes some additional features that were not available on the AD9054A including LVDS outputs, a data clock out (DCO), power down, data output options, and a flexible reference. Table X provides a summary of the changes to the AD9054A pin out and how to connect the AD9480 to function the same as the AD9054A. topologies are recommended with a 100 termination resistor as close to the receiver as possible. It is recommended to keep the trace length no longer than 3-4 inches and to keep differential output trace lengths as equal as possible. Note that LVDS mode typically offers superior SFDR performance at higher analog input frequencies compared to CMOS mode operation.
LVDS , CMOS
66 64
AD9480 SFDR Comparison
Digital Outputs
The off-chip drivers on the chip can be configured to provide CMOS- or LVDS-compatible output levels via Pin S2. See Table 1 for more information. The CMOS digital outputs are TTL/CMOS-compatible for lower power consumption. The outputs are biased from a separate supply (DRVDD), allowing easy interface to external logic. The outputs are CMOS devices that will swing from ground to DRVDD (with no dc load). It is recommended to minimize the capacitive load the ADC drives by keeping the output traces short (<1 inch, for a total CLOAD < 5 pF). When operating in CMOS mode, it is also recommended to place low value series damping resistors on the data lines to reduce switching transient effects on performance.
62 SFDR lvds 60 58 56 54 0 50 100 150 200 SFDR cmos
Ain MHz
Figure 9 LVDS/CMOS SFDR Comparison
LVDS OUTPUTS
LVDS outputs are available when pin 30 is tied to ground and a 3.4 k RSET resistor is placed at Pin 42 (LVDSBIAS) to ground. The RSET resistor current (~ 1.2/RSET) is ratioed on-chip setting the output current at each output equal to a nominal 3.5 mA. A 100 differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. LVDS mode facilitates interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net
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AD9480
Output Coding
Code 255 255 254 * * 129 128 127 * * 2 1 0 0 Ain+ - Ain??> 0.512 V 0.512 V 0.508 V * * 0.004 V 0.0 V -0.004 V * * -0.504 V -0.508 V -0.512 V < -0.512 V Offset Binary 1111 1111 1111 1111 1111 1110 * * 1000 0001 1000 0000 0111 1111 * * 0000 0010 0000 0001 0000 0000 0000 0000 Two's Complement 0111 1111 0111 1111 0111 1110 * * 0000 0001 0000 0000 1111 1111 * * 1000 0010 1000 0001 1000 0000 1000 0000
Preliminary Technical Data
S3 Voltage AVDD AGND Data Clock Out Active High impedance
Table 11: S3 Voltage Levels
Interleaving Two AD9480s
Instrumentation applications may prefer to interleave ("pingpong") two AD9480s to achieve twice the sample rate, or 500 MSPS. In these applications, it is important to match the gain and offset of the two ADCs. Varying the reference voltage allows adjustment of the ADC's gain, external DC Offset compensation can be used to reduce offset mismatch between two ADCs.
DS INPUTS
In CMOS output mode, the Data Sync inputs (DS+, DS-) can be used in applications requiring that a given sample will appear at a specific output port (A or B) relative to a given external timing signal. The DS inputs can also be used to synchronize two or more ADCs in a system to maintain phasing between Ports A and B on separate ADCs (in effect, synchronizing multiple DCO outputs). When DS+ is held high (DS- low), the ADC data outputs do not switch and are held static. Synchronization is accomplished by the assertion (falling edge) of DS+ within the timing constraints tSDS and tHDS, relative to a clock rising edge. (On initial synchronization, tHDS is not relevant.) If DS+ falls within the required setup time (tSDS) before a given clock rising edge N, the analog value at that point in time will be digitized and available at Port A, 8 cycles later in interleaved mode. The very next sample, N + 1, will be sampled by the next rising clock edge and available at Port B, 8 cycles after that clock edge. In dual parallel mode, Port A has a 9 cycle latency and Port B has a 8 cycle latency, but data is available at the same time. Driving each ADC's DS inputs by the same sync signal will accomplish synchronization between multiple ADC's. An easy way to accomplish synchronization is by a one-time sync at power-on reset. Note that when running the AD9480 in LVDS mode, set DS+ to ground and DS- to 3.3 V, as the DS inputs are relevant only in CMOS output mode. LVDS mode can simplify the design for some applications as well as potentially affording superior SNR/SINAD performance at higher encode/analog frequencies
Table 10: Output Coding
Data Clock Out
A data clock out is available at DCO+ and DCO- for both CMOS and LVDS outputs. These clocks can facilitate latching off-chip, providing a low skew clocking solution. If the AD9480 is in CMOS mode, the DCO rate is half of the input clock (CLK) rate, and the DCO levels are CMOS. The on-chip clock buffers should not drive more than X pf of capacitance to limit switching transient effects on performance. In LVDS mode, the DCO rate is equal to the input clock rate and the levels are LVDS. Note that in LVDS mode, the DCO requires a 100 differential termination at the receiver. The DCO is an optional feature. To activate the DCO, tie pin S3 to VDD, as shown in Table X. To disable the DCO, tie S3 to GND. If the DCO is disabled, the DCO outputs are placed in a high impedance state.
Powerdown
The AD9480 can be placed in a low power dissipation state by asserting PDWN (pin 29). Driving PDWN to AVDD places the part in a low power down state where power dissipation is typically less than 15mW. The data outputs go to a high impedance state when PDWN is asserted when operating in LVDS or CMOS mode.
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Preliminary Technical Data
EQUIVALENT CIRCUITS
AD9480
Figure 10 Analog Inputs
Figure 14 S3/LVDSBIAS Pin
Figure 11 Clock/DS Inputs
Figure 15 CMOS Outputs
Figure 12 S1,S2 Logic Inputs
Figure 13 PDWN Input
Figure 16 LVDS Outputs
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AD9480
PIN FUNCTION DESCRIPTIONS
LVDS MODE
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Preliminary Technical Data
Name
CLK+ CLKAVDD AGND DRVDD DrGND D0_C D0_T D1_C D1_T D2_C D2_T D3_C D3_T DrGND DCODCO+ DRVDD D4_C D4_T D5_C D5_T
Description
Input Clock - True Input Clock - Complement 3.3 V Analog Supply Analog Ground 3.3 V Digital Output Supply Digital Ground Data Ouput Bit 0 - Complement (LSB) Data Output Bit 0 - True (LSB) Data Output Bit 1 - Complement Data Output Bit 1 - True Data Output Bit 2 - Complement Data Output Bit 2 - True Data Output Bit 3 - Complement Data Output Bit 3 - True Digital Ground Data Clock Output - Complement Data Clock Output - True 3.3 V Digital Output Supply Data Output Bit 4 - Complement Data Output Bit 4 - True Data Output Bit 5 - Complement Data Output Bit 5 - True
Pin No.
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Name
D6_C D6_T D7_C D7_T DrGND S1 PDWN S2 AVDD AGND SENSE VREF AGND AVDD AGND VINVIN+ AGND AVDD LVDSBIAS DSDS+
Description
Data Output Bit 6 - Complement Data Output Bit 6 - True Data Output Bit 7 - Complement (MSB) Data Output Bit 7 - True (MSB) Digital Ground Data Format Select and Duty Cycle Stabilizer Selection Power Down Selection Output Mode State (AGND = LVDS) 3.3 V Analog Supply Analog Ground Reference Mode Selection Voltage Reference Input/Output Analog Ground 3.3 V Analog Supply Analog Ground Analog Input - Complement Analog Input - True Analog Ground 3.3 V Analog Supply LVDS Output Current Data Sync Complement (Not Used in LVDS Mode, Tie to DRVDD) Data Sync True (Not Used in LVDS Mode, Tie to DGND)
Table 12: Pin Function Descriptions -- LVDS Mode
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Preliminary Technical Data
CMOS MODE
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
AD9480
Pin No.
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Name
CLK+ CLKAVDD AGND DRVDD DrGND D7A D6A D5A D4A D3A D2A D1A D0A DrGND DCODCO+ DRVDD D0B D1B D2B D3B
Description
Input Clock - True Input Clock - Complement 3.3 V Analog Supply Analog Ground 3.3 V Digital Output Supply Digital Ground Data Output Bit 7 - Channel A (MSB) Data Output Bit 6 - Channel A Data Output Bit 5 - Channel A Data Output Bit 4 - Channel A Data Output Bit 3 - Channel A Data Output Bit 2 - Channel A Data Output Bit 1 - Channel A Data Output Bit 0 - Channel A (LSB) Digital Ground Data Clock Output - Complement Data Clock Output - True 3.3 V Digital Output Supply Data Output Bit 0 - Channel B (LSB) Data Output Bit 1 - Channel B Data Output Bit 2 - Channel B Data Output Bit 3 - Channel B
Name
D4B D5B D6B D7B DrGND S1 PDWN S2 AVDD AGND SENSE VREF AGND AVDD AGND VINVIN+ AGND AVDD S3 DSDS+
Description
Data Output Bit 4 - Channel B Data Output Bit 5 - Channel B Data Output Bit 6 - Channel B Data Output Bit 7 - Channel B (MSB) Digital Ground
Data Format Select and Duty Cycle Stabilizer Select
Power Down Selection Output Mode State 3.3 V Analog Supply Analog Ground Reference Mode Selection Voltage Reference Input/Output Analog Ground 3.3 V Analog Supply Analog Ground Analog Input - Complement Analog Input - True Analog Ground 3.3 V Analog Supply DCO Enable Select Data Sync Complement (If Unused, tie to DRVDD) Data Sync True (If Unused, Tie to DGND)
Table 13: Pin Function Descriptions - CMOS Mode
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AD9480
PIN CONFIGURATIONS
42 LVDSBIAS DS+ DS40 AGND 37 AGND 35 AGND 41 AVDD 36 AVDD 34 VREF 39 VIN+ 38 VIN-
Preliminary Technical Data
44 CLK+ CLKAVDD AGND DRVDD DrGND D0_C (LSB) D0_T (LSB) D1_C D1_T 1 2 3 4 5 6 7 8 9 10
43
33 SENSE
PIN 1 IDENTIFIER
32 AGND 31 AVDD 30 S2
AD9480 - LVDS OUTPUTS TOP VIEW (PINS DOWN)
29 PDWN 28 S1
27 DrGND 26 D7_T (MSB) 25 D7_C (MSB) 24 D6_T 23 D6_C 12 D2_T 13 D3_C 14 D3_T 15 DrGND 16 DCO17 DCO+ 18 DRVD D 19 D4_C 20 D4_T 21 D5_C 22 D5_T
D2_C 11
Figure 17 LVDS Mode
AGND
AGND
AVDD
AVDD
AGND 35
DS+
44 CLK+ CLKAVDD AGND DRVDD DrGND D7A (MSB) D6A D5A D4A D3A 1 2 3 4 5 6 7 8 9 10 11 12 D2A
43
42
41
40
39
38
VIN-
37
36
34 33 SENSE
PIN 1 IDENTIFIER
VREF 32 AGND 31 AVDD 30 S2 29 PDWN 28
DS-
AD9480 - CMOS OUTPUTS TOP VIEW (PINS DOWN)
VIN+
S3
S1
27 DrGND 26 D7B (MSB) 25 D6B 24 D5B 23 D4B
13 D1A
14 D0A (LSB)
15 DrGND
16 DCO-
17 DCO+
18 DRVDD
19 D0B (LSB)
20 D1B
21 D2B
22 D3B
Figure 18 CMOS Mode
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Preliminary Technical Data
TIMING DIAGRAM
LVDS Timing:
N-1 N
AD9480
tA
N+9 N+1 N+8
N+10
N+11
AIN 8 cycles tEH CLK+ CLKtPD DATA OUT DCO+ DCODemuxed CMOS Timing:
N-1
tEL
1/fs
z
tv N-7 N N+1 N+2
N-8 tCPDR tCPDF
tA
N N+9 N+1 N+8
N+10
N+11
AIN 8 cycles tEH CLK+ CLKtHDS DS+ DSInterleaved Data Out PORT A D7 - D0 PORT B D7 - D0 STATIC STATIC INVALID tSDS INVALID tEL 1/fs
tPD N INVALID N+1
tv
Parallel Data Out PORT A D7 - D0 PORT B D7 - D0 DCO+ DCOSTATIC STATIC INVALID INVALID INVALID INVALID tCPD STATIC N N+1
Figure 19 Timing Diagram
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AD9480
OUTLINE DIMENSIONS
Preliminary Technical Data
Figure 20 Mechanical Drawing
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Ordering Guide
Model AD9480BSU-250 AD9480BSU-250EB Temperature Range -40C to +85C (Ambient) 25C (Ambient) Description 44-pin TQFP Evaluation Board
Table 14: Ordering Guide
(c) 2002 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. Printed in the U.S.A. PR04619-0-3/04(PrH).
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