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Quad 8-Bit, 65 MSPS Serial LVDS 3V A/D Converter
Preliminary Technical Data
FEATURES
* * * * * Four ADCs in one package Serial LVDS digital output data rates up to 520 MHz (ANSI-644) Data clock output provided SNR = 47 dB (to Nyquist) Excellent Linearity: - DNL = 0.25 LSB (Typical) - INL = 0.5 LSB (Typical) 400 MHz full power analog bandwidth Power dissipation = 330 mW at 65 MSPS 1 Vpp - 2 Vpp input voltage range +3.0 V supply operation Power down mode
AD9289
FUNCTIONAL BLOCK DIAGRAM
AVDD DRGND PDWN S1 S3 DRVDD OR+ OR8 Pipeline ADC Serial LVDS
AD9289
VIN+A VIN-A SHA
D1+A D1-A
* * * * *
VIN+D VIN-D VREF SENSE REFT_A REFB_A REFT_B REFB_B
8 SHA Pipeline ADC
Serial LVDS
D1+D D1-D
LVDSBIAS LOCK Ref Select
+ -
APPLICATIONS
* Tape drives * Medical imaging
0.5 V
Data Rate Multiplier MSB+ MSB- CLK+ CLK-
DCO+ DCO-
SHARED_REF CML AGND
Figure 1. Functional Block Diagram
PRODUCT DESCRIPTION
The AD9289 is a quad 8-bit, 65 MSPS analog-to-digital converter with an on-chip track-and-hold circuit and is designed for low cost, low power, small size and ease of use. The product operates up to 65 MSPS conversion rate and is optimized for outstanding dynamic performance where a small package size is critical. The ADC requires a single+3V power supply and LVDS, TTL, or PECL-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. A separate output power supply pin supports LVDS compatible serial digital output levels. The ADC automatically multiplies up the sample rate clock for the appropriate LVDS serial data rate. An MSB trigger is provided to signal a new output byte. Power down is supported, and the ADC consumes less than 10mW when enabled. Fabricated on an advanced CMOS process, the AD9289 is available in a 64-ball mini-BGA package (64 CSP_BGA) specified over the industrial temperature range (-40C to +85C).
PRODUCT HIGHLIGHTS
1. 2. 3. Four analog-to-digital converters are contained in one small, space saving package. A Data Clock Out (DCO) is provided which operates up to 260 MHz. The outputs of each ADC are serialized and provided on the rising and falling edge of DCO (rising edge only is also an option). Output data rates up to 520 MHz (8 bits x 65 MSPS) are available. The AD9289 operates from a single 3V power supply.
4.
Rev. PrD 2/20/2003
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD9289
TABLE OF CONTENTS
AD9289--Specifications.........................................................................3 DIGITAL SPECIFICATIONS............................................................4 AC SPECIFICATIONS.......................................................................4
Preliminary Technical Data
SWITCHING SPECIFICATIONS ....................................................5 EXPLANATION OF TEST LEVELS ................................................5 Ordering Guide....................................................................................6
Rev. PrD | Page 2 of 6
Preliminary Technical Data
AD9289--SPECIFICATIONS1
AVDD = 3.0V, DRVDD = 3.0V; EXT REF; DIFFERENTIAL ANALOG AND CLOCK INPUTS
Parameter
RESOLUTION No Missing Codes Offset Matching Gain Matching2 ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Offset Error TEMPERATURE DRIFT Gain Error2 Reference Internal Reference Voltage REFERENCE Output Current Input Current Input Resistance Differential Input Voltage Range Common Mode Voltage Input Resistance Input Capacitance Analog Bandwidth, Full Power AVDD DRVDD Power Dissipation3 Power Down Dissipation Power Supply Rejection Ratio (PSRR) IAVDD3 DRVDD3 Crosstalk Full 25C 25C 25C Full 25C Full Full Full Full 25C Full Full Full Full Full Full Full Full Full Full Full 25C Full Full Full
Table 1
AD9289
Temp
Test Level
VI I I I VI I VI V V V I V V V V V V V IV IV VI VI I VI VI V
Min
Typ
8 Guaranteed 25 2 0.25 0.5 16 150 0.5
Max
Unit
Bits mV % FS LSB LSB LSB LSB ppm/C ppm/C ppm/C V uA uA
7 1 -2 1.5 tbd 5 400 3.0 3.0 330 <10 110 27 70
k Vpp V k pF MHz V V mW mW mV/V mA mA dB
ANALOG INPUTS
2.7 2.7
3.6 3.6
POWER SUPPLY
CROSSTALK
1 2
Specifications subject to change without notice Gain error and gain temperature coefficients are based on the ADC only (with a fixed 0.5 V external reference and a 1 V p-p differential analog input). 3 Power dissipation measured with rated encode and a dc analog input (Outputs Static, IVDD = 0.). IVCC and IVDD measured with TBD MHz analog input @ 0.5dBFS. Rev. PrD | Page 3 of 6
AD9289
DIGITAL SPECIFICATIONS
AVDD = 3.0V, DRVDD = 3.0V
Parameter
Differential Input VIH VIL Input Resistance Input Capacitance Logic `1' Voltage Logic `0' Voltage Input Resistance Input Capacitance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding
1
Preliminary Technical Data
Temp
Full Full Full Full 25C Full Full Full Full Full Full Full
Test Level
IV IV IV IV IV IV IV IV IV IV IV IV
Min
100
Typ
350
Max
Unit
mV V V k pF
DIGITAL INPUTS (CLK+, CLK-)
2.0 0.8 30 4 247 454 1.125 1.375 Twos Complement or Binary
LOGIC INPUTS
V V k PF mV V
DIGITAL OUTPUTS (LVDS Mode)
Table 2: Digital Specifications
AC SPECIFICATIONS
Parameter
AVDD = 3.0 V, DRVDD = 3.0 V; INTERNAL REF; DIFFERENTIAL ANALOG AND CLOCK INPUT, LVDS OUTPUT MODE
Temp
fIN= 10.3 MHz SIGNAL TO NOISE RATIO (SNR) - Without Harmonics fIN= 19.6 MHz fIN= 32.5 MHz fIN= 51 MHz fIN= 10.3 MHz SIGNAL TO NOISE RATIO (SINAD) - With Harmonics fIN= 19.6 MHz fIN= 32.5 MHz fIN= 51 MHz fIN= 10.3 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN= 19.6 MHz fIN= 32.5 MHz fIN= 51 MHz fIN= 10.3 MHz SPURIOUS FREE DYNAMIC RANGE (SFDR) fIN= 19.6 MHz fIN= 32.5 MHz fIN= 51 MHz fIN= 10.3 MHz SECOND AND THIRD HARMONIC DISTORTION fIN= 19.6 MHz fIN= 32.5 MHz fIN= 51 MHz fIN= 10.3 MHz TOTAL HARMONIC DISTORTION (THD) fIN= 19.6 MHz fIN= 32.5 MHz fIN= 51 MHz TWO TONE INTERMOD DISTORTION (IMD) fIN1= 19 MHz, fIN2= 20 MHz fIN1= xx MHz, fIN2= xx MHz 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C
Test Level
V V I V V V I V V V I V V V I V V V I V V V I V V V
Min
Typ
47.5 47.5 47 47 7.5 7.5 62 59 62 59 60 58
Max
Unit
dB dB dB dB dB dB dB dB Bits Bits Bits Bits dB dB dB dB dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
Table 3: AC Specifications
1
SNR/harmonics based on an analog input voltage of -0.5 dBFS referenced to a 1 Vpp full-scale input range. Rev. PrD | Page 4 of 6
Preliminary Technical Data
SWITCHING SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V; DIFFERENTIAL ENCODE INPUT
Parameter
CLOCK Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) Valid Time (tV)1 Propagation Delay (tPD) 1 MSB Propagation Delay (tMSB) 1 Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) DCO Propagation Delay (tCPD) Data to DCO Skew (tPD - tCPD) Pipeline Latency Aperture Delay (tA) Aperture Uncertainty (Jitter)
AD9289
Temp
Full Full Full Full Full Full Full Full Full Full Full 25C 25C
Test Level
VI IV IV VI VI VI V V VI IV VI V V
Min
65 6.9 6.9 1.5
Typ
Max
Unit
MSPS ns ns ns ns ns ns ns ns ns cycles ps ps rms
3.5 0.7 0.7 3 0.5 6 <1
OUTPUT PARAMETERS IN LVDS MODE
APERTURE
Table 4: Switching Specifications
EXPLANATION OF TEST LEVELS
TEST LEVEL
I II III IV V VI 100% production tested. 100% production tested at +25C and guaranteed by design and characterization at specified temperatures. Sample Tested Only Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at +25C and guaranteed by design and characterization for industrial temperature range.
1 tV and tPD are measured from the transition points of the CLK input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 5 pF or a dc current of 40 A. Rise and fall times measured from 20% to 80%.
Rev. PrD | Page 5 of 6
AD9289
OUTLINE DIMENSIONS
Preliminary Technical Data
Figure 2:
Figure 3:
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Ordering Guide
Model AD9289BBC AD9289/PCB Temperature Range -40C to +85C (Ambient) 25C (Ambient) Description 64 CSP_BGA Evaluation Board
Table 5: Ordering Guide
(c) 2002 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. Printed in the U.S.A. C02959-0-11/02(0)
Rev. PrD | Page 6 of 6

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