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Memory ICs
1,024-Bit Serial Electrically Erasable PROM
BR93LC46 / BR93LC46F / BR93LC46RF / BR93LC46FV
*Features CMOS Technology * Low power
* 64 x 16bit configuration * 2.7V to 5.5V operation * Low power dissipation - 3mA (max.) active current: 5V - 5A (max.) standby current: 5V * Auto increment for efficient data dump * Automatic erase-before-write * Hardware and software write protection - Default to write-disabled state at power up - Software instructions for write-enable / disable - Vcc lockout inadvertent write protection * 8-pin SOP / 8-pin SSOP-B / 8-pin DIP packages * Device status signal during write cycle * TTL-compatible Input / Output * 100,000 ERASE / write cycles * 10 years Data Retention
*Pin assignments
CS 1 SK 2 DI 3 8 VCC 7 N.C. 6 N.C. 5 GND N.C. 1 VCC 2 CS 3 SK 4 8 N.C. 7 GND
BR93LC46 / BR93LC46RF
BR93LC46F / BR93LC46FV
6 DO 5 DI
DO 4
*Pin descriptions
Pin name CS SK DI DO GND N.C. N.C. VCC Chip select input Serial clock input Start bit, operating code, address, and seria data input Serial data output, READY / BUSY internal status display output Ground Not connected Not connected Power supply Function
*Overview series are CMOS serial input / output-type memory circuits (EEPROMs) that can be programmed The BR93LC46
electrically. Each is configured of 64 words x 16 bits (1,024 bits), and each word can be accessed individually and data read from it and written to it. Operation control is performed using five types of commands. The commands, addresses, and data are input through the DI pin under the control of the CS and SK pins. In a write operation, the internal status signal (READY or BUSY) can be output from the DO pin.
1
Memory ICs
BR93LC46 / BR93LC46F / BR93LC46RF / BR93LC46FV
*Block diagram
Power supply CS Command decode Control Clock generation SK Write disable High voltage generator voltage detector
Address Command DI register buffer
6bit
Address decoder 6bit 1,024-bit
Data 16bit register DO Dummy bit
R/W amplifier 16bit
EEPROM array
*Absolute maximum ratings (Ta = 25C)
Parameter Applied voltage BR93LC46 Power dissipation BR93LC46F / RF BR93LC46FV Storage temperature Operating temperature Terminal voltage Tstg Topr -- Pd Symbol VCC Limits - 0.3 ~ + 6.5 5001 3502 3003 - 65 ~ + 125 - 40 ~ + 85 - 0.3 ~ VCC + 0.3 C C V mW Unit V
1 Reduced by 5.0mW for each increase in Ta of 1C over 25C. 2 Reduced by 3.5mW for each increase in Ta of 1C over 25C. 3 Reduced by 3.0mW for each increase in Ta of 1C over 25C.
*Recommended operating conditions (Ta = 25C)
Parameter Power supply voltage Input voltage Writing Reading VIN Symbol VCC Min. 2.7 2.0 0 Typ. -- -- -- Max. 5.5 5.5 VCC Unit V V V
2
Memory ICs
BR93LC46 / BR93LC46F / BR93LC46RF / BR93LC46FV
*Electrical characteristics For 5V operation (unless otherwise noted, Ta = - 40 to + 85C, VCC = 5V 10%)
Parameter Input low level voltage Input high level voltage Output low level voltage 1 Output high level voltage 1 Output low level voltage 2 Output high level voltage 2 Input leakage current Output leakage current Operating current dissipation 1 Operating current dissipation 2 Standby current Symbol VIL VIH VOL1 VOH1 VOL2 VOH2 ILI ILO ICC1 Min. - 0.3 2.0 -- 2.4 -- VCC - 0.4 - 1.0 - 1.0 -- Typ. -- -- -- -- -- -- -- -- 1.5 Max. 0.8 VCC + 0.3 0.4 -- 0.2 -- 1.0 1.0 3 Unit V V V V V V A A mA IOL = 2.1mA IOH = - 0.4mA IOL = 10A IOH = - 10A VIN = 0V ~ VCC VOUT = 0V ~ VCC, CS = GND VIN = VIH / VIL, DO = OPEN f = 1MHz, WRITE VIN = VIH / VIL, DO = OPEN f = 1MHz, READ CS = SK = DI = GND, DO = OPEN Conditions -- --
ICC2 ISB
-- --
0.7 1.0
1.5 5
mA A
For 3V operation (unless otherwise noted, Ta = - 40 to + 85C, VCC = 3V 10%)
Parameter Input low level voltage Input high level voltage Output low level voltage Output high level voltage Input leakage current Output leakage current Operating current dissipation 1 Operating current dissipation 2 Standby current ICC2 ISB -- -- 0.2 0.4 1 3 mA A Symbol VIL VIH VOL VOH ILI ILO ICC1 Min. - 0.3 0.7 x VCC -- VCC - 0.4 - 1.0 - 1.0 -- Typ. -- -- -- -- -- -- 0.5 Max. 0.15 x VCC VCC + 0.3 0.2 -- 1.0 1.0 2 Unit V V V V A A mA IOL = 10A IOH = - 10A VIN = 0V ~ VCC VOUT = 0V ~ VCC, CS = GND VIN = VIH / VIL, DO = OPEN f = 250kHz, WRITE VIN = VIH / VIL, DO = OPEN f = 250kHz, READ CS = SK = DI = GND, DO = OPEN Conditions -- --
For 2V operation (unless otherwise noted, Ta = - 40 to + 85C, VCC = 2.0V)
Parameter Input low level voltage Input high level voltage Output low level voltage Output high level voltage Input leakage current Output leakage current Operating current dissipation 2 Standby current ISB -- 0.4 3 A Symbol VIL VIH VOL VOH ILI ILO ICC2 Min. - 0.3 0.7 x VCC -- VCC - 0.4 - 1.0 - 1.0 -- Typ. -- -- -- -- -- -- 0.2 Max. 0.15 x VCC VCC + 0.3 0.2 -- 1.0 1.0 1 Unit V V V V A A mA IOL = 10A IOH = - 10A VIN = 0V ~ VCC VOUT = 0V ~ VCC, CS = 0V VIN = VIH / VIL, DO = OPEN f = 200kHz, READ CS = SK = DI = 0V, DO = OPEN Conditions -- --
3
Memory ICs
BR93LC46 / BR93LC46F / BR93LC46RF / BR93LC46FV
Start bit Operating Address code
*Circuit operation (1) Command mode
Command
Data
With these ICs, commands are not 1 10 A5 ~ A0 -- Read (READ)1 recognized or acted upon until the 1 00 11XXXX -- Write enabled (WEN) start bit is received. The start bit is 2 1 01 A5 ~ A0 D15 ~ D0 Write (WRITE) taken as the first "1" that is received 1 00 01XXXX D15 ~ D0 Write all addresses (WRAL)2 after the CS pin rises. 1 After setting of the read command 1 00 00XXXX -- Write disabled (WDS) and input of the SK clock, data corre1 11 A5 ~ A0 -- Erase (ERASE)3 sponding to the specified address is 3 1 00 10XXXX -- Chip erase (ERAL) output, with data corresponding to upX: Either VIH or VIL per addresses then output in sequence. (Auto increment function) 2 When the write or write all addresses command is executed, all data in the selected memory cell is erased automatically, and the input data is written to the cell. 3 These modes are optional modes. Please contact Rohm for information on operation timing.
(2) Operation timing characteristics For 5V operation (unless otherwise noted, Ta = - 40 to + 85C, VCC = 5V 10%)
Parameter SK clock frequency SK "H" time SK "L" time CS "L" time CS setup time DI setup time CS hold time DI hold time Data "1" output delay time Data "0" output delay time Time from CS to output confirmation Time from CS to output High impedance Write cycle time Symbol fSK tSKH tSKL tCS tCSS tDIS tCSH tDIH tPD1 tPD0 tSV tDF tE / W Min. -- 450 450 450 50 100 0 100 -- -- -- -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 1 -- -- -- -- -- -- -- 500 500 500 100 10 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ms
4
Memory ICs
BR93LC46 / BR93LC46F / BR93LC46RF / BR93LC46FV
For low voltage operation (unless otherwise noted, Ta = - 40 to + 85C, VCC = 3V 10%)
Parameter SK clock frequency SK "H" time SK "L" time CS "L" time CS setup time DI setup time CS hold time DI hold time Data "1" output delay time Data "0" output delay time Time from CS to output confirmation Time from CS to output High impedance Write cycle time Symbol fSK tSKH tSKL tCS tCSS tDIS tCSH tDIH tPD1 tPD0 tSV tDF tE / W Min. -- 1 1 1 200 400 0 400 -- -- -- -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 250 -- -- -- -- -- -- -- 2 2 2 400 25 Unit kHz s s s ns ns ns ns s s s ns ms
When reading at low voltage (unless otherwise noted, Ta = - 40 to + 85C, VCC = 2.0V)
Parameter SK clock frequency SK "H" time SK "L" time CS "L" time CS setup time DI setup time CS hold time DI hold time Data "1" output delay time Data "0" output delay time Time from CS to output high impedance
Not designed for radiative rays.
Symbol fSK tSKH tSKL tCS tCSS tDIS tCSH tDIH tPD1 tPD0 tDF
Min. -- 2 2 2 400 800 0 800 -- -- --
Typ. -- -- -- -- -- -- -- -- -- -- --
Max. 200 -- -- -- -- -- -- -- 4 4 800
Unit kHz s s s ns ns ns ns s s ns
5
Memory ICs
(3) Timing chart
CS
BR93LC46 / BR93LC46F / BR93LC46RF / BR93LC46FV
tCSS
tSKH
tSKL
tCSH
SK
tDIS
DI
tDIH
tPD0
DO (READ)
tPD1
tDF
tDF
DO (WRITE) STATUS VALID
* Data is acquired from DI in synchronization with the SK rise. * During a reading operation, data is output from DO in synchronization with the SK rise. * During a writing operation, a Status Valid (READY or BUSY) is valid from the time CS is HIGH until time tCS after CS falls following the input of a write command and before the output of the next command start bit. Also, DO must be in a HIGH-Z state when CS is LOW. * After the completion of each mode, make sure that CS is set to LOW, to reset the internal circuit, before changing modes.
Fig. 1 Synchronized data timing
6
Memory ICs
BR93LC46 / BR93LC46F / BR93LC46RF / BR93LC46FV
(4) Reading (Figure 2) When the read command is acknowledged, the data (16 bits) for the input address is output serially. The data is synchronized with the SK rise during A0 acquisition and a "0" (dummy bit) is output. All further data is output in synchronization with the SK pulse rises. (5) Write enable (Figure 3) These ICs are set to the write disabled state by the internal reset circuit when the power is turned on. Therefore, before performing a write command, the write enable command must be executed. When this command is executed, it remains valid until a write disable command is issued or the power supply is cut
off. However, read commands can be used in either the write enable or write disable state. (6) Write (Figure 4) This command writes the input 16-bit data (D15 to D0) to the specified address (A5 to A0). Actual writing of the data begins after CS falls (following the 25th clock pulse after the start bit input), and DO is in the Acquire state. STATUS is not detected if CS = LOW after the time tE / W. When STATUS is detected (CS = HIGH), no commands are accepted while DO is LOW (BUSY). Therefore, no commands should be input during this period.
CS (1) SK 1 2 4 9 10 25 26
DI
1
1
0
A5
A4
A1
A0 (2)
DO High Z
0
D15
D14
D1
D0
D15
D14
(1) If the first data input following the rise of the start bit CS is "1", the start bit is acknowledged. Also, if a "1" is input following several zeroes in succession, the "1" is recognized as the start bit, and subsequent operation commences. This applies also to all commands described subsequently. (2) Address auto increment function: These ICs are equipped with an address auto increment function which is effective only during reading operations. With this function, if the SK clock is input following execution of one of the above reading commands, data is read from upper addresses in succession. CS is held in HIGH state during automatic incrementing.
Fig. 2 Read cycle timing (READ)
CS
SK
DI
1
0
0
1
1
DO High Z
Fig. 3 Write enable cycle timing
7
Memory ICs
BR93LC46 / BR93LC46F / BR93LC46RF / BR93LC46FV
CS
tCS
STATUS
SK
1
2
4
9
10
25
DI 1 0 1 A5 A4 A1 A0 D15 D14 D1 D0 tSV DO High Z tE / W BUSY READY
Fig. 4 Write cycle timing (WRITE)
tSV CS STATUS
SK
1
2
5
10
25
DI 1 0 0 0 1 D15 D14 D1 D0 tCS DO High Z tE / W BUSY READY
Fig. 5 Write all address cycle timing. (WRAL)
(STATUS) After time tCS following the fall of CS, after input of the write command), if CS is set to HIGH, the write execute = BUSY (LOW) and the command wait status READY (HIGH) are output. If in the command wait status (STATUS = READY), the next command can be performed within the time tE / W. Thus, if data is input via SK and DI with CS = HIGH in the tE / W period, erroneous operations may be performed. To avoid this, make sure that DI = LOW when CS = HIGH. (Caution is especially important when common input ports are used.) This applies to all of the write commands.
(7) All address write (Figure 5) With this command, the input 16-bit data is written simultaneously to all of the addresses (64 words). Rather than writing one word at a time, in succession, data is written all at one time, enabling a write time of tE / W. (8) Write disable (Figure 6) When the power supply is turned on, the IC enters the write disable status. Similarly, when the write disable command is issued, the IC enters the same status. When in this status, all write commands are ignored, but read commands may be executed. In the write enable status, writing begins even if a write command is entered accidentally. To prevent errors of this type, we recommend executing a write disable command after writing has been completed.
CS
SK
DI
1
0
0
0
0
DO High Z
Fig. 6 Write disable cycle timing (WDS)
8
Memory ICs
BR93LC46 / BR93LC46F / BR93LC46RF / BR93LC46FV
*Operation notes (1) Cancelling modes
READ Start bit 1 bit Operating code 2 bits Address 6 bits Data 16 bits
Cancel can be performed for the entire read mode space Cancellation method: CS LOW
WRITE, WRAL tE / W
Start bit
Operating code 2 bits
Address 6 bits
Data 16 bits
1 bit
a
b
a: Canceled by setting CS LOW or VCC OFF ( ) b: Cannot be canceled by any method. If VCC is set to OFF during this time, the data in the designated address is not secured. VCC OFF (VCC is turned off after CS is set to LOW)
Fig.7
9
Memory ICs
BR93LC46 / BR93LC46F / BR93LC46RF / BR93LC46FV
To prevent erroneous writing, these ICs are equipped with a POR (Power On Reset) circuit, but in order to achieve operation at a low power supply, VCC is set to operate at approximately 1.3V. After the POR has been activated, writing is disabled, but if CS is set to HIGH, writing may be enabled because of noise or other factors. However, the POR circuit is effective only when the power supply is on, and will not operate when the power is off. Also, to prevent erroneous writing at low voltages, these ICs are equipped with a built-in circuit (VCC-lockout circuit) which resets the write command if VCC drops to approximately 2V or lower (typ.) (). With the BR93LC46A, the circuit is tripped at approximately 3V or less
(typ).
(2) Timing in the standby mode As shown in Figure 8, during standby, if CS rises when SK is HIGH, the DI state may be read on the rising edge. If this happens, and DI is HIGH, this is taken to be the start bit, causing a bit error (see point "a" in Figure 8). Make sure all inputs are LOW during standby or when turning the power supply on or off (see Figure 9).
Point a: Start bit position during erroneous operation Point b: Timing during normal operation
SK
CS + 5V VCC DI a 0 1 b CS GND + 5V
Fig. 8 Erroneous operation timing
SK
GND Bad example Good example
(Bad example)
CS
Here, the CS pin is pulled up to VCC. In this case, CS is HIGH (active state). Please be aware that the EEPROM may perform erroneous operations or write erroneous data because of noise or other factors. Please be aware that this can occur even if the CS input is HIGH-Z. In this case, CS is LOW when the power supply is turned on or off.
(Good example)
DI
0
1 b
Fig. 10
Fig. 9 Normal operation timing
(3) Precautions when turning power on and off When turning the power supply on and off, make sure CS is set to LOW (see Figure 10). When CS is HIGH, the EEPROM enters the active state. To avoid this, make sure CS is set to LOW (disable mode) when turning on the power supply. (When CS is LOW, all input is cancelled.) When the power supply is turned off, the low power state can continue for a long time because of the capacity of the power supply line. Erroneous operations and erroneous writing can occur at such times for the same reasons as described above. To avoid this, make sure CS is set to LOW before turning off the power supply.
(4) Clock (SK) rise conditions If the clock pin (SK) signal of the BR93LC46 has a long rise time (tr) and if noise on the signal line exceeds a certain level, erroneous operation can occur due to erroneous counts in the clock. To prevent this, a Schmitt trigger is built into the SK input of the BR93LC46. The hysteresis amplitude of this circuit is set to approximately 0.2V, so if the noise exceeds the SK input, the noise amplitude should be set to 0.2VP-P or lower. Furthermore, rises and falls in the clock input should be accelerated as much as possible. (5) Power supply noise The BR93LC46 discharge high volumes of high voltage when a write is completed. The power supply may fluctuate at such times. Therefore, make sure a capacitor of 1000pF or greater is connected between VCC (Pin 8) and GND (Pin 5).
10
Memory ICs
BR93LC46 / BR93LC46F / BR93LC46RF / BR93LC46FV
(6) Connecting DI and DO directly The BR93LC46 have an independent input pin (DI) and output pin (DO). These are treated as individual signals on the timing chart but can be controlled through one control line. Control can be initiated on a single control line by inserting a resistor R.
BR93LC46 COM
IO port DI
R
DO
Fig. 11 Common connections for the DI and DO control line
1) Data collision between the -COM output and the DO output Within the input and output timing of the BR93LC46 the drive from the -COM output to the DI input and a signal output from the DO output can be emitted at the same time. This happens only for the 1 clock cycle (a dummy bit "0" is output to the DO pin) which acquires the A0 address data during a read cycle. When the address data A0 = 1, the -COM output becomes a
direct current source for the DO pin. The resistor R is the only resistance which limits this current. Therefore, a resistor with a value which satisfies the -COM and the BR93LC46 current capacity is required. When using a single control line, when a dummy bit "0" is output to the DO, the -COM I / O address data A0 is also output. Therefore, the dummy bit cannot be detected. 2) Feedback to the DI input from the DO output Data is output from the DO pin and then feeds back into the DI input through the resistor R. This happens when: * DO data is output during a read operation * A READY / BUSY signal is output during WRITE or WRAL operation Such feedback does not cause problems in the basic operation of the BR93LC46. The -COM input level must be adequately maintained for the voltage drop at R which is caused by the total input leakage current for the -COM and the BR93LC46. In the state in which SK is input, when the READY / BUSY function is used, make sure that CS is dropped to LOW within four clock pulses of the output of the READY signal HIGH and the standby mode is restored. For input after the fifth clock pulse, the READY HIGH will be taken as the start bit and WDS or some other mode will be activated, depending on the DI state.
11
Memory ICs
BR93LC46 / BR93LC46F / BR93LC46RF / BR93LC46FV
*External dimension (Units: mm)
BR93LC46 BR93LC46F / RF
9.3 0.3 6.5 0.3 8 5
5.0 0.2 8 6.2 0.3 4.4 0.2 5
1 0.51Min.
4 7.62
3.2 0.2 3.4 0.3
1.5 0.1
1
4
0.3 0.1
0.11
1.27
0.4 0.1
0.3Min. 0.15
2.54
0.5 0.1 0 ~ 15
DIP8
BR93LC46FV
3.0 0.2 8 6.4 0.3 4.4 0.2 5
SOP8
1.15 0.1
1 0.1
4
(0.52)
0.65 0.22 0.1
0.3Min. 0.1
SSOP-B8
12
0.15 0.1
0.15 0.1

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