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80C32/80C52
CMOS 0 to 44 MHz Single Chip 8-bit Microcontroller
1. Description
TEMIC's 80C52 and 80C32 are high performance CMOS versions of the 8052/8032 NMOS single chip 8 bit Microcontroller. The fully static design of the TEMIC 80C52/80C32 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The 80C52 retains all the features of the 8052: 8 K bytes of ROM; 256 bytes of RAM; 32 I/O lines; three 16 bit timers; a 6-source, 2-level interrupt structure; a full duplex serial port; and on-chip oscillator and clock circuits. In addition, the 80C52 has 2
D 80C32: Romless version of the 80C52 D 80C32/80C52-L16: Low power version VCC: 2.7 - 5.5 V Freq: 0-16 MHz D 80C32/80C52-12: 0 to 12 MHz D 80C32/80C52-16: 0 to 16 MHz D 80C32/80C52-20: 0 to 20 MHz D 80C32/80C52-25: 0 to 25 MHz D 80C32/80C52-30: 0 to 30 MHz D 80C32/80C52-36: 0 to 36 MHz
software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the RAM, the timers, the serial port and the interrupt system continue to function. In the power down mode the RAM is saved and all other functions are inoperative. The 80C32 is identical to the 80C52 except that it has no on-chip ROM. TEMIC's 80C52/80C32 are manufactured using SCMOS process which allows them to run from 0 up to 44 MHz with VCC = 5 V. TEMIC's 80C52 and 80C32 are also available at 16 MHz with 2.7 V < VCC < 5.5 V.
D 80C32-40: 0 to 40 MHz(1) D 80C32-42: 0 to 42 MHz(1) D 80C32-44: 0 to 44 MHz(1)
Notes: 1. 0 to 70_C temperature range. 2. For other speed and temperature range availability, please contact your sales office.
2. Features
D D D D D D D Power control modes 256 bytes of RAM 8 Kbytes of ROM (80C52) 32 programmable I/O lines Three 16 bit timer/counters 64 K program memory space 64 K data memory space D D D D D D Fully static design 0.8 CMOS process Boolean processor 6 interrupt sources Programmable serial port Temperature range: commercial, industrial, automotive, military
3. Optional
D Secret ROM: Encryption D Secret TAG: Identification number
Rev. I
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1
80C32/80C52
4. Interface
VCC VSS INT0 INT1
RST XTAL1 XTAL2 EA ALE PSEN WR RD AD0-AD7 A8-A15 Parallel I/O Ports & External Bus 8-BIT INTERNAL BUS Oscillator & Timing CPU RAM 256 bytes ROM 8 Kbytes Interrupt Unit
Serial I/O Port
Timer 0
Timer 1
Timer 2
P0
P1
P2
P3
RxD
TxD
T0
T1
T2
T2EX
Figure 1. Block Diagram
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80C32/80C52
P1.1/T2EX
P0.0/A0
P0.1/A1
P0.2/A2
6
P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5
5
4
3
2
1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
P0.4/A4 P0.5/A5 P0.6/A6 P0.7/A7 EA NC ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
P2.2/A10 P2.3/A11 P2.1/A9 P2.4/A12 XTAL2 XTAL1 VSS NC WR/P3.6 RD/P3.7 P2.0/A8
80C32/80C52
DIL
P1.1/T2EX P1.0/T2 A0/P0.0 A1/P0.1 A2/P0.2 A3/P0.3 P1.4 P1.3 P1.2 NC VCC
LCC
P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5
P0.4/A4 P0.5/A5 P0.6/A6 P0.7/A7 EA
80C32/80C52
NC ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13
XTAL2
XTAL1
NC
P2.2/A10
P2.3/A11
WR/P3.6
VSS
P2.0/A8
P2.1/A9
QFP Diagrams are for reference only. Package sizes are not to scale.
Figure 2. Pin Configuration
P2.4/A12
RD/P3.7
P0.3/A3
P1.0/T2
VCC
P1.4
P1.3
P1.2
NC
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80C32/80C52
5. Pin Description
5.1. VSS
Circuit ground potential.
5.2. VCC
Supply voltage during normal, Idle, and Power Down operation.
5.3. Port 0
Port 0 is an 8 bit open drain bi-directional I/O port. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application it uses strong internal pullups when emitting 1's. Port 0 also outputs the code bytes during program verification in the 80C52. External pullups are required during program verification. Port 0 can sink eight LS TTL inputs.
5.4. Port 1
Port 1 is an 8 bit bi-directional I/O port with internal pullups. Port 1 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL, on the data sheet) because of the internal pullups. Port 1 also receives the low-order address byte during program verification. In the 80C52, Port 1 can sink/ source three LS TTL inputs. It can drive CMOS inputs without external pullups. 2 inputs of PORT 1 are also used for timer/counter 2 : P1.0 [T2]: External clock input for timer/counter 2. P1.1 [T2EX]: A trigger input for timer/counter 2, to be reloaded or captured causing the timer/counter 2 interrupt.
5.5. Port 2
Port 2 is an 8 bit bi-directional I/O port with internal pullups. Port 2 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (ILL, on the data sheet) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16 bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1's. During accesses to external Data Memory that use 8 bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function Register. It also receives the high-order address bits and control signals during program verification in the 80C52. Port 2 can sink/source three LS TTL inputs. It can drive CMOS inputs without external pullups.
5.6. Port 3
Port 3 is an 8 bit bi-directional I/O port with internal pullups. Port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (ILL, on the data sheet) because of the pullups. It also serves the functions of various special features of the TEMIC 51 Family, as listed below.
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Port Pin
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
Alternate Function
RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) TD (Timer 0 external input) T1 (Timer 1 external input) WR (external Data Memory write strobe) RD (external Data Memory read strobe)
Port 3 can sink/source three LS TTL inputs. It can drive CMOS inputs without external pullups.
5.7. RST
A high level on this for two machine cycles while the oscillator is running resets the device. An internal pull-down resistor permits Power-On reset using only a capacitor connected to VCC. As soon as the Reset is applied (Vin), PORT 1, 2 and 3 are tied to one. This operation is achieved asynchronously even if the oscillator does not start-up.
5.8. ALE
Address Latch Enable output for latching the low byte of the address during accesses to external memory. ALE is activated as though for this purpose at a constant rate of 1/6 the oscillator frequency except during an external data memory access at which time one ALE pulse is skipped. ALE can sink/source 8 LS TTL inputs. It can drive CMOS inputs without an external pullup.
5.9. PSEN
Program Store Enable output is the read strobe to external Program Memory. PSEN is activated twice each machine cycle during fetches from external Program Memory. (However, when executing out of external Program Memory, two activations of PSEN are skipped during each access to external Data Memory). PSEN is not activated during fetches from internal Program Memory. PSEN can sink/source 8 LS TTL inputs. It can drive CMOS inputs without an external pullup.
5.10. EA
When EA is held high, the CPU executes out of internal Program Memory (unless the Program Counter exceeds 1 FFFH). When EA is held low, the CPU executes only out of external Program Memory. EA must not be floated.
5.11. XTAL1
Input to the inverting amplifier that forms the oscillator. Receives the external oscillator signal when an external oscillator is used. Output of the inverting amplifier that forms the oscillator. This pin should be floated when an external oscillator is used.
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80C32/80C52
6. Idle And Power Down Operation
Figure 3. shows the internal Idle and Power Down clock configuration. As illustrated, Power Down operation stops the oscillator. Idle mode operation allows the interrupt, serial port, and timer blocks to continue to function, while the clock to the CPU is gated off. These special modes are activated by software via the Special Function Register, PCON. Its hardware address is 87H. PCON is not bit addressable.
Figure 3. Idle and Power Down Hardware
PCON: Power Control Register (MSB) 7 SMOD Symbol
SMOD
(LSB) 6 - Position
PCON.7 Double Baud rate bit When set to a 1, the baud rate is doubled when the serial port is being used in either modes 1, 2 or 3. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. General-purpose flag bit General-purpose flag bit Power Down bit. Setting this bit activates power down operation
5 -
4 -
3 GF1
2 GF0
1 PD
0 IDL
Name and Function
-
PCON.6
-
PCON.5
- GF1 GF0
PCON.4 PCON.3 PCON.2
PD(1)
PCON.1
Cleared by hardware when an interrupt or reset occurs. Set to activate the Power-Down mode. If IDL and PD are both set, PD takes precedence. Idle mode bit
IDL(1)
PCON.0
Cleared by hardware when an interrupt or reset occurs. Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence.
1.
If 1's are written to PD and IDL at the same time. PD takes, precedence. The reset value of PCON is (000X0000).
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80C32/80C52
6.1. Idle Mode
The instruction that sets PCON.0 is the last instruction executed before the Idle mode is activated. Once in the Idle mode the CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator, RAM and all other registers maintain their data during idle. Table 1. describes the status of the external pins during Idle mode. There are three ways to terminate the Idle mode. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating Idle mode. The interrupt is serviced, and following RETI, the next instruction to be executed will be the one following the instruction that wrote 1 to PCON.0. The flag bits GF0 and GF1 may be used to determine whether the interrupt was received during normal execution or during the Idle mode. For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits. When Idle mode is terminated by an enabled interrupt, the service routine can examine the status of the flag bits. The second way of terminating the Idle mode is with a hardware reset. Since the oscillator is still running, the hardware reset needs to be active for only 2 machine cycles (24 oscillator periods) to complete the reset operation.
6.2. Power Down Mode
The instruction that sets PCON.1 is the last executed prior to entering power down. Once in power down, the oscillator is stopped. The contents of the onchip RAM and the Special Function Register is saved during power down mode. The hardware reset initiates the Special Fucntion Register. In the Power Down mode, VCC may be lowered to minimize circuit power consumption. Care must be taken to ensure the voltage is not reduced until the power down mode is entered, and that the voltage is restored before the hardware reset is applied which freezes the oscillator. Reset should not be released until the oscillator has restarted and stabilized. Table 1. describes the status of the external pins while in the power down mode. It should be noted that if the power down mode is activated while in external program memory, the port data that is held in the Special Function Register P2 is restored to Port 2. If the data is a 1, the port pin is held high during the power down mode by the strong pullup, T1, shown in Figure 4. Table 1. Status of the external pins during idle and power down modes
Mode
Idle Idle Power Down Power Down
Program Memory
Internal External Internal External
Ale
1 1 0 0
PSEN
1 1 0 0
PORT0
Port Data Floating Port Data Floating
PORT1
Port Data Port Data Port Data Port Data
PORT2
Port Data Address Port Data Port Data
PORT3
Port Data Port Data Port Data Port Data
6.3. Stop Clock Mode
Due to static design, the TEMIC 80C32/C52 clock speed can be reduced until 0 MHz without any data loss in memory or registers. This mode allows step by step utilization, and permits to reduce system power consumption by bringing the clock frequency down to any value. At 0 MHz, the power consumption is the same as in the Power Down Mode.
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80C32/80C52
6.4. I/O Ports
The I/O buffers for Ports 1, 2 and 3 are implemented as shown in Figure 4.
Figure 4. I/O Buffers in the 80C52 (Ports 1, 2, 3)
When the port latch contains a 0, all pFETS in figure 4 are off while the nFET is turned on. When the port latch makes a 0-to-1 transition, the nFET turns off. The strong pFET, T1, turns on for two oscillator periods, pulling the output high very rapidly. As the output line is drawn high, pFET T3 turns on through the inverter to supply the IOH source current. This inverter and T form a latch which holds the 1 and is supported by T2. When Port 2 is used as an address port, for access to external program of data memory, any address bit that contains a 1 will have his strong pullup turned on for the entire duration of the external memory access. When an I/O pin on Ports 1, 2, or 3 is used as an input, the user should be aware that the external circuit must sink current during the logical 1-to-0 transition. The maximum sink current is specified as ITL under the D.C. Specifications. When the input goes below approximately 2 V, T3 turns off to save ICC current. Note, when returning to a logical 1, T2 is the only internal pullup that is on. This will result in a slow rise time if the user's circuit does not force the input line high.
6.5. Oscillator Characteristics
XTAL1 and XTAL2 are the input and output respectively, of an inverting amplifier which is configured for use as an on-chip oscillator, as shown in Figure 5. Either a quartz crystal or ceramic resonator may be used.
Figure 5. Crystal Oscillator To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected as shown in Figure 6. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the Data Sheet must be observed.
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80C32/80C52
Figure 6. External Drive Configuration
7. Hardware Description
Same as for the 80C51, plus a third timer/counter.
7.1. Timer/Event Counter 2
Timer 2 is a 16 bit timer/counter like Timers 0 and 1, it can operate either as a timer or as an event counter. This is selected by bit C/T2 in the Special Function Register T2CON (Figure 1.). It has three operating modes : "capture", "autoload" and "baud rate generator", which are selected by bits in T2CON as shown in Table 2. In the capture mode there are two options which are selected by bit EXEN2 in T2CON; If EXEN2 = 0, then Timer 2 is a 16 bit timer or counter which upon overflowing sets bit TF2, the Timer 2 overflow bit, which can be used to generate an interrupt. If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively, (RCAP2L and RCAP2H are new Special Function Register in the 80C52). In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2, like TF2, can generate an interrupt. Table 2. Timer 2 Operating Modes
RCLK + TCLK
0 0 1 X
CP/RL2
0 1 X X
TR2
1 1 1 0 16 bit auto-reload 16 bit capture baud rate generator (off)
MODE
The capture mode is illustrated in Figure 7.
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80C32/80C52
OSC T2 C/T2
T2CON.1
12
Overflow
0 1
TH2 (8 bits) TR2
T2CON.2
TL2 (8 bits)
TF2
T2CON.7
Timer 2 Interrupt Request RCAP2H RCAP2L
T2EX EXEN2
T2CON.3
EXF2
T2CON.6
Figure 7. Timer 2 in Capture Mode In the auto-reload mode there are again two options, which are selected by bit EXEN2 in T2CON.If EXEN2 = 0, then when Timer 2 rolls over it does not only set TF2 but also causes the Timer 2 register to be reloaded with the 16 bit value in registers RCAP2L and RCAP2H, which are preset by software. If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input T2EX will also trigger the 16 bit reload and set EXF2. The auto-reload mode is illustrated in Figure 8. OSC T2 C/T2
T2CON.1
12
0 1
TH2 (8 bits) TR2
T2CON.2
TL2 (8 bits)
Overflow
TF2
T2CON.7
Timer 2 Interrupt Request RCAP2H RCAP2L
T2EX EXEN2
T2CON.3
EXF2
T2CON.6
Figure 8. Timer in Auto-Reload Mode
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80C32/80C52
T2CON (S:C8h) Timer/Counter 2 Control Register
7 TF2 Bit Number
7
6 EXF2 Bit Mnemonic
TF2
5 RCLK
4 TCLK
3 EXEN2 Description
2 TR2
1 C/T2#
0 CP/RL2#
Timer 2 Overflow flag TF2 is not set if RCLK= 1 or TCLK= 1. Set by hardware when Timer 2 overflows. Must be cleared by software Timer 2 External flag EXF2 does not cause an interrupt in up/down counter mode (DCEN= 1). Set by hardware if EXEN2= 1 when a negative transition on T2EX pin is detected. Receive Clock bit Clear to select Timer 1 as the Timer Receive Baud Rate Generator for the Serial Port in modes 1 and 3. Set to select Timer 2 as the Timer Receive Baud Rate Generator for the Serial Port in modes 1 and 3. Transmit Clock bit Clear to select Timer 1 as the Timer Transmit Baud Rate Generator for the Serial Port in modes 1 and 3. Set to select Timer 2 as the Timer Transmit Baud Rate Generator for the Serial Port in modes 1 and 3. Timer 2 External Enable bit Clear to ignore events on T2EX pin for Timer 2. Set to cause a capture or reload when a negative transition on T2EX pin is detected unless Timer 2 is being used as the Baud Rate Generator for the Serial Port. Timer 2 Run Control bit Clear to turn off Timer 2. Set to to turn on Timer 2. Timer 2 Counter/Timer Select bit Clear for Timer operation: Timer 2 counts the divided-down system clock. Set for Counter operation: Timer 2 counts negative transitions on external pin T2. Capture/Reload bit CP/RL2# is ignored and Timer 2 is forced to auto-reload on Timer 2 overflow if RCLK= 1 or TCLK= 1. Clear to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2= 1. Set to capture on negative transitions on T2EX pin if EXEN2= 1
6
EXF2
5
RCLK
4
TCLK
3
EXEN2
2
TR2
1
C/T2#
0
CP/RL2#
Reset Value= 0000 0000b
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- September 18, 1998
11
80C32/80C52
7.2. 80C52 with Secret ROM
TEMIC offers 80C52 with the encrypted secret ROM option to secure the ROM code contained in the 80C52 microcontrollers. The clear reading of the program contained in the ROM is made impossible due to an encryption through several random keys implemented during the manufacturing process. The keys used to do such encryption are selected randomwise and are definitely different from one microcontroller to another. This encryption is activated during the following phases : - Everytime a byte is addressed during a verify of the ROM content, a byte of the encryption array is selected. - MOVC instructions executed from external program memory are disabled when fetching code bytes from internal memory. - EA is sampled and latched on reset, thus all state modification are disabled. For further information please refer to the application note (ANM053) available upon request.
7.3. 80C52 with Secret TAG
TEMIC offers special 64-bit identifier called "SECRET TAG" on the microcontroller chip. The Secret Tag option is available on both ROMless and masked microcontrollers. The Secret Tag feature allows serialization of each microcontroller for identification of a specific equipment. A unique number per device is implemented in the chip during manufacturing process. The serial number is a 64-bit binary value which is contained and addressable in the Special Function Registers (SFR) area. This Secret Tag option can be read-out by a software routine and thus enables the user to do an individual identity check per device. This routine is implemented inside the microcontroller ROM memory in case of masked version which can be kept secret (and then the value of the Secret Tag also) by using a ROM Encryption. For further information, please refer to the application note (ANM031) available upon request.
8. Electrical Characteristics
8.1. Absolute Maximum Ratings(1) in Commercial and Industrial Temp Range
Ambiant Temperature Under Bias: C = commercial . . . . . . . . . . . . . . . . . . . . . I = industrial . . . . . . . . . . . . . . . . . . . . . . . . A = automotive . . . . . . . . . . . . . . . . . . . . . M = military . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . Voltage on VCC to VSS . . . . . . . . . . . . . . . Voltage on Any Pin to VSS . . . . . . . . . . . . . . . Power Dissipation . . . . . . . . . . . . . . . . . . . 0_C to 70_C -40_C to 85_C -40_C to +125_C -55_C to +125_C -65_C to + 150_C -0.5 V to + 7 V -0.5 V to VCC + 0.5 V 1 W(2)
Notes: 1. Stresses at or above those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. 2. This value is based on the maximum allowable die temperature and the thermal resistance of the package.
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80C32/80C52
8.2. DC parameters - Commercial and Industrial
Table 3. DC Parameters TA= 0C to 70C; VSS= 0 V; VCC= 5 V 10 %; F= 0 to 44 MHz TA= -40C + 85C; VSS= 0 V; VCC= 5 V 10 %; F= 0 to 36 MHz
Symbol
VIL VIH VIH1 VOL Input Low Voltage Input High Voltage (Except XTAL and RST) Input High Voltage (for XTAL and RST) Output Low Voltage (Port 1, 2 and 3)
Parameter
Min
- 0.5 0.2 VCC + 1.4 0.7 VCC
Max
0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5 0.3 0.45 1.0 0.3 0.45 1.0
Unit
V V V V V V V V V V V V V V V
Test Conditions
IOL= 100 A IOL= 1.6 mA(4) IOL= 3.5 mA IOL= 200 A IOL= 3.2 mA(4) IOL= 7.0 mA IOH= - 10 A IOH= - 30 A IOH= - 60 A VCC= 5 V 10 % IOH= - 200 A IOH= - 3.2 mA IOH= - 7.0 mA VCC= 5 V 10 % Vin= 0.45 V 0.45 < Vin < VCC Vin= 2.0 V VCC= 2.0 V to 5.5 V(3)
VOL1
Output Low Voltage (Port 0, ALE, PSEN)
VOH
Output High Voltage Port 1, 2, 3
VCC - 0.3 VCC - 0.7 VCC - 1.5
VOH1
Output High Voltage (Port 0, ALE, PSEN)
VCC - 0.3 VCC - 0.7 VCC - 1.5
IIL ILI ITL IPD RRST CIO ICC
Logical 0 Input Current (Ports 1, 2 and 3) Input leakage Current Logical 1 to 0 Transition Current (Ports 1, 2 and 3) Power Down Current RST Pulldown Resistor Capacitance of I/O Buffer Power Supply Current Freq= 1 MHz Icc op Icc idle Freq= 6 MHz Icc op Icc idle Freq 12 MHz Icc op= 1.25 Freq (MHz) + 5 mA Icc idle= 0.36 Freq (MHz) + 2.7 mA 50
- 50 10 - 650 50 200 10 1.8 1 10 4
A A A A KOhm pF mA mA mA mA
1 MHz, Ta= 25_C VCC= 5.5 V(1) (2)
Notes: 1. ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL= 5 ns, VIL= VSS + .5 V, VIH= VCC -.5 V; XTAL2 N.C. ; EA= RST= Port 0= VCC. ICC would be slighty higher if a crystal oscillator used. 2. Idle ICC is measured with all output pins disconnected ; XTAL1 driven with TCLCH, TCHCL= 5 ns, VIL= VSS + 5 V, VIH= VCC -.5 V ; XTAL2 N.C; Port 0= VCC; EA= RST= VSS. 3. Power Down ICC is measured with all output pins disconnected; EA= PORT 0= VCC; XTAL2 N.C. ; RST= VSS. 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operations. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed 0.45 V may exceed 0,45 V with maxi VOL peak 0.6 V. A Schmitt Trigger use is not necessary.
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80C32/80C52
8.3. DC parameters - Automotive
Table 4. DC Parameters TA= -40C + 125C; VSS= 0 V; VCC= 5 V 10 %; F= 0 to 36 MHz
Symbol
VIL VIH VIH1 VOL Input Low Voltage Input High Voltage (Except XTAL and RST) Input High Voltage (for XTAL and RST) Output Low Voltage (Port 1, 2 and 3)
Parameter
Min
- 0.5 0.2 VCC + 1.4 0.7 VCC
Max
0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5 0.3 0.45 1.0 0.3 0.45 1.0
Unit
V V V V V V V V V V V V V V V
Test Conditions
IOL= 100 A IOL= 1.6 mA(4) IOL= 3.5 mA IOL= 200 A IOL= 3.2 mA(4) IOL= 7.0 mA IOH= - 10 A IOH= - 30 A IOH= - 60 A VCC= 5 V 10 % IOH= - 200 IOH= - 3.2 mA IOH= - 7.0 mA VCC= 5 V 10 % Vin= 0.45 V 0.45 < Vin < VCC Vin= 2.0 V VCC= 2.0 V to 5.5 V(3)
VOL1
Output Low Voltage (Port 0, ALE, PSEN)
VOH
Output High Voltage Port 1, 2 and 3
VCC - 0.3 VCC - 0.7 VCC - 1.5
VOH1
Output High Voltage (Port 0, ALE, PSEN)
VCC - 0.3 VCC - 0.7 VCC - 1.5
IIL ILI ITL IPD RRST CIO ICC
Logical 0 Input Current (Ports 1, 2 and 3) Input leakage Current Logical 1 to 0 Transition Current (Ports 1, 2 and 3) Power Down Current RST Pulldown Resistor Capacitance of I/O Buffer Power Supply Current Freq= 1 MHz Icc op Icc idle Freq= 6 MHz Icc op Icc idle Freq 12 MHz Icc op= 1.25 Freq (MHz) + 5 mA Icc idle= 0.36 Freq (MHz) + 2.7 mA 50
- 75 10 - 750 75 200 10 1.8 1 10 4
A A A A KOhm pF mA mA mA mA
1 MHz, Ta= 25_C VCC= 5.5 V(1) (3)
Notes: 1. ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL= 5 ns, VIL= VSS + .5 V, VIH= VCC -.5 V; XTAL2 N.C. ; EA= RST= Port 0= VCC. ICC would be slighty higher if a crystal oscillator used. 2. Idle ICC is measured with all output pins disconnected ; XTAL1 driven with TCLCH, TCHCL= 5 ns, VIL= VSS + 5 V, VIH= VCC -.5 V ; XTAL2 N.C; Port 0= VCC; EA= RST= VSS. 3. Power Down ICC is measured with all output pins disconnected; EA= PORT 0= VCC; XTAL2 N.C. ; RST= VSS. 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operations. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed 0.45 V may exceed 0,45 V with maxi VOL peak 0.6 V. A Schmitt Trigger use is not necessary.
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8.4. DC parameters -Military
Table 5. DC Parameters TA= -55C + 125C; VSS= 0 V; VCC= 5 V 10 %; F= 0 to 36 MHz
Symbol
VIL VIH VIH1 VOL VOL1 VOH Input Low Voltage Input High Voltage (Except XTAL and RST) Input High Voltage (for XTAL and RST) Output Low Voltage (Port 1, 2 and 3) Output Low Voltage (Port 0, ALE, PSEN) Output High Voltage (Port 1, 2 and 3) 2.4 0.75 VCC 0.9 VCC VOH1 Output High Voltage (Port 0 in External Bus Mode, ALE, PEN) 2.4 0.75 VCC 0.9 VCC IIL ILI ITL IPD RRST CIO ICC Logical 0 Input Current (Ports 1, 2 and 3) Input leakage Current Logical 1 to 0 Transition Current (Ports 1, 2 and 3) Power Down Current RST Pulldown Resistor Capacitance of I/O Buffer Power Supply Current Freq= 1 MHz Icc op Icc idle Freq= 6 MHz Icc op Icc idle Freq 12 MHz Icc op= 1.25 Freq (MHz) + 5 mA Icc idle= 0.36 Freq (MHz) + 2.7 mA 50 - 75 +/- 10 - 750 75 200 10 1.8 1 10 4
Parameter
Min
- 0.5 0.2 VCC + 1.4 0.7 VCC
Max
0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5 0.45 0.45
Unit
V V V V V V V V V V V A A A A K pF mA mA mA mA
Test Conditions
IOL= 1.6 mA(4) IOL= 3.2 mA(4) IOH= - 60 A VCC= 5 V 10 % IOH= - 25 A IOH= - 10 A IOH= - 400 A VCC= 5 V 10 % IOH= - 150 A IOH= - 40 A Vin= 0.45 V 0.45 < Vin < VCC Vin= 2.0 V VCC= 2.0 V to 5.5 V(3)
MHz, Ta= 25_C VCC= 5.5 V
Notes: 1. ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL= 5 ns, VIL= VSS + .5 V, VIH= VCC -.5 V; XTAL2 N.C. ; EA= RST= Port 0= VCC. ICC would be slighty higher if a crystal oscillator used. 2. Idle ICC is measured with all output pins disconnected ; XTAL1 driven with TCLCH, TCHCL= 5 ns, VIL= VSS + 5 V, VIH= VCC -.5 V ; XTAL2 N.C; Port 0= VCC; EA= RST= VSS. 3. Power Down ICC is measured with all output pins disconnected; EA= PORT 0= VCC; XTAL2 N.C. ; RST= VSS. 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operations. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed 0.45 V may exceed 0,45 V with maxi VOL peak 0.6 V. A Schmitt Trigger use is not necessary.
Rev. I
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15
80C32/80C52
8.5. DC parameters - Low voltage - Commercial and Industrial
Table 6. DC Characteristics TA= 0C to 70C; VCC= 2.7 V to 5.5 V; VSS= 0 V; F= 0 to 16 MHz TA= -40C to 85C; VCC= 2.7 V to 5.5 V
Symbol
VIL VIH VIH2 VIH1 VPD VOL VOL1 VOH VOH1 IIL ILI ITL IPD RRST CIO
Parameter
Input Low Voltage Input High Voltage (Except XTAL and RST) Input High Voltage to RST for Reset Input High Voltage to XTAL1 Power Down Voltage to VCC in PD Mode Output Low Voltage (Ports 1, 2, 3) Output Low Voltage Port 0, ALE, PSEN Output High Voltage Ports 1, 2, 3 Output High Voltage (Port 0 in External Bus Mode), ALE, PSEN Logical 0 Input Current Ports 1, 2, 3 Input Leakage Current Logical 1 to 0 Transition Current (Ports 1, 2, 3) Power Down Current RST Pulldown Resistor Capacitance of I/O Buffer
Min
- 0.5 0.2 VCC + 1.4 0.7 VCC 0.7 VCC 2.0
Max
0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5 VCC + 0.5 5.5 0.45 0.45
Unit
V V V V V V V V V
Test Conditions
IOL= 0.8 mA(4) IOL= 1.6 mA(4) IOH= - 10 A IOH= - 40 A Vin= 0.45 V 0.45 < Vin < VCC Vin= 2.0 V VCC= 2.0 V to 5.5 V(3)
0.9 VCC 0.9 VCC - 50 10 - 650 50 50 200 10
A A A A k pF
MHz, TA= 25_C
Notes: 1. ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL= 5 ns, VIL= VSS + .5 V, VIH= VCC -.5 V; XTAL2 N.C. ; EA = RST = Port 0 = VCC. ICC would be slighty higher if a crystal oscillator used. 2. Idle ICC is measured with all output pins disconnected ; XTAL1 driven with TCLCH, TCHCL= 5 ns, VIL= VSS + 5 V, VIH= VCC -.5 V ; XTAL2 N.C; Port 0= VCC; EA= RST= VSS. 3. Power Down ICC is measured with all output pins disconnected; EA= PORT 0= VCC; XTAL2 N.C. ; RST= VSS. 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operations. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed 0.45 V may exceed 0,45 V with maxi VOL peak 0.6 V. A Schmitt Trigger use is not necessary.
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Rev. I
- September 18, 1998
80C32/80C52
Table 7. Maximum Icc (mA)
Operating(1)
FREQUENCY/VCC 1 MHz 6 MHz 12 MHz 16 MHz Freq > 12 MHz (VCC= 5.5 V) 2.7 V 0.8 mA 4 mA 8 mA 10 mA 3V 1 mA 5 mA 10 mA 12 mA 3.3 V 1.1 mA 6 mA 12 mA 14 mA 5.5 V 1.8 mA 10 mA 2.7 V 400 A 1.5 mA 2.5 mA 3 mA 3V 500 A 1.7 mA 3 mA 3.8 mA
IDLE(2)
3.3 V 600 A 2 mA 3.5 mA 4.5 mA 5.5 V 1 mA 4 mA
Icc (mA)= 1.25 x Freq (MHz) + 5 Icc Idle (mA)= 0.36 x Freq (MHz) + 2.7
Notes: 1. ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL= 5 ns, VIL= VSS + .5 V, VIH= VCC -.5 V; XTAL2 N.C. ; EA= RST= Port 0= VCC. ICC would be slighty higher if a crystal oscillator used. Idle ICC is measured with all output pins disconnected ; XTAL1 driven with TCLCH, TCHCL= 5 ns, VIL= VSS + 5 V, VIH= VCC -.5 V ; 2. XTAL2 N.C; Port 0= VCC; EA= RST= VSS. 3. Power Down ICC is measured with all output pins disconnected; EA= PORT 0= VCC; XTAL2 N.C. ; RST= VSS. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1 and 3. The 4. noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operations. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed 0.45 V may exceed 0,45 V with maxi VOL peak 0.6 V. A Schmitt Trigger use is not necessary.
Figure 9. ICC Test Condition, Idle Mode. All other pins are disconnected
Figure 10. ICC Test Condition, Active Mode. All other pins are disconnected
Rev. I
- September 18, 1998
17
80C32/80C52
Figure 11. ICC Test Condition, Power Down Mode. All other pins are disconnected
Note: TCLCH= TCHCL= 5ns
Figure 12. Clock Signal Waveform for ICC Tests in Active and Idle Modes
8.6. Explanation of the AC Symbol
Each timing symbol has 5 characters. The first character is always a "T" (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example : TAVLL= Time for Address Valid to ALE low. TLLPL= Time for ALE low to PSEN low.
A: Address. C: Clock. D: Input data. H: Logic level HIGH I: Instruction (program memory contents). L: Logic level LOW, or ALE. P: PSEN. Q: Output data. R: READ signal. T: Time. V: Valid. W: WRITE signal. X: No longer a valid logic level. Z: Float.
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- September 18, 1998
80C32/80C52
8.7. AC Parameters
TA= 0 to + 70C; VSS= 0 V; VCC= 5 V 10 %; F= 0 to 44 MHz TA= 0 to +70C; VSS= 0 V; 2.7 V < VCC < 5.5 V; F= 0 to 16 MHz TA= -40 to + 85C; VSS= 0 V; 2.7 V < VCC < 5.5 V; F= 0 to 16 MHz TA= -55 + 125C; VSS= 0 V; VCC= 5 V 10 %; F= 0 to 36 MHz
(Load Capacitance for PORT 0, ALE and PSEN= 100 pF; Load Capacitance for all other outputs= 80 pF)
Table 8. External Program Memory Characteristics (values in ns)
16 MHz Symbol
TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TPXAV TAVIV TPLAZ
20 MHz
25 MHz
30 MHz
36 MHz
40 MHz
42 MHz
44 MHz
Parameter
ALE Pulse Width Address valid to ALE Address Hold After ALE ALE to valid instr in ALE to PSEN PSEN pulse Width PSEN to valid instr in Input instr Hold After PSEN Input instr Float After PSEN PSEN to Address Valid Address to Valid instr in PSEN low to Address Float
min max min max min max min max min max min max min max min max
110 40 35 185 45 165 125 0 50 55 230 10 50 210 10 0 45 40 170 8 40 130 110 0 35 35 130 6 90 30 35 170 30 100 85 0 30 30 90 5 70 20 35 130 25 80 65 0 25 25 80 5 60 15 35 100 20 75 50 0 20 20 75 5 50 10 35 80 15 65 45 0 15 15 70 5 40 9 30 70 13 60 40 0 10 35 8 25 65 12 54 35 30 7 17 65
12 TCLCL
TLHLL TLLIV TLLPL TPLPH
ALE
PSEN
TLLAX TAVLL TPLIV TPLAZ TPXIX
TPXAV TPXIZ
PORT 0
INSTR IN
A0-A7
TAVIV
INSTR IN
A0-A7
INSTR IN
PORT 2
ADDRESS OR SFR-P2
ADDRESS A8-A15
ADDRESS A8-A15
Figure 13. External Program Memory Read Cycle
Rev. I
- September 18, 1998
19
80C32/80C52
Table 9. External Data Memory Characteristics (values in ns)
16 MHz Symbol
TRLRH TWLWH TLLAX TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH
20 MHz
25 MHz
30 MHz
36 MHz
40 MHz
42 MHz
44 MHz
Parameter
RD pulse Width WR pulse Width Address Hold After ALE RD to Valid Data in Data hold after RD Data float after RD ALE to Valid Data In Address to Valid Data IN ALE to WR or RD Address to WR or RD Data valid to WR transition Data Setup to WR transition Data Hold after WR RD low to Address Float RD or WR high to ALE high
min max min max min max min max min max min max min max min max
340 340 85 240 0 90 435 480 150 180 35 380 40 0 35 90 35 250 135 180 35 325 35 0 60 25 0 90 370 400 170 120 140 30 250 30 0 45 20 270 270 85 210 0 80 290 320 130 90 115 20 215 20 0 40 20 210 210 70 175 0 70 235 260 115 70 75 15 170 15 0 40 15 180 180 55 135 0 50 170 190 100 60 65 10 160 10 0 35 13 120 120 35 110 0 45 150 180 95 55 60 8 150 8 0 33 13 100 100 30 90 0 40 140 175 90 50 55 6 140 6 0 33 90 90 25 80 0 35 130 170 85 80 80 25 70
TWHLH
ALE
PSEN
TLLWL
TWLWH
WR
TQVWX TLLAX TQVWH TWHQX
PORT 0
A0-A7
TAVWL
DATA OUT
PORT 2
ADDRESS OR SFR-P2
ADDRESS A8-A15 OR SFR P2
Figure 14. External Data Memory Write Cycle
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Rev. I
- September 18, 1998
80C32/80C52
TWHLH
ALE
TLLDV
PSEN
TLLWL
TRLRH
RD
TAVDV TLLAX TRHDX
TRHDZ
PORT 0
A0-A7
TAVWL TRLAZ
DATA IN
PORT 2
ADDRESS OR SFR-P2
ADDRESS A8-A15 OR SFR P2
Figure 15. External Data Memory Read Cycle
Table 10. Serial Port Timing - Shift Register Mode (values in ns)
16 MHz Symbol
TXLXL TQVXH TXHQX TXHDX TXHDV
20 MHz
25 MHz
30 MHz
36 MHz
40 MHz
42 MHz
44 MHz
Parameter
Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Input Data Hold after Clock Rising Edge Clock Rising Edge to Input Data Valid
min max min max min max min max min max min max min max min max
750 563 63 0 563 600 480 90 0 450 480 380 65 0 350 400 300 50 0 300 330 220 45 0 250 250 170 35 0 200 230 150 30 0 180 227 140 25 0 160
Figure 16. Shift Register Timing Waveforms
Rev. I
- September 18, 1998
21
80C32/80C52
Table 11. External Clock Drive Characteristics (XTAL1)
Symbol
FCLCL TCLCL TCHCX TCLCX TCLCH TCHCL
Parameter
Oscillator Frequency Oscillator period High Time Low Time Rise Time Fall Time
Min
Max
44
Unit
MHz ns ns ns
22.7 5 5 5 5
ns ns
Figure 17. External Clock Drive Waveforms
Figure 18. AC Testing Input/Output Waveforms AC inputs during testing are driven at VCC - 0.5 for a logic "1" and 0.45 V for a logic "0". Timing measurements are made at VIH min for a logic "1" and VIL max for a logic "0".
Figure 19. Float Waveforms For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. Iol/IoH 20 mA.
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Rev. I
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80C32/80C52
Figure 20. Clock Waveforms This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA = 25C fully loaded) RD and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications.
Rev. I
- September 18, 1998
23
80C32/80C52
9. Ordering Information
I S 80C52C xxx -36 D
Temperature Range blank : Commercial I : Industrial A : Automotive M : Military
Part Number 80C52 Rom 8 K x 8 80C32 External ROM 80C52C Secret ROM version 80C52T Secret Tag version 80C32E Radiation Tolerant 80C52E Radiation Tolerant
-12 -16 -20 -25 -30 -36 -40 -42 -44 -L16
Package Type P: PDIL 40 S: PLCC 44 F1: PQFP 44 (Foot print 13.9 mm) F2: PQFP 44 (Foot print 12.3 mm) V: VQFP (1.4 mm) T: TQFP (1.0 mm) D: CDIL 40 Customer Rom Code Q: CQFP 44 R: LCC 44 C: Side Brazed 40 (.6) J: J Leaded LCC
: 12 MHz version : 16 MHz version : 20 MHz version : 25 MHz version : 30 MHz version : 36 MHz version : 40 MHz version (1) : 42 MHz version (1) : 44 MHz version (1) : Low Power (VCC: 2.7-5.5 V Freq: 0-16 MHz)
1.
Only for 80C32 at Commercial range.
blank /883 SB/SC SHXXX FHXXX EHXXX MHXXX LHXXX :R : RD :D
= = = = = = = = = = =
MHS standards MIL STD 883 Class B or S SCC 9000 level B/C Special customer request Flight models (space) Engineering models (space) Mechanical parts (space) Life test parts (space) Tape and reel Tape and reel dry pack Dry pack
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Rev. I
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80C32/80C52
Temp. range Packages
L-16
Speed (MHz)
16,00 20,00 25,00 30,00 36,00
Std process 80C32/52
RT process 80C32E
Mil flows M D R J Q X C J R X x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Mil flows x x x
Space flows
S
x x x x
Rev. I
- September 18, 1998
25

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