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Triple Port PHY (Physical Layer) for 25.6 and 51.2 Mbps ATM Networks
PRELIMINARY IDT77V1253
Integrated Device Technology, Inc.
FEATURES
* Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for three 25.6 Mbps ATM channels * Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5 specifications for 25.6 Mbps physical interface * Also operates at 51.2Mbps * UTOPIA Level 1, UTOPIA Level 2, or DPI-4 Interface * 3-Cell Transmit & Receive FIFOs * LED Interface for status signalling * Supports UTP Category 3 physical media * Interfaces to standard magnetics * Low-Power CMOS * 3.3V supply with 5V tolerant inputs * 144-pin PQFP Package (28 x 28 mm)
DESCRIPTION
The IDT77V1253 is a member of IDT's family of products supporting Asynchronous Transfer Mode (ATM) data communications and networking. The IDT77V1253 implements the physical layer for 25.6 Mbps ATM, connecting three serial copper links (UTP Category 3) to one ATM layer device such as a SAR or a switch ASIC. The IDT77V1253 also operates at 51.2 Mbps, and is well suited to backplane driving applications. The 77V1253-to-ATM layer interface is selectable as one of three options: 16-bit UTOPIA Level 2, 8-bit UTOPIA Level 1 Multi-PHY, or triple 4-bit DPI (Data Path Interface). The IDT77V1253 is fabricated using IDT's state-of-the-art CMOS technology, providing the highest levels of integration, performance and reliability, with the low-power consumption characteristics of CMOS.
FUNCTIONAL BLOCK DIAGRAM - UTOPIA LEVEL 2 MODE
TxCLK TxDATA[15:0] TxPARITY TxSOC TxCLAV TxADDR[4:0] MODE[1:0] PHY-ATM Interface (UTOPIA or DPI)
Tx/Rx ATM Cell FIFO
Scrambler/ Descrambler
5B/4B Encoding/ Decoding
Driver P/S and S/P NRZI Clock/Data Recovery
+ Tx 0 - + Rx 0 -
RxADDR[4:0] RxCLK RxDATA[15:0] RxPARITY RxSOC RxCLAV
Tx/Rx ATM Cell FIFO
Scrambler/ Descrambler
5B/4B Encoding/ Decoding
Driver P/S and S/P NRZI Clock/Data Recovery
+ Tx 1 - + Rx 1 -
Microprocessor (Utility Bus) Interface AD[7:0] ALE
Tx/Rx ATM Cell FIFO
Scrambler/ Descrambler
5B/4B Encoding/ Decoding
Driver P/S and S/P NRZI Clock/Data Recovery
+ - Tx 2 + - Rx 2
OSC
3
3
RxLED[2:0]
TxLED[2:0]
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
(c)1998 Integrated Device Technology, Inc.
NOVEMBER 1998
DSC-4781/1
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IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
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VDD GND TX0TX0+ VDD MM MODE1 MODE0
GND DNC TXLED2 TXLED1 TXLED0 VDD TXDATA0 TXDATA1 TXDATA2 TXDATA3 TXDATA4 TXDATA5 TXDATA6 TXDATA7 TXDATA8 TXDATA9 TXDATA10 TXDATA11 TXDATA12 TXDATA13 TXDATA14 TXDATA15 TXPARITY TXSOC TXADDR4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
TX1+ TX1GND AGND AVDD RX0+ RX0AVDD AGND AGND AVDD RX1+ RX1AVDD AGND AGND AVDD AGND OSC AVDD AGND AGND AVDD RX2+ RX2AVDD AGND AGND AVDD MB MA AVDD AGND GND TX2+ TX2-
77V1253
144-PQFP
VDD GND DNC DNC VDD DA SE AD7 AD6 AD5 AD4 GND AD3 AD2 AD1 AD0 VDD ALE
GND VDD GND DNC RXLED2 RXLED1 RXLED0 VDD GND RXDATA0 RXDATA1 RXDATA2 RXDATA3
TXADDR3 VDD TXADDR2 TXADDR1 TXADDR0 TXCLAV TXCLK GND VDD RXCLK
RXADDR0 RXADDR1 GND RXADDR2 RXADDR3 RXADDR4 RXCLAV RXSOC GND VDD RXPARITY RXDATA15 RXDATA14 RXDATA13 RXDATA12 RXDATA11 RXDATA10 RXDATA9 RXDATA8 GND VDD RXDATA7 RXDATA6 RXDATA5 RXDATA4
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
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Figure 1. Pin Assignments
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IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
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TABLE 1. SIGNAL DESCRIPTIONS
SIGNAL NAME
RX0+, RX1+, RX2+, TX0+, TX1+, TX2+, -
PIN NUMBER
139, 138 133, 132 121, 120 4, 3 144, 143 110, 109
LINE SIDE SIGNALS I/O
In In In Out Out Out
SIGNAL DESCRIPTION
Port 0 positive and negative receive differential input pair Port 1 positive and negative receive differential input pair Port 2 positive and negative receive differential input pair Port 0 positive and negative transmit differential output pair Port 1 positive and negative transmit differential output pair Port 2 positive and negative transmit differential output pair
UTILITY BUS SIGNALS SIGNAL NAME
AD[7:0]
PIN NUMBER
101, 100, 99, 98 96, 95, 94, 93
I/O
In/Out
SIGNAL DESCRIPTION
Utility bus address/data bus. The address input is sampled on the falling edge of ALE. Data is output on this bus when a read is performed. Input data is sampled at the completion of a write operation. Utility bus address latch enable. Asynchronous input. An address on the AD bus is sampled on the falling edge of ALE. ALE may be either high low when the AD bus is being used for data. Utility bus asynchronous chip select. CS must be asserted to read or write an internal register. It may remain asserted at all times if desired. Utility bus read enable. Active low asynchronous input. After latching an address, a read is performed by deasserting WR and asserting RD and CS. Utility bus write enable. Active low asynchronous input. After latching an address, a write is performed by deasserting RD, placing data on the AD bus, and asserting WR and CS. Data is sampled when WR or CS is deasserted.
ALE
91
In
CS RD WR
90
In
89
In
88
In
MISCELLANEOUS SIGNALS SIGNAL NAME
DA DNC
PIN NUMBER
103 12, 82, 105, 106 85
I/O
In Out Out open drain
SIGNAL DESCRIPTION
Reserved signal. This input must be connected to logic low. Do Not Connect. Do not connect these pins to anything external to the chip. They must remain open. Interrupt. INT is an open-drain output, driven low to indicate an interrupt. Once low, INT remains low until the interrupt status in the appropriate Interrupt Status Register is read. Interrupt sources are programmable via the Interrupt Mask Registers. Reserved signal. This input must be connected to logic low. Reserved signal. This input must be connected to logic low. Reserved signal. This input must be connected to logic high. Mode Selects. They determine the configuration of the PHY/ATM interface. 00 = UTOPIA Level 2. 01 = UTOPIA Level 1. 10 = DPI. 11 is reserved. TTL line rate clock source, driven by a 100 ppm oscillator. 32 MHz for 25.6 Mbps; 64 MHz for 51.2 Mbps. Reset. Active low asynchronous input resets all control logic, counters and FIFOs. A reset must be performed after power up prior to normal operation of the part. Receive LED drivers. Driven low for 223 RCLK or DPICLK cycles, beginning with RXSOC when that port receives a good (non-null and non-errored) cell. Drives 8 mA both high and low. One per port.
INT
MA MB MM MODE[1:0]
114 115 6 7, 8
In In In In
OSC
126 87
In In
RST
RXLED[2:0]
81, 80, 79
Out
3
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TABLE 1. SIGNAL DESCRIPTIONS (continued)
SIGNAL NAME RXREF PIN NUMBER
9
I/O
Out
SIGNAL DESCRIPTION
Receive Reference. Active low, synchronous to OSC. RXREF pulses low for a programmable number of clock cycles when an X_8 command byte is received. Register 0x40 is programmed to indicate which port is referenced. Reserved signal. This input must be connected to logic low. Ports 2 thru 0 Transmit LED driver. Goes low for 223 TCLK or DPICLK cycles, beginning with TXSOC when this port receives a cell for transmission. 8mA drive current both high and low. One per port. Transmit Reference. Synchronous to OSC. When this pin is asserted, an X_8 command byte is inserted into the transmit data stream. Logic for this signal is programmed in register 0x40. Typical application is WAN timing.
SE TXLED[2:0]
102 13, 14, 15
In Out
TXREF
10
In
POWER SUPPLY SIGNALS SIGNAL NAME
AGND
PIN NUMBER
112, 117, 118, 123,124,127, 129,130,135, 136, 141 113, 116, 119, 122, 125, 128, 131, 134, 137, 140 2, 11, 44, 50, 56 67, 77, 83, 86, 97, 107, 111, 142 1, 5, 16, 38, 45 57, 68, 78, 84, 92, 104, 108
I/O
-
SIGNAL DESCRIPTION
Analog ground. AGND supply a ground reference to the analog portion of the chip, which sources a more constant current than the digital portion. Analog power supply. 3.3 0.3V AVDD supply power to the analog portion of the chip, which draws a more constant current than the digital portion. Digital Ground
AVDD
-
GND
-
VDD
-
Digital power supply. 3.3 0.3V
SIGNAL NAME
RXADDR[4:0]
16-BIT UTOPIA 2 SIGNALS (MODE[1:0] = 00) PIN NUMBER I/O SIGNAL DESCRIPTION
53, 52, 51, 49, 48 In Utopia 2 Receive Address Bus. This bus is used in polling and selecting the receive port. The port addresses are defined in bits [4:0] of the Enhanced Control Registers. Utopia 2 Receive Cell Available. Indicates the cell available status of the addressed port. It is asserted when a full cell is available for retrieval from the receive FIFO. When none of the three ports is addressed, RXCLAV is high impedance. Utopia 2 Receive Clock. This is a free running clock input. Utopia 2 Receive Data. When one of the three ports is selected, the 77V1253 transfers received cells to an ATM device across this bus. Also see RXPARITY. Utopia 2 Receive Enable. Driven by an ATM device to indicate its ability to receive data across the RXDATA bus. Utopia 2 Receive Data Parity. Odd parity over RXDATA[15:0]. Utopia 2 Receive Start of Cell. Asserted coincident with the first word of data for each cell on RXDATA. Utopia 2 Transmit Address Bus. This bus is used in polling and selecting the transmit port. The port addresses are defined in bits [4:0] of the Enhanced Control Registers. Utopia 2 Transmit Cell Available. Indicates the availability of room in the transmit FIFO of the addressed port for a full cell. When none of the three ports is addressed, TXCLAV is high impedance.
RXCLAV
54
Out
RXCLK RXDATA[15:0]
RXEN
RXPARITY RXSOC TXADDR[4:0]
46 59, 60, 61, 62, 63, 64, 65, 66, 69, 70, 71, 72, 73, 74, 75, 76 47 58 55 36, 37, 39, 40, 41
In Out
In Out Out In
TXCLAV
42
Out
4
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
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TABLE 1. SIGNAL DESCRIPTIONS (continued)
SIGNAL NAME
TXCLK TXDATA[15:0]
PIN NUMBER
43 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17 34 33
I/O
In In
SIGNAL DESCRIPTION
Utopia 2 Transmit Clock. This is a free running clock input. Utopia 2 Transmit Data. An ATM device transfers cells across this bus to the 77V1253 for transmission. Also see TXPARITY.
TXEN
TXPARITY
In In
TXSOC
35
In
Utopia 2 Transmit Enable. Driven by an ATM device to indicate it is transmitting data across the TXDATA bus. Utopia 2 Transmit Data Parity. Odd parity across TXDATA[15:0]. Parity is checked and errors are indicated in the Interrupt Status Registers, as enabled in the Master Control Registers. No other action is taken in the event of an error. Tie high or low if unused. Utopia 2 Transmit Start of Cell. Asserted coincident with the first word of data for each cell on TXDATA.
8-BIT UTOPIA LEVEL 1 SIGNALS (MODE[1:0] = 01) SIGNAL NAME
RXCLAV[2:0]
PIN NUMBER
65, 66, 54
I/O
Out
SIGNAL DESCRIPTION
Utopia 1 Receive Cell Available. Indicates the cell available status of the respective port. It is asserted when a full cell is available for retrieval from the receive FIFO. Utopia 1 Receive Clock. This is a free running clock input. Utopia 1 Receive Data. When one of the three ports is selected, the 77V1253 transfers received cells to an ATM device across this bus. Bit 5 in the Diagnostic Control Registers determines whether RXDATA tri-states when RXEN[2:0] are high. Also see RXPARITY. Utopia 1 Receive Enable. Driven by an ATM device to indicate its ability to receive data across the RXDATA bus. One for each port. Utopia 1 Receive Data Parity. Odd parity over RXDATA[7:0]. Utopia 1 Receive Start of Cell. Asserted coincident with the first word of data for each cell on RXDATA. Tri-statable as determined by bit 5 in the Diagnostic Control Registers. Utopia 1 Transmit Cell Available. Indicates the availability of room in the transmit FIFO of the respective port for a full cell. Utopia 1 Transmit Clock. This is a free running clock input. Utopia 1 Transmit Data. An ATM device transfers cells across this bus to the 77V1253 for transmission. Also see TXPARITY. Utopia 1 Transmit Enable. Driven by an ATM device to indicate it is transmitting data across the TXDATA bus. One for each port. Utopia 1 Transmit Data Parity. Odd parity across TXDATA[7:0]. Parity is checked and errors are indicated in the Interrupt Status Registers, as enabled in the Master Control Registers. No other action is taken in the event of an error. Tie high or low if unused. Utopia 1 Transmit Start of Cell. Asserted coincident with the first word of data for each cell on TXDATA.
RXCLK RXDATA[7:0]
46 69, 70, 71, 72, 73, 74, 75, 76
In Out
RXEN[2:0]
RXPARITY RXSOC
49, 48, 47 58 55
In Out Out
TXCLAV[2:0] TXCLK TXDATA[7:0]
40, 41, 42 43 24, 23, 22, 21, 20, 19, 18, 17 26, 25, 34 33
Out In In In In
TXEN[2:0]
TXPARITY
TXSOC
35
In
DPI MODE SIGNALS (MODE[1:0] = 10) SIGNAL NAME
DPICLK Pn_RCLK
PIN NUMBER
43 51, 49, 48
I/O
In In
SIGNAL DESCRIPTION
DPI Source Clock for Transmit. This is the free-running clock used as the source to generate Pn_TCLK. DPI Port 'n' Receive CLock. Pn_RCLK is cycled to indicate that the interfacing device is ready to receive a nibble of data on Pn_RD[3:0] of port 'n'. DPI Port 'n' Receive Data. Cells received on port 'n' are passed to the interfacing device across this bus. Each port has its own dedicated bus.
Pn_RD[3:0]
63, 64, 65, 66, 69, 70, 71, 72, 73, 74, 75, 76
Out
5
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
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TABLE 1. SIGNAL DESCRIPTIONS (continued)
SIGNAL NAME
Pn_RFRM Pn_TCLK
PIN NUMBER
58, 54, 55 39, 40, 41
I/O
Out Out
SIGNAL DESCRIPTION
DPI Port 'n' Receive Frame. Pn_RFRM is asserted for one cycle immediately preceding the transfer of each cell on Pn_RD[3:0]. DPI Port 'n' Transmit Clock. Pn_TCLK is derived from DPICLK, and is cycled when the respective port is ready to accept another 4 bits of data on Pn_TD[3:0]. DPI Port 'n' Transmit Data. Cells are passed across this bus to the PHY for transmission on port 'n'. Each port has its own dedicated bus. DPI Port 'n' Transmit Frame. Start of cell signal which is asserted for one cycle immediately preceding the first 4 bits of each cell on Pn_TD[3:0].
Pn_TD[3:0]
Pn_TFRM
28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17 36, 33, 34, 35
In
In
TABLE 2. SIGNAL ASSIGNMENT AS A FUNCTION OF PHY/ATM INTERFACE MODE
SIGNAL NAME VDD GND TX0TX0+ VDD MM MODE1 MODE0 PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 16-BIT UTOPIA 2 MODE[1,0] = 00 8-BIT UTOPIA 1 MODE[1,0] = 01 DPI MODE[1,0] = 10
RXREF TXREF
GND DNC TXLED2 TXLED1 TXLED0 VDD TXDATA0 TXDATA1 TXDATA2 TXDATA3 TXDATA4 TXDATA5 TXDATA6 TXDATA7 TXDATA8 TXDATA9 TXDATA10 TXDATA11 TXDATA12
TXDATA0 TXDATA1 TXDATA2 TXDATA3 TXDATA4 TXDATA5 TXDATA6 TXDATA7 TXDATA8 TXDATA9 TXDATA10 TXDATA11 TXDATA12
TXDATA0 TXDATA1 TXDATA2 TXDATA3 TXDATA4 TXDATA5 TXDATA6 TXDATA7
TXEN[1] TXEN[2]
see note 2 see note 2 see note 2
P0_TD[0] P0_TD[1] P0_TD[2] P0_TD[3] P1_TD[0] P1_TD[1] P1_TD[2] P1_TD[3] P2_TD[0] P2_TD[1] P2_TD[2] P2_TD[3] see note 2
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TABLE 2. SIGNAL ASSIGNMENT AS A FUNCTION OF PHY/ATM INTERFACE MODE (cont.)
SIGNAL NAME TXDATA13 TXDATA14 TXDATA15 TXPARITY PIN MUMBER 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 16-BIT UTOPIA 2 TXDATA13 TXDATA14 TXDATA15 TXPARITY 8-BIT UTOPIA 1 see note 2 see note 2 see note 2 TXPARITY DPI see note 2 see note 2 see note 2 P2_TFRM P1_TFRM P0_TFRM see note 2 see note 2 P2_TCLK P1_TCLK P0_TCLK see note 1 DPICLK
TXEN
TXSOC TXADDR4 TXADDR3 VDD TXADDR2 TXADDR1 TXADDR0 TXCLAV TXCLK GND VDD RXCLK
TXEN
TXSOC TXADDR4 TXADDR3 TXADDR2 TXADDR1 TXADDR0 TXCLAV TXCLK
TXEN[0]
TXSOC see note 2 see note 2 see note 1 TXCLAV[2] TXCLAV[1] TXCLAV[0] TXCLK
RXCLK
RXCLK
RXEN
RXADDR0 RXADDR1 GND RXADDR2 RXADDR3 RXADDR4 RXCLAV RXSOC GND VDD RXPARITY RXDATA15 RXDATA14 RXDATA13 RXDATA12 RXDATA11 RXDATA10 RXDATA9 RXDATA8 GND VDD RXDATA7 RXDATA6 RXDATA5 RXDATA4 RXDATA3 RXDATA2 RXDATA1
RXEN
RXADDR0 RXADDR1 RXADDR2 RXADDR3 RXADDR4 RXCLAV RXSOC
RXEN[0] RXEN[1] RXEN[2]
see note 2 see note 2 see note 2 RXCLAV[0] RXSOC
see note 2 see note 2 P0_RCLK P1_RCLK P2_RCLK see note 2 see note 2 P1_RFRM P0_RFRM
RXPARITY RXDATA15 RXDATA14 RXDATA13 RXDATA12 RXDATA11 RXDATA10 RXDATA9 RXDATA8
RXPARITY see note 1 see note 1 see note 1 see note 1 see note 1 see note 1 RXCLAV[2] RXCLAV[1]
P2_RFRM see note 1 see note 1 see note 1 see note 1 P2_RD[3] P2_RD[2] P2_RD[1] P2_RD[0]
RXDATA7 RXDATA6 RXDATA5 RXDATA4 RXDATA3 RXDATA2 RXDATA1
RXDATA7 RXDATA6 RXDATA5 RXDATA4 RXDATA3 RXDATA2 RXDATA1
P1_RD[3] P1_RD[2] P1_RD[1] P1_RD[0] P0_RD[3] P0_RD[2] P0_RD[1]
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TABLE 2. SIGNAL ASSIGNMENT AS A FUNCTION OF PHY/ATM INTERFACE MODE (cont.)
SIGNAL NAME RXDATA0 GND VDD RXLED0 RXLED1 RXLED2 DNC GND VDD PIN MUMBER 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 16-BIT UTOPIA 2 RXDATA0 8-BIT UTOPIA 1 RXDATA0 DPI P0_RD[0]
INT
GND
RST WR RD CS
ALE VDD AD0 AD0 AD0 AD0 GND AD0 AD0 AD0 AD0 SE DA VDD DNC DNC GND VDD TX2TX2+ GND AGND AVDD MA MB AVDD AGND AGND AVDD RX2RX2+
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TABLE 2. SIGNAL ASSIGNMENT AS A FUNCTION OF PHY/ATM INTERFACE MODE (cont.)
SIGNAL NAME AVDD AGND AGND AVDD OSC AGND AVDD AGND AGND AVDD RX1RX1+ AVDD AGND AGND AVDD RX0RX0+ AVDD AGND GND TX1TX1+ PIN MUMBER 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 16-BIT UTOPIA 2 8-BIT UTOPIA 1 DPI
NOTES: 1. This output signal is unused in this mode. It must be left unconnected. 2. This input signal is unused in this mode. It must be connected to either logic high or logic low.
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77V1253 OVERVIEW
The 77V1253 is a three-port implementation of the physical layer standard for 25.6Mbps ATM network communications as defined by ATM Forum document af-phy-040.000 and ITUT I.432.5. The physical layer is divided into a Physical Media Dependent sub layer (PMD) and Transmission Convergence (TC) sub layer. The PMD sub layer includes the functions for the transmitter, receiver and clock recovery for operation across 100 meters of category 3 unshielded twisted pair (UTP) cable. This is referred to as the Line Side Interface. The TC sub layer defines the line coding, scrambling, data framing and synchronization. On the other side, the 77V1253 interfaces to an ATM layer device (such as a switch core or SAR). This cell level interface is configurable as either 8-bit Utopia Level 1 Multi-PHY, 16-bit Utopia Level 2, or as three 4-bit DPI interfaces, as determined by two MODE pins. This is referred to as the PHY-ATM Interface. The pinout and front page block diagram are based on the Utopia 2 configuration. Table 2 shows the corresponding pin functions for the other two modes, and Figures 2 and 3 show functional block diagrams. The 77V1253 is based on the 77105, and maintains significant register compatibility with it. The 77V1253, however, has
additional register features, and also duplicates most of its registers to provide significant independence between the three ports. Access to these status and control registers is through the utility bus. This is an 8-bit muxed address and data bus, controlled by a conventional asynchronous read/write handshake. Additional pins permit insertion and extraction of an 8 kHz timing marker, and provide LED indication of receive and transmit status. OPERATION AT 51.2 Mbps In addition to operation at the standard rate of 25.6 Mbps, the 77V1253 is also specified to operate at 51.2 Mbps. Except for the doubled bit rate, all other aspects of operation are identical to the 25.6 Mbps mode. The data rate is determined by the frequency of the clock applied to the OSC input. OSC is 32 MHz for the 25.6 Mbps line rate, and 64 MHz for the 51.2 Mbps line rate. All ports operate at the same frequency. See page 30 for recommended line magnetics. Magnetics for 51.2 Mbps operation have a higher bandwidth than magnetics optimized for 25.6 Mbps.
TxCLK TxDATA[7:0] TxParity TxSOC [2:0] TxCLAV[2:0] Mode[1:0] UTOPIA Multi-PHY Interface
Driver Tx/Rx ATM Cell FIFO Scrambler/ Descrambler 5B/4B Encoding/ Decoding P/S and S/P NRZI Clock/Data Recovery
+ Tx Port 0 - + Rx Port 0 -
RxCLK RxDATA[7:0] RxParity RxSOC [2:0] RxCLAV[2:0]
Driver Tx/Rx ATM Cell FIFO Scrambler/ Descrambler 5B/4B Encoding/ Decoding P/S and S/P NRZI Clock/Data Recovery
+ Tx Port 1 - + Rx Port 1 -
Microprocessor (Utility Bus) Interface AD[7:0] ALE
Driver Tx/Rx ATM Cell FIFO Scrambler/ Descrambler 5B/4B Encoding/ Decoding P/S and S/P NRZI Clock/Data Recovery
+ - Tx Port 2 + - Rx Port 2
OSC
3
3
RxLED[2:0] TxLED[2:0]
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Figure 2. Block Diagram for Utopia Level 1 configuration (MODE[1:0] = 01)
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IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
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DPICLK Mode[1:0] P0_TCLK P0_TFRM P0_TD[3:0] P0_RCLK P0_RFRM P0_RD[3:0]
Tx/Rx ATM Cell FIFO
Scrambler/ Descrambler
5B/4B Encoding/ Decoding
Driver P/S and S/P NRZI Clock/Data Recovery
+ Tx Port 0 - + Rx Port 0 -
P1_TCLK P1_TFRM P1_TD[3:0] P1_RCLK P1_RFRM P1_RD[3:0]
DPI Multi-PHY Interface
Tx/Rx ATM Cell FIFO
Scrambler/ Descrambler
5B/4B Encoding/ Decoding
Driver P/S and S/P NRZI Clock/Data Recovery
+ Tx Port 1 - + Rx Port 1 -
P2_TCLK P2_TFRM P2_TD[3:0] P2_RCLK P2_RFRM P2_RD[3:0]
Tx/Rx ATM Cell FIFO
Scrambler/ Descrambler
5B/4B Encoding/ Decoding
Driver P/S and S/P NRZI Clock/Data Recovery
+ - Tx Port 2 + - Rx Port 2
3
3
Microprocessor (Utility Bus) Interface AD[7:0] ALE OSC RxLED[2:0] TxLED[2:0]
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Figure 3. Block Diagram for DPI configuration (MODE[1:0] = 10)
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IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
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FUNCTIONAL DESCRIPTION
TRANSMISSION CONVERGENCE (TC) SUB LAYER Introduction The TC sub layer defines the line coding, scrambling, data framing and synchronization. Under control of a switch interface or Segmentation and Reassembly (SAR) unit, the 25.6Mbps ATM PHY accepts a 53-byte ATM cell, scrambles the data, appends a command byte to the beginning of the cell, and encodes the entire 53 bytes before transmission. These data transformations ensure that the signal is evenly distributed across the frequency spectrum. In addition, the serialized bit stream is NRZI coded. An 8 kHz timing sync pulse may be used for isochronous communications. Data Structure and Framing Each 53-byte ATM cell is preceded with a command byte. This byte is distinguished by an escape symbol followed by one of 17 encoded symbols. Together, this byte forms one of seventeen possible command bytes. Three command bytes are defined: 1. X_X (read: 'escape' symbol followed by another 'escape'): Start-of-cell with scrambler/descrambler reset.
2. X_4 ('escape' followed by '4'): Start-of-cell without scrambler/descrambler reset. 3. X_8 ('escape' followed by '8'): 8kHz timing marker. This command byte is generated when the 8kHz sync pulse is detected, and has priority over all line activity (data or command bytes). It is transmitted immediately when the sync pulse is detected. When this occurs during a cell transmission, the data transfer is temporarily interrupted on an octet boundary, and the X_8 command byte is inserted. This condition is the only allowed interrupt in an otherwise contiguous transfer. Below is an illustration of the cell structure and command byte usage: {X_X} {53-byte ATM cell} {X_4} {53-byte ATM {X_8} cell} ... In the above example, the first ATM cell is preceded by the X_X start-of-cell command byte which resets both the transmitter-scrambler and receiver-descrambler pseudo-random nibble generators (PRNG) to their initial states. The following cell illustrates the insertion of a start-of-cell command without scrambler/descrambler reset. During this cell's transmission, an 8kHz timing sync pulse triggers insertion of the X_8 8kHz timing marker command byte.
FUNCTIONAL BLOCK DIAGRAM (Continued)
Start of Cell (8kHz) 3 Cells 4 Scrambler 4 Command Byte Insertion
UTOPIA or DPI Interface
PHY-ATM Interface Control, HEC Gen. & Insertion
4 Scramble Nibble PRNG
4
Next 4b/5b Encoding
1
32MHz Clock Input
NRZI Encoding
Tx + Tx 3505 drw 05
Figure 4. TC Transmit Block Diagram
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IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Transmission Description Refer to Figure 4 on the previous page. Cell transmission begins with the PHY-ATM Interface. An ATM layer device transfers a cell into the 77V1253 across the Utopia or DPI transmit bus. This cell enters a 3-cell deep transmit FIFO. Once a complete cell is in the FIFO, transmission begins by passing the cell, four bits (MSB first) at a time to the 'Scrambler'. The 'Scrambler' takes each nibble of data and exclusiveORs them against the 4 high order bits (X(t), X(t-1), X(t-2), X(t3)) of a 10 bit pseudo-random nibble generator (PRNG). Its function is to provide the appropriate frequency distribution for the signal across the line. The PRNG is clocked every time a nibble is processed, regardless of whether the processed nibble is part of a data or command byte. Note however that only data nibbles are scrambled. The entire command byte (X _C) is NOT scrambled before it's encoded (see diagram for illustration). The PRNG is based upon the following polynomial: X
10
Data 0000 0100 1000 1100 Data 0010 0110 1010 1110
Symbol 10101 00111 10010 10111 Symbol 01010 01110 11010 11110
Data 0001 0101 1001 1101 Data 0011 0111 1011 1111
Symbol 01001 01101 11001 11101 Symbol 01011 01111 11011 11111
3217 tbl 01
ESC(X) = 00010
+X +1
7
With this polynomial, the four output data bits (D3, D2, D1, D0) will be generated from the following equations: D3 = d3 xor X(t-3) D2 = d2 xor X(t-2) D1 = d1 xor X(t-1) D0 = d0 xor X(t) The following nibble is scrambled with X(t+4), X(t+3), X(t+2), and X(t+1). A scrambler lock between the transmitter and receiver occurs each time an X_X command is sent. An X_X command is initiated only at the beginning of a cell transfer after the PRNG has cycled through all of its states (210 - 1 = 1023 states). The first valid ATM data cell transmitted after power on will also be accompanied with an X_X command byte. Each time an X_X command byte is sent, the first nibble after the last escape (X) nibble is XOR'd with 1111b (PRNG = 3FFx). Because a timing marker command (X_8) may occur at any time, the possibility of a reset PRNG start-of-cell command and a timing marker command occurring consecutively does exist (e.g. X_X_X_8). In this case, the detection of the last two consecutive escape (X) nibbles will cause the PRNG to reset to its initial 3FFx state. Therefore, the PRNG is clocked only after the first nibble of the second consecutive escape pair. Once the data nibbles have been scrambled using the PRNG, the nibbles are further encoded using a 4b/5b process. The 4b/5b scheme ensures that an appropriate number of signal transitions occur on the line. A total of seventeen 5-bit symbols are used to represent the sixteen 4-bit data nibbles and the one escape (X) nibble. The table below lists the 4-bit data with their corresponding 5-bit symbols:
This encode/decode implementation has several very desirable properties. Among them is the fact that the output data bits can be represented by a set of relatively simple symbols; * Run length is limited to <= 5; * Disparity never exceeds +/- 1. On the receiver, the decoder determines from the received symbols whether a timing marker command (X_8) or a startof-cell command was sent (X_X or X_4). If a start-of-cell command is detected, the next 53 bytes received are decoded and forwarded to the descrambler. (See TC Receive Block Diagram, Figure 4). The output of the 4b/5b encoder provides serial data to the NRZI encoder. The NRZI code transitions the wire voltage each time a '1' bit is sent. This, together with the previous encoding schemes guarantees that long run lengths of either '0' or '1's are prevented. Each symbol is shifted out with its most significant bit sent first. When no cells are available to transmit, the 77V1253 keeps the line active by continuing to transmit valid symbols. But it does not transmit another start-of-cell command until it has another cell for transmission. The 77V1253 never generates idle cells. Transmit HEC Byte Calculation/Insertion Byte #5 of each ATM cell, the HEC (Header Error Control) is calculated automatically across the first 4 bytes of the cell header, depending upon the setting of bit 5 of registers 0x03, 0x13 and 0x23. This byte is then either inserted as a replacement of the fifth byte transferred to the PHY by the external system, or the cell is transmitted as received. A third operating mode provides for insertion of "Bad" HEC codes which may aid in communication diagnostics. These modes are controlled by the LED Driver and HEC Status/Control Registers.
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IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
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Receiver Description The receiver side of the TC sublayer operates like the transmitter, but in reverse. The data is NRZI decoded before each symbol is reassembled. The symbols are then sent to the 5b/4b decoder, followed by the Command Byte Interpreter, De-Scrambler, and finally through a FIFO to the UTOPIA or DPI interface to an ATM Layer device. Note that although the IDT77V1253 can detect symbol and HEC errors, it does not attempt to correct them. Upon reset or the re-connect, each port's receiver is typically not symbol-synchronized. When not symbol-synchro-
nized, the receiver will indicate a significant number of bad symbols, and will deassert the Good Signal Bit as described below. Synchronization is established immediately once that port receives an Escape symbol, usually as part of the startof-cell command byte preceding the first received cell. The IDT77V1253 monitors line conditions and can provide an interrupt if the line is deemed 'bad'. The Interrupt Status Registers (registers 0x01, 0x11 and 0x21) contain a Good Signal Bit (bit 6, set to 0 = Bad signal initially) which shows the status of the line per the following algorithm: To declare 'Good Signal' (from "Bad" to "Good"): There is an up-down counter that counts from 7 to 0 and is initially set to 7. When the clock ticks for 1,024 cycles (32MHz clock, 1,024 cycles = 204.8 symbols) and no "bad symbol" has been received, the counter decreases by one. However, if at least one "bad symbol" is detected during these 1,024 clocks, the counter is increased by one, to a maximum of 7. The Good Signal Bit is set to 1 when this counter reaches 0. The Good Signal Bit could be set to 1 as quickly as 1,433 symbols (204.8 x 7) if no bad symbols have been received.
ATM CELL FORMAT
Bit 7 Bit 0 Bit 7 UDF Payload Byte 1 Payload Byte 48 Bit 0 Header Byte 1 Header Byte 2 Header Byte 3 Header Byte 4
UDF = User Defined Field (or HEC)
FUNCTIONAL BLOCK DIAGRAM (Continued)
PRNG Reset Scramble Nibble 4 Next Command Byte Detection, Removal, & Decode
Rx + Rx
NRZI Decoding
5
5b/4b Decoding
4
4
DeScrambler
Start of Cell 4
3 Cells 32.0MHz Clock Synthesizer & PLL
PHY-ATM Interface Control RECV
UTOPIA or DPI Interface
OSC
3505 drw 06
Figure 5. TC Receive Block Diagram
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IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
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To declare 'Bad Signal' (from "Good" to "Bad"): The same up-down counter counts from 0 to 7 (being at 0 to provide a "Good" status). When the clock ticks for 1,024 cycles (32MHz clock, 1,024 cycles = 204.8 symbols) and there is at least one "bad symbol", the counter increases by one. If it detects all "good symbols" and no "bad symbols" in the next time period, the counter decreases by one. The "Bad Signal" is declared when the counter reaches 7. The Good Signal Bit could be set to 0 as quickly as 1,433 symbols (204.8 x 7) if at least one "bad symbol" is detected in each of seven consecutive groups of 204.8 symbols.
8kHz Timing Marker The 8kHz timing marker, described earlier, is a completely optional feature which is essential for some applications requiring synchronization for voice or video, and unnecessary for other applications. Figure 6 shows the options available for generating and receiving the 8kHz timing marker. The source of the marker is programmable in the RXREF and TXREF Control Register (0x40). Each port is individually programmable to either a local source or a looped remote source. The local source is TXREF, which is an 8kHz clock of virtually any duty cycle. When unused, TXREF should be tied high. Also note that it is not limited to 8kHz, should a different frequency be desired. When looped, a received X_8 command byte causes one to be generated on the transmit side. A received X_8 command byte causes the 77V1253 to issue a negative pulse on RXREF. The source channel of the marker is programmable.
Input
LTSel#0 ( Reg 40, Bit 0) RxRef#0 (X_8 received)
Mux
TxRef#0 (X_8 generator) LTSel#1 ( Reg 40, Bit 1)
RxRef#1 (X_8 received)
Mux
TxRef#1 (X_8 generator) LTSel#2 ( Reg 40, Bit 2)
RxRef#2 (X_8 received)
Mux
TxRef#2 (X_8 generator)
RxRefSel[1:0]
RxRef Select Decoder
IDT77V1253
Output
4781 drw 07
Figure 6.
RXREF and TXREF Block Diagram
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IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PHY-ATM INTERFACE
The 77V1253 PHY offers three choices in interfacing to ATM layer devices such as segmentation and reassembly (SAR) and switching chips. MODE[1:0] are used to select the configuration of this interface, as shown in the table below. MODE[1:0] 00 01 10 PHY-ATM Interface configuration one 16-bit UTOPIA Level 2 port one 8-bit UTOPIA Level 1 (Multi-PHY)port three 4-bit Data Path Interface (DPI) ports
RXCLK
ATM to PHY
UTOPIA is a Physical Layer to ATM Layer interface standardized by the ATM Forum. It has separate transmit and receive channels and specific handshaking protocols. UTOPIA Level 2 has dedicated address signals for both the transmit and receive directions that allow the ATM layer device to specify with which of the four PHY channels it is communicating. UTOPIA Level 1 does not have address signals. Instead, key handshaking signals are duplicated so that each channel has its own signals. In both versions of UTOPIA, all channels share a single transmit data bus and a single receive data bus for data transfer. DPI is a low-pincount Physical Layer to ATM Layer interface. The low-pincount characteristic allows the 77V1253 to incorporate three separate DPI 4-bit ports, one for each of the three serial ports. As with the UTOPIA interfaces, the transmit and receive directions have their own data paths and handshaking. UTOPIA LEVEL 2 INTERFACE OPTION The 16-bit Utopia Level 2 interface operates as defined in ATM Forum document af-phy-0039. This PHY-ATM interface is selected by setting the MODE[1:0] pins both low. This mode is configured as a single 16-bit data bus in the transmit (ATM-to-PHY) direction, and a single 16-bit data bus in the receive (PHY-to-ATM) direction. In addition to the data bus, each direction also includes a single optional parity bit, an address bus, and several handshaking signals. The UTOPIA address of each channel is determined by bits 4 to 0 in the Enhanced Control Registers. Please note that the transmit bus and the receive bus operate completely independently. The Utopia 2 signals are summarized below: TXDATA[15:0] TXPARITY TXSOC TXADDR[4:0] ATM to PHY ATM to PHY ATM to PHY ATM to PHY ATM to PHY PHY to ATM ATM to PHY PHY to ATM PHY to ATM PHY to ATM ATM to PHY ATM to PHY PHY to ATM
The ATM device starts by polling the PHY ports on the Utopia 2 bus to determine if any of them has room to accept a cell for transmission (TXCLAV), or has a receive cell available to pass on to the ATM device (RXCLAV). To poll, the ATM device drives an address (TXADDR or RXADDR) then observes TXCLAV or RXCLAV on the next cycle of TXCLK or RXCLK. A port must tri-state TXCLAV and RXCLAV except when it is addressed. If TXCLAV or RXCLAV is asserted, the ATM device may select that port, then transfer a cell to or from it. Selection of a port is performed by driving the address of the desired port while TXEN or RXEN is high, then driving TXEN or RXEN low. When TXEN is driven low, TXSOC (start of cell) is driven high to indicate that the first 16 bits of the cell are being driven on TXDATA. The ATM device may chose to temporarily suspend transfer of the cell by deasserting TXEN. Otherwise, TXEN remains asserted as the next 16 bits are driven onto TXDATA with each cycle of TXCLK. In the receive direction, the ATM device selects a port if it wished to receive the cell that the port is holding. It does this by asserting RXEN. The PHY then transfers the data 16 bits each clock cycle, as determined by RXEN. As in the transmit direction, the ATM device may suspend transfer by deasserting RXEN at any time. Note that the PHY asserts RXSOC coincident with the first 16 bits of each cell. TXPARITY and RXPARITY are parity bits for the corresponding 16-bit data fields. Odd parity is used. Figures 8 through 13 may be referenced for Utopia 2 bus examples. Because this interface transfers an even number of bytes, rather than the ATM standard of 53 bytes, a filler byte is inserted between the 5-byte header and the 48-byte payload. This is shown in Figure 7.
Bit 15 First Header byte 1 Header byte 3 Header byte 5 Payload byte 1 Payload byte 3 Payload byte 5
Bit 0 Header byte 2 Header byte 4 stuff byte Payload byte 2 Payload byte 4 Payload byte 6
TXEN
TXCLAV TXCLK RXDATA[15:0] RXPARITY RXSOC RXADDR[4:0]
Payload byte 45 Last Payload byte 47
Payload byte 46 Payload byte 48
3505 drw 08
RXEN
Figure 7. Utopia Level 2 Data Format and Sequence
RXCLAV
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IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
polling:
polling
selection
polling
TxCLK
TxADDR[4:0]
1F
N+3
1F
N+2
1F
N+3
1F
N
1F
TxCLAV
N+1
High-Z
N+3
N+2
N+3
N
TxData[15:0], TxPARITY TxSOC
P39, 40
P41, 42
P43, 44
P45, 46
P47, 48
H1, 2
H3, 4
H5, undefined
P1, 2
cell transmission to:
PHY N
PHY N+3
3505 drw 09
Figure 8. Utopia 2 Transmit Handshake - Back to Back Cells
polling:
polling
selection
polling
TxCLK
TxADDR[4:0]
1F
N+3
1F
N+2
1F
N+3
1F
N
1F
TxCLAV
N+1
High-Z
N+3
N+2
N+3
N
TxData[15:0], TxPARITY TxSOC
P43, 44
P45, 46
P47, 48
H1, 2
H3, 4
H5, undefined
P1, 2
cell transmission to:
PHY N
PHY N+3
3505 drw 10
Figure 9. Utopia 2 Transmit Handshake - Delay Between Cells
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IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
polling:
polling
selection
polling
TxCLK
TxADDR[4:0]
1F
N+3
1F
N+2
1F
M
1F
N
1F
TxCLAV
N+1
High-Z
N+3
N+2
M
N
TxData[15:0], TxPARITY TxSOC
P25, 26
P27, 28
P29, 30
High-Z
P31, 32
P33, 34
P35, 36
High-Z
cell transmission to:
PHY M
PHY M
3505 drw 11
Figure 10. Utopia 2 Transmit Handshake - Transmission Suspended
polling:
polling
selection
polling
RxCLK
RxADDR[4:0]
N+3
1F
N+2
1F
N+3
1F
N
1F
N+1
1F
RxCLAV
N+3
N+2
High-Z
N+3
N
RxData[15:0], RxPARITY RxSOC
P39, 40
P41, 42
P43, 44
P45, 46
P47, 48
High-Z
H1, 2
H3, 4
H5, undefined
P1, 2
High-Z
cell transmission to:
PHY N
PHY N+3
3505 drw 12
Figure 11. Utopia 2 Receive Handshake - Back to Back Cells
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IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
polling:
polling
selection
polling
RxCLK
RxADDR[4:0]
N+3
1F
N+2
1F
N+1
1F
N+1
1F
N
1F
RxCLAV
N+3
High-Z
N+2
N+1
N+1
RxData[15:0], RxPARITY RxSOC
P45, 46
P47, 48
undefined
High-Z
H1, 2
H3, 4
High-Z
cell transmission to:
PHY N+3
PHY N+1
3505 drw 13
Figure 12. Utopia 2 Receive Handshake - Delay Between Cells
polling:
polling
re-selection
polling
RxCLK
RxADDR[4:0]
N+3
1F
N+2
1F
M
1F
N+1
1F
N+2
RxCLAV
N+3
High-Z
N+2
M
N+1
RxData[15:0], RxPARITY RxSOC
P25, 26
P27, 28
P29, 30
High-Z
P31, 32
P33, 34
P35, 36
High-Z
cell transmission from:
PHY M
PHY M
3505 drw 14
Figure 13. Utopia 2 Receive Handshake - Suspended Transfer of Data
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IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
UTOPIA LEVEL 1 MULTI-PHY INTERFACE OPTION The UTOPIA Level 1 MULTI-PHY interface operates as defined in ATM Forum document af-phy-0017 and clarified in af-phy-0039. Utopia Level 1 is essentially the same as Utopia Level 2, but without the addressing, polling and selection features. Instead of addressing, it utilizes separate TxCLAV, TxEN, RxCLAV and RxEN signals for each channel of the 77V1254. There are just one each of the TxSOC and RxSOC signals, which are shared across all three channels. In addition to Utopia Level 2's cell mode transfer protocol, Utopia Level 1 also offers the option of a byte mode protocol. Bit 1 of the Master Control Registers is used to program whether the UTOPIA Level 1 bus is in cell mode or byte mode. In byte mode, the PHY is allowed to control data transfer on a byte-by-byte basis via the TXCLAV and RXCLAV signals. In cell mode, TXCLAV and RXCLAV are ignored once the transfer of a cell has begun. In every other way the two modes are identical. Cell mode is the default configuration and is the one described later. The Utopia 1 signals are summarized below: TXDATA[7:0] TXPARITY TXSOC ATM to PHY ATM to PHY ATM to PHY ATM to PHY PHY to ATM ATM to PHY PHY to ATM PHY to ATM PHY to ATM ATM to PHY PHY to ATM ATM to PHY
Bit 7 First
Bit 0
Header byte 1 Header byte 2 Header byte 3 Header byte 4 Header byte 5 Payload byte 1 Payload byte 2 Payload byte 3
Payload byte 46 Payload byte 47 Last Payload byte 48
3505 drw 15
Figure 14. Utopia 1 Data Format and Sequence transmit FIFO to accept at least one 53-byte ATM cell. When the ATM layer device is ready to begin passing the cell, it asserts TXEN (transmit enable) and TXSOC (start of cell), coincident with the first byte of the cell on TXDATA. TXEN remains asserted for the duration of the cell transfer, but the ATM device may deassert TXEN at any time once the cell transfer has begun, but data is transfered only when TXEN is asserted. In the receive direction, RXEN indicates when the ATM device is prepared to receive data. As with transmit, it may be asserted or deasserted at any time. The PHY asserts RXCLAV to indicate that it has an entire cell to transfer. In both transmit and receive, TXSOC and RXSOC (start of cell) is asserted for one clock, coincident with the first byte of each cell. Odd parity is utilized across each 8-bit data field. Figure 14 shows the data sequence for an ATM cell over Utopia Level 1, and Figures 15 to 21 are examples of the Utopia Level 1 handshake.
TXEN[2:0]
TXCLAV[2:0] TXCLK RXDATA[7:0] RXPARITY RXSOC
RXEN[2:0]
RXCLAV[2:0] RXCLK
Transmit and receive both utilize free running clocks, which are inputs to the 77V1253. All Utopia signals are timed to these clocks. In the transmit direction, the PHY first asserts TXCLAV (transmit cell available) to indicate that it has room in its
TxCLK
TxCLAV[2:0]
[2:0]
TxDATA[7:0], TxPARITY TxSOC
X
H1
H2
P44
P45
P46
P47
P48
X
4781 drw 16
Figure 15. Utopia 1 Transmit Handshake - Single Cell
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IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TxCLK
TxCLAV[2:0]
[2:0]
TxDATA[7:0], TxPARITY TxSOC
P46
P47
P48
H1
H2
H3
H4
X
H5
4781 drw 17
Figure 16. Utopia 1 Transmit Handshake - Back-to-Back Cells, and TXEN Suspended Transmission
TxCLK
TxCLAV[2:0]
[2:0]
TxDATA[7:0], TxPARITY TxSOC
P42
P43
P44
P45
P46
X
X
X
P47
P48
H1
4781 drw 18
Figure 17. Utopia 1 Transmit Handshake - TXEN Suspended Transmission and Back-to-Back Cells (Byte Mode Only)
RxCLK
RxCLAV[2:0]
[2:0]
RxDATA[7:0], RxPARITY RxSOC
P47
P48
High-Z
H1
H2
H3
High-Z
4781 drw 19
Figure 18. Utopia 1 Receive Handshake - Delay Between Cells
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IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RxCLK
RxCLAV[2:0]
[2:0]
RxDATA[7:0], RxPARITY RxSOC
P47
P48
High-Z
H1
P47
P48
X
X
H1
H2
High-Z
4781 drw 20
Figure 19. Utopia 1 Receive Handshake - RXEN and RXCLAV Control
RxCLK
RxCLAV[2:0]
Early RxCLAV option (bit 6=1, registers 0x02, 0x12, 0x22)
[2:0]
RxDATA[7:0], RxPARITY RxSOC
P42
High-Z
P43
P44
P45
P46
P47
P48
X
X
High-Z
High-Z
High-Z
4781 drw 21
Figure 20. Utopia 1 Receive Handshake - RXCLAV Deassertion
RxCLK
RxCLAV[2:0]
[2:0]
RxDATA[7:0], RxPARITY RxSOC
High-Z
H1
H2
X
H3
H4
H5
P1
High-Z
4781 drw 22
Figure 21. Utopia 1 Receive Handshake - RXCLAV Suspended Transfer (Byte Mode Only)
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IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DPI INTERFACE OPTION The DPI interface is relatively new and worth additional description. The biggest difference between the DPI configurations and the UTOPIA configurations is that each channel has its own DPI interface. Each interface has a 4-bit data path, a clock and a start-of-cell signal, for both the transmit direction and the receive direction. Therefore, each signal is point-to-point, and none of these signals has high-Z capability. Additionally, there is one master DPI clock input (DPICLK) into the 77V1253 which is used as a source for the DPI transmit clock outputs. DPI is a cell-based transfer scheme like Utopia Level 2, whereas UTOPIA Level 1 transfers can be either byte- or cell-based. Another unique aspect of DPI is that it is a symmetrical interface. It is as easy to connect two PHYs back-to-back as it is to connect a PHY to a switch fabric chip. In contrast, Utopia is asymmetrical. Note that for the 77V1253, we are using the "transmit" and "receive" nomenclature in the naming of the DPI signals, whereas other devices may use more generic "in" and "out" nomenclature for their DPI signals. The DPI signals are summarized below, where "Pn_" refers to the signals for channel number "n": DPICLK Pn_TCLK Pn_TD[3:0] Pn_TFRM Pn_RCLK Pn_RD[3:0] Pn_RFRM input to PHY PHY to ATM ATM to PHY ATM to PHY ATM to PHY PHY to ATM PHY to ATM
The DPI protocol is exactly symmetrical in the receive direction, with the 77V1253 driving the data and start-of-cell signals while receiving Pn_RCLK as an input. The DPI data interface is four bits, so the 53 bytes of an ATM cell are transferred in 106 cycles. Figure 22 shows the sequence of that data transfer. Figures 23 through 30 show how the handshake operates.
Bit 3 First
Bit 0
Header byte 1, (8:5) Header byte 1, (4:1) Header byte 2, (8:5) Header byte 2, (4:1) Header byte 3, (8:5) Header byte 3, (4:1) Header byte 4, (8:5) Header byte 4, (4:1) Header byte 5, (8:5) Header byte 5, (4:1) Payload byte 1, (8:5) Payload byte 1, (4:1)
In the transmit direction (ATM to PHY), the ATM layer device asserts start-of-cell signal (Pn_TFRM) for one clock cycle, one clock prior to driving the first nibble of the cell on Pn_TD[3:0]. Once the ATM side has begun sending a cell, it is prepared to send the entire cell without interruption. The 77V1253 drives the transmit DPI clocks (Pn_TCLK) back to the ATM device, and can modulate (gap) it to control the flow of data. Specifically, if it cannot accept another nibble, the 77V1253 disables Pn_TCLK and does not generate another rising edge until it has room for the nibble. Pn_TCLK are derived from the DPICLK free running clock source.
Last
Payload byte 47, (8:5) Payload byte 47, (4:1) Payload byte 48, (8:5) Payload byte 48, (4:1)
3505 drw 23
Figure 22. DPI Data Format and Sequence
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IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
P_RCLK (in)
P_RFRM (out)
P_RD(3:0) (out)
X
X
Cell 1 Nibble 0
Cell 1 Nibble 104
Cell 1 Nibble 105
X
X
3505 drw 24
Figure 23. DPI Receive Handshake - One Cell Received
P_RCLK (in)
P_RFRM (out)
P_RD(3:0) (out)
X
X
Cell 1 Nibble 0
Cell 1 Nibble 1
Cell 1
Cell 1 Nibble 104
Cell 1 Nibble 105
Cell 2 Nibble 0
Cell 2 Nibble 1
3505 drw 25
Figure 24. DPI Receive Handshake - Back-to-Back Cells
P_RCLK (in)
P_RFRM (out)
P_RD(3:0) (out)
Cell 1 Nibble 104
Cell 1 Nibble 105
Cell 2 Nibble 0
Cell 2 Nibble 1
Cell 2 Nibble 2
Cell 2 Nibble 3
Cell 2 Nibble 4
3505 drw 26
Figure 25. DPI Receive Handshake - ATM Layer Device Suspends Transfer
24
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ATM Layer Device Not Ready 77V1254 Not Ready
P_RCLK (in)
P_RFRM (out)
P_RD(3:0) (out)
Cell 1 Nibble 104
Cell 1 Nibble 105
X
X
X
X
Cell 2 Nibble 0
Cell 2 Nibble 1
Cell 2 Nibble 2
3505 drw 27
Figure 26. DPI Receive Handshake - Neither Device Ready
P_TCLK (out)
P_TFRM (in)
P_TD(3:0) (in)
X
X
Cell 1 Nibble 0
Cell 1 Nibble 1
Cell 1 Nibble 104
Cell 1 Nibble 105
X
X
3505 drw 28
Figure 27. DPI Transmit Handshake - One Cell for Transmission
P_TCLK (out)
P_TFRM (in)
P_TD(3:0) (in)
X
X
Cell 1 Nibble 0
Cell 1 Nibble 1
Cell 1
Cell 1 Nibble 104
Cell 1 Nibble 105
Cell 2 Nibble 0
Cell 2 Nibble 1
3505 drw 29
Figure 28. DPI Transmit Handshake - Back-to-Back Cells for Transmission
25
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
P_TCLK (out)
P_TFRM (in)
P_TD(3:0) (in)
Cell 1 Nibble 104
Cell 1 Nibble 105
Cell 2 Nibble 0
Cell 2 Nibble 1
Cell 2 Nibble 2
Cell 2 Nibble 3
Cell 2 Nibble 4
3505 drw 30
Figure 29. DPI Transmit Handshake - 77V1254 Transmit FIFO Full
77V1254 Not Ready ATM Layer Device Not Ready
P_TCLK (out)
P_TFRM (in)
P_TD(3:0) (in)
Cell 1 Nibble 104
Cell 1 Nibble 105
X
X
X
X
Cell 2 Nibble 0
Cell 2 Nibble 1
Cell 2 Nibble 2
3505 drw 31
Figure 30. DPI Transmit Handshake - Neither Device Ready
26
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CONTROL AND STATUS INTERFACE
UTILITY BUS The Utility Bus is a byte-wide interface that provides access to the registers within the IDT77V1253. These registers are used to select desired operating characteristics and functions, and to communicate status to external systems. The Utility Bus is implemented using a multiplexed address and data bus (AD[7:0]) where the register address is latched via the Address Latch Enable (ALE) signal. The Utility Bus interface is comprised of the following pins: AD[7:0], ALE, CS, RD, WR Read Operation Refer to the Utility Bus timing waveforms in Figures 42 - 43. A register read is performed as follows: 1. Initial condition: - RD, WR, CS not asserted (logic 1) - ALE not asserted (logic 0) 2. Set up register address: - place desired register address on AD[7:0] - set ALE to logic 1; - latch this address by setting ALE to logic 0. 3. Read register data: - Remove register address data from AD[7:0] - assert CS by setting to logic 0; - assert RD by setting to logic 0 - wait minimum pulse width time (see AC specifications) Write Operation A register write is performed as described below: 1. Initial condition: - RD, WR, CS not asserted (logic 1) - ALE not asserted (logic 0) 2. Set up register address: - place desired register address on AD[7:0] - set ALE to logic 1; - latch this address by setting ALE to logic 0. 3. Write data: - place data on AD[7:0] - assert CS by setting to logic 0; - assert WR (logic 0) for minimum time (according to timing specification); reset WR to logic 1 to complete register write cycle. INTERRUPT OPERATIONS The IDT77V1253 provides a variety of selectable interrupt and signalling conditions which are useful both during `normal' operation, and as diagnostic aids. Refer to the Status and Control Register List section. Overall interrupt control is provided via bit 0 of the Master Control Registers. When this bit is cleared (set to 0), interrupt signalling is prevented on the respective port. The Interrupt Mask Registers allow individual masking of different interrupt sources. Additional interrupt signal control is provided by bit 5 of the Master Control Registers. When this bit is set (=1),
receive cell errors will be flagged via interrupt signalling and all other interrupt conditions are masked. These errors include: - Bad receive HEC - Short (fewer than 53 bytes) cells - Received cell symbol error Normal interrupt operations are performed by setting bit 0 and clearing bit 5 in the Master Control Registers. INT (pin 85) will go to a low state when an interrupt condition is detected. The external system should then interrogate the 77V1253 to determine which one (or more) conditions caused this flag, and reset the interrupt for further occurrences. This is accomplished by reading the Interrupt Status Registers. Decoding the bits in these bytes will tell which error condition caused the interrupt. Reading these registers also: - clears the (sticky) interrupt status bits in the registers that are read - resets INT This leaves the interrupt system ready to signal an alarm for further problems. LED CONTROL AND SIGNALLING The LED outputs provide bi-directional LED drive capability of 8 mA. As an example, the RxLED outputs are described in the truth table:
STATE Cells being received Cells not being received PIN VOLTAGE Low High
As illustrated in the following drawing (Figure 31), this could be connected to provide for a two-LED condition indicator. These could also be different colors to provide simple status indication at a glance. (The minimum value for R should be 330, but a value closer to 1 k is recommended). TxLED Truth Table
STATE Cells being transmitted Cells not being transmitted PIN VOLTAGE Low High
3.3V
R
(Indicates: Cells being received or transmitted) RxLED(2:0) TxLED(2:0) (Indicates: Cells are not being received or transmitted)
3505 drw 32
R
Figure 31.
27
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DIAGNOSTIC FUNCTIONS 1. LOOPBACK There are two loopback modes supported by the 77V1253. The loopback mode is controlled via bits 1 and 0 of the Diagnostic Control Registers: Bit 1 0 1 1 Bit 0 0 0 1 MODE Normal operating mode PHY Loopback Line Loopback
PHY Loopback As Figure 33 illustrates below, this loopback mode provides a connection within the PHY from the transmit PHYATM interface to the PHY-ATM receive interface. Note that while this mode is operating, no data is forwarded to or received from the line interface. Line Loopback Figure 34 might also be called "remote loopback" since it provides for a means to test the overall system, including the line. Since this mode will probably be entered under direction from another system (at a remote location), receive data is also decoded and transferred to the upstream system to allow it to listen for commands. A common example would be a command asking the upstream system to direct the TC to leave this loopback state, and resume normal operations.
Normal Mode This mode, Figure 32, supports normal operating conditions: data to be transmitted is transferred to the TC, where it is queued and formatted for transmission by the PMD. Receive data from the PMD is decoded along with its clock for transfer to the receiving "upstream system".
ATM Layer Device
IDT77V1253 TC sublayer PMD sublayer
Line Interface
4781 drw 33
Figure 32. Normal Mode
IDT77V1253 ATM Layer Device TC sublayer PMD sublayer
Line Interface
4781 drw 34
Figure 33. PHY Loopback
28
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ATM Layer Device
TC sublayer
IDT77V1253
PMD sublayer
Line Interface
4781 drw 35
Figure 34. Line Loopback
2. COUNTERS Several condition counters are provided to assist external systems (e.g. software drivers) in evaluating communications conditions. It is anticipated that these counters will be polled from time to time (user selectable) to evaluate performance. A separate set of registers exists for each channel of the PHY. * Symbol Error Counters - 8 bits - counts all invalid 5-bit symbols received * Transmit Cell Counters - 16 bits - counts all transmitted cells * Receive Cell Counters - 16 bits - counts all received cells, excluding idle cells and HEC errored cells * Receive HEC Error Counters - 5 bits - counts all HEC errors received The TxCell and RxCell counters are sized (16 bits) to provide a full cell count (without roll over) if the counter is read once/second. The Symbol Error counter and HEC Error counter were given sufficient size to indicate exact counts for low error-rate conditions. If these counters overflow, a gross condition is occurring, where additional counter resolution does not provide additional diagnostic benefit. Reading Counters 1. Decide which counter value is desired. Write to the Counter Select Register(s) (0x06, 0x16 and 0x26) to the bit location corresponding to the desired counter. This loads the High and Low Byte Counter Registers with the selected counter's value, and resets this counter to zero.
NOTE: Only one counter may be enabled at any time in each of the Counter Select Registers.
VPI/VCI SWAPPING
For compatibility with IDT's SwitchStar products (77V400 and 77V500), the 77V1253 has the ability to swap parts of the VPI/VCI address space in the header of receive cells. This function is controlled by the VPI/VCI Swap bits, which are bit 5 of the Enhanced Control Registers (0x08, 0x18 and 0x28). The portions of the VPI/VCI that are swapped are shown below. Bits X(7:0) are swapped with Y(7:0) when the VPI/VCI Swap bit is set and the chip is in DPI mode.
7 GFC/VPI VPI VCI VCI HEC PTI VPI VCI
0 Byte 0 Byte 1 Byte 2 CLP Byte 3 Byte 4
7 X7 Y3 X6 Y2 X5 Y1 X4 Y0 X3 Y7 X2 Y6 X1 Y5
0 X0 Y4 Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
3505 drw 51
2. Read the Counter Registers (0x04, 0x14 or 0x24 (low byte)) and (0x05, 0x15 or 0x25 (high byte)) to get the value. Further reads may be accomplished in the same manner by writing to the Counter Select Registers.
29
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
LINE SIDE (SERIAL) INTERFACE
Each of the four ports has two pins for differential serial transmission, and two pins for differential serial receiving. PHY TO MAGNETICS INTERFACE A standard connection to 100 and 120 unshielded twisted pair cabling is shown in Figure 35. Note that the transmit signal is somewhat attenuated in order to meet the launch amplitude specified by the standards. The receive circuitry is designed to attenuate low frequencies in order to
compensate for the high frequency attenuation of the cable. Also, the receive circuitry biases the positive and negative RX inputs to slightly different voltages. This is done so that the receiver does not receive false signals in the absence of a real signal. This can be important because the 77V1253 does not disable error detection or interrupts when an input signal is not present. When connecting to UTP at 51.2 Mbps, it is necessary to use magnetics with sufficient bandwidth. Such a device can also operate satisfactorily at 25.6 Mbps.
AGND R1 1 2 7 8 2 R2 Magnetics C1 16 10 9 14 13 15 12 R9 R8 R4 L1 AVDD R5 3 4 5 1 R3
IDT77V1253 IDT77V1254 TxD+
RJ45 Connector
3 4 5 6 7 8
TxD-
RxD+ R7
RxDC2 R6 AGND AGND
3505 drw 36
Figure 35. Recommended Connection to Magnetics
Table 3 Analog Component Values
Component R1 R2 R3 R4 R5 R6 R7 R8 R9 C1 C2 L1 Value 47 47 620 110 2700 2700 82 33 33 470pF 470pF 3.3H Tolerance 5% 5% 5% 5% 5% 5% 5% 5% 5% 20% 20% 20%
Magnetics Modules for 25.6 Mbps
Pulse PE-67583 or R4005 TDK TLA-6M103 Valor SF1153 (619) 674-8100 (847) 803-6100 (800) 318-2567
Magnetics Modules for 51.2 Mbps
Pulse R4005 (619) 674-8100
30
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
STATUS AND CONTROL REGISTER LIST
The 77V1253 has 28 registers that are accessible through the utility bus. Each of the three ports has 9 registers dedicated to that port. There is only one register (0x40) which is not port specific. For those register bits which control operation of the Utopia interface, the operation of the Utopia interface is determined by the registers corresponding to the port which is selected at that particular time. For consistent operation, the Utopia control bits should be programmed the same for all three ports, except for the Utopia 2 port addresses in the Enhanced Control Registers. Register Address Register Name Master Control Registers Interrupt Status Registers Diagnostic Control Registers LED Driver and HEC Status/Control Low Byte Counter Register [7:0] High Byte Counter Register [15:8] Counter Registers Read Select Interrupt Mask Registers Enhanced Control Registers Port 0 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 Port 1 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 Port 2 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x40 All Ports
RxREF and TxREF Control Register
Nomenclature "Reserved" register bits, if written, should always be written "0" R/W = register may be read and written via the utility bus R-only or W-only = register is read-only or write-only sticky = register bit is cleared after the register containing it is read; all sticky bits are read-only "0" = `cleared' or `not set' "1" = `set'
MASTER CONTROL REGISTERS
Addresses: 0x00, 0x10, 0x20
Bit 7 6 Type R/W R/W Initial State 0 1 = discard errored cells 0 = all interrupts Function Reserved Discard Receive Error Cells On receipt of any cell with an error (e.g. short cell, invalid command mnemonic, receive HEC error (if enabled)), this cell will be discarded and will not enter the receive FIFO. Enable Cell Error Interrupts Only If Bit 0 in this register is set (Interrupts Enabled), setting of this bit enables only "Received Cell Error" (as defined in bit 6) to trigger interrupt line. Transmit Data Parity Check Directs TC to check parity of TxDATA against parity bit located in TxPARITY. Discard Received Idle Cells Directs TC to discard received idle (VPI/VCI = 0) cells from PMD without signaling external systems. Halt Tx Halts transmission of data from TC to PMD and forces both TxD signals low. UTOPIA Level 1 mode select: 0 = cell mode, 1 = byte mode. Not applicable for Utopia 2 or DPI modes. Enable Interrupt Pin (Interrupt Mask Bit) Enables interrupt output pin (pin 85). If cleared, pin is always high and interrupt is masked. If set, an interrupt will be signaled by setting the interrupt pin to "0".
5
R/W
4 3
R/W R/W
0 = disabled 1 = discard idle cells 0 = not halted 0 = cell mode 1 = enable interrupts
2 1 0
R/W R/W R/W
31
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
INTERRUPT STATUS REGISTERS
Addresses: 0x01, 0x11, 0x21
Bit 7 6 R Type Initial State Reserved 0 = Bad Signal Good Signal Bit 1 = Good Signal 0 = Bad Signal See definitions on pages 14 and 15 Function
5 4
sticky sticky
0 0
HEC error cell received
Set when a HEC error is detected on a received cell.
"Short Cell" Received Interrupt signal which flags received cells with fewer than 53 bytes. This condition is detected when receiving Start-of-Cell command bytes with fewer than 53 bytes between them. Transmit Parity Error If Bit 4 of Register 0x00 / 0x10 / 0x20 is set (Transmit Data Parity Check), this interrupt flags a transmit data parity error condition. Odd parity is used. Receive Signal Condition change This interrupt is set when the received `signal' changes either from `bad to good' or from `good to bad'. Received Symbol Error Set when an undefined 5-bit symbol is received. Receive FIFO Overflow Interrupt which indicates when the receive FIFO has filled and cannot accept additional data.
3
sticky
0
2 1 0
sticky sticky sticky
0 0 0
DIAGNOSTIC CONTROL REGISTERS
Addresses: 0x02, 0x12, 0x22
Bit 7 Type R/W Initial State 0=normal Function Force TxCLAV deassert (applicable only in Utopia 1 and 2 modes) Used during line loopback mode to prevent upstream system from continuing to send data to the 77V1253. Not applicable in DPI mode. RxCLAV Operation Select (for Utopia 1 mode) The UTOPIA standard dictates that during cell mode operation, if the receive FIFO no longer has a complete cell available for transfer from PHY, RxCLAV is deasserted following transfer of the last byte out of the PHY to the upsteam system. With this bit set, early deassertion of this signal will occur coincident with the end of Payload byte 44 (as in octet mode for TxCLAV). This provides early indication to the upstream system of this impending condition. 0 = "Standard UTOPIA RxCLAV" 1 = "Cell mode = Byte mode" 5 R/W 1 = tri-state Single/Multi-PHY configuration select (applicable and writable only in Utopia 1 mode) 0 = single: Never tri-state RxDATA, RxPARITY and RxSOC 1 = Multi-PHY mode: Tri-state RxDATA, RxPARITY and RxSOC when RxEN = 1 RFLUSH = Clear Receive FIFO This signal is used to tell the TC to flush (clear) all data in the receive FIFO. The TC signals this completion by clearing this bit. Insert Transmit Payload Error Tells TC to insert cell payload errors in transmitted cells. This can be used to test error detection and recovery systems at destination station, or, under loopback control, at the local receiving station. This payoad error is accomplished by flipping bit 0 of the last cell payload byte. Insert Transmit HEC Error Tells TC to insert HEC error in Byte 5 of cell. This can be used to test error detection and recovery systems in down-stream switches, or, under loopback control, the local receiving station. This HEC error is accomplilshed by flipping bit 0 of the HEC byte. Loopback Control bit# 1 0 0 0 Normal mode (receive from network) 1 0 PHY Loopback 1 1 Line Loopback
6
R/W
0=UTOPIA
4
R/W
0=normal
3
R/W
0=normal
2
R/W
0=normal
1,0
R/W
00=normal
32
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
LED DRIVER AND HEC STATUS/CONTROL REGISTERS
Addresses: 0x03, 0x13, 0x23
Bit 7 6 R/W Type Initial State 0 0 = enable checking Function Reserved Disable Receive HEC Checking (HEC Enable) When not set, the HEC is calculated on first 4 bytes of received cell, and compared against the 5th byte. When set ( = 1), the HEC byte is not checked. Disable Xmit HEC Calculate & Replace When set, the 5th header byte of cells queued for transmit is not replaced with the HEC calculated across the first four bytes of that cell.
5
R/W
0 = enable calculate & replace
4,3
R/W
00 = 1 cycle
RxREF Pulse Width Select
bit # 4 0 0 1 1 3 0 1 0 1
RxREF active for 1 OSC cycle RxREF active for 2 OSC cycles RxREF active for 4 OSC cycles RxREF active for 8 OSC cycles
0=TxFIFO not empty 0=Cell NOT Received 0=Cell NOT Received
2 1 0
R R R
1 = empty 0 0
FIFO Status TxLED Status RxLED Status
1=TxFIFO empty 1=Cell Received 1=Cell Received
LOW BYTE COUNTER REGISTERS [7:0]
Addresses: 0x04, 0x14, 0x24
Bit [7:0] Type R Initial State 0x00 Function Provides low-byte of counter value selected via registers 0x06, 0x16, 0x26 and 0x36.
HIGH BYTE COUNTER REGISTERS [15:8]
Addresses: 0x05, 0x15, 0x25
Bit [7:0] Type R Initial State 0x00 Function Provides high-byte of counter value selected via register 0x06, 0x16, 0x26 and 0x36.
COUNTER SELECT REGISTERS
Addresses: 0x06, 0x16, 0x26
Bit 7 6 5 4 3 2 1 0 Type -- -- -- -- W W W W Initial State -- -- -- -- 0 0 0 0 Function Reserved Reserved Reserved Reserved Symbol Error Counter TxCell Counter RxCell Counter Receive HEC Error Counter
NOTE: Only one bit may set at any time for proper operation
33
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
INTERRUPT MASK REGISTERS
Addresses: 0x07, 0x17, 0x27
Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W Type Initial State 0 0 0 = interrupt enabled 0 = interrupt enabled 0 = interrupt enabled 0 = interrupt enabled 0 = interrupt enabled 0 = interrupt enabled Function Reserved Reserved HEC Error Cell Short Cell Error Transmit Parity Error Receive Signal Condition Change Received Cell Symbol Error Receive FIFO Overflow
Note: When set to "1", these bits mask the corresponding interrupts going to the interrupt pin (INT). When set to "0", the interrupts are unmasked. These interrupts correspond to the interrupt status bits in the Interrupt Status Registers.
ENHANCED CONTROL REGISTERS
Addresses: 0x08, 0x18, 0x28
Bit 7 6 Type R/W R/W Initial State 0 = not reset 0 = OSC Function Individual Port Software Reset 1 = Reset. This bit is not self clearing; must write 0 to exit reset. Transmit Line Clock (or Loop Timing Mode) When set to 0, the OSC input is used as the transmit line clock. When set to 1, the recovered receive clock is used as the transmit line clock. VPI/VCI Swap DPI mode only. Receive direction only. See description on page 29. Utopia 2 Port Address When operating in Utopia 2 Mode, these register bits determine the Utopia 2 port addresses.
5 4-0
R/W R/W
0 = no swap Port 0 (Reg 0x08): 00000 Port 1 (Reg 0x18): 00001 Port 2 (Reg 0x28): 00010
RXREF AND TXREF CONTROL REGISTER
Address: 0x40
Bit 7, 6 5 4-3 2-0 R/W Type R/W R/W Initial State 00 = RxREF0 (Port 0) 0 = not reset 0 0000 = not looped Function
RxREF Source Select
Selects which of the three ports (0 to 2) is the source of RxREF. Master Software Reset 1 = Reset. This bit is not self clearing; must write 0 to exit reset. Reserved
RxREF to TxREF Loop Select
When set to 0, TxREF is used to generate X_8 timing marker commands. When set to 1, TxREF input is ignored, and received X_8 timing commands are looped back and added to the transmit stream of that same port. See Figure 6. bit 2: port 2 bit 1: port 1 bit 0: port 0
34
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TBIAS TSTG IOUT Rating Terminal Voltage with respect to GND Temperature Under Bias Storage Temperature DC Output Current Value -0.5 to +5.5 -55 to +125 -55 to +125 50 Unit V C C mA
RECOMMENDED DC OPERATING CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
VDD GND VIH VIL AVDD AGND VDIF
Digital Supply Voltage Digital Ground Voltage Input High Voltage Input Low Voltage Analog Supply Voltage Analog Ground Voltage VDD - AVDD
3.0 0 2.0 -0.3 3.0 0 -0.5
3.3 0 -- -- 3.3 0 0
3.6 0 5.25 0.8 3.6 0 0.5
V V V V V V V
NOTE: 3139 tbl 02 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty.
CAPACITANCE (TA = +25C, f = 1MHz) RECOMMENDED OPERATING TEMPERATURE and SUPPLY VOLTAGE
Grade Commercial Industrial Ambient Temperature 0C to 70C -40C to +85C GND, AGND 0V 0V VDD, AVDD 3.3V 0.3V 3.3V 0.3V Symbol CIN
(1)
Parameter Input Capacitance I/O Capacitance
Conditions VIN = 0V VOUT = 0V
Max. 10 10
Unit pF pF
CIO(1)
NOTES: 1. Characterized values, not currently tested.
3139 tbl 05
DC ELECTRICAL CHARACTERISTICS (All pins except TX+/- and RX+/-)
Symbol ILI ILO VOH1 VOH2 VOL
(1) (2)
Parameter Input Leakage Current I/O (as input) Leakage Current Output Logic "1" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Digital Power Supply Current - VDD Analog Power Supply Current - AVDD
Test Conditions Gnd VIN VDD Gnd VIN VDD IOH = -2 mA, VDD= min. IOH = -8 mA, VDD= min. IOL = 8 mA, VDD= min. OSC = 32 MHz, all outputs unloaded OSC = 32 MHz, all outputs unloaded
Min. -5 -10 2.4 2.4 -- -- --
Max 5 10 -- -- 0.4 140 140
Unit A A V V V mA mA
(3)
IDD1(4, 5) IDD2(5)
NOTES: 1. 2. 3. 4. 5.
For AD[7:0] pins only. For all output pins except AD[7:0], INT and TX+/-. For all output pins except TX+/-. Add 15mA for each TX+/- pair that is driving a load Total supply current is the sum of IDD1 and IDD2.
DC ELECTRICAL CHARACTERISTICS (TX+/- output pins only)
Symbol VOH1 VOL Parameter Output Logic "1" Voltage Output Logic "0" Voltage Test Conditions IOH = -20 mA IOL = 20 mA Min. VDD - 0.5V -- Max -- 0.5 Unit V V
35
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
UTOPIA Level 2 Bus Timing Parameters
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 Parameter TxCLK Fequency TxCLK Duty Cycle (% of t1) TxDATA[15:0], TxPARITY Setup Time to TxCLK TxDATA[15:0], TxPARITY Hold Time toTxCLK TxADDR[4:0] Setup Time to TxCLK TxADDR[4:0] Hold Time to TxCLK TxSOC, TxEN Setup Time to TxCLK TxSOC, TxEN Hold Time to TxCLK TxCLK to TxCLAV High-Z TxCLK to TxCLAV Low-Z (min) and Valid (max) RxCLK Fequency RxCLK Duty Cycle (% of t12) Min. 0.2 40 7 2 7 2 7 2 2 2 0.2 40 7 2 7 2 2 2 2 2 2 2 Max. 50 60 -- -- -- -- -- -- 10 14 50 60 -- -- -- -- 14 10 10 14 10 14 Units MHz % ns ns ns ns ns ns ns ns MHz % ns ns ns ns ns ns ns ns ns ns
RxEN Setup Time to RxCLK RxEN Hold Time to RxCLK
RxADDR[4:0] Setup Time to RxCLK RxADDR[4:0] Hold Time to RxCLK RxCLK to RxCLAV High-Z RxCLK to RxCLAV Low-Z (min) and Valid (max) RxCLK to RxSOC High-Z RxCLK to RxSOC Low-Z (min) and Valid (max) RxCLK to RxDATA, RxPARITY High-Z RxCLK to RxDATA, RxPARITY Low-Z (min) and Valid (max)
t3 TxCLK TxDATA[15:0], TxPARITY t5 TxADDR[4:0] t7 TxSOC t8
t4
t1
t2
Octet 1 t6
Octet 2
t9
t10
t10
TxCLAV
High-Z
High-Z
3505 drw 37
Figure 36. UTOPIA Level 2 Transmit
36
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
t12 RxCLK t14 t15
t13
t16 RxADDR[4:0]
t17
t18 RxCLAV RxSOC RxDATA[15:0], RxPARITY
High-Z High-Z
t19
t19
t21
High-Z
t21 t23
t20
High-Z
t23
High-Z
t22
High-Z
3505 drw 38
Figure 37. UTOPIA Level 2 Receive
UTOPIA Level 1 Bus Timing Parameters
Symbol t31 t32 t33 t34 t35 t36 t37 t39 t40 t41 t42 t43 t44 t45 t46 t47 Parameter TxCLK Fequency TxCLK Duty Cycle (% of t31) TxDATA[7:0], TxPARITY Setup Time to TxCLK TxDATA[7:0], TxPARITY Hold Time toTxCLK TxSOC, TxEN[3:0] Setup Time to TxCLK TxSOC, TxEN[3:0] Hold Time toTxCLK TxCLK to TxCLAV[3:0] Invalid (min) and Valid (max) RxCLK Fequency RxCLK Duty Cycle (% of t39) Min. 0.2 40 7 2 7 2 2 0.2 40 7 2 2 2 2 2 2 Max. 50 60 -- -- -- -- 14 50 60 -- -- 14 10 14 10 14 Units MHz % ns ns ns ns ns MHz % ns ns ns ns ns ns ns
RxEN[3:0] Setup Time to RxCLK RxEN[3:0] Hold Time to RxCLK
RxCLK to RxCLAV[3:0] Invalid (min) and Valid (max) RxCLK to RxSOC High-Z RxCLK to RxSOC Low-Z (min) and Valid (max) RxCLK to RxDATA, RxPARITY High-Z RxCLK to RxDATA, RxPARITY Low-Z (min) and Valid (max)
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IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
t33 TxCLK TxDATA[7:0], TxPARITY t35 TxSOC
t34
t31
t32
Octet 1 t36
Octet 2 t37
TxCLAV[2:0]
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Figure 38. UTOPIA Level 1 Transmit
t39 RxCLK t41 t42
t40
t43 RxCLAV[2:0] t45 RxSOC RxDATA[7:0], RxPARITY
High-Z
t45 t47
t44
High-Z
t47
High-Z
t46
High-Z
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Figure 39. UTOPIA Level 1 Receive
38
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DPI Bus Timing Parameters
Symbol t51 t52 t53 t54 t55 t56 t57 t61 t62 t63 t64 t65 Parameter DPICLK Frequency DPICLK Duty Cycle (% of t51) DPICLK to Pn_TCLK Propagation Delay Pn_TFRM Setup Time to Pn_TCLK Pn_TFRM Hold Time to Pn_TCLK Pn_TD[3:0] Setup Time to Pn_TCLK Pn_TD[3:0] Hold Time to Pn_TCLK Pn_RCLK Period Pn_RCLK High Time Pn_RCLK Low Time Pn_RCLK to Pn_RFRM Invalid (min) and Valid (max) Pn_RCLK to Pn_RD Invalid (min) and Valid (max) Min. 0.2 40 2 11 1 11 1 25 10 10 2 2 Max. 40 60 14 -- -- -- -- -- -- -- 12 12 Units MHz % ns ns ns ns ns ns ns ns ns ns
t51 DPICLK t53 Pn_TCLK t54 Pn_TFRM t55
t52
t56 Pn_TD[3:0]
t57
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Figure 40. DPI Transmit
t61 Pn_RCLK
t62
t63
t64 Pn_RFRM t65 Pn_RD[3:0]
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Figure 41. DPI Receive
39
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Utility Bus Read Cycle
Name Tas Tcsrd Tah Tapw Ttria Trdpw Tdh Tch Ttrid Trd Tar Trdd Min 10 0 5 10 -- 20 0 0 -- 5 5 0 Max -- -- -- -- 0 -- -- -- 10 18 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns Description Address setup to ALE Chip select to read enable Address hold to ALE ALE min pulse width Address tri-state to RD assert Min. RD pulse width Data Valid hold time RD deassert to CS deassert RD deassert to data tri-state Read Data access ALE low to start of read Start of read to Data low-Z
Utility Bus Write Cycle
Name Tapw Tas Tah Tcswr Twrpw Tdws Tdwh Tch Taw Min 10 10 5 0 20 20 10 0 20 Max -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns Description ALE min pulse width Address set up to ALE Address hold time to ALE CS Assert to WR Min. WR pulse width Write Data set up Write Data hold time WR deassert to CS deassert ALE low to end of write
Tas AD[7:0] (input) Address Tapw ALE
Tah
Tcsrd
Tch
Tar
Trdpw
Ttrid
Trd Trdd AD[7:0] (output) Data
Tdh
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Figure 42. Utility Bus Read Cycle
Tas AD[7:0] Address Tapw ALE
Tah
Tdws Data (input)
Tdwh
Taw
Tch
Tcswr
Twrpw
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Figure 43. Utility Bus Write Cycle
40
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OSC, RXREF TXREF and Reset Timing RXREF,
Symbol Tcyc Tch Tcl Tcc Trrpd Ttrh Ttrl Trspw(2)
(1)
Parameter OSC cycle period (25.6 Mbps) (51.2 Mbps) OSC high time OSC low time OSC cycle to cycle period variation OSC to RXREF Propagation Delay
TXREF TXREF
Min. 30 15 40 40 -- 1 35 35 two TxCLK cycles two RxCLK cycles two DPICLK cycles two OSC cycles
Typ. 31.25 15.625 -- -- -- -- -- -- --
Max. 33 16.5 60 60 1 30 -- -- --
Unit ns ns % % % ns ns ns --
High Time Low Time
Minimum RST Pulse Width
NOTES: 1. The width of the RXREF pulse is programmable in the LED Driver and HEC Status/Control Registers. 2. The minimum RESET Pulse Width is either two RxCLK cycles, two TxCLK cycles, two DPICLK cycles or two OSC cycles, whichever is greater (and applicable).
Tcyc OSC
Tch
Tcl
Trrpd
Trrpd
Ttrl
Ttrh
Trspw
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Figure 44. OSC, RXREF TXREF and Reset Timing RXREF,
3.3V
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V See Figure 45
1.2K D.U.T. 900 30pF*
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Figure 45. Output Load
* Includes jig and scope capacitances.
41
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
A note about Figures 46 and 47: The ATM Forum and ITU-T standards for 25 Mbps ATM define "Network" and "User" interfaces. They are identical except that transmit and receive are switched between the two. A Network device can be connected directly to a User device with a straight-through cable. User-to-User or Network-to-Network connections require a cable with 1-to-7 and 2-to-8 crossovers.
Note 3
111
Note 1 AGND Note 2
110 109 TX2+ TX2-
112 120 RX2121 RX2+
1 Rx 2 RJ45 Connector 7 Tx 8
87654321 Magnetics 9 10 11 12 13 14 15 16
AGND
Rx Filter
Tx Filter
IDT 77V1253
RJ45
Magnetics
RJ45
Magnetics 141 142
4781 drw 47
NOTES: 1. 2. 3. 4. 5.
Figure 46. PC Board Layout for ATM Network
No power or ground plane inside this area. Analog power plane inside this area. Digital power plane inside this area. A single ground plane should extend over the area covered by the analog and digital power planes, without breaks. All analog signal traces should avoid 90 corners.
Note 3 Note 1 AGND Note 2
111 112
110 109 TX2+ TX2-
1 Tx 2 RJ45 Connector 7 Rx 8
87654321 Magnetics 9 10 11 12 13 14 15 16
AGND
Tx Filter
Rx Filter
120 RX2121 RX2+
IDT 77V1253
RJ45
Magnetics
RJ45
Magnetics 141 142
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Figure 47. PC Board Layout for ATM User
NOTES: 1. 2. 3. 4. 5. No power or ground plane inside this area. Analog power plane inside this area. Digital power plane inside this area. A single ground plane should extend over the area covered by the analog and digital power planes, without breaks. All analog signal traces should avoid 90 corners.
42
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PACKAGE DIMENSIONS
144 1 109 A2 108 A1 e 144-Pin PQFP
4'-4" E E1 5'-5"
36 37 72
73 A 2'-6"
D1 4'-5" D 5'-6"
L
b
SYMBOL A A1 A2 D D1 E E1 L e b
MIN. 0.25 3.20 0.73 0.22
NOM. 3.70 0.33 3.37 31.20 28.00 31.20 28.00 0.88 0.65 -
MAX. 4.07 3.60 1.03 0.38
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Dimensions are in millimeters
43
IDT77V1253 25.6 and 51.2 Mbps ATM Triple PHY
PRELIMINARY COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT NNNNN Device Type A Power NNN Speed A Package A Process/ Temp. Range Blank I PG Commercial (0C to +70C) Industrial (-40C to +85C) 144-Pin PQFP
25
Speed in Mb/s
L
77V1253 Triple 25Mb/s ATM PHY Transmission Convergence (TC) and PMD Sublayers
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PRELIMINARY DATASHEET: DEFINITION "PRELIMINARY" datasheets contain descriptions for products soon to be, or recently, released to production, including features, pinouts and block diagrams. Timing data are based on simulation or initial characterization and are subject to change upon full characterization. Datasheet Document History 11/30/98: PRELIMINARY. Initial draft.
Integrated Device Technology, Inc. reserves the right to make changes to the specifications in this data sheet in order to improve design or performance and to supply the best possible product.
Integrated Device Technology, Inc.
2975 Stender Way, Santa Clara, CA 95054-3090 Telephone: (408) 727-6116 FAX 408-492-8674
44

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