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IDT74LVC109A 3.3V CMOS DUAL J-K FLIP-FLOP WITH SET AND RESET
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS DUAL J-K FLIP-FLOP WITH SET AND RESET, POSITIVE-EDGE TRIGGER, AND 5 VOLT TOLERANT I/O
* 0.5 MICRON CMOS Technology * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * CMOS power levels (0.4 W typ. static) * Rail-to-Rail output swing for increased noise margin * All inputs, outputs, and I/Os are 5V tolerant * Supports hot insertion * Available in QSOP, SOIC, SSOP, and TSSOP packages
IDT74LVC109A
FEATURES:
DESCRIPTION:
DRIVE FEATURES: APPLICATIONS:
* High Output Drivers: 24mA * Reduced system switching noise
The LVC109A dual J-K flip-flop with set and reset, positive-edge trigger is built using advanced dual metal CMOS technology. This device features individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active low inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the function table. The J and K inputs must be stable one setup time prior to the low-to-high clock transition for predictable operation. The J-K design allows operation as a D-type flip-flop by tying the J and K inputs together. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVC109A has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
* 5V and 3.3V mixed voltage systems * Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
7
Q
K
3
C
C
C
C 6
Q
J
2 C C C C
5
SD
RD
1
CP
4
C C
NOTE: Pin numbers are for section 1. Refer to pin configuration for section 2 pin numbers.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
(c)1999 Integrated Device Technology, Inc.
AUGUST 1999
DSC-4744/1
IDT74LVC109A 3.3V CMOS DUAL J-K FLIP-FLOP WITH SET AND RESET
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1RD 1J 1K 1CP 1SD 1Q 1Q
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND Max -0.5 to +6.5 -65 to +150 -50 to +50 -50 100 Unit V C mA mA mA
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC
2RD 2J 2K 2CP 2SD 2Q 2Q
VTERM TSTG IOUT IIK IOK ICC ISS
GND
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
QSOP/ SOIC/ SSOP/ TSSOP TOP VIEW
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 5.5 6.5 Max. 6 8 8 Unit pF pF pF
FUNCTIONAL DIAGRAM
CIN COUT CI/O
5 2 4 3 1 11 14 12 13 15
1SD
1J 1CP 1K
NOTE: 1. As applicable to the device type.
SD Q CP FF1 K RD Q J
1Q
6 7
1Q
PIN DESCRIPTION
Pin Names xCP xRD Description Clock Inputs, LOW-to-HIGH, edge-triggered Asynchronous Reset Input (Active LOW) Asynchronous Set Inputs (Active LOW) Synchronous Inputs True Flip-Flop Outputs Complement Flip-Flop Outputs
1RD
2SD 2J 2CP 2K
SD J Q Q RD
2Q
xSD
10 9
xJ, xK xQ xQ
CP FF2
2Q
K
2RD
2
IDT74LVC109A 3.3V CMOS DUAL J-K FLIP-FLOP WITH SET AND RESET
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLE (1)
Inputs Operating Modes Asynchronous set Asynchronous reset Undetermined Toggle Load "0" (reset) Load "1" (set) Hold "no change" xSD L H L H H H H xRD H L L H H H H xCP X X X xJ X X X h l h l xK X X X l l h h xQ H L H Q(2) L H Q
(3)
Outputs xQ L H H Q(3) H L Q(2)
NOTES: 1. H = HIGH Voltage Level h = HIGH voltage level of input set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level l = LOW voltage level of input set-up time prior to LOW-to-HIGH CP transition X = Don't Care = LOW-to-HIGH transition 2. Complement of Q or level of Q before the indicated steady-state input conditions were established. 3. Level of Q before the indicated steady-state input conditions were established.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V, VIN = GND or VCC -- -- -- -- -- -0.7 100 -- 50 -1.2 -- 10 A V mV A VCC = 3.6V VO = 0 to 5.5V -- -- 10 A Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VI = 0 to 5.5V Test Conditions Min. 1.7 2 -- -- -- Typ.(1) -- -- -- -- -- Max. -- -- 0.7 0.8 5 A V Unit V
Quiescent Power Supply Current Variation
One input at VCC - 0.6V, other inputs at VCC or GND
--
--
500
A
NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient.
3
IDT74LVC109A 3.3V CMOS DUAL J-K FLIP-FLOP WITH SET AND RESET
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2.2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
OPERATING CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 25C
Symbol CPD Parameter Power Dissipation Capacitance per Flip-Flop Test Conditions CL = 0pF, f = 10Mhz Typical -- Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V 0.2V Symbol tPLH tPHL tPLH tPHL tSU tH tREM tW tW tSK(o) Parameter Propagation Delay xCP to xQ or x Q Propagation Delay xSD to xQ or xRD xQ Propagation Delay xSD to xQ or xRD xQ Set-up Time, xJ, xK to xCP Hold Time, xJ, xK to xCP Removal Time, xSD, xRD to xCP Pulse Width, CLK HIGH or LOW Set or Reset Pulse Width, HIGH or LOW Output Skew(2) Min. -- -- -- 2.5 2 3 3.3 3 -- Max. 9 11 10 -- -- -- -- -- -- VCC = 2.7V Min. -- -- -- 2.5 2 3 3.3 3 -- Max. 8.5 9 10 -- -- -- -- -- -- VCC = 3.3V 0.3V Min. -- -- -- 2.5 2 3 3.3 3 -- Max. 7.5 8 9 -- -- -- -- -- 500 Unit ns ns ns ns ns ns ns ns ps
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2 Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVC109A 3.3V CMOS DUAL J-K FLIP-FLOP WITH SET AND RESET
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 VCC(2)= 3.3V0.3V & 2.7V 6 2.7 1.5 300 300 50 Unit V V V mV mV pF
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
Propagation Delay
LVC QUAD Link
VCC 500 Pulse Generator
(1, 2)
VLOAD Open GND ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
LVC QUAD Link
VIN D.U.T. RT
VOUT
500 CL
LVC QUAD Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
DATA INPUT TIMING INPUT SYNCHRONOUS CONTROL ASYNCHRONOUS CONTROL
tSU
tH
tREM
INPUT
tPLH1
tPHL1
VIH VT 0V VOH VT VOL VOH VT VOL
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
LVC QUAD Link
Set-up, Hold, and Release Times
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE VT
LVC QUAD Link
OUTPUT 1
tSK (x)
tSK (x)
VT
OUTPUT 2 tPLH2 tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC QUAD Link
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
Pulse Width
5
IDT74LVC109A 3.3V CMOS DUAL J-K FLIP-FLOP WITH SET AND RESET
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
XX IDT XXXX XX LVC Device Type Package Temp. Range
Q DC PY PG 109A 74
Quarter Size Outline Package Small Outline IC Shrink Small Outline Package Thin Shrink Small Outline Package Dual J-K Flip-Flop with Set and Reset, Postive-Edge Trigger, 24mA -40C to +85C
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for Tech Support: logichelp@idt.com (408) 654-6459
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