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Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger (3-State)
74ABT374A
FEATURES
* 8-bit positive edge triggered register * 3-State output buffers * Output capability: +64mA/-32mA * Latch-up protection exceeds 500mA per Jedec Std 17 * ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT374A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT374A is an 8-bit, edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE) control gates. The register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-State buffers independent of the clock operation. When OE is Low, the stored data appears at the outputs. When OE is High, the outputs are in the High-impedance "OFF" state, which means they will neither drive nor load the bus.
* Power-up 3-State * Power-up reset * Live insertion/extraction permitted
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN COUT ICCZ PARAMETER Propagation delay CP to Qn Input capacitance Output capacitance Total supply current CONDITIONS Tamb = 25C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC Outputs disabled; VO = 0V or VCC Outputs disabled; VCC =5.5V TYPICAL 3.4 3.8 4 7 110 UNIT ns pF pF A
ORDERING INFORMATION
PACKAGES 20-Pin Plastic DIP 20-Pin plastic SO 20-Pin Plastic SSOP Type II 20-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74ABT374A N 74ABT374A D 74ABT374A DB 74ABT374A PW NORTH AMERICA 74ABT374A N 74ABT374A D 74ABT374A DB 74ABT374APW DH DWG NUMBER SOT146-1 SOT163-1 SOT339-1 SOT360-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER SYMBOL OE D0-D7 FUNCTION Output enable input (active-Low) Data inputs
OE Q0 D0 D1 Q1 Q2 D2 D3 Q3
1 2 3 4 5 6 7 8 9
20 19 18 17 16 15 14 13 12 11
VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP
1 3, 4, 7, 8, 13, 14, 17, 18 2, 5, 6, 9, 12, 15, 16, 19 11 10 20
Q0-Q7 CP GND VCC
Data outputs Clock pulse input (active rising edge) Ground (0V) Positive supply voltage
GND 10
SA00110
1995 Sep 06
1
853-1448 15704
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger (3-State)
74ABT374A
LOGIC SYMBOL
3 4 7 8 13 14 17 18
LOGIC SYMBOL (IEEE/IEC)
1 11
EN C1
D0 D1 D2 D3 D4 D5 D6 D7 11 1 CP OE 3 4 7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 8 13 2 5 6 9 12 15 16 19 14 17
1D
2 5 6 9 12 15 16 19
SA00111
18
SA00112
FUNCTION TABLE
INPUTS OE L L L H H H= h= L= l= NC= X= Z= = = CP Dn l h X X INTERNAL REGISTER L H NC NC OUTPUTS Q0 - Q7 L H NC Z Hold OPERATING MODE
Latch and read register
Disable outputs Dn Dn Z High voltage level High voltage level one set-up time prior to the Low-to-High clock transition Low voltage level Low voltage level one set-up time prior to the Low-to-High clock transition No change Don't care High impedance "off" state Low-to-High clock transition not a Low-to-High clock transition
LOGIC DIAGRAM
D0 3 D1 4 D2 7 D3 8 D4 13 D5 14 D6 17 D7 18
D
D
D
D
D
D
D
D
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
11 CP
1 OE 2 Q0 5 Q1 6 Q2 9 Q3 12 Q4 15 Q5 16 Q6 19 Q7
SA00113
1995 Sep 06
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger (3-State)
74ABT374A
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 output in Off or High state output in Low state VI < 0 CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 128 -65 to 150 UNIT V mA V mA V mA C
DC output diode current DC output voltage3
DC output current Storage temperature range
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 -40 PARAMETER MIN 4.5 0 2.0 0.8 -32 64 10 +85 MAX 5.5 VCC V V V V mA mA ns/V C UNIT
1995 Sep 06
3
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger (3-State)
74ABT374A
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C MIN VIK Input clamp voltage VCC = 4.5V; IIK = -18mA VCC = 4.5V; IOH = -3mA; VI = VIL or VIH VOH High-level output voltage VCC = 5.0V; IOH = -3mA; VI = VIL or VIH VCC = 4.5V; IOH = -32mA; VI = VIL or VIH VOL VRST II IOFF IPU/IPD IOZH IOZL ICEX IO ICCH ICCL ICCZ ICC Additional supply current per input pin2 Quiescent supply current Low-level output voltage Power-up output low voltage3 Input leakage current Power-off leakage current Power-up/down 3-State output current 3-State output High current 3-State output Low current Output High leakage current Output current1 VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; IO = 1mA; VI = GND or VCC VCC = 5.5V; VI = GND or 5.5V VCC = 0.0V; VO or VI 4.5V VCC = 0.0V; IO = 1mA; VI = GND or VCC; V OE = Don't Care VCC = 5.5V; VO = 2.7V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = GND or VCC VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND -50 2.5 3.0 2.0 TYP -0.9 2.9 3.4 2.4 0.42 0.13 0.01 5.0 5.0 5.0 -5.0 5.0 -100 110 24 110 0.5 0.55 0.55 1.0 100 50 50 -50 50 -180 250 30 250 1.5 -50 MAX -1.2 2.5 3.0 2.0 0.55 0.55 1.0 100 50 50 -50 50 -180 250 30 250 1.5 Tamb = -40C to +85C MIN MAX -1.2 V V V V V V A A A A A A mA A mA A mA UNIT
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Min fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum clock frequency Propagation delay CP to Qn Output enable time to High and Low level Output disable time from High and Low level 1 1 3 4 3 4 200 1.7 2.0 1.2 2.2 1.8 1.5 Tamb = +25oC VCC = +5.0V Typ 300 3.4 3.8 3.5 4.3 3.6 3.0 4.5 4.9 4.5 5.4 4.7 4.1 Max Tamb = -40 to +85oC VCC = +5.0V 0.5V Min 200 1.7 2.0 1.2 2.2 1.8 1.5 5.1 5.2 5.4 6.2 5.2 4.3 Max ns ns ns ns UNIT
1995 Sep 06
4
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger (3-State)
74ABT374A
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25oC VCC = +5.0V Min ts(H) ts(L) th(H) th(L) tw(H) tw(L) Setup time, High or Low Dn to CP Hold time, High or Low Dn to CP CP pulse width High or Low 2 2 1 1.5 1.2 1.0 1.0 2.0 2.8 Typ 0.6 0.3 -0.3 -0.5 0.8 1.0 Tamb = -40 to +85oC VCC = +5.0V 0.5V Min 1.5 1.2 1.0 1.0 2.0 2.8 ns ns ns UNIT
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
1/fMAX OE VM tPZH tw(H) tPHL Qn VM tw(L) tPLH VM Qn VM VOH-0.3V 0V VM tPHZ
CP
VM
VM
VM
SA00056
SA00066
Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency
Waveform 3. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Dn
CP
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
1995 Sep 06
EEEEEEEEEE EEE E EEEEEEEEEE EEE E EEEEEEEEEE EEE E
VM VM VM VM ts(H) th(H) ts(L) th(L) VM VM
OE
VM tPZL
VM tPLZ
Qn
VM
VOL+0.3V 0V
SA00107
SA00067
Waveform 2. Data Setup and Hold Times
Waveform 4. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
5
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger (3-State)
74ABT374A
TEST CIRCUIT AND WAVEFORM
VCC 7.0V RL 90% NEGATIVE PULSE VM 10% tTHL (tF) CL RL POSITIVE PULSE 10% tW tTLH (tR) 90% 90% VM 10% 0V 10% 0V tTLH (tR) tTHL (tF) AMP (V) tW VM 90% AMP (V)
PULSE GENERATOR
VIN D.U.T. RT
VOUT
Test Circuit for 3-State Outputs
VM
SWITCH POSITION
TEST tPLZ tPZL All other SWITCH closed closed open
VM = 1.5V Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS FAMILY Amplitude 74ABT 3.0V Rep. Rate 1MHz tW 500ns tR 2.5ns tF 2.5ns
SA00012
1995 Sep 06
6

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