View 7333_970512.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TSA1001
10-BIT, 25MSPS, 35mW A/D CONVERTER
s 10-bit A/D converter in deep submicron s s s s s s s s
CMOS technology Ultra low power consumption: 35mW @ 25Msps (10mW @ 5Msps) Single supply voltage: 2.5V Input range: 2Vpp differential 25Msps sampling frequency ENOB=9.7 @ 25Msps, Fin=5MHz SFDR typically up to 80dB @ 25Msps, Fin=5MHz Built-in reference voltage with external bias capability Pinout compatibility with TSA0801, TSA1002 and TSA1201 ORDER CODE
Part Number TSA1001CF TSA1001CFT TSA1001IF TSA1001IFT EVAL1001/AA Temperature Range 0C to +70C 0C to +70C -40C to +85C -40C to +85C Package TQFP48 TQFP48 TQFP48 TQFP48 Conditioning Tray Tape & Reel Tray Tape & Reel Marking SA1001C SA1001C SA1001I SA1001I
Evaluation board
PIN CONNECTIONS (top view)
AGND AVCC VCCB GNDB AVCC DFSB VCCB OEB NC NC DR NC
DESCRIPTION The TSA1001 is a 10-bit, 25Msps sampling frequency Analog to Digital converter using a CMOS technology combining high performances and very low power consumption. The TSA1001 is based on a pipeline structure and digital error correction to provide excellent static linearity and achieve 9.7 effective bits at Fs=25Msps, and Fin=5MHz. Especially designed for portable applications, the TSA1001 only dissipates 35mW at 25Msps. When running at lower sampling frequencies, even lower consumption can be achieved. A voltage reference is integrated in the circuit to simplify the design and minimize external components. It is nevertheless possible to use the circuit with an external reference. The output data can be coded into two different formats. A Data Ready signal is raised as the data is valid on the output and can be used for synchronization purposes. The TSA1001 is available in commercial (0 to +70C) and extended (-40 to +85C) temperature range, in a small 48 pins TQFP package. APPLICATIONS
index corner
48 1 2 3 4 5 6 7 8 9 10 11 12 13
47 46
45
44 43
42
41
40
39
38
37 36 NC 35 NC 34 NC 33 D0 (LSB) 32 D1 31 D2
IPOL VREFP VREFM AGND VIN AGND VINB AGND INCM AGND AVCC AVCC
TSA1001
30 D3 29 D4 28 D5 27 D6 26 D7 25 D8
14 15
16
17
18 19
20
21
22
23
24
DGND
DVCC
DVCC
DGND
CLK
DGND
NC
GNDB
GNDB
VCCB
OR
D9 (MSB)
PACKAGE
7 x 7 mm TQFP48
s s s s s
Portable instrumentation Video processing Medical imaging and ultrasound High resolution fax and scanners Digital communications
September 2002
1/20
TSA1001
ABSOLUTE MAXIMUM RATINGS
Symbol AVCC DVCC VCCB IDout Tstg ESD Analog Supply voltage Digital Supply voltage
1)
Parameter
Values 0 to 3.3 0 to 3.3 0 to 3.3 -100 to 100 +150 2 1.5
Unit V V V mA C KV
1)
Digital buffer Supply voltage 1) Digital output current Storage temperature Electrical Static Discharge: - HBM - CDM-JEDEC Standard
1). All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must never exceed -0.3V or VCC+0V
OPERATING CONDITIONS
Symbol AVCC DVCC VCCB VREFP Analog Supply voltage Digital Supply voltage Digital buffer Supply voltage Forced top reference voltage 1) Parameter Min 2.25 2.25 2.25 0.5 0 0.2 Typ 2.5 2.5 2.5 1 0 0.5 Max 2.7 2.7 2.7 1.8 0.5 1.1 Unit V V V V V V
VREFM Forced bottom reference voltage 1) INCM
1) Condition
Forced input common mode voltage
VRefP-VRefM>0.3V
BLOCK DIAGRAM
VREFP
+2.5V
GNDA VIN INCM VINB stage 1 stage 2 stage n Reference circuit IPOL VREFM
Sequencer-phase shifting CLK
DFSB OEB
Timing
Digital data correction DR DO Buffers TO D9 OR GND
2/20
TSA1001
PIN CONNECTIONS (top view)
AGND AVCC VCCB GNDB AVCC DFSB VCCB OEB
NC
NC
NC
DR
index corner
48 1 2 3 4 5 6 7 8 9 10 11 12 13
47 46
45
44 43
42
41
40
39
38
37 36 NC 35 NC 34 NC 33 D0 (LSB) 32 D1 31 D2
IPOL VREFP VREFM AGND VIN AGND VINB AGND INCM AGND AVCC AVCC
TSA1001
30 D3 29 D4 28 D5 27 D6 26 D7 25 D8
14 15
16
17
18
19
20
21
22
23
24
DGND
DVCC
DVCC
DGND
CLK
DGND
NC
GNDB
GNDB
VCCB
OR
D9 (MSB)
PIN DESCRIPTION
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name IPOL VREFP VREFM AGND VIN AGND VINB AGND INCM AGND AVCC AVCC DVCC DVCC DGND CLK DGND NC DGND GNDB GNDB VCCB OR Description Analog bias current input Top voltage reference Bottom voltage reference Analog ground Analog input Analog ground Inverted analog input Analog ground Input common mode Analog ground Analog power supply Analog power supply Digital power supply Digital power supply Digital ground Clock input Digital ground Non connected Digital ground Digital buffer ground Digital buffer ground Digital buffer power supply Out Of Range output 0V 0V 0V 2.5V CMOS output (2.5V) CMOS output (2.5V) 1V 0V 0V 1Vpp 0V 1Vpp 0V 0.5V 0V 2.5V 2.5V 2.5V 2.5V 0V 2.5V compatible CMOS input 0V Observation Pin No 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name D8 D7 D6 D5 D4 D3 D2 D1 D0(LSB) NC NC NC NC DR VCCB GNDB VCCB NC NC OEB DFSB AVCC AVCC AGND Description Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Least Significant Bit output Non connected Non connected Non connected Non connected Data Ready output Digital Buffer power supply Digital Buffer ground Digital Buffer power supply Non connected Non connected Output Enable input Data Format Select input Analog power supply Analog power supply Analog ground 2.5V compatible CMOS input 2.5V compatible CMOS input 2.5V 2.5V 0V CMOS output (2.5V) 2.5V 0V 2.5V Observation CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V) CMOS output (2.5V)
D9(MSB) Most Significant Bit output
3/20
TSA1001
ELECTRICAL CHARACTERISTICS AVCC = DVCC = VCCB = 2.5V, Fs= 25Msps, Fin=1MHz, Vin@ -1.0dBFS, VREFM = 0V Tamb = 25C (unless otherwise specified) TIMING CHARACTERISTICS
Symbol FS DC TC1 TC2 Tod Tpd Ton Toff Parameter Sampling Frequency Clock Duty Cycle Clock pulse width (high) Clock pulse width (low) Data Output Delay (Fall of Clock 10pF load capacitance to Data Valid) Data Pipeline delay Falling edge of OEB to digital output valid data Rising edge of OEB to digital output tri-state Test conditions Min 0.5 30 18 18 50 20 20 5 5.5 1 1 Typ Max 25 70 Unit MHz % ns ns ns cycles ns ns
TIMING DIAGRAM
N+4 N+3 N+5 N+6
N+2 N-1 N N+1
N+7 N+8
CLK
Tpd + Tod OEB Tod Toff N-6 N-5 N-4 N-3 N-2 N-1 Ton N+1 N+2
DATA OUT
N-7
DR
HZ state
4/20
TSA1001
CONDITIONS: AVCC = DVCC = VCCB = 2.5V, Fs= 25Msps, Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V Tamb = 25C (unless otherwise specified) ANALOG INPUTS
Symbol Parameter Test conditions Min Typ 2.0 21 5.0 Vin@Full Scale, FS=25Msps 1000 60 Max Unit Vpp
VIN-VINB Full scale reference voltage Req Cin BW ERB Input resistance Input capacitance Analog Input Bandwidth Effective Resolution Bandwidth1)
k
pF MHz MHz
1). See parameters definition for more information
REFERENCE VOLTAGE
Symbol VREFP Parameter Top internal reference voltage Test conditions Min 0.91 Tmin= -40C to Tmax= 85C1) 0.90 1.20 Vpol Ipol Ipol VINCM Analog bias voltage Analog bias current Analog bias current Input common mode voltage Tmin= -40C to Tmax=
1). Not fully tested over the temperature range. Guaranteed by sampling.
Typ 1.03
Max 1.15 1.16
Unit V V V V A A
1.27
1.35 1.36
Tmin= -40C to Tmax= 85C Normal operating mode Shutdown mode
1)
1.19 25 50 0 0.48 0.57
70
0.65 0.66
V V
85C1)
0.48
5/20
TSA1001
CONDITIONS: AVCC = DVCC = VCCB = 2.5V, Fs= 25Msps, Fin= 1MHz, Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V Tamb = 25C (unless otherwise specified) POWER CONSUMPTION
Symbol ICCA Parameter
1)
Test conditions
Min
Typ 11.8
Max 14 14
Unit mA mA mA mA mA mA A mW mW mW C/W C/W
Analog Supply current Tmin= -40C to Tmax= 85C2)
1)
1
2 2
ICCD
Digital Supply Current
Tmin= -40C to Tmax= 85C2)
1)
1.4
5 5
ICCB
Digital Buffer Supply Current Digital Buffer Supply Current in High Impedance Mode Power consumption in normal operation mode Power consumption in High Impedance mode Junction-ambient thermal resistor (TQFP48) Junction-case thermal resistor (TQFP48)
Tmin= -40C to Tmax= 85C2)
1) 1)
ICCBZ
40 35
100 47 47
Pd
Tmin= -40C to Tmax= 85C2)
1)
PdZ Rthja Rthjc
32 80 18
37
1). Rpol= 25K. Equivalent load: Rload= 470 and Cload= 6pF 2). Not fully tested over the temperature range. Guaranteed by sampling.
DIGITAL INPUTS AND OUTPUTS
Symbol Digital inputs VIL VIH Logic "0" voltage Logic "1" voltage 2.0 0.8 V V Parameter Test conditions Min Typ Max Unit
Digital Outputs VOL VOH IOZ CL Logic "0" voltage Logic "1" voltage Iol=10A Ioh=10A 2.4 -1.5 1.5 15 0.4 V V A pF
High Impedance leakage current OEB set to VIH Output Load Capacitance
ACCURACY
Symbol OE DNL INL 6/20 Parameter Offset Error Differential Non Linearity Integral Non Linearity Monotonicity and no missing codes Test conditions Min -40 -0.7 -0.8 Typ 1 0.3 0.3 Max 40 +0.7 +0.8 Unit mV LSB LSB
Guaranteed
TSA1001
CONDITIONS: AVCC = DVCC = 2.5V, Fs= 25Msps Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V Tamb = 25C (unless otherwise specified) DYNAMIC CHARACTERISTICS
Symbol Parameter Test conditions Fin= 5MHz Fin= 10MHz SFDR Spurious Free Dynamic Range Fin= 5MHz Fin= 10MHz Fin= 5MHz Fin= 10MHz Fin= 5MHz Fin= 10MHz Fin= 5MHz Fin= 10MHz Fin= 5MHz Fin= 10MHz Fin= 5MHz Fin= 10MHz Fin= 5MHz Fin= 10MHz Fin= 5MHz Fin= 10MHz Fin= 5MHz Fin= 10MHz
2) 1)
Min
Typ -80.5 -76
Max -66 -66 -66 -66
Unit dBc
dBc
1)
58 58
59.3 59.3
dB
SNR
Signal to Noise Ratio
2)
58 58
dB -79.5 -75 -63 -63 -62 -62
1)
dB
THD
Total Harmonic Distortion
2)
dB
1)
58 58
59.0 59.0
dB
SINAD
Signal to Noise and Distortion Ratio
2)
58 58
dB 9.70 9.70
1)
9.5 9.5
bits
ENOB
Effective Number of Bits
2)
9.5 9.5
bits
1). Rpol= 25K. Equivalent load: Rload= 470 and Cload= 6pF 2). Tmin= -40C to Tmax= 85C. Not fully tested over the temperature range. Guaranteed by sampling.
7/20
TSA1001
DEFINITIONS OF SPECIFIED PARAMETERS STATIC PARAMETERS Static measurements are performed through method of histograms on a 2MHz input signal, sampled at 25Msps, which is high enough to fully characterize the test frequency response. The input level is +1dBFS to saturate the signal. Differential Non Linearity (DNL) The average deviation of any output code width from the ideal code width of 1LSB. Integral Non linearity (INL) An ideal converter presents a transfer function as being the straight line from the starting code to the ending code. The INL is the deviation for each transition from this ideal curve. DYNAMIC PARAMETERS Dynamic measurements are performed by spectral analysis, applied to an input sinewave of various frequencies and sampled at 25Msps. Spurious Free Dynamic Range (SFDR) The ratio between the amplitude of fundamental tone (signal power) and the power of the worst spurious signal (not always an harmonic) over the full Nyquist band. It is expressed in dBc. Total Harmonic Distortion (THD) The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB. Signal to Noise Ratio (SNR) The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (fs/2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB. Signal to Noise and Distortion Ratio (SINAD) Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). It is expressed in dB. From the SINAD, the Effective Number of Bits (ENOB) can easily be deduced using the formula: SINAD= 6.02 x ENOB + 1.76 dB. When the applied signal is not Full Scale (FS), but has an A0 amplitude, the SINAD expression becomes: SINAD= 6.02 x ENOB + 1.76 dB + 20 log (2A0/FS) The ENOB is expressed in bits. Analog Input Bandwidth The maximum analog input frequency at which the spectral response of a full power signal is reduced by 3dB. Higher values can be achieved with smaller input levels. Effective Resolution Bandwidth (ERB) The band of input signal frequencies that the ADC is intended to convert without loosing linearity i.e. the maximum analog input frequency at which the SINAD is decreased by 3dB or the ENOB by 1/2 bit. Pipeline delay Delay between the initial sample of the analog input and the availability of the corresponding digital data output, on the output bus. Also called data latency. It is expressed as a number of clock cycles.
8/20
TSA1001
Static parameter: Integral Non Linearity Fs=25MSPS; Fin=1MHz; Icca=11mA; N=131072pts
0 .4 0 .3 0 .2 0 .1 INL (LSBs) 0 - 0 .1 - 0 .2 - 0 .3 - 0 .4 - 0 .5 0 200 400 O u tp u t C o d e 600 800 1000
Static parameter: Differential Non Linearity Fs=25MSPS; Fin=1MHz; Icca=11mA; N=131072 pts
0 .3
0 .2
0 .1 DNL (LSBs)
0
-0 .1
-0 .2
-0 .3 0 200 400 O u tp u t C o d e 600 800 1000
Linearity vs. Fs Fin=1MHz; Rpol adjustment
80 10 ENOB 9.5 9 8.5 SNR SINAD 8 7.5 7 6.5 6 5.5 5 5 15 25 35 45 ENOB (bits)
Distortion vs. Fs Fin=1MHz; Rpol adjustment
-40
Dynamic parameters (dB)
75 70 65 60 55 50 45 40
Dynamic parameters (dB)
-50 -60 -70 -80 SFDR -90 -100 5 15 25 35 45 THD
Fs (MHz)
Fs (MHz)
9/20
TSA1001
Linearity vs. Fs Fin=15MHz; Rpol adjustment
80 11 ENOB 10 ENOB (bits) 9 SNR 60 55 50 45 40 5 15 25 35 45 6 5 SINAD 8 7
Distortion vs. Fs Fin=15MHz; Rpol adjustment
-40
Dynamic parameters (dB)
75 70 65
Dynamic parameters (dB)
-50 -60 THD -70 -80 -90 -100 5 15 25 35 45 SFDR
Fs (MHz)
Fs (MHz)
Linearity vs. Fin Fs=25MSPS; Icca=11mA
80 10 ENOB 9.5 9
Linearity vs. Fin Fs=25MSPS; Icca=11mA
80 10 ENOB 9.5 9
Dynamic parameters (dB)
75 70 65
Dynamic parameters (dB)
75 70 65
ENOB (bits)
SNR 60 55 50 45 40 0 20 40 60 SINAD
8 7.5 7 6.5 6 5.5 5
SNR 60 55 50 45 40 0 20 40 60 SINAD
8 7.5 7 6.5 6 5.5 5
Fin (MHz)
Fin (MHz)
Linearity vs.Temperature Fs=25MSPS; Icca=11mA; Fin=5MHz
10
Distortion vs. Temperature Fs=25MSPS; Icca=11mA; Fin=5MHz;
90
70
Dynamic Parameters (dB)
68 66 64 62 60 58 56 54 52 50 -40 10 60 SINAD SNR ENOB
Dynamic Parameters (dB)
9.5 9 8.5 8 7.5 7
85 80 75 70 65 60 55 50 -40 10 60 SFDR THD
Temperature (C)
Temperature (C)
10/20
ENOB (bits)
8.5
8.5
TSA1001
Linearity vs. AVcc Fs=25MSPS; Icca=11mA; Fin=1MHz
70 10
Distortion vs. AVcc Fs=25MSPS; Icca=11mA; Fin=1MHz
-50
Dynamic parameters (dB)
Dynamic Parameters (dB)
68 66 64 62 60 58 56 54 52 50 2.25 2.35 2.45 2.55 2.65 SINAD SNR ENOB
9.8 9.6 9.4 9.2 9 8.8 8.6 8.4 8.2 8
-55 -60 -65 -70 -75 -80 -85 -90 -95 -100 2.25 2.35 2.45 2.55 2.65 SFDR THD
AVCC (V)
ENOB (bits)
AVCC (V)
Linearity vs. DVcc Fs=25MSPS; Icca=11mA; Fin=1MHz
70 10
Distortion vs. DVcc Fs=25MSPS; Icca=11mA; Fin=1MHz
-50
Dynamic parameters (dB)
Dynamic Parameters (dB)
68 66 64 62 60
9.9 ENOB 9.8 9.7 9.6 9.5 SNR SINAD 9.4 9.3 9.2 9.1 9 2.35 2.45 2.55 2.65
-55 -60 -65 -70 -75 -80 -85 -90 -95 -100 2.25 2.35 2.45 2.55 2.65 SFDR THD
58 56 2.25
DVCC (V)
ENOB (bits)
DVCC (V)
Linearity vs. VccB Fs=25MSPS; Icca=11mA; Fin=1MHz
65 10 9.9 ENOB 9.8 9.7 SNR SINAD 9.6 9.5 9.4 9.3 9.2 9.1 9 2.35 2.45 2.55 2.65
Distortion vs. VccB Fs=25MSPS; Icca=11mA; Fin=1MHz
-60
64 63 62 61 60 59 58 57 56 55 2.25
Dynamic Parameters (dB)
Dynamic parameters (dB)
-65 -70 -75 -80 -85 -90 -95 -100 2.25 SFDR THD
ENOB (bits)
2.35
2.45
2.55
2.65
VCCB (V)
VCCB (V)
11/20
TSA1001 APPLICATION NOTE
DETAILED INFORMATION The TSA1001 is a High Speed analog to digital converter based on a pipeline architecture and the latest deep submicron CMOS process to achieve the best performances in terms of linearity and power consumption. The pipeline structure consists of 9 internal conversion stages in which the analog signal is fed and sequentially converted into digital data. Each 8 first stages consists of an Analog to Digital converter, a Digital to Analog converter, a Sample and Hold and a gain of 2 amplifier. A 1.5bit conversion resolution is achieved in each stage. The latest stage simply is a comparator. Each resulting LSB-MSB couple is then time shifted to recover from the conversion delay. Digital data correction completes the processing by recovering from the redundancy of the (LSB-MSB) couple for each OPERATIONAL MODES DESCRIPTION Inputs Analog input differential level (VIN-VINB) > RANGE -RANGE > (VIN-VINB) RANGE> (VIN-VINB) >-RANGE (VIN-VINB) > RANGE -RANGE > (VIN-VINB) RANGE> (VIN-VINB) >-RANGE X Data Format Select (DFSB) When set to low level (VIL), the digital input DFSB provides a two's complement digital output MSB. This can be of interest when performing some further signal processing. When set to high level (VIH), DFSB provides a standard binary output coding. DFSB H H H L L L X OEB L L L L L L H OR H H L H H L HZ DR CLK CLK CLK CLK CLK CLK HZ Outputs Most Significant Bit (MSB) D9 D9 D9 Complemented D9 Complemented D9 Complemented D9 HZ stage. The corrected data are outputted through the digital buffers. Signal input is sampled on the rising edge of the clock while digital outputs are delivered on the falling edge of the Data Ready signal. The advantages of such a converter reside in the combination of pipeline architecture and the most advanced technologies. The highest dynamic performances are achieved while consumption remains at the lowest level. Some functionalities have been added in order to simplify as much as possible the application board. These operational modes are described in the following table. The TSA1001 is pin to pin compatible with the 8bits/40Msps TSA0801, the 10bits/50Msps TSA1002 and the 12bits/50Msps TSA1201. This ensures a conformity within the product family and above all, an easy upgrade of the application.
Output Enable (OEB) When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital outputs buffers are in high impedance state. This results in lower consumption while the converter goes on sampling. When OEB is set to low level again, the data is then valid on the output with a very short Ton delay.
12/20
TSA1001
The timing diagram summarizes this operating cycle. Out of Range (OR) This function is implemented on the output stage in order to set up an "Out of Range" flag whenever the digital data are over the full scale range. Typically, there is a detection of all the data being at '0' or all the data being at '1'. This ends up with an output signal OR which is in low level state (VOL) when the data stay within the range, or in high level state (VOH) when the data is out of the range. Data Ready (DR) The Data Ready output is an image of the clock being synchronized on the output data (D0 to D9). This is a very helpful signal that simplifies the synchronization of the measurement equipment or the controlling DSP. As digital output, DR goes in high impedance state when OEB is asserted to High level as described in the timing diagram. REFERENCES AND COMMON MODE CONNECTION VREFM must be always connected externally. Internal reference and common mode In the default configuration, the ADC operates with its own reference and common mode voltages generated by its internal bandgap. VREFM pin is connected externally to the Analog Ground while VREFP (respectively INCM) is set to its internal voltage of 1.03V (respectively 0.57V). It is recommended to decouple the VREFP in order to minimize low and high frequency noise (refer to Figure 1) Figure 1 : Internal reference and common mode setting
1.03V VIN VREFP 0.57V
330pF 10nF 4.7uF 330pF 10nF 4.7uF
application needs (Refer to Table 'OPERATING CONDITIONS' page 2 for min/max values). The VREFP, VREFM voltages set the analog dynamic at the input of the converter that has a full scale amplitude of 2*(VREFP-VREFM). In case of analog dynamic lower than 2Vpp, the best linearity and distortion performance is achieved while increasing the VREFM voltage instead of lowering the VREFP one. The INCM is the mid voltage of the analog input signal. It is possible to use an external reference voltage device for specific applications requiring even better linearity, accuracy or enhanced temperature behavior. Using the STMicroelectronics TS821 or TS4041-1.2 Vref leads to optimum performances when configured as shown on Figure 2. Figure 2 : External reference setting
1k
330pF 10nF 4.7uF
VCCA VREFP VIN
TSA1001
VINB VREFM
TS821 TS4041 external reference
At 15Msps sampling frequency, 1MHz input frequency and -1dBFS amplitude signal, performances can be improved up to 2dBc on SFDR and 0.3dB on SINAD. At 25Msps sampling frequency, 1MHz input frequency and -1dBFS amplitude signal, performances can be improved up to 1dBc on SFDR and 0.5dB on SINAD. This can be very helpful for example for multichannel application to keep a good matching among the sampling frequency range.
TSA1001
VINB INCM VREFM
External reference and common mode Each of the voltages VREFM, VREFP and INCM can be fixed externally to better fit to the
13/20
TSA1001
DRIVING THE ANALOG INPUT Differential inputs The TSA1001 has been designed to obtain optimum performances when being differentially driven. An RF transformer is a good way to achieve such performances. Figure 3 describes the schematics. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs. Figure 3 : Differential input configuration with transformer
Analog source ADT1-1 1:1 VIN
50 100pF
configuration. Both inputs VIN and VINB are centered around the common mode voltage, that can be let internal or fixed externally. Figure 5 shows a DC-coupled configuration with forced INCM to the DC analog input (mid-voltage) while VREFM is connected to ground and VREFP is let internal; we achieve a 2Vpp differential amplitude. Figure 5 : DC-coupled 2Vpp differential analog input
analog DC analog DC
330pF 10nF
4.7uF
AC+DC VIN
VREFP
TSA1001
VINB
VREFM
TSA1001
VINB INCM
INCM
330pF
10nF
4.7uF
VREFP-VREFM = 1 V
Single-ended input configuration The common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.57V. The INCM is decoupled to maintain a low noise level on this node. Our evaluation board is mounted with a 1:1 ADT1-1WT transformer from Minicircuits. You might also use a higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on the analog signal source. For example, with internal references, each analog input can drive a 1Vpp amplitude input signal, so the resultant differential amplitude is 2Vpp. Figure 4 : AC-coupled differential input The single-ended input configuration of the TSA1001 requires particular biasing and driving. The structure being fully differential, care has to be taken in order to properly bias the inputs in single ended mode. Figure 6 summarizes the link from the differential configuration to the single-ended one; a wrong configuration is also presented. - With differential driving, both inputs are centered around the INCM voltage. - The transition to single-ended configuration implies to connect the unused input (VINB for instance) to the DC component of the single input (VIN) and also to the input common mode in order to be well balanced. The mid-code is achieved at the crossing between VIN and VINB, therefore inputs are conveniently biased. - Unlikely other structures of converters in which the unused channel can be grounded; in our case it will end with unbalanced inputs and saturation of the internal amplifiers leading to a non respect of the output codes.
50 common mode
10nF 100k 33pF 100k 10nF
VIN INCM
TSA1001
VINB
50
Figure 4 represents the biasing of a differential input signal in AC-coupled differential input
14/20
TSA1001
Figure 6 : Input dynamic range for the various configurations
Differential configuration +FS: code 1023 VIN - VINB +FS: code 1023 VIN - VINB VINB VIN INCM VIN 0: code 511 0: code 511 INCM VIN Single-ended configuration: balanced inputs Single-ended configuration: unbalanced inputs +FS + offset: code > 1023 VIN - VINB
INCM
-FS: code 0 -FS: code 0 Ao + ac VIN VINB Ao + ac VIN VINB Ao
-FS + offset: code > 0
Ao + ac
VIN VINB
Ao + ac
INCM Ao
INCM
INCM
Ao Wrong configuration!
The applications requiring single-ended inputs can be configured like reported on Figure 7 for an AC-coupled input or on Figure 8 and 9 for a DC-coupled input. In the case of AC-coupled analog input, the analog inputs VIN and VINB are biased to the same voltage that is the common mode voltage of the circuit (INCM). The INCM and reference voltages may remain at their internal level but can also be fixed externally. Figure 7 : AC-coupled Single-ended input
is let internal; we achieve a 2Vpp differential amplitude. Figure 8 : DC-coupled 2Vpp analog input
Analog DC
AC+DC VIN
VREFP
TSA1001
VINB
VREFM
INCM
330pF
10nF
4.7uF
VREFP-VREFM = 1 V
Signal source
10nF 50 common mode 33pF 100k
VIN INCM
100k
TSA1001
VINB
Figure 9 describes a configuration for a 1Vpp analog signal with a 0.5V DC input. In this case, while VREFP is kept internally at 1V, VREFM is connected to VINB and INCM externally to 0.5V; the dynamic is then 1Vpp (VREFP-VREFM=0.5V).
In the case of DC-coupled analog input with 1V DC signal, the DC component of the analog input set the common mode voltage. As an example figure 8, INCM is set to the 1V DC analog input while VREFM is connected to ground and VREFP
15/20
TSA1001
Figure 9 : DC-coupled 1Vpp analog input
Analog DC AC+DC VIN
Linearity, distortion performance towards Clock Duty Cycle variation The TSA1001 has an outstanding behaviour towards clock duty cycle variation. Linearity vs. Duty cycle Fs=25MSPS; Icca=11mA; Fin=10MHz
TSA1001
VINB VREFM INCM
70
0.5V power supply
10 9.8 ENOB 9.6 9.4 9.2 SNR SINAD 9 8.8 8.6 8.4 8.2 8 30 40 50 60 70
Dynamic parameters (dB)
330pF
10nF
4.7uF
68 66 64 62 60 58 56 54 52 50
Dynamic characteristics, while not being as remarkable as for differential configuration, are still of very good quality. Clock input The converter quality is very dependant on clock input accuracy, in terms of aperture jitter; the use of low jitter crystal controlled oscillator is recommended. The clock power supplies must be separated from the ADC output ones to avoid digital noise modulation at the output. It is recommended to keep the circuit clocked, to avoid random states, before applying the supply voltages. Power consumption optimization The internal architecture of the TSA1001 enables to optimize the power consumption according to the sampling frequency of the application. For this purpose, a resistor is placed between IPOL and the analog Ground pins. The TSA1001 will combine highest performances and lowest consumption at 25Msps when Rpol is equal to 25k. At lower sampling frequency range (< 10Msps), this value of resistor may be adjusted in order to decrease the analog current without any degradation of dynamic performances. As an example, 10mW total power consumption is achieved at 5 Msps with Rpol equal to 390k. The table below sums up the relevant data. Total power consumption optimization depending on Rpol value
Fs (Msps) Rpol (k) Optimized power (mW) 5 390 10 15 40 25 25 25 35
Duty Cycle (%)
Distortion vs. Duty cycle Fs=25MSPS; Icca=11mA; Fin=10MHz
-50
Dynamic Parameters (dB)
-55 -60 -65 -70 -75 -80 -85 -90 -95 -100 30 40 50 60 70
THD
SFDR
Duty Cycle (%)
16/20
ENOB (bits)
VREFP-VREFM = 0.5 V
TSA1001
Layout precautions To use the ADC circuits in the best manner at high frequencies, some precautions have to be taken for power supplies: - First of all, the implementation of 4 separate proper supplies and ground planes (analog, digital, internal and external buffer ones) on the PCB is recommended for high speed circuit applications to provide low inductance and low resistance common return. The separation of the analog signal from the digital part is essential to prevent noise from coupling onto the input signal. - Power supply bypass capacitors must be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion. - Proper termination of all inputs and outputs must be incorporated with output termination resistors; then the amplifier load will be only resistive and the stability of the amplifier will be improved. All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. - To keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. To minimize this output capacitance, buffers or latches close to the output pins will relax this constraint. - Choose component sizes as small as possible (SMD). EVAL1001 evaluation board The characterization of the board has been made with a fully ADC devoted test bench as shown on Figure 10. The analog signal must be filtered to be very pure. The dataready signal is the acquisition clock of the logic analyzer. The ADC digital outputs are latched by the octal buffers 74LCX573. All characterization measurements have been made with: SFSR=+0.2dB for static parameters. SFSR=-0.5dB for dynamic parameters.
Figure 10 : Analog to Digital Converter characterization bench
HP8644 Sine Wave Generator Vin ADC evaluation board
Data Logic Analyzer Clk Clk HP8133 Pulse Generator PC
HP8644
Sine Wave Generator
17/20
J9 DFSB J11 1 2 1 2 1 2 VCCB2 C34
+
J10 OEB J13 1 2
J17 VDDBUFF3V
R10 47K R11 47K R12 47K R13 47K C16 AVCC 470nF C15 10nF C14 R2 1K 330pF 330pF R14 R15 R16 R17 R18 R19 47K 47K 47K 47K 47K 47K 330pF 10nF C25 10nF C26 DR DO D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 74LCX573 C41 10F C29 6 2 4
+
1 2
C28 VCCB1 470nF C27 470nF C39
47 C37
J2 Raj1 47K
1 2
VrefP
J6
J5
1 2
VrefM 6 2 AGND AVCC AVCC DFSB OEB NC NC 2.5VCCBUFF GNDBUFF 2.5VCCBUFF DR D0 C1 100pF 470nF 10nF C30 330pF 470nF 10nF 330pF C32 C31 C13 C12 C11 48 47 46 45 44 43 42 41 40 39 38 37
Figure 11: TSA1001 Evaluation board schematic
J1 Vin
1
T2
R1 50 3
4 T2-AT1-1WT C10 8-14bits ADC TSA1001 74LCX573 470nF 10nF C7 C3 470nF 10nF AVCC 470nF 10nF 330pF 330pF C4 C2 DVCC DVCC DGND CLK DGND NC DGND GNDBUFF GNDBUFF 2.5VCCBUFF OR D13 C6 C5 330pF C9 C8
1 2 3 4 5 6 7 8 9 10 OEB VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 U2 D5 Q5 D6 Q6 D7 Q7 GND LE
20 19 18 17 16 15 14 13 12 11
J7
1 2
Regl com mode J8
1 2 13 14 15 16 17 18 19 20 21 22 23 24
1 2 3 4 5 6 7 8 9 10 11 12 Ipol VrefP VrefM AGND Vin AGND VINB AGND INCM AGND AVCC AVCC 1 2 3 4 5 6 7 8 9 10 OEB VCC D0 Q0 D1 U3 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 GND LE 20 19 18 17 16 15 14 13 12 11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12
36 35 34 33 32 31 30 29 28 27 26 25
Mes com Mode J12
2 1
AVCC
+
C42 47F
D13 C38 OR
J19 C20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 470nF C40 32PIN
1 2
AGND
J20 1 3 R3 50
1 2 10nF C22 470nF C23 10
+
330pF C21 10nF C19 470nF C24 10
+
10F C17 T1 T2-AT1-1WT 330pF C18
10nF C33 330pF
DGND
J21
1 2
GndB2 C36 47 2 1 J4 CLJ/SMB C35 47 VCCB1
J22
1 2 2 1
GndB1 J15 DVCC J16 CON2
J18 VccB1
2 1
TSA1001
18/20
TSA1001
Figure 12: Printed circuit board - Top side silkscreen
Printed circuit board - List of components
P ar t T ype 10 uF 10 uF 10 uF 10 uF 10 0pF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 1K 3 2P IN 3 30pF 3 30pF D es ign F o o t pr int at o r C2 4 C2 3 C4 1 C2 9 C1 C12 C3 9 C15 C4 0 C2 7 C4 C2 1 C3 1 C6 C9 C18 R2 J6 C2 5 C2 6 1210 1210 1210 1210 60 3 60 3 60 3 60 3 60 3 60 3 60 3 60 3 60 3 60 3 60 3 60 3 60 3 ID C 32 60 3 60 3 P ar t T ype 3 30 pF 3 30 pF 3 30 pF 3 30 pF 3 30 pF 3 30 pF 3 30 pF 3 30 pF 3 30 pF 4 7uF 4 7uF 4 7uF 4 7uF 4 70 nF 4 70 nF 4 70 nF 4 70 nF 4 70 nF 4 70 nF 4 70 nF D es i gn F o o t pr int at o r C 33 C 20 C8 C2 C5 C 11 C 30 C 17 C 14 C 36 C 34 C 35 C 42 C 22 C 32 C 37 C 38 C 13 C 28 C 10 60 3 60 3 60 3 60 3 60 3 60 3 60 3 60 3 60 3 CA P CA P CA P CA P 80 5 80 5 80 5 80 5 80 5 80 5 80 5 P ar t T ype 470 nF 470 nF 470 nF 470 nF 47K 47K 47K 47K 47K 47K 47K 47K 47K 47K 47K 50 50 D es ign F o o t pr int at o r C7 C 16 C 19 C3 R 12 R 14 R 11 R aj 1 R 10 R 19 R 13 R 15 R 16 R 17 R 18 R3 R1 8 05 8 05 8 05 8 05 6 03 6 03 6 03 VR 5 6 03 6 03 6 03 6 03 6 03 6 03 6 03 6 03 6 03 T S S OP 20 T S S OP 20 S IP 2 P ar t T ype A VC C C L J /S M B A GN D DF SB D GN D D VC C GndB 1 GndB 2 D es ign at o r J 12 J4 J 19 J9 J20 J 15 J22 J21 F IC H E 2M M S M B /H F IC H E 2M M F IC H E 2M M F IC H E 2M M F IC H E 2M M F IC H E 2M M F IC H E 2M M F IC H E 2M M F IC H E 2M M F IC H E 2M M AD T AD T F IC H E 2M M F IC H E 2M M S M B /H F IC H E 2M M F IC H E 2M M T QF P 48 F o o t pr int
M es co m mo de J 8 OE B J 10
R egl co m mo de J 7 T 2-A T 1-1W T T 2-A T 1-1W T VccB 1 VD D B U F F 3V Vin Vr ef M Vr ef P T S A 100 1 T2 T1 J 18 J 17 J1 J5 J2 U1
74L C X57 3 U 3 74L C X57 3 U 2 CON 2 J 16
19/20
TSA1001
PACKAGE MECHANICAL DATA 48 PINS - PLASTIC PACKAGE
A A2 48 1 e A1 37 36 0,10 mm .004 inch SEATING PLANE
12 13 24
25
E3 E1 E
D3 D1 D
L1
L
K
Millimeters Dim. Min. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.05 1.35 0.17 0.09 Typ. Max. 1.60 0.15 1.45 0.27 0.20
0,25 mm .010 inch GAGE PLANE
B
c
Inches Min. 0.002 0.053 0.007 0.004 Typ. Max. 0.063 0.006 0.057 0.011 0.008 1.40 0.22 9.00 7.00 5.50 0.50 9.00 7.00 5.50 0.60 1.00 0.055 0.009 0.354 0.276 0.216 0.0197 0.354 0.276 0.216 0.024 0.039 0.45 0.75 0.018
0.030
0 (min.), 7 (max.)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States (c) http://www.st.com
20/20

▲Up To Search▲

Price & Availability of 7333

	To Download 7333 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .