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M68Z512
4 Mbit (512Kb x8) Low Power SRAM with Output Enable
PRELIMINARY DATA
ULTRA LOW DATA RETENTION CURRENT - 100nA (typical) - 10A (max) OPERATION VOLTAGE: 5V 10% 512 Kbit x8 SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 70ns LOW VCC DATA RETENTION: 2V TRI-STATE COMMON I/O CMOS for OPTIMUM SPEED/POWER AUTOMATIC POWER-DOWN WHEN DESELECTED INTENDED FOR USE WITH ST ZEROPOWER AND TIMEKEEPER CONTROLLERS DESCRIPTION The M68Z512 is a 4 Mbit (4,194,304 bit) CMOS SRAM, organized as 524,288 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 5V 10% supply, and all inputs and outputs are TTL compatible. This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68Z512 is available in a 32 lead TSOP II (10 x 20mm) package.
32
1
TSOP II 32 (t.b.d. ) (10 x 20mm)
Figure 1. Logic Diagram
VCC
19 A0-A18
8 DQ0-DQ7
W
M68Z512
Table 1. Signal Names
A0-A18 DQ0-DQ7 E G W VCC VSS Address Inputs Data Inputs / Outputs Chip Enable Output Enable Write Enable Supply Voltage Ground
E G
VSS
AI03030
May 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M68Z512
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG VIO (2) VCC IO (3) PD Parameter Ambient Operating Temperature Storage Temperature Input or Output Voltages Supply Voltage Output Current Power Dissipation Value 0 to 70 -65 to 150 -0.3 to VCC + 0.3 -0.3 to 7.0 20 1 Unit C C V V mA W
Notes: 1. Except for the rating "Operating Temperature Range" stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Up to a maximum operating VCC of 5.5V only. 3. One output at a time, not to exceed 1 second duration.
Figure 2. TSOP Pin Connections
A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1
32
8 9
M68Z512
25 24
16
17
AI03031
VCC A15 A18 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
READ MODE The M68Z512 is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, and Chip Enable (E) is asserted. This provides access to data from eight of the 4,194,304 locations in the static memory array, specified by the 19 address inputs. Valid data will be available at the eight output pins within tAVQV after the last stable address, providing G is Low and E is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV or tGLQV) rather than the address. Data out may be indeterminate at tELQX and tGLQX, but data lines will always be valid at tAVQV. WRITE MODE The M68Z512 is in the Write mode whenever the W and E pins are Low. Either the Chip Enable input (E) or the Write Enable input (W) must be de-asserted during Address transitions for subsequent write cycles. Write begins with the concurrence of Chip Enable being active with W low. Therefore, address setup time is referenced to Write Enable and Chip Enable as tAVWL and tAVEH respectively, and is determined by the latter occurring edge. The Write cycle can be terminated by the earlier rising edge of E, or W.
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M68Z512
Table 3. Operating Modes
Mode Read Read Write Deselect
Note: X = VIH or VIL
E VIL VIL VIL VIH
W VIH VIH VIL X
G VIH VIL X X
DQ0-DQ7 Hi-Z Data Output Data Input Hi-Z
Power Active Active Active Standby
Table 4. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 5ns 0 to 3V 1.5V
Figure 4. AC Testing Load Circuit
5.0V
Note that Output Hi-Z is defined as the point where data is no longer driven.
DEVICE UNDER TEST 994
1838
OUT
If the Output is enabled (E = Low and G = Low), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for tDVEH before the rising edge of E, whichever occurs first, and remain valid for tWHDX or tEHDX. OPERATIONAL MODE The M68Z512 has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E = High). An Output Enable (G) signal provides a high speed tri-state control, allowing fast read/write cycles to Table 5. Capacitance (1) (TA = 25 C, f = 1 MHz)
Symbol CIN COUT
(2)
CL = 100pF or 5pF
CL includes JIG capacitance
AI03032
be achieved with the common I/O data bus. Operational modes are determined by device control inputs W and E as summarized in the Operating Modes table.
Parameter Input Capacitance on all pins (except DQ) Output Capacitance
Test Condition TA = 25C, f = 1MHz, VCC = 5V TA = 25C, f = 1MHz, VCC = 5V
Min
Max 6 8
Unit pF pF
Notes: 1. Sampled only, not 100% tested 2. Outputs deselected
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M68Z512
Figure 3. Block Diagram
VCC VSS (10) A CHIP ENABLE. DQ (8) DQ INPUT DATA CTRL I/O CIRCUITS COLUMN DECODER ROW DECODER MEMORY ARRAY
A
CHIP ENABLE. (9) A E W A
G
AI03033
Table 6. DC Characteristics (TA = 0 to 70 C; VCC = 5V 10%)
Symbol ILI ILO ICC1 (1) ICC2
(2)
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Test Condition 0V VIN VCC 0V VOUT VCC VCC = 5.5V, (-55) VCC = 5.5V, E = VIH VCC = 5.5V, E VCC - 0.3V, f=0
Min
Typ
Max 1 1 90 15
Unit A A mA mA A V V V V
ICC3 (3) VIL VIH VOL VOH
1.6 -0.3 2.2
20 0.8 VCC + 0.3 0.4
IOL = 2.1mA IOH = -1mA 2.4
Notes: 1. Average AC current, Outputs open, cycling at tAVAV minimum 2. All other Inputs at VIL 0.8V or VIH 2.2V 3. All other Inputs at VIL 0.3V or VIH VCC - 0.3V
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M68Z512
Table 7. Read and Standby Modes AC Characteristics (TA = 0 to 70C; VCC = 5V 10%)
M68Z512 Symbol Parameter Min tAVAV tAVQV (1) tELQV tGLQV tELQX
(1) (1) (3)
-70 Max
Unit
Read Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition Chip Enable Low to Power Up Chip Enable High to Power Down
70 70 70 35 10 5 25 25 10 0 70
ns ns ns ns ns ns ns ns ns ns ns
tGLQX (3) tEHQZ tGHQZ
(2,3) (2,3) (1)
tAXQX tPU tPD
Notes: 1. CL = 100pF (see Figure 4) 2. CL = 5pF (see Figure 4) 3. At any given temperature and voltage condition, tEHQZ is less than tELQX and tGHQZ is less than tGLQX for any given device.
Figure 5. Address Controlled, Read Mode AC Waveforms
tAVAV A0-A18 tAVQV VALID tAXQX
DQ0-DQ7
DATA VALID
AI03034
Note: E1 = Low, E2 = High, G = Low, W = High
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M68Z512
Figure 6. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV A0-A18 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID
AI03035
VALID tAXQX tEHQZ
tGHQZ
Note: Write Enable (W) = High
Figure 7. Standby Mode AC Waveforms
E ICC1 ICC2 tPU 50% tPD
AI03036
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M68Z512
Table 8. Write Mode AC Characteristics (TA = 0 to 70C; VCC = 5V 10%)
M68Z512 Symbol Parameter Min tAVAV tAVWL tAVWH tAVEH tWLWH tWHAX tWHDX tWHQX
(2)
-70 Max
Unit
Write Cycle Time Address Valid to Write Enable Low Address Valid to Write Enable High Address Valid to Chip Enable High Write Enable Pulse Width Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Output Transition Write Enable Low to Output Hi-Z Address Valid to Chip Enable Low Chip Enable Low to Chip Enable High Chip Enable High to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable High
70 0 60 60 55 0 0 5 25 0 45 0 25 25
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tWLQZ (1,2) tAVEL tELEH tEHAX tDVWH tDVEH
Note: 1. CL = 5pF (see Figure 4) 2. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device.
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M68Z512
Figure 8. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A18 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI03037
tWHAX
tWHQX
Note: Output Enable (G) = Low
Figure 9. Chip Enable Controlled, Write AC Waveforms (1,2)
tAVAV A0-A18 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI03038
tELEH
tEHAX
Notes: 1. Output Enable (G) = High 2. If E goes High with W high, the output remains in a high-impedance state.
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M68Z512
Table 9. Low VCC Data Retention Characteristics (TA = 0 to 70C)
Symbol ICCDR VDR tCDR tER (2)
(1)
Parameter Supply Current (Data Retention) Supply Voltage (Data Retention) Chip Disable to Power Down Operation Recovery Time
Test Condition VCC = 3V, E VCC - 0.3V E VCC - 0.3V or E2 0.3V, f = 0 E VCC - 0.3V or E2 0.3V, f = 0
Min
Typ 0.1
Max 10
Unit A V ns ns
2 0 tAVAV
Note: 1. Typical condition: TA = 25C 2. See Figure 10 for measurement points. Guaranteed but not tested. tAVAV is Read cycle time.
Figure 10. Low VCC Data Retention AC Waveforms
DATA RETENTION MODE 5V VCC 3V VDR > 2.0V tCDR E VDR - 0.3V E 2.2V tER
AI03039
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M68Z512
ORDERING INFORMATION SCHEME Example: M68Z512 -70 1
Speed -70 70 ns t.b.d.
Package TSOP II 32 (10 x 20mm)
Temperature Range 1 0 to 70 C
For a list of available options (Speed, Package, etc... ) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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M68Z512
TSOP II 32 - 32 lead Plastic Thin Small Outline II (10 x 20mm)
Symbol Typ A A1 A2 B C D D1 E e L a N CP 1.27 0.05 0.95 0.30 0.12 11.56 10.03 20.82 0.40 0 32 0.10 mm Min Max 1.20 0.15 1.05 0.52 0.21 11.96 10.29 21.08 0.60 5 0.050 0.002 0.037 0.012 0.004 0.455 0.395 0.820 0.016 0 32 0.004 Typ inches Min Max 0.047 0.007 0.041 0.020 0.008 0.471 0.405 0.830 0.024 5
E
16
1
D1
D
17
32
B
e
A
A2 C A1 CP L
TSOP-d
Drawing is not to scale
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M68Z512
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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