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ADE-203-124G (Z)
HN58C257 Series
32768-word x 8-bit Electrically Erasable and Programmable CMOS ROM
Rev. 7.0 May. 25, 1995
The Hitachi HN58C257 is a electrically erasable and programmable ROM organized as 32768-word x 8-bit. It realizes high speed, low power consumption, and a high level of reliability, employing advanced MNOS memory technology and CMOS process and circuitry technology. It also has a 64-byte page programming function to make its erase and write operations faster.
Ordering Information
Type no. HN58C257T-20 Access time Package 200 ns 32-pin plastic TSOP (TFP-32DA)
Features
* * * * * * Single 5 V supply On-chip latches: address, data, CE, OE, WE Automatic byte write: 10 ms max Automatic page write (64 bytes): 10 ms max Fast access time: 200 ns max Low power dissipation: 20 mW/MHz typ (active) 1.1 mW max (standby) Data polling Data protection circuit on power on/off Conforms to JEDEC byte-wide standard Reliable CMOS with MNOS cell technology 105 erase/write cycles (in page mode) 10 years data retention Write protection by RES pin
* * * * * * *
HN58C257 Series
Pin Arrangement
HN58C257T series
A2 A1 A0 NC I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 NC CE A10 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A3 A4 A5 A6 A7 A12 A14 RDY/Busy VCC RES WE A13 A8 A9 A11 OE
(Top view)
Pin Description
Pin name A0-A14 I/O0-I/O7 OE CE WE VCC VSS RES RDY/Busy Function Address inputs Data input/output Output enable Chip enable Write enable Power (+5 V) Ground Reset Ready /Busy
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HN58C257 Series
Block Diagram
I/O0 VCC VSS RES OE CE WE Control Logic and Timing High Voltage Generator
I/O7
RDY/Busy
I/O Buffer and Input Latch
A0 A5 Address Buffer and Latch A6 A14
Y Decoder
Y Gating
X Decoder
Memory Array
Data Latch
Mode Selection
Pin Mode Read Standby Write Deselect Write inhibit Data polling Program reset Note: CE (31) VIL VIH VIL VIL x x VIL x OE (1) VIL x*2 VIH VIH x VIL VIL x WE (6) VIH x VIL VIH VIH x VIH x VOL High-Z VH VIL Data out (I/O7) High-Z RDY/Busy (9) High-Z High-Z High-Z to VOL High-Z High-Z RES (7) VH*1 x VH VH x I/O (21-23, 25-29) Dout High-Z Din High-Z --
1. Refer to the recommended DC operating condition. 2. x = Don't care
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HN58C257 Series
Absolute Maximum Ratings
Parameter Supply voltage *1 Input voltage *1 Operationg temperature range *3 Storage temperature range Symbol VCC Vin Topr Tstg Value -0.6 to +7.0 -0.5*2 to +7.0 0 to +70 -55 to +125 Unit V V C C
Notes: 1. With respect to VSS 2. Vin min = -3.0 V for pulse width 50 ns 3. Including electrical characteristics and data retention
Recommended DC Operating Conditions
Parameter Supply voltage Input voltage Symbol VCC VIL VIH VH Operating temperature Topr Min 4.5 -0.3 2.2 VCC - 0.5 0 Typ 5.0 -- -- -- -- Max 5.5 0.8 VCC + 1.0 VCC + 1.0 70 Unit V V V V C
DC Characteristics (Ta=0 to +70C, VCC = 5.0 V 10 %)
Parameter leakage current Output leakage current VCC current (standby) VCC current (active) Symbol Min ILI ILO ICC1 ICC2 ICC3 -- -- -- -- -- -- Input low voltage Input high voltage VIL VIH VH Output low voltage Output high voltage Note: VOL VOH -0.3*2 2.2 VCC-0.5 -- 2.4 Typ -- -- -- -- -- -- -- -- -- -- -- Max 2*1 2 200 1 12 30 0.8 Unit Test conditionsInput A A A mA mA mA V VCC = 5.5 V, Vin = 5.5 V VCC = 5.5 V, Vout = 5.5/0.4 V CE = VCC CE = VIH Iout = 0 mA, Duty = 100%, Cycle = 1 s at VCC = 5.5 V Iout = 0 mA, Duty = 100%, Cycle = 200 ns at VCC = 5.5 V
VCC + 1.0 V VCC + 1.0 V 0.4 -- V V IOL = 2.1 mA IOH = -400 A
1. ILI on RES = 100 A max 2. VIL min = -1.0 V for pulse width 50 ns
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HN58C257 Series
Capacitance (Ta = 25C, f = 1 MHz)
Parameter Input capacitance*1 Output capacitance*1 Note: Symbol Cin Cout Min -- -- Typ -- -- Max 6 12 Unit pF pF Test condition Vin = 0 V Vout = 0 V
1. This parameter is periodically sampled and not 100% tested.
AC Characteristics (Ta = 0 to +70C, VCC = 5.0 V 10 %)
Test Conditions * Input pulse levels : 0.4 V to 2.4 V 0V to VCC (RES pin) * Input rise and fall time : 20 ns * Output load : 1TTL Gate +100 pF * Reference levels for measuring timing : 0.8 V, 2.0 V Read Cycle
Parameter Address to output delay CE to output delay OE to output delay OE (CE) high to output float*1 RES low to output float*1 Data output hold RES to output delay Note: Symbol tACC tCE tOE tDF tDFR tOH tRR Min -- -- 10 0 0 0 0 Max 200 200 90 70 350 -- 450 Unit ns ns ns ns ns ns ns Test conditions CE = OE = VIL, WE = VIH OE = VIL, WE = VIH CE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = OE = VIL, WE = VIH
1. tDF, tDFR are defined at which the outputs achieve the open circuit conditions and are no longer driven.
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HN58C257 Series
Read Timing Waveform
Address t ACC CE tCE OE tOE WE High tDF tOH
Data Out t RR
Data Out Valid
RES
t DFR
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HN58C257 Series
Write Cycle
Parameter Address setup time Address hold time CE to write setup time (WE controlled) CE hold time (WE controlled) WE to write setup time (CE controlled) WE hold time (CE controlled) OE to write setup time OE hold time Data setup time Data hold time WE pulse width (WE controlled) CE pulse width (CE controlled) Data latch time Byte load cycle Byte load window Write cycle time Time to device busy Write start time Reset protect time Reset low time Note: Symbol tAS tAH tCS tCH tWS tWH tOES tOEH tDS tDH tWP tCW tDL tBLC tBL tWC tDB tDW tRP tRES Min*1 0 150 0 0 0 0 0 0 100 0 150 150 200 0.35 100 -- 120 150*3 100 1 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- 30 -- 10*2 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s ms ns ns s s Test conditions
1. Use this device in longer cycle than this value. 2. tWC must be longer than this value unless polling technique or RDY/Busy are used. This device automatically completes the internal write operation within this value. 3. Next read or write operation can be initiated after tDW if polling technique or RDY/Busy are used.
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HN58C257 Series
Byte Write Timing Waveform(1) (WE Controlled)
t WC Address t CS CE t AS tWP WE t OES OE t DS Din t DW RDY/Busy High-Z tRP t DB High-Z t DH t OEH t BL t AH t CH
tRES RES V CC
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HN58C257 Series
Byte Write Timing Waveform(2) (CE Controlled)
Address t WS CE t AS WE t OES OE t DS Din t DW High-Z t RP t DB High-Z t DH t OEH t AH t CW t WH t BL t WC
RDY/Busy
t RES RES
V CC
9
HN58C257 Series
Page Write Timing Waveform (1)(WE Controlled)
Address A6 to A14
Address A0 to A5 t AS WE t CS CE
t AH t WP t DL t CH
t BLC
t BL
t WC
t OEH t OES OE t DH t DS
Din t DW RDY/Busy High-Z t DB High-Z
t RP
RES t RES VCC
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HN58C257 Series
Page Write Timing Waveform (2)(CE Controlled)
Address A6 to A14
Address A0 to A5 t AS CE t WS WE
t AH t CW t DL t WH
t BLC
t BL
t WC
t OEH t OES OE t DH t DS
Din t DW RDY/Busy High-Z t DB High-Z
t RP
RES t RES VCC
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HN58C257 Series
Data Polling Timing Waveform
Address
An
An
An
CE
WE t BL OE
t CE t OES
t OE I/O7 Din X Dout X t WC Dout X
t DW
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HN58C257 Series
Functional Description
Automatic Page Write Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write cycle. Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each additional byte load cycle must be started within 30 s from the preceding falling edge of WE or CE. When CE or WE is high for 100 s after data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM. Data Polling polling allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a write cycle, an inversion of the last byte of data to be loaded outputs from I/O7 to indicate that the EEPROM is performing a write operation.
Data
WE, CE Pin Operation During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising edge of WE or CE. Write/Erase Endurance and Data Retention Time The endurance is 105 cycles in case of the page programming and 10 4 cycles in case of byte programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is page-programmed less than 104 cycles. Data Protection 1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming mode by mistake. To prevent this phenomenon, this device has a noise cancelation function that cuts noise if its width is 20 ns or less in program mode. Be careful not to allow noise of a width of more than 20 ns on the control pins.
RDY/Busy Signal RDY/Busy signal also allows the status of the EEPROM to be determined. The RDY/Busy signal has high impedance except in write cycle and is lowered to VOL after the first write signal. At the end of a write cycle, the RDY/Busy signal changes state to high impedance. RES Signal When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping RES low when VCC is switched. RES should be high during read and programming because it dosen't provide a latch function.
WE CE
5V 0V
5V OE 0V
VCC
Read inhibit
Read inhibit
RES
20 ns max
Program inhibit Program inhibit
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HN58C257 Series
2. Data Protection at VCC On/Off When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may turn the EEPROM to programming mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in unprogrammable state by using a CPU reset signal to RES pin. RES pin should be kept at VSS level when VCC is turned on or off. The EEPROM breaks off programming operation when RES becomes low, programming operation doesn't finish correctly in case that RES falls low during programming operation. RES should be kept high for 10 ms after the last data input.
VCC
RES Program inhibit WE or CE Program inhibit
1 s min 100 s min
10 ms min
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HN58C257 Series
Package Dimensions
HN58C257T Series (TFP-32DA) Unit : mm
8.0 8.2 Max 32 17
1
16 0.50
0.20 0.10
0.08 M 0.17 0.05 0-5 0.08 Min 0.18 Max 0.5 0.1
0.45 Max
1.2 Max
0.10
12.4
14.0 0.2
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