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CS5525 CS5526
16-Bit/20-Bit Multi-Range ADC with 4-Bit Latch
Features General Description
The 16-bit CS5525 and the 20-bit CS5526 are highly integrated A/D converters which include an instrumentation amplifier, a PGA (programmable gain amplifier), eight digital filters, and self and system calibration circuitry. The converters are designed to provide their own negative supply which enables their on-chip instrumentation amplifiers to measure bipolar ground-referenced signals 100 mV. By directly supplying NBV with -2.5 V and with VA+ at 5 V, 2.5 V signals (with respect to ground) can be measured. The digital filters provide programmable output update rates between 3.76 Hz to 202 Hz (XIN = 32.768 kHz). Output word rates can be increased by approximately 3X by using XIN = 100 kHz. Each filter is designed to settle to full accuracy for its output update rate in one conversion cycle. The filters with word rates of 15 Hz or less (XIN = 32.768 kHz) reject both 50 and 60 Hz (3 Hz) line interference simultaneously. Low power, single conversion settling time, programmable output rates, and the ability to handle negative input signals make these single supply products ideal solutions for isolated and non-isolated applications. ORDERING INFORMATION See page 26.
l Delta-Sigma A/D Converter l Bipolar/Unipolar Input Ranges l Chopper Stabilized Instrumentation Amplifier l On-Chip Charge Pump Drive Circuitry l 4-Bit Output Latch l Simple three-wire serial interface l Programmable Output Word Rates
- SPITM and MicrowireTM Compatible - Schmitt Trigger on Serial Clock (SCLK) - 3.76 Hz to 202Hz (XIN = 32.768 kHz) - 11.47 Hz to 616 Hz (XIN = 100 kHz) - 25 mV, 55 mV, 100 mV, 1 V, 2.5 V and 5 V - Linearity Error: 0.0015%FS - Noise Free Resolution: 18-bits
l Output Settles in One Conversion Cycle l Simultaneous 50/60 Hz Noise Rejection l System and Self-Calibration with
Read/Write Registers l Single +5 V Analog Supply +3.0 V or +5 V Digital Supply l Low Power Mode Consumption: 4 mW
- 1.8 mW in 1 V, 2.5 V, and 5 V Input Ranges
VA+ AGND VREF+
VREF-
DGND
VD+
AIN+ AIN-
+ X20 -
Programmable Gain
Differential 4th Order Delta-Sigma Modulator
Digital Filter
Calibration Register
CS SCLK
NBV A0 A1 A2 A3
Control Register
SDI
Latch Calibration Memory Calibration C Clock Gen.
Output Register
SDO
CPD
XIN XOUT
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com
Copyright (c) Cirrus Logic, Inc. 1998 (All Rights Reserved)
JAN `98 DS202F1 1
CS5525 CS5526
(TA = 25 C; VA+, VD+ = 5 V 5%; VREF+ = 2.5 V, VREF- = AGND, NBV = -2.1 V, FCLK = 32.768 kHz, OWR (Output Word Rate) = 15 Hz, Bipolar Mode, Input Range = 100 mV; See Notes 1 and 2.) CS5525 Parameter Min 16 1 Typ Max Min 20 1 CS5526 Typ Max Unit %FS Bits LSB LSB nV/C ppm ppm ppm/C V dB dB pF A/V
ANALOG CHARACTERISTICS
Accuracy Linearity Error No Missing Codes Bipolar Offset (Note 3) Unipolar Offset (Note 3) Offset Drift (Notes 3 and 4) Bipolar Gain Error Unipolar Gain Error Gain Drift (Note 4) Voltage Reference Input Range (VREF+) - (VREF-) Common Mode Rejection dc 50, 60 Hz Input Capacitance CVF Current (Note 5)
0.0015 0.003 1 2 20 8 16 1 2.5 110 130 16 0.6 2 4 31 62 3 3.0 -
0.0007 0.0015 16 32 20 8 16 1 2.5 110 130 16 0.6 32 64 31 62 3 3.0 -
Notes: 1. Applies after system calibration at any temperature within -40 C ~ +85 C. 2. Specifications guaranteed by design, characterization, and/or test. 3. Specification applies to the device only and does not include any effects by external parasitic thermocouples. LSB = LSB16 for the CS5525, and LSB20 for the CS5526. 4. Drift over specified temperature range after calibration at power-up at 25 C. 5. See the section of the data sheet which discusses input models on page 15.
RMS NOISE (Notes 6 and 7)
Output Rate -3 dB Filter (Hz) Frequency 3.76 3.27 7.51 6.55 15.0 12.7 30.1 25.4 60.0 50.4 123.2 (Note 8) 103.6 168.9 (Note 8) 141.3 202.3 (Note 8) 169.2 25 mV 90 nV 110 nV 170 nV 250 nV 500 nV 2.0 V 10 V 30 V Input Range, (Bipolar/Unipolar Mode) 55 mV 100 mV 1V 2.5 V 90 nV 130 nV 1.0 V 2.0 V 130 nV 190 nV 1.5 V 3.0 V 200 nV 250 nV 2.0 V 5.0 V 300 nV 500 nV 4.0 V 10 V 1.0 V 1.5 V 15 V 45 V 4.0 V 8.0 V 72 V 190 V 20.0 V 30 V 340 V 900 V 55 V 105 V 1.1 mV 2.4 mV 5V 4.0 V 7 V 10 V 15 V 85 V 350 V 2.0 mV 5.3 mV
Notes: 6. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 C. 7. For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates. 8. For input ranges <100 mV and output word rates >60 Hz, 32.768 kHz chopping frequency is used. Specifications are subject to change without notice.
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CS5525 CS5526
ANALOG CHARACTERISTICS (Continued)
Parameter Min Typ Max Unit
Analog Input Common Mode + Signal on AIN+ or AINBipolar/Unipolar Mode NBV = -1.8 to -2.5 V Range = 25 mV, 55 mV, or 100 mV Range = 1 V, 2.5 V, or 5 V NBV = AGND Range = 25 mV, 55 mV, or 100 mV Range = 1 V, 2.5 V, or 5 V Common Mode Rejection dc 50, 60 Hz Input Capacitance CVF Current on AIN+ or AIN(Note 5) Range = 25 mV, 55 mV, or 100 mV Range = 1 V, 2.5 V, or 5 V System Calibration Specifications Full Scale Calibration Range Bipolar/Unipolar Mode (Note 9) 25 mV 55 mV 100 mV 1V 2.5 V 5V Offset Calibration Range Bipolar/Unipolar Mode 25 mV 55 mV 100 mV (Note 10) 1V 2.5 V 5V Power Supplies DC Power Supply Currents (Normal Mode) IA+ ID+ INBV
Power Consumption Normal Mode Low Power Mode Standby Sleep dc Positive Supplies dc NBV (Note 11)
-0.150 NBV 1.85 0.0 -
120 120 10 100 1.2
0.950 VA+ 2.65 VA+ 300 -
V V V V dB dB pF pA A/V
17.5 38.5 70 0.70 1.75 3.50 -
1.3 15 400 7.5 4.0 1.2 500 95 110
32.5 71.5 105 1.30 3.25 VA+ 12.5 27.5 50 0.5 1.25 2.50 1.7 30 550 10 6.5 -
mV mV mV V V V mV mV mV V V V mA A A mW mW mW W dB dB
Power Supply Rejection
Notes: 9. The minimum Full Scale Calibration Range (FSCR) is limited by the maximum allowed gain register value (with margin). The maximum FSCR is limited by the modulator's 1's density range. 10. The maximum full scale signal can be limited by saturation of circuitry within the internal signal path. 11. All outputs unloaded. All input CMOS levels.
DS202F1
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CS5525 CS5526
5 V DIGITAL CHARACTERISTICS (TA = 25 C; VA+, VD+ = 5 V 5%; GND = 0;
See Notes 2 and 12.)) Parameter High-Level Input Voltage All Pins Except XIN and SCLK XIN SCLK All Pins Except XIN and SCLK XIN SCLK Symbol VIH Min 0.6 VD+ 3.5 (VD+) - 0.45 0.0 (VA+) - 1.0 (VD+) - 1.0 (VD+) - 1.0 VOL Iin IOZ Cout 1 9 0.4 0.4 0.4 10 10 V V V A A pF Typ Max VD+ 0.8 1.5 0.6 Unit V V V V V V V V V
Low-Level Input Voltage
VIL
High-Level Output Voltage All Pins Except CPD and SDO (Note 13) CPD, Iout = -4.0 mA SDO, Iout = -5.0 mA Low-Level Output Voltage All Pins Except CPD and SDO, Iout = 1.6 mA CPD, Iout = 2 mA SDO, Iout = 5.0 mA Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance Notes: 12. All measurements performed under static conditions.
VOH
13. Iout = -100 A unless stated otherwise. (VOH = 2.4 V @ Iout = -40 A.)
3.0 V DIGITAL CHARACTERISTICS
See Notes 2 and 12.)) Parameter High-Level Input Voltage
(TA = 25 C; VA+ = 5 V 5%; VD+ = 3.0 V 10%; GND = 0; Symbol VIH Min 0.6 VD+ 0.54 VA+ (VD+) - 0.45 0.0 (VA+) - 0.3 (VD+) - 1.0 (VD+) - 1.0 VOL Iin IOZ Cout 1 9 0.3 0.4 0.4 10 10 V V V A A pF Typ Max VD+ 0.16 VD+ 1.5 0.6 Unit V V V V V V V V V
All Pins Except XIN and SCLK XIN SCLK All Pins Except XIN and SCLK XIN SCLK
Low-Level Input Voltage
VIL
High-Level Output Voltage All Pins Except CPD and SDO, Iout = -400 A CPD, Iout = -4.0 mA SDO, Iout = -5.0 mA Low-Level Output Voltage All Pins Except CPD and SDO, Iout = 400 A CPD, Iout = 2 mA SDO, Iout = 5.0 mA Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance
VOH
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CS5525 CS5526
DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Frequency Filter Settling Time to 1/2 LSB (Full Scale Step) Symbol fs ts Ratio XIN/2 1/fout Unit Hz s
RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0 V; See Note 14.))
Parameter DC Power Supplies Analog Reference Voltage Negative Bias Voltage Notes: 14. All voltages with respect to ground. Positive Digital Positive Analog (VREF+) - (VREF-) Symbol VD+ VA+ VRefdiff NBV Min 2.7 4.75 1.0 -1.8 Typ 5.0 5.0 2.5 -2.1 Max 5.25 5.25 3.0 -2.5 Unit V V V V
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V; See Note 14.)
Parameter DC Power Supplies (Note 15) Positive Digital Positive Analog Negative Potential (Note 16 and 17) (Note 18) VREF pins AIN Pins Symbol VD+ VA+ NBV IIN IOUT PDN VINR VINA VIND TA Tstg Min -0.3 -0.3 +0.3 -0.3 NBV - 0.3 -0.3 -40 -65 Max +6.0 +6.0 -3.0 10 25 500 (VA+) + 0.3 (VA+) + 0.3 (VD+) + 0.3 85 150 Unit V V V mA mA mW V V V C C
Negative Bias Voltage Input Current, Any Pin Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: 15. No pin should go more negative than NBV - 0.3 V. 16. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins. 17. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is 50 mA. 18. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
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CS5525 CS5526
(TA = 25 C; VA+ = 5 V 5%; VD+ = 3.0 V 10% or 5 V 5%; Input Levels: Logic 0 = 0 V, Logic 1 = VD+; CL = 50 pF.)) Parameter Master Clock Frequency (Note 19) Internal Clock External Clock (Note 20) Any Digital Input Except SCLK SCLK Any Digital Output (Note 20) Any Digital Input Except SCLK SCLK Any Digital Output XTAL = 32.768 kHz (Note 21) Symbol XIN 30 30 40 trise tfall tost tpor 50 500 1003 1.0 100 s s ns ms XIN cycles MHz ns ns ns ns ns ns ns ns ns ns 50 1.0 100 s s ns 32.768 32.768 36 100 60 kHz % Min Typ Max Unit
SWITCHING CHARACTERISTICS
Master Clock Duty Cycle Rise Times
Fall Times
Start-up Oscillator Start-up Time
Power-on Reset Period
Serial Port Timing Serial Clock Frequency SCLK Falling to CS Falling for continuous running SCLK (Note 22) Serial Clock Pulse Width High Pulse Width Low SDI Write Timing CS Enable to Valid Latch Clock
Data Set-up Time prior to SCLK rising Data Hold Time After SCLK Rising SCLK Falling Prior to CS Disable
SCLK t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
0 100 250 250 50 50 100 100 -
-
2 150 150 150
SDO Read Timing CS to Data Valid
SCLK Falling to New Data Bit CS Rising to SDO Hi-Z
Notes: 19. Device parameters are specified with a 32.768 kHz clock; however, clocks up to 100 kHz can be used for increased throughput. 20. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 21. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. 22. Applicable when SCLK is continuously running.
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DS202F1
CS5525 CS5526
CS
t0
t3
t1
t6
SCLK
t2
Continuous Running SCLK Timing (Not to Scale)
CS
t3
SDI
MSB
t4
MSB-1
t5 t1
LSB
t6
SCLK
t2
SDI Write Timing (Not to Scale)
CS
t7 t9
SDO
MSB
t8
MSB-1
t2
LSB
SCLK
t1
SDO Read Timing (Not to Scale)
DS202F1
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CS5525 CS5526
GENERAL DESCRIPTION
The CS5525 and CS5526 are 16-bit and 20-bit pin compatible converters which include a chopperstabilized instrumentation amplifier input, and an on-chip programmable gain amplifier. They are both optimized for measuring low-level unipolar or bipolar signals in process control and medical applications. The CS5525/26 also include a fourth order deltasigma modulator, a calibration microcontroller, eight digital filters, a 4-bit analog latch, and a serial port. The digital filters provide any one of eight different output update rates. The CS5525/26 include a CPD (Charge Pump Drive) output (shown in Figure 1). CPD provides a negative bias voltage to the on-chip instrumentation amplifier when used with a combination of external diodes and capacitors. This enables the CS5525/26 to measure negative voltages with re+5V Analog Supply
spect to ground, making the converters ideal for thermocouple temperature measurements.
Theory of Operation
The CS5525/26 A/D converters are designed to operate from a single +5 V analog supply and provide several different input ranges. See the Analog Characteristics section on page 3 for details. Figure 1 illustrates the CS5525/26 connected to generate their own negative bias supply using the on-chip CPD (Charge Pump Drive). This enables the CS5525/26 to measure ground referenced signals with magnitudes down to NBV (Negative Bias Voltage, approximately -2.1 V in this example). Figure 2 illustrates a charge pump circuit when the converters are powered from a +3.0 V digital supply. Alternatively, the negative bias supply can be generated from a negative supply voltage or a resistive divider as illustrated in Figure 3.
10
0.1 F
0.1 F
2 VA+ 2.5V 20 19 Up to 100 mV Input 10 k BAV199 0.1 F 10 k Note: Cold-junction measurement is performed by a second A/D or via a multiplexer. Logic Outputs: A0 - A3 Switch from VA+ to AGND. 4 1 16 15 7 6 AINAGND A3 A2 A1 A0 NBV 5 VREF+ VREF-
13 VD+ XOUT 10 32.768 ~ 100 kHz Optional Clock Source
XIN
9
3
AIN+
CS5525 CS5526 18 CS 11 SCLK 17 SDI 14 SDO
Serial Data Interface
CPD DGND 8 12 *5M
0.015 F
* Optional, see Charge Pump Drive section. Charge-pump network for VD+ = 5V only and XIN = 32.768 kHz.
1N4148 10 F +
1N4148
Figure 1. CS5525/26 Configured to use on-chip charge pump to supply NBV.
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DS202F1
CS5525 CS5526
Figure 4 illustrates the CS5525/26 connected to measure ground referenced unipolar signals of a positive polarity using the 1 V, 2.5 V, and 5 V input voltage ranges on the converter. For the 25 mV, 55 mV, and 100 mV ranges the signal must have a common mode near +2.5 V (NBV = 0V). The CS5525/26 are optimized for the measurement of thermocouple outputs, but they are also well suited for the measurement of ratiometric bridge transducer outputs. Figure 5 illustrates the CS5525/26 connected to measure the output of a ratiometric differential bridge transducer while operating from a single +5 V supply.
2N5087 or similar NBV 10F +
34.8K NBV 30.1K
2.0K
+
10 F
2.1K
-5V
-5V
Figure 2. Charge Pump Drive Circuit for VD+ = 3 V.
Figure 3. Alternate NBV Circuits.
+5V Analog Supply
10
0.1 F 0.1 F
2 VA+
13 VD+ XOUT 10 32.768 ~ 100 kHz Optional Clock Source
2.5V
20 19
VREF+ VREFCS5525 CS5526
XIN
9
3 0 to +5V Input + CM = 0 to VA+ 4 1 16 15 7 6
AIN+
18 CS AIN11 SCLK AGND 17 A3 SDI A2 14 SDO A1 A0 NBV CPD DGND 5 8 12
Serial Data Interface
Figure 4. CS5525/26 Configured for ground-referenced Unipolar Signals.
DS202F1
9
CS5525 CS5526
+5V Analog Supply
10
0.1 F
0.1 F 2 VA+ 20 19 VREF+ VREFAIN+ CS5525 CS5526 13 VD+ XOUT 10 32.768 ~ 100kHz Optional Clock Source
-
30mV F.S.
+
XIN
9
3
4 1 16 15 7 6
18 CS 11 AINSCLK AGND 17 A3 SDI 14 A2 SDO A1 A0 NBV CPD DGND 5 8 12
Serial Data Interface
Figure 5. CS5525/26 Configured for Single Supply Bridge Measurement.
System Initialization
When power to the CS5525/26 is applied, they are held in a reset condition until their 32.768 kHz oscillators have started and their start-up counter-timer elapses. Due to the high Q of a 32.768 kHz crystal, the oscillators take 400-600 ms to start. The converter's counter-timer counts no more than 1024 oscillator clock cycles to make sure the oscillator is fully stable. During this time-out period the serial port logic is reset and the RV (Reset Valid) bit in the configuration register is set. A reset can be initiated at any time by writing a logic 1 to the RS (Reset System) bit in the configuration register. This automatically sets the RV bit until the RS bit is written to logic 0, and the configuration register is read. After a reset, the on-chip registers are initialized to the following states and the converters are ready to perform conversions.
configuration register: offset register: gain register: 000040(H) 000000(H) 800000(H)
Command Operation
The CS5525/26 include a microcontroller with five registers used to control the converter. Each register is 24-bits in length except the 8-bit command register (command, configuration, offset, gain, and conversion data). After a system initialization or reset, the serial port is initialized to the command mode and the converter stays in this mode until a valid 8-bit command is received (the first 8-bits into the serial port). Table 1 lists all the valid commands. Once a valid 8-bit command (a read or a write command word) is received and interpreted by the command register, the serial port enters the data mode. In data mode the next 24 serial clock pulses shift data either into or out of the serial port (72 serial clock pulses are needed if set-up register is selected). See Table 2 for configuring the CS5525/26.
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DS202F1
CS5525 CS5526
Reading/Writing On-Chip Registers
The CS5525/26's offset, gain, and configuration registers are read/writable while the conversion data register is read only. To perform a read from a specific register, the R/W bit of the command word must be a logic 1. The SC, CC, and PS/R bits must be logic 0 and the CB (MSB) bit must be a logic 1. The register to be written is selected with the RSB2-RSB0 bits of the command word. To perform a write to a specific register, the R/W bit of the command word must be a logic 0. The SC, CC, and PS/R bits must be logic 0 and the CB (MSB) bit must be a logic 1. The register to be written is selected with the RSB2-RSB0 bits of the command word. Figure 6 illustrates the serial sequence necessary to write to, or read from the serial port. If the Set-up Registers are chosen with the RSB2RSB0 bits, the registers are read or written in the following sequence: Offset, Gain and Configuration. This is accomplished by following one 8-bit command word with three 24-bit data words for a total of 72 data bits.
Command Register
D7(MSB) CB BIT D7 D6 SC D5 CC NAME Command Bit, CB D4 R/W D3 RSB2 VALUE 0 1 D6 D5 D4 D3-D1 Single Conversion, SC Continuous Conversions, CC Read/Write, R/W Register Select Bit, RSB2-RSB0 0 1 0 1 0 1 000 001 010 011 100 101 110 111 0 1 D2 RSB1 D1 RSB0 D0 PS/R FUNCTION Null command (no operation). All command bits, including CB must be 0. Logic 1 for executable commands. Single Conversion not active. Perform a conversion. Continuous Conversions not active. Perform conversions continuously. Write to selected register. Read from selected register. Offset Register Gain Register Configuration Register Conversion Data Register (read only) Set-up Registers (Offset, Gain, Configuration) Reserved Reserved Reserved Run Power Save
D0
Power Save/Run, PS/R
Table 1. Command Set
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CS5525 CS5526
Configuration Register
D23(MSB) A3 D11 G2 BIT D23-D20 D19 D18 D17 D16 D15-D13 D22 A2 D10 G1 D21 A1 D9 G0 NAME Latch Outputs, A3-A0 Not Used, NU Chop Frequency Select, CFS Not Used, NU Low Power Mode, LPM Word Rate, WR2-0 Note: For XIN = 32.768kHz D20 A0 D8 PD VALUE 0000 0 0 1 0 0 1 000 001 010 011 100 101 110 111 0 1 000 001 010 011 100 101 110/111 0 1 0 1 0 1 0 1 0 1 0 1 000 001 010 011 100 101 110 111 R Must always be logic 0. R 256 Hz Amplifier chop frequency 32768 Hz Amplifier chop frequency R Must always be logic 0. R Normal Mode Reduced Power mode R 15.0 Hz (2182 XIN cycles) 30.1 Hz (1090 XIN cycles) 60.0 Hz (546 XIN cycles) 123.2 Hz (266 XIN cycles) 168.9 Hz (194 XIN cycles) 202.3 Hz (162 XIN cycles) 3.76 Hz (8722 XIN cycles) 7.51 Hz (4362 XIN cycles) R Bipolar Measurement mode Unipolar Measurement mode R 100 mV (assumes VREF = 2.5V) 55 mV 25 mV 1V 5.0 V 2.5 V Not Used. R Charge Pump Enabled For PD = 1, the CPD pin goes to a Hi-Z output state. R Normal Operation Activate a Reset cycle. To return to Normal Operation write bit to zero. No reset has occurred or bit has been cleared (read only). R Valid Reset has occurred. (Cleared when read.) R Port Flag mode inactive Port Flag mode active R Standby Mode (Oscillator active, allows quick power-up) Sleep Mode (Oscillator inactive) R Done Flag bit is cleared (read only). Calibration or Conversion cycle completed (read only). R Normal Operation (no calibration) Offset -- Self-Calibration Gain -- Self-Calibration Offset Self-Calibration followed by Gain Self-Calibration Not used. Offset -- System Calibration Gain -- System Calibration Not Used. D19 NU D7 RS D18 CFS D6 RV D17 NU D5 PF D16 LPM D4 PSS D15 WR2 D3 DF FUNCTION R* Latch Output Pins A3-A0 mimic the D23-D20 Register bits. D14 WR1 D2 CC2 D13 WR0 D1 CC1 D12 U/B D0 CC0
D12 D11-D9
Unipolar/Bipolar, U/B Gain Bits, G2-G0
D8 D7 D6 D5 D4 D3 D2-D0
Pump Disable, PD Reset System, RS Reset Valid , RV Port Flag, PF Power Save Select, PSS Done Flag, DF Calibration Control Bits, CC2-CC0
* R indicates the bit value after the part is reset Table 2. Configuration Register 12 DS202F1
CS5525 CS5526
CS
SCLK
SDI Command Time 8 SCLKs
MSB
LSB
Data Time 24 SCLKs (or 72 SCLKs for Set-up Registers) Write Cycle
CS
SCLK
SDI Command Time 8 SCLKs SDO
MSB LSB
Data Time 24 SCLKs (or 72 SCLKs for Set-up Registers) Read Cycle
SCLK
SDI
Command Time 8 SCLKs SDO
td*
XIN/OWR Clock Cycles
8 SCLKs Clear SDO Flag
MSB LSB
* td = XIN/OWR clock cycles for each conversion except the first conversion which will take XIN/OWR + 7 clock cycles
SDO Continuous Conversion Read (PF bit = 1)
Data Time 24 SCLKs
Figure 6. Command and Data Word Timing.
DS202F1
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CS5525 CS5526
Analog Input
Figure 7 illustrates a block diagram of the analog input signal path inside the CS5525/26. The front end consists of a chopper-stabilized instrumentation amplifier with 20X gain and a programmable gain section. The instrumentation amplifier is powered from VA+ and from the NBV (Negative Bias Voltage) pin allowing the CS5525/26 to be operated in either of two analog input configurations. The NBV pin can be biased to a negative voltage between -1.8 V and -2.5 V, or tied to AGND. The choice of the operating mode for the NBV voltage depends upon the input signal and its common mode voltage. For the 25 mV, 55 mV, and 100 mV input ranges, the input signals to AIN+ and AIN- are amplified by the 20X instrumentation amplifier. For ground referenced signals with magnitudes less then 100 mV, the NBV pin should be biased with -1.8 V to -2.5 V. If NBV is tied between -1.8 V and -2.5 V, the (Common Mode + Signal) input on AIN+ and AIN- must stay between -0.150 V and 0.950 V to ensure proper operation. Alternatively, NBV can be tied to AGND where the input (Common Mode + Signal) on AIN+ and AIN- must stay between 1.85 V and 2.65 V to ensure that the amplifier operates properly. For the 1 V, 2.5 V, and 5 V input ranges, the instrumentation amplifier is bypassed and the input signals are directly connected to the Programmable Gain block. With NBV tied between -1.8 V and -2.5 V, the (Common Mode + Signal) input on AIN+ and AIN- must stay between NBV and VA+. Alternatively, NBV can be tied to AGND where the input (Common Mode + Signal) on AIN+ and AIN- pins can span the entire range between AGND and VA+. The CS5525/26 can accommodate full scale ranges other than 25 mV, 55 mV, 100 mV, 1 V, 2.5 V and 5 V by performing a system calibration within the limits specified. See the Calibration section for more details. Another way to change the full scale range is to increase or to decrease the voltage reference to other than 2.5 V. See the Voltage Reference section for more details. Three factors set the operating limits for the input span. They include: instrumentation amplifier saturation, modulator 1's density, and a lower reference voltage. When the 25 mV, 55 mV or 100 mV range is selected, the input signal (including the common mode voltage and the amplifier offset voltage) must not cause the 20X amplifier to saturate in either its input stage or output stage. To prevent saturation the absolute voltages on AIN+ and AINmust stay within the limits specified (refer to the `Analog Input' table on page 3). Additionally, the differential output voltage of the amplifier must not exceed 2.8 V. The equation ABS(VIN + VOS) x 20 = 2.8 V defines the differential output limit, where VIN = (AIN+) - (AIN-) is the differential input voltage and VOS is the absolute maximum offset voltage for the instrumentation amplifier (VOS will not exceed 40 mV). If the
VREF+ VREF-
AIN+
AINNBV
X20
Programmable Gain
Differential 4th order deltasigma modulator
Digital Filter
Figure 7. Block Diagram of Analog Signal Path 14 DS202F1
CS5525 CS5526
- Nominal(1) Differential Input 0.5 V 1.1 V 2.0 V 1.0 V 2.5 V 5.0 V -(1) Max. Input 0.75 V 1.65 V 3.0 V 1.5 V 5.0 V 0V, VA+
Input Range(1) 25 mV 55 mV 100 mV 1.0 V 2.5 V 5.0 V
Max. Differential Output 20X Amplifier 2.8 V (2) 2.8 V (2) 2.8 V (2) -
VREF 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V
Gain Factor 5 2.272727... 1.25 2.5 1.0 0.5
Note:
1. The converter's actual input range, the delta-sigma's nominal full scale input, and the delta-sigma's maximum full scale input all scale directly with the value of the voltage reference. The values in the table assume a 2.5 V VREF voltage. Table 3. Relationship between Full Scale Input, Gain Factors, and Internal Analog Signal Limitations
differential output voltage from the amplifier exceeds 2.8 V, the amplifier may saturate, which will cause a measurement error. The input voltage into the modulator must not cause the modulator to exceed a low of 20 percent or a high of 80 percent 1's density. The nominal full scale input span of the modulator (from 30 percent to 70 percent 1's density) is determined by the VREF voltage divided by the Gain Factor. See Table 3 to determine if the CS5525/26 are being used properly. For example, in the 55 mV range to determine the nominal input voltage to the modulator, divide VREF (2.5 V) by the Gain Factor (2.2727). When a smaller voltage reference is used, the resulting code widths are smaller causing the converter output codes to exhibit more changing codes for a fixed amount of noise. Table 3 is based upon a VREF = 2.5 V. For other values of VREF, the values in Table 3 must be scaled accordingly. Figure's 8 and 9 illustrate the input models for the AIN and VREF pins. The dynamic input current for each of the pins can be determined from the models shown and is dependent upon the setting of the CFS (Chop Frequency Select) bit. The effective input impedance for the AIN+ and AIN- pins remains constant for the three low level measurement ranges (25 mV, 55 mV, and 100 mV). The input current is lowest with the CFS bit cleared to logic 0.
DS202F1
Note: Residual noise appears in the converter's baseband for output word rates greater than 60 Hz if CFS is logic 0. By setting CFS to logic 1, the amplifier's chop frequency chops at 32768 Hz eliminating the residual noise, but increasing the current. Note that C=48pF is for input current modeling only. For physical input capacitance see `Input Capacitance' specification under `Analog Characteristics' on page 3.
25mV, 55mV, and 100mV Ranges
AIN Vos 25mV in = fVos C
C = 48pF
CFS = 0 , f = 256 Hz CFS = 1 , f = 32.768 kHz
1V, 2.5 V, and 5V Ranges
AIN+ AINC = 32pF
i n = [(VAIN+) - (VAIN- )] fC
f = 32.768 kHz Figure 8. Input models for AIN+ and AIN- pins
VREF+ VREFC = 16pF
in = [(VREF+) - (VREF-)] fC f = 32.768 kHz
Figure 9. Input model for VREF+ and VREF- pins.
15
CS5525 CS5526
Charge Pump Drive
The CPD (Charge Pump Drive) pin of the converters can be used with external components (shown in Figure 1) to develop an appropriate negative bias voltage for the NBV pin. When CPD is used to generate the NBV, the NBV voltage is regulated with an internal regulator loop referenced to VA+. Therefore, any change on VA+ results in a proportional change on NBV. With VA+ = 5 V, NBV's regulation is set proportional to VA+ at approximately -2.1 V. Figure 3 illustrates a means of supplying NBV voltage from a -5 V supply. For ground based signals with the instrumentation amplifier engaged (when in the 25mV, 55mV, or 100mV ranges), the voltage on the NBV pin should at no time be less negative than -1.8 V or more negative than -2.5 V. To prevent excessive voltage stress to the chip the NBV voltage should not be more negative than -3.0 V. The components in Figure 1 are the preferred components for the CPD filter. However, smaller capacitors can be used with acceptable results. The 10 F ensures very low ripple on NBV. Intrinsic safety requirements prohibit the use of electrolytic capacitors. In this case, two 0.47 F ceramic capacitors in parallel can be used. The CPD pin itself is a tri-state output and enters tri-state whenever the converters are placed into the Sleep Mode, Standby Mode, or when the charge pump is disabled (when the Pump Disable bit, bit D8 in the configuration register, is set). Once in tristate, the digital current can increase if this CPD output floats near 1/2 digital supply. To ensure the CPD pin stays near ground and to minimize the digital current, add a 5M resistor between it and DGND (see Figure 1). If the resistor is left out, the digital supply current may increase from 2 A to 10 A.
Voltage Reference
The CS5525/26 are specified for operation with a 2.5 V reference voltage between the VREF+ and VREF- pins of the devices. For a single-ended reference voltage, such as the LT1019-2.5, the reference's output is connected to the VREF+ pin of the CS5525/26. The ground reference for the LT10192.5 is connected to the VREF- pin. The differential voltage between the VREF+ and VREF- can be any voltage from 1.0 V up to 3.0 V, however, the VREF- pin can not go below analog ground.
Calibration
The CS5525/26 offer five different calibration functions including self calibration and system calibration. However, after the CS5525/26 are reset, they can perform measurements without being calibrated. In this case, the converters will utilize the initialized values of the on-chip registers (Gain = 1.0, Offset = 0.0) to calculate output words for the 100 mV range. Any initial offset and gain errors in the internal circuitry of the chips will remain. The gain and offset registers, which are used for both self and system calibration, are used to set the zero and full-scale points of the converter's transfer function. One LSB in the offset register is 2-24 proportion of the input span (bipolar span is 2 times the unipolar span). The MSB in the offset register determines if the offset to be trimmed is positive or negative (0 positive, 1 negative). The converters can typically trim 50 percent of the input span. The gain register spans from 0 to (2 - 2-23). The decimal equivalent meaning of the gain register is
N
D = b0 2 + b 1 2
0
-1
+ b2 2
-2
+ ... + bN 2
-N
=
bi2
i=0
-i
where the binary numbers have a value of either zero or one (b0 corresponds to the MSB). Refer to Table 4 for details.
16
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CS5525 CS5526
Offset Register
Register
Reset (R) 2-2 0 2-3 0 2-4 0 2-5 0
MSB Sign 0
LSB 2-20 0 2-21 0 2-22 0 2-23 0 2-24 0
2-6 0
2-19 0
One LSB represents 2-24 proportion of the input span (bipolar span is 2 times unipolar span) Offset and data word bits align by MSB (bit MSB-4 of offset register changes bit MSB-4 of data)
Gain Register
Register
Reset (R) 2 1
0
2 0
-1
2 0
-2
2 0
-3
2 0
-4
MSB
LSB 2
-19
2 0
-5
2
-18
2
-20
2
-21
2
-22
0
0
0
0
0
2-23 0
The gain register span is from 0 to (2-2-23). After Reset the MSB = 1, all other bits are 0. Table 3. Table 4. Offset and Gain Registers
The offset and gain calibration steps each take one conversion cycle to complete. At the end of the calibration step, the calibration control bits will be set back to logic 0, and the DF (Done Flag) bit will be set to a logic 1. For the combination self-calibration (CC2-CC0= 011; offset followed by gain), the calibration will take two conversion cycles to complete and will set the DF bit after the gain calibration is completed. The DF bit will be cleared any time the data register, the offset register, the gain register, or the setup register is read. Reading the configuration register alone will not clear the DF bit.
of the modulator are connected together and then routed to the VREF- pin as shown in Figure 11. For self-calibration of gain, the differential inputs of the modulator are connected to VREF+ and
S1 OP EN A IN+ S2 CLOSED AIN+ X20 +
Self Calibration
The CS5525/26 offer both self offset and self gain calibrations. For the self-calibration of offset in the 25 mV, 55 mV, and 100 mv ranges, the converter internally ties the inputs of the instrumentation amplifier together and routes them to the AIN- pin as shown in Figure 10. For proper self-calibration of offset to occur in the 25 mV, 55 mV, and 100 mV ranges, the AIN- pin must be at the proper common-mode-voltage (i.e. AIN- = 0V, NBV must be between -1.8 V to -2.5 V). For self-calibration of offset in the 1.0 V, 2.5 V, and 5 V ranges, the inputs
Figure 10. Self Calibration of Offset (Low Ranges).
S1 OPEN
AIN+
+ X20 S3 CLOSED S2 OPEN
S4 CLOSED
+
AINVREF-
-
-
Figure 11. Self Calibration of Offset (High Ranges).
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CS5525 CS5526
OPEN AIN+ + X20 AINVREF+ Reference + VREFCLOSED CLOSED OPEN +
External Connections + AIN+ 0V + AINX20 +
CM + -
Figure 12. Self Calibration of Gain (All Ranges).
Figure 13. System Calibration of Offset (Low Ranges).
VREF- as shown in Figure 12. For any input range other than the 2.5 V range, the modulator gain error can not be completely calibrated out. This is due to the lack of an accurate full scale voltage internal to the chips. The 2.5 V range is an exception because the external reference voltage is 2.5 V nominal and is used as the full scale voltage. In addition, when self-calibration of gain is performed in the 25 mV, 55 mV, and 100 mV input ranges, the instrumentation amplifier's gain is not calibrated. These two factors can leave the converters with a gain error of up to 20% after self-calibration of gain. Therefore, a system gain is required to get better accuracy, except for the 2.5 V range.
External Connections + AIN+ 0V + CM + AINX20 +
Figure 14. System Calibration of Offset (High Ranges).
External Connections + A IN+ Full S cale + CM + A INX20 +
System Calibration
For the system calibration functions, the user must supply the converters calibration signals which represent ground and full scale. When a system offset calibration is performed, a ground reference signal must be applied to the converter. See Figures 13 and 14. As shown in Figures 15 and 16, the user must input a signal representing the positive full scale point to perform a system gain calibration. In either case, the calibration signals must be within the specified calibration limits for each specific calibration step (refer to the System Calibration Specifications).
Figure 15. System Calibration of Gain (Low Ranges)
External Connections + AIN+ Full Scale + CM + AINX20 +
Figure 16. System Calibration of Gain (High Ranges).
18
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CS5525 CS5526
Assuming a system can provide two known voltages, equations can allow the user to manually compute the calibration register's values based on two uncalibrated conversions. The offset and gain calibration registers are used to adjust a typical conversion as follows: Rc = (Ru + Co>>4) * Cg / 223. Calibration can be performed using the following equations: Co = (Rc0/G - Ru0) << 4 Cg = 223 * G where G = (Rc1 - Rc0)/(Ru1-Ru0).
Note: Uncalibrated conversions imply that the gain and offset registers are at default {gain register = 0x800000 (Hex) and offset register = 0x000000 (Hex)}. of 20 bits. To get the equations to work correctly pad the 16 bit results with four zeros (on the right).
Calibration Tips
Calibration steps are performed at the output word rate selected by the WR2-WR0 bits of the configuration register. Since higher word rates result in conversion words with more peak-to-peak noise, calibration should be performed at lower output word rates. Also, to minimize digital noise near the devices, the user should wait for each calibration step to be completed before reading or writing to the serial port. For maximum accuracy, calibrations should be performed for offset and gain for each gain setting (selected by changing the G2-G0 bits of the configuration register). And if factory calibration is performed using the system calibration capabilities of the CS5525/26, the offset and gain register contents can be read by the system microcontroller and recorded in EEPROM. These same calibration words can then be uploaded into the offset and gain registers of the converters when power is first applied to the system, or when the gain range is changed. Two final tips include two ways to determine when calibration is complete: 1) wait for SDO to fall. It falls to logic 0 if the PF (Port Flag) bit of the configuration register is set to logic 1; or 2) poll the DF (Done Flag) bit in the configuration register which is set at completion of calibration. Whichever method is used, the calibration control bits (CC2CC0) will return to logic 0 upon completion of any calibration.
The variables are defined below.
V0 V1 Ru Ru0 Ru1 Rc Rc0 Rc1 Co Cg >> << = = = = = = = = = = First calibration voltage Second calibration voltage (greater than V0) Result of any uncalibrated conversion Result of uncalibrated conversion V0 (20-bit integer or 2's complement) Result of uncalibrated conversion of V1 (20-bit integer or 2's complement) Result of any conversion Desired calibration result of converting V0 (20-bit integer or 2's complement) Desired calibration result of converting V1 (20-bit integer or 2's complement) Offset calibration register value (24-bit 2's complement) Gain calibration register value (24-bit integer)
= The shift right operator (e.g. x >>2 is x shifted right 2 bits) = The shift left operator (e.g. x<<2 is x shifted left 2 bits)
Limitations in Calibration Range
System calibration can be limited by signal headroom in the analog signal path inside the chip as discussed under the Analog Input section of this data sheet. System calibration can also be limited by the intrinsic gain errors of the instrumentation amplifier and the modulator. For gain calibrations
Note: The shift operators are used here to align the decimal points of words of various lengths. Data to the right of the decimal point may be used in the calculations shown. For the CS5525 all conversion results (Ru, Rc...) are 16 bits instead DS202F1
19
CS5525 CS5526
the input signal can be reduced to the point in which the gain register reaches its upper limit of 2.0 (decimal) [FFFFFF Hex] (this is most likely to occur with an input signal approximately 1/2 the nominal range). Alternatively, the input signal can be increased to a point in which the modulator reaches its one's density upper limit of 80% (this is most likely to occur with an input signal approximately 1.5 times the nominal range). Also, for full scale inputs larger than the nominal full scale value of the range selected, there is some voltage at which the various internal circuits may saturate due to limited amplifier headroom (this is most likely to occur on the 100 mV range setting when NBV = 1.8 V).
Serial Port Initialization
The serial port is initialized to the command mode whenever a power-on reset is performed inside the converter, when the port initialization sequence is completed, or whenever a command byte, data word sequence is completed. The port initialization sequence involves clocking 15 (or more) bytes of all 1's, followed by one byte with the following bit contents (11111110). This sequence places the chips in the command mode where it waits for a valid command.
Performing Conversions (With PF bit = 0)
Setting the SC (Single Conversion) bit of the command word to a logic 1 with the CB bit = 1, all other command bits = 0, the CS5525/CS5526 will perform one conversion. At the completion of the conversion the DF (Done Flag) bit of the configuration register will be set to a logic 1. The user can read the configuration register to determine if the DF bit is set. If DF has been set, a command can be issued to read the conversion data register to obtain the conversion data word. The DF bit of the configuration register will be cleared to logic 0 when the data register, the gain register, the offset register, or the set-up registers are read. Reading only the configuration register will not clear the DF flag bit. If an SC command is issued to the converters while they are performing a conversion, the filter will restart a convolution cycle to perform a new conversion.
Analog Output Latch Pins
The A3-A0 pins of the converters mimic the D23D20 bits of the configuration register. A3-A0 can be used to control multiplexers and other logic functions outside the converter. The outputs can sink or source at least 1 mA, but it is recommended to limit drive currents to less than 20 A to reduce self-heating of the chip. These outputs are powered from VA+, hence, their output voltage for a logic 1 will be limited to the VA+ voltage.
Serial Port Interface
The CS5525/26 serial interface consist of four pins, SCLK, SDO, SDI, and CS. The CS pin must be held low (logic 0) before SCLK transitions can be recognized by the port logic. The SDO output will be held at high impedance any time CS is a logic 1. If the CS pin is tied low, the port can function as a three wire interface. The SCLK input is designed with a Schmitt-trigger input to allow an optoisolator with slower rise and fall times to directly drive the pin. The SDO output is capable of sinking or sourcing up to 5 mA to directly drive an optoisolator LED. SDO will have less than a 400 mV loss in the drive voltage when sinking or sourcing 5 mA.
20
Performing Conversions (With PF bit = 1)
Setting the PF bit of the configuration register to a logic 1 enables the SDO output pin to behave as a flag signal whenever conversions are completed. This eliminates the need for the user to read the DF flag bit of the configuration register to determine if the conversion data word is available. If the SC (Single Conversion) command is issued (SC = 1, CB= 1, all other command bits = 0) the SDO pin will go low at the completion of a converDS202F1
CS5525 CS5526
sion. The user would then issue 8 SCLKs (with SDI = logic 0) to clear the SDO flag. Upon the falling edge of the 8th SCLK, the SDO pin will present the first bit (MSB) of the conversion word. 24 SCLKs (high, then low) are required to read the conversion word from the port. The user must not give an explicit command to read the conversion data register when the PF bit is set to logic 1. The data conversion word must be read before a new command can be entered (if the SC command is used with PF = 1). If the CC (Continuous Conversion) command is issued (CC = 1, CB =1, all other command bits = 0) the SDO pin will go low at the completion of a conversion. The user would then issue 8 SCLKs (with SDI = logic 0) to clear the SDO flag. Upon the falling edge of the 8th SCLK, the SDO pin will present the first bit (MSB) of the conversion word. 24 SCLKs (high, then low) are required to read the conversion word from the port. The user must not give an explicit command to read the conversion data register when the PF bit is set to logic 1. When operating in the continuous conversion mode, the user need not read every conversion. If the user does nothing after SDO falls, SDO will rise one XIN clock cycle before the next conversion word is available and then fall again to signal that another conversion word is available. If the user begins to clear the SDO flag and read the conversion data, this action must be finished before the conversion cycle which is occurring in the background is complete if the user wants to be able to read the new conversion data. To exit the continuous conversion mode, issue any valid command to the SDI input when the SDO flag falls. If a CC command is issued to the converter while it is performing a conversion, the filter will restart a convolution cycle to perform a new conversion.
Output Word Rate Selection
The WR2-WR0 bits of the configuration register set the output conversion word rate of the converters as shown in Table 2. The word rates indicated in the table assume a master clock of 32.768 kHz. Upon reset the converters are set to operate with an output word rate of 15.0 Hz.
Clock Generator
The CS5525/26 include a gate which can be connected with an external crystal to provide the master clock for the chips. They are designed to operate using a low-cost 32.768 kHz "tuning fork" type crystal. One lead of the crystal should be connected to XIN and the other to XOUT. Lead lengths should be minimized to reduce stray capacitance. The converters will operate with an external (CMOS compatible) clock with frequencies up to three times the typical crystal frequency of 32.768 kHz. Figure 17 details the converter's performance at increased clock rates.
Figure 17. High Speed Clock Performance
The 32.768 kHz crystal is normally specified as a time-keeping crystal with tight specifications for both initial frequency and for drift over temperature. To maintain excellent frequency stability, these crystals are specified only over limited operating temperature ranges (i.e. -10 C to +60 C). However, applications with the CS5525/26 don't generally require such tight tolerances. When 32.768 kHz surface mount crystals are used, it is recommended that protection components, an external resistor and capacitor as shown in Figure 18, be used.
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21
CS5525 CS5526
VA+
VD+ XOUT
500 k
20 pF
CS5525 CS5526
XIN
32.768 kHz
Figure 18. Surface Mount Crystal Connection Diagram
Digital Filter
The CS5525/26 have eight different linear phase digital filters which set the output word rates (OWRs) as stated in Table 2. These rates assume that XIN is 32.768 kHz. Each of the filters has a magnitude response similar to that shown in Figure 19. The filters are optimized to settle to full accuracy every conversion and yield better than 80 dB rejection for both 50 and 60 Hz with output word rates at or below 15.0 Hz. The converter's digital filters scale with XIN. For example with an output word rate of 15 Hz, the filter's corner frequency is typically 12.7 Hz. If XIN is increased to 64.536 kHz the OWR doubles and the filter's corner frequency moves to 25.4 Hz.
Figure 19. Filter Response (Normalized to Output Word Rate = 1)
first followed by the rest of the data bits in descending order. For the CS5525 the last byte is composed of bits D7-D4, which are always logic 1; D3-D2, which are always logic 0; and bits D1-D0 which are the two flag bits. For the CS5526 the last byte includes data bits D7-D4, D3-D2 which are always logic 0 and the two flag bits. The OF (Overrange Flag) bit is set to a logic 1 any time the input signal is: 1) more positive than positive full scale, 2) more negative than zero (unipolar mode), 3) more negative than negative full scale (bipolar mode). It is cleared back to logic 0 whenever a conversion word occurs which is not overranged. The OD (Oscillation Detect) bit is set to a logic 1 any time that an oscillatory condition is detected in the modulator. This does not occur under normal operating conditions, but may occur whenever the input
Output Coding
The CS5525/26 output data in binary format when operating in unipolar mode and in two's complement when operating in bipolar mode. The output conversion word is 24 bits, or three bytes long, as shown in Table 5. The MSB is output
Output Conversion Data CS5525 (16 bits + flags)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D8 LSB D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 0 0 OD OF
Output Conversion Data CS5526 (20 bits + flags)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 MSB 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D4 LSB D3 D2 D1 D0 0 0 OD OF
Table 5. Data Conversion Word
22
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CS5525 CS5526
CS5525 16-Bit Output Coding Unipolar Input Offset Voltage Binary >(VFS-1.5 LSB) FFFF VFS-1.5 LSB FFFF ----FFFE 8000 ----7FFF 0001 ----0000 0000 Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 LSB Two's Complement 7FFF 7FFF ----7FFE 0000 ----FFFF 8001 ----8000 8000 CS5526 20-Bit Output Coding Unipolar Input Offset Voltage Binary >(VFS-1.5 LSB) FFFFF VFS-1.5 LSB FFFFF ----FFFFE 80000 ----7FFFF 00001 ----00000 00000 Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 LSB Two's Complement 7FFFF 7FFFF ----7FFFE 00000 ----FFFFF 80001 ----80000 80000
VFS/2-0.5 LSB
-0.5 LSB
VFS/2-0.5 LSB
-0.5 LSB
+0.5 LSB <(+0.5 LSB)
-VFS+0.5 LSB <(-VFS+0.5 LSB)
+0.5 LSB <(+0.5 LSB)
-VFS+0.5 LSB <(-VFS+0.5 LSB)
Note: VFS in the table equals the voltage between ground and full scale for any of the unipolar gain ranges, or the voltage between full scale for any of the bipolar gain ranges. See text about error flags under overrange conditions. Table 6. 5525/26 Output Coding
to the converters is extremely overranged. If the OD bit is set, the conversion data bits can be completely erroneous. The OD flag bit will be cleared to logic 0 when the modulator becomes stable. Table 6 illustrates the output coding for the CS5525/26.
Power Consumption
The CS5525/26 accommodate four power consumption modes: normal, low power, standby, and sleep. The normal mode, the default mode, is entered after a power-on-reset and typically consumes 7.5 mW. The low power mode is an alternate mode that reduces the consumed power to 4 mW. It is entered by setting bit D16 (the low power mode bit) in the configuration register to logic 1. Since the converter's noise performance improves with increased power consumption, slightly degraded noise or linearity performance should be expected in the low power mode. The final two modes are referred to as the power save modes. They power down most of the analog portion of the chips and stop filter convolutions. The power save modes are entered whenever the PS/R bit and the CB bit of the
command word are set to logic 1. The particular power save mode entered depends on state of bit D4 (the Power Save Select bit) in the configuration register. If D4 is logic 0, the converters enters the standby mode reducing the power consumption to 1.2mW. The standby mode leaves the oscillator and the on-chip bias generator running. This allows the converters to quickly return to the normal or low power mode once the PS/R bit is set back to a logic 1. If D4 in the configuration register and CB and PS/R in the command word are set to logic 1, the sleep mode is entered reducing the consumed power to less than 500 W. Since the sleep mode disables the oscillator, approximately a 500ms oscillator start-up delay period is required before returning to the normal or low power mode.
PCB Layout
The CS5525/26 should be placed entirely over an analog ground plane with both the AGND and DGND pins of the device connected to the analog plane. Place the analog-digital plane split immediately adjacent to the digital portion of the chip.
DS202F1
23
CS5525 CS5526
PIN DESCRIPTIONS
ANALOG GROUND POSITIVE ANALOG POWER DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT NEGATIVE BIAS VOLTAGE LOGIC OUTPUT LOGIC OUTPUT CHARGE PUMP DRIVE CRYSTAL IN CRYSTAL OUT AGND VA+ AIN+ AINNBV A0 A1 CPD XIN XOUT
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VREF+ VOLTAGE REFERENCE INPUT VREF- VOLTAGE REFERENCE INPUT CS SDI A3 A2 SDO VD+ CHIP SELECT SERIAL DATA INPUT LOGIC OUTPUT LOGIC OUTPUT SERIAL DATA OUTPUT POSITIVE DIGITAL POWER
DGND DIGITAL GROUND SCLK SERIAL CLOCK INPUT
Clock Generator
XIN; XOUT - Crystal In; Crystal Out, Pins 9, 10. A gate inside the chip is connected to these pins and can be used with a crystal to provide the master clock for the device. Alternatively, an external (CMOS compatible) clock can be supplied into the XIN pin to provide the master clock for the device.
Control Pins and Serial Data I/O
CS - Chip Select, Pin 18. When active low, the port will recognize SCLK. When high the SDO pin will output a high impedance state. CS should be changed when SCLK = 0. SDI - Serial Data Input, Pin 17. SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK. SDO - Serial Data Output, Pin 14. SDO is the serial data output. It will output a high impedance state if CS = 1. SCLK - Serial Clock Input, Pin 11. A clock signal on this pin determines the input/output rate of the data for the SDI/SDO pins respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin will recognize clocks only when CS is low. A0, A1, A2, A3 - Logic Outputs, Pin 6, 7, 15, 16. The logic states of A0-A3 mimic the states of the D20-D23 bits of the configuration register. Logic Output 0 = AGND, and Logic Output 1 = VA+.
24
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CS5525 CS5526
Measurement and Reference Inputs
AIN+, AIN- - Differential Analog Input, Pins 3, 4. Differential input pins into the device. VREF+, VREF- - Voltage Reference Input, Pins 20, 19. Fully differential inputs which establish the voltage reference for the on-chip modulator. NBV - Negative Bias Voltage, Pin 5. Input pin to supply the negative supply voltage for the 20X gain instrumentation amplifier. May be tied to AGND if AIN+ and AIN- inputs are centered around +2.5 V; or it may be tied to a negative supply voltage (-2.1 V typical) to allow the amplifier to handle low level signals more negative than ground. CPD - Charge Pump Drive, Pin 8. Square wave output used to provide energy for the charge pump.
Power Supply Connections
VA+ - Positive Analog Power, Pin 2. Positive analog supply voltage. Nominally +5 V. VD+ - Positive Digital Power, Pin 13. Positive digital supply voltage. Nominally +3.0 V or +5 V. AGND - Analog Ground, Pin 1. Analog Ground. DGND - Digital Ground, Pin 12. Digital Ground.
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CS5525 CS5526
SPECIFICATION DEFINITIONS
Linearity Error The deviation of a code from a straight line which connects the two endpoints of the A/D Converter transfer function. One endpoint is located 1/2 LSB below the first code transition and the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in percent of full-scale. Differential Nonlinearity The deviation of a code's width from the ideal width. Units in LSBs. Full Scale Error The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} - 3/2 LSB]. Units are in LSBs. Unipolar Offset The deviation of the first code transition from the ideal (1/2 LSB above the voltage on the AIN- pin.). When in unipolar mode (U/B bit = 1). Units are in LSBs. Bipolar Offset The deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 LSB below the voltage on the AIN- pin). When in bipolar mode (U/B bit = 0). Units are in LSBs.
ORDERING GUIDE
Model Number CS5525-AP CS5525-AS CS5526-BP CS5526-BS Linearity Error (Max) 0.003% 0.003% 0.0015% 0.0015% Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package 20-pin 0.3" Plastic DIP 20-pin 0.2" Plastic SSOP 20-pin 0.3" Plastic DIP 20-pin 0.2" Plastic SSOP
SPITM is a trademark of Motorola Inc., MicrowireTM is a trademark of National Semiconductor Corp. 26 DS202F1
CS5525 CS5526
20 PIN PLASTIC (PDIP) PACKAGE DRAWING
D E 1 SEATING PLANE e b A A1 b1 L
TOP VIEW
c eA
SIDE VIEW
BOTTOM VIEW
INCHES DIM A A1 b b1 c D E e eA L MIN 0.155 0.020 0.015 0.050 0.008 0.960 0.240 0.095 0.300 0.125 0 MAX 0.180 0.040 0.022 0.065 0.015 1.040 0.260 0.105 0.325 0.150 15
MILLIMETERS MIN MAX 3.94 4.57 0.51 1.02 0.38 0.56 1.27 1.65 0.20 0.38 24.38 26.42 6.10 6.60 2.41 2.67 7.62 8.25 3.18 3.81 0 15
Notes: 1. Positional tolerance of leads shall be within 0.25 mm (0.010 in.) at maximum material condition, in relation to seating plane and each other. 2. Dimension eA to center of leads when formed parallel. 3. Dimension E does not include mold flash.
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CS5525 CS5526
20 PIN SSOP PACKAGE DRAWING
N
D
E11 A2 A1
L
E
A
e
b2 SIDE VIEW
END VIEW
SEATING PLANE
123
TOP VIEW
INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.064 0.009 0.272 0.291 0.197 0.024 0.025 0 MAX 0.084 0.010 0.074 0.015 0.295 0.323 0.220 0.027 0.040 8
MILLIMETERS MIN MAX -2.13 0.05 0.25 1.62 1.88 0.22 0.38 6.90 7.50 7.40 8.20 5.00 5.60 0.61 0.69 0.63 1.03 0 8
NOTE
2,3 1 1
Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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CDB5525 CDB5526
CDB5525/26 Evaluation Board and Software
Features General Description
The CDB5525/26 is an inexpensive tool designed to evaluate the performance of the CS5525 and CS5526, 16-bit and 20-bit Multi-Range Analog-to-Digital Converters (ADC). The evaluation board includes an LT1019 voltage reference, an 80C51 microcontroller, an RS232 driver/receiver, and firmware. The 8051 controls the serial communication between the evaluation board and the PC via the firmware, thus, enabling quick and easy access to all of the CS5525/26's registers. The CDB5525/26 also includes software for Time Domain Analysis, Histogram Analysis, and Frequency Domain Analysis.
l Direct Thermocouple Interface l RS-232 Serial Communication with PC l On-board 80C51 Microcontroller l On-board Voltage Reference l Lab Windows/CVITM Evaluation Software
Register Setup & Chip Control FFT Analysis Time Domain Analysis Noise Histogram Analysis
l On-board Charge Pump Drive Circuitry l Integrated RS-232 Test Mode
ORDERING INFORMATION: CDB5526
-5 ANALOG
+5 ANALOG
AGND
DGND
+5 DIGITAL RS232 CONNECTOR
VOLTAGE REFERENCE
J1
REF+
CS5526
AIN+
80C51 MICROCONTROLLER TEST SWITCHES OFF ON 1 2 3
AIN+ AINREF-
HDR6 AINCS SDI SDO SCLK A3 A2 A1 A0
RS232 DRIVER/RECEIVER
CPD NBV DRIVE CIRCUITRY
LEDs
NBV
CRYSTAL 32768Hz
XIN XOUT
CRYSTAL 11.0592MHz
RESET CIRCUITRY
Preliminary Product Information
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 1998 (All Rights Reserved)
JAN `98 DS202DB5 29
CDB5525 CDB5526
PART I: HARDWARE
thermocouple's output to reduce any interference picked up by the thermocouple leads. The evaluation board provides two voltage reference options, on-board and external. With HDR5's jumpers in positions 1 and 4, the LT1019 provides 2.5 volts (the LT1019 was chosen for its low drift, typically 5ppm/C). By setting HDR5's jumpers to position 2 and 3, the user can supply an external voltage reference to J1's REF+ and REF- inputs (Application Note 4 in the back of the 1995 Crystal Semiconductor Data Acquisition Databook details various voltage references). The ADC serial interface is SPITM and MICROWIRETM compatible. The interface control lines (CS, SDI, SDO, and SCLK) are connected to the 80C51 microcontroller via port one. To interface an external microcontroller, these control lines are also connected to HDR6. However to accomplish this, the evaluation board must be modified in one of three ways: 1) cut the interface control traces going to the microcontroller, 2) remove resistors R1-R8, or 3) remove the microcontroller. Figure 2 illustrates the schematic of the digital section. It contains the microcontroller, a Motorola MC145407 interface chip, and test switches. The test switches aid in debugging communication problems between the CDB5525/26 and the PC. The microcontroller derives its clock from an 11.0592 MHz crystal. From this, the controller is configured to communicate via RS-232 at 9600 baud, no parity, 8-bit data, and 1 stop bit.
Introduction
The CDB5525/26 evaluation board provides a quick means of testing the CS5525 and CS5526 Analog-to-Digital Converters (ADCs). The board interfaces the CS5525/26 to an IBMTM compatible PC via an RS-232 interface while operating from a +5V and -5V power supply. To accomplish this, the board comes equipped with an 80C51 microcontroller and a 9-pin RS-232 cable physically interfaces the evaluation board to the PC. Additionally, analysis software provides easy access to the internal registers of the converter, and provides a means to display the converter's time domain, frequency domain, and noise histogram performance.
Evaluation Board Overview
The board is partitioned into two main sections: analog and digital. The analog section consists of the CS5525 or the CS5526, a precision voltage reference, and the circuitry to generate a negative voltage. The digital section consists of the 80C51 microcontroller, the hardware test switches, the reset circuitry, and the RS-232 interface. The CS5525/26 is designed to digitize low level signals while operating from a 32.768 KHz crystal. As shown in Figure 1, a thermocouple can be connected to the converter's inputs via J1's AIN+ and AIN- inputs. Note, a simple RC network filters the
30
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R21 10 +5V Analog C16 0.1F +5V Analog C30 10F 2 1 HDR1 1, AGND 2, AIN+ R17 301 C2 4700pF VA+ AGND VD+ XIN 13 9 C31 10F
C11 0.1F
JP6
R18 301
3
U4 CS5526
AIN+ XOUT CS SDI SDO SCLK A3 A2 A1 A0 DGND
REF-
10 18 17 14 11 16 15 7 6 12
Y2 32768Hz
J1 REF+ AIN+ AINREF-
C3 0.68F
JP3
7 HDR2 R15 301 C1 R16 4700pF 301 R22 50
C4 0.68F 1, AIN4 AIN2, AGND HDR5 20 19
JP4 JP5
1,LT1019 2,REF+ 3,REF4,AGND
DO3 DO2 DO1 DO0
To Figure 2
REF+
+5V Analog
U3 LT1019 2.5V
C21 0.1F D2 BAT85 -5V Analog U2 LM337_LZ VIN C22 1F + C13 0.1F ADJ VOUT
C15 0.1F
5
NBV
CPD
8 HDR3 1 2
TP70
C29 + 10F 3 GC 3 NP 7 DD HDR4 R20 1k 3 R19 1k 2 1
TP68
CPD D3 1N4148 C9 0.015F
D5 1N4148
+
Note: CS5525 and CS5526 are interchangeable
Figure 1. Analog Schematic Section
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31
DO3 DO2 DO1 DO0 SCLK SDO SDI CS
32
+5V Digital HDR6 C26 10F + R14 10k +5V Digital R13 10k + 40 39 JP2 P3.0 10 11 P3.1 S1 P1.4 P1.5 P1.6 P1.7 P2.0 21 18 XTAL1 P2.1 Y1 11.0592MHz 19 C24 33pF C0G +5V Digital D4 1N4148 Bypass Cap C19 0.1F 9 RST XTAL2 P2.3 +5V Digital UM1 80C51 P2.2 22 23 24 12 P3.2 13 P3.3 14 P3.4 R12 5.11k R11 5.11k R10 5.11k 8 7 6 5 +1 +2 +3 +4 D1 LED_555_5003 RESET COMM GAINCAL OFFSETCAL Test Switch 1 Test Switch 2 Test Switch 3 13 Loopback 12 11 U1 MC145407 2 4 + 9 10 DTR DSR DCD C28 10F 4 6 1 5 8 CTS 8 Normal 14 7 RTS 7 HDR7 From RS-232 C7 47F C17 0.1F C27 10F + 3 1 CS SDI SDO From Figure 1 SCLK DO3 DO2 DO1 DO0 C23 33pF C0G R1 1 200 R2 2 200 R3 3 200 R4 4 200 R5 5 200 R6 6 200 R7 7 200 R8 8 200 VCC C2C2+ 17 VDD 18 C1C1+ 20 + C25 10F RI 5 6 TXD RXD 9 3 2 P1.0 P1.1 P1.2 P1.3 VDD P0.0 RXD TP71 TXD TP72 16 15 To RS-232
CDB5525 CDB5526
R9 750k C18 0.1F
RESET VSS 20
Figure 2. Digital Schematic Section
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Register Offset Register Gain Register Configuration Register Conversion Data Register
Read Command Byte 0x90 (H) 0x92 (H) 0x94 (H) 0x96 (H) Table 1. Microcontroller Command via RS-232
Write Command Byte 0x80 (H) 0x82 (H) 0x84 (H) ---
Table 1 lists the RS-232 commands used to communicate between the PC and the microcontroller. To develop additional code to communicate to the evaluation board via RS-232, the following applies: to write to an internal ADC register, choose the appropriate write command byte (See Table 1), and transmit it LSB first. Then, transmit the three data bytes lowest order byte (bits 7-0) first with the LSB of each byte transmitted first. These three data bytes provide the 24-bits of information to be written to the desired register. To read from an internal register, choose the appropriate read command byte and transmit it LSB first. Then, the microcontroller automatically acquires the ADC's register contents and returns the 24-bits of information. The returned data is transmitted lowest order byte first with the LSB of each byte transmitted first. Figure 3 illustrates the power supply connections to the evaluation board. The +5V Analog supplies the analog section of the evaluation board, the LT1019 and the ADC. The -5V Analog supplies the negative bias voltage circuitry. The +5V Digital supplies a separate five volts to the digital section of
the evaluation board, the 80C51, the reset circuitry, and the RS-232 interface circuitry.
Using the Evaluation Board
The CS5525/26 are highly integrated ADCs. They contain an instrumentation amplifier (IA), a programmable gain amplifier (PGA), an on-chip charge pump drive (CPD), and programmable output word rates (OWR). The IA provides a set gain of 20 while the PGA sets the input levels of the ADC at either 25 mV, 55 mV, 100 mV, 1 V, 2.5 V, or 5 V (for VREF = 2.5 V). The CPD provides a square wave output. This output is used to supply the negative supply to the IA, enabling measurements of ground referenced signals. The ADC's digital filter allows the user to select output word rates (OWR's) from 3.76 Hz up to 202 Hz. 606 Hz output word rates can be attained when a 100kHz clock source is used. Since the CS5525/26 have such a high degree of integration and flexibility, the CS5525/26 data sheet should be read thoroughly before and consulted during the use of the CDB5525/26.
+5V Analog
+5V Analog
+5V Digital
+5V Digital
Z2 P6KE6V8P AGND
+
C6 47F
C20 0.1F
Z1 P6KE6V8P DGND
+
C8 47F
C12 0.1F
Z3 P6KE6V8P
-5V Analog
+
C5 47F
C14 0.1F
-5V Analog
Figure 3. Power Supplies
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CDB5525 CDB5526
Negative Bias Voltage
The evaluation board provides three means of supplying the Negative Bias Voltage (NBV). HDR4 selects between them. When HRD4 is in position one, the LM337 supplies NBV with an adjustable voltage. R19 is used to adjust this voltage between -1.25 V and -5 V. When in position two, HDR4 grounds NBV. And by setting HDR4 to position three, the converter's Charge Pump Drive provides NBV with a dc rectified voltage, nominally -2.1 V.
Note: NBV should not exceed a voltage more negative than -3.0 V.
Name HDR1 HDR2 HDR3 Function Description Used to switch AIN+ between J1 input and AGND. Used to switch AIN- between J1 input and AGND. Used in conjunction with HDR4 to switch the power for NBV from the LM337, CPD or analog ground. Used in conjunction with HDR3 to switch the power for NBV from the LM337, CPD or analog ground. Used to switch VREF+ and VREFpins from external J1 connection header to the on board LT1019 reference. Used to connect external micro-controller. Used in conjunction with the self test modes to test the UART communication between the microcontroller and the PC.
Software
The evaluation board comes with software and an RS-232 cable to link the evaluation board to the PC. The executable software was developed with Lab Windows/CVITM and meant to run under WindowsTM 3.1 or later. After installing the software, read the readme.txt file for last minute changes in the software. Additionally, Part II: Software further details how to install and use the software.
HDR4
HDR5
IBM, AT and PS/2 are trademarks of International Business Machines Corporation. Windows is a trademark of Microsoft Corporation. Lab Windows and CVI are trademarks of National Instruments. SPITM is a trademark of Motorola. MICROWIRETM is a trademark of National Semiconductor.
HDR6 HDR7
34
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PART II: SOFTWARE
Using the Software
At start-up, the window START-UP CONFIGURATION appears first. This window contains information concerning the software's title, revision number, copyright date, etc. Additionally, at the top of the screen is a menu bar which displays user options. Notice, the menu bar item Menu is initially disabled. This eliminates any conflicts with the mouse or concurrent use of modems. Before proceeding any further, the user is prompted to select the serial communication port. To initialize a port, pull down option Setup from the menu bar and select either COM1 or COM2. After a port is initialized, it is a good idea to test the RS-232 link between the PC and the evaluation board. To do this, pull down the Setup menu from the menu bar and select the option TESTRS232. The user is then prompted to set the evaluation board's test switches to 011 and then reset the board. Once this is done, proceed with the test. If the test fails, check the hardware connection and repeat again. Otherwise, set the test switches to 000 (normal mode) and reset the board. The option Menu is now available and performance tests can be executed. The evaluation software provides three types of analysis tests - Time Domain, Frequency Domain, and Histogram. The Time Domain analysis processes acquired conversions to produce a plot of Conversion Sample Number versus Magnitude. The Frequency Domain analysis processes acquired conversions to produce a magnitude versus frequency plot using the Fast-Fourier transform (results up to Fs/2 are calculated and plotted). Also, statistical noise calculations are calculated and displayed. The Histogram analysis test processes acquired conversions to produce a histogram plot. Statistical noise calculations are also calculated and displayed (see figures 4 through figure 9). The evaluation software was developed with Lab Windows/CVITM, a software development package from National Instruments. More sophisticated
35
Installation Procedure
To install the software: 1) Turn on the PC. 2) At DOS prompt type WIN to Launch Windows 3.1TM or later. 3) Insert the Installation Diskette into the PC. 4) From within the Windows Program Manager, pull down File from the menu bar and select the Run option. 5) At the prompt type: A:\SETUP.EXE . 6) The program will begin installation. 7) After a few seconds, the user will be prompted to enter the directory in which to install the CVI Run-Time EngineTM. The Run-Time EngineTM manages executable created with Lab Windows/CVITM and takes approximately 1.5 megabytes of hard drive space. If the default directory is acceptable, select OK and the RunTime EngineTM will be installed there. 8) After the Run-Time EngineTM is installed, the user is prompted to enter the directory in which to install the CDB5525/26 software. Select OK to accept the default directory. 9) The program takes a few minutes to install. After the program is installed, double click on the Eval5526 icon to launch it. After a few seconds, the user should be in the CS5525/26 environment.
Note: The software is written to run with 640 x 480 (standard VGA in Windows 3.1TM) resolution; however, it will work with 1024 x 768 resolution. If the user interface seems to be a little small, the user might consider setting the display settings to the 640 x 480 standard (640x480 was chosen to accommodate a variety of computers).
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CDB5525 CDB5526
analysis software can be developed by purchasing the development package from National Instruments (512-794-0100). file save format. The format is: part number, throughput (or sample rate), number of conversions, maximum range, and the data conversions. The user is prompted to enter the path and file name of previously saved data. To prevent hardware conflicts, this option is deactivated while in the Input/Output Window. TESTRS232: This test mode tests the ability of the PC to communicate to the evaluation board. It consists of two subtests: 1) test the link between the PC and the RS-232 interface circuitry; and 2) test the RS-232 link between the PC and the microcontroller. HDR7 distinguishes these two subtests. Set HDR7 to Normal to test the complete communication link. Or set HDR7 to Loop Back to test the link between the RS-232 Circuitry and the PC. Then, set the test switches to 110 and reset the evaluation board. The LED's should indicate a binary six signifying that the hardware is ready to initiate the test. To complete the test, the user must initialize the PC. First, use the SETUP menu to select a communications port and then select the TESTRS232 option. From there, user prompts navigate the user through the test. The PC indicates if the test passes or fails. Once either test is complete, the LED's toggle to indicate that the test mode is complete. PART: Allows user to select a different converter. QUIT: Allows user to exit program.
Menu Bars Overview
The menu bar controls the link between windows and allows the user to exit the program. It also allows the user to initialize the serial port and load presaved data conversions from a file. The five principal windows are the START UP CONFIGURATION (also referred to as the Setup Window), the Input / Output Window, the Histogram Window, the Power Spectrum Window (also referred to as the FFT window), and the Time Domain Window. Specifically, the menu bar has the following control items: Menu: To select, click on option Menu from the menu bar, or use associated hot keys. The items associated with MENU are listed and described below. Setup Window Input/Output Window Histogram Window Power Spectrum Window Time Domain Window (F1) (F2) (F3) (F4) (F5)
These five menu items allow the user to navigate between the five windows. They are available at all times via the menu bar or hot keys. SETUP: To select, click on option Setup from the menu bar. The functions available under Setup are: COM1: When selected, COM1 is initialized to 9600 baud, no parity, 8 data bits, and 1 stop bit. COM2: When selected, COM2 is initialized to 9600 baud, no parity, 8 data bits, and 1 stop bit. Load From Disk: Used to load and display previously saved data conversions from a file. The file must comply with the CDBCAPTURE
36
Input/Output Window Overview
The Input/Output Window allows the user to read and write to the internal register of the converter in either binary or hexadecimal, and acquire real-time conversions. It has quick access control icons that quickly reset the converter, reset the converter's serial port, or self-calibrate the converter's offset and
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CDB5525 CDB5526
gain. The following are controls and indicators associated with this window. Acquire: This is a control icon. When pressed, the PC transmits the collect single conversion command to the microcontroller. The microcontroller in turn collects a conversion from the ADC and returns it to the PC. The PC stores the conversion and collects additional conversions to form a set. From the sample set collected, the high, the low, peak-to-peak, average, and standard deviation, are computed (the size of the data set is set by the Num To Average input) and then the display icons are updated. This process continues until the STOP button is pressed, or until another window is selected. Note: The quick access control icons are disabled once Acquire is selected. This eliminates potential hardware conflicts. BINARY: Input icons set or clear the 24 individual bits in the gain, configuration, or offset registers. The bits are first set, then the control icon Write All Registers is selected to update the registers in the converter. CONFIGURATION REGISTER: Text display box that displays the decoded meaning of each bit in the configuration register. DECIMAL: Three display icons that display in decimal the contents of the gain, configuration, and offset registers. DIGITAL OUTPUT: Display icon that displays the four states of the output latch. GAIN REGISTER: Display icon that displays the decimal equivalent of the bits set in gain register. HEX: Three input/display icons that allow a user to set the 24 bits in the gain, configuration, or offset registers via 6 hexadecimal nibbles. If the upper nibbles in the registers are zero's, then leading zero nibbles need to be entered. Num To Average: Input icon that sets the size of the data conversion set referred to when the Acquire button is pressed. Read All Registers: This is a control icon. When pressed the gain, offset, and configuration registers contents are acquired. Then, the configuration text box and the register content icons are updated. Reinitialize: This is a control icon. When pressed, 128 logic 1's followed by a logic `0' are sent to the ADC's serial port to reset its port. It does not reset the RS-232 link. Reset A/D: This is a control icon. When pressed, the microcontroller sends the appropriate commands to return the converter to its initial default state. SELF Calibrate: This is a control icon. When pressed, the appropriate commands are sent to the ADC to calibrate its own offset and gain. STOP: Stops the collection of conversion data. Write All Registers: This is a control icon. When pressed, the 72 binary input icons settings are acquired. This data is then transmitted to the ADC's gain, offset, and configuration registers. Then, the PC's display is updated to reflect the registers changes.
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Histogram Window Overview
The following is a description of the controls and indicators associated with the Histogram Window. Many of the control icons are usable from the Histogram Window, the Frequency Domain Window, and the Time Domain Window. For brevity, they are only described in this section. BIN: Displays the x-axis value of the cursor on the Histogram. CANCEL: Once selected, it allows a user to exit from the COLLECT algorithm. If data conversion sample sets larger than 64 are being collected and the CANCEL button is selected, it is recommended that the user reset the evaluation board. The board will eventually recover from the continuous collection mode, but the recovery time could be as long as 10 minutes. COLLECT: Initiates the data conversion collection process. COLLECT has two modes of operation: collect from file or collect from converter. To collect from a file an appropriate file from the SETUP-DISK menu bar option must be selected. Once a file is selected, its content is displayed in the graph. If the user is collecting real-time conversions to analyze, the appropriate COM port must be selected. The user is then free to collect the preset number of conversions (preset by the CONFIG pop-up menu discussed below). Notice, there is a significant acquisition time difference in the two methods. CONFIG: Opens a pop-up panel to configure how much data is to be collected, and how to process the data once it is collected. The following are controls and indicators associated with the CONFIG panel. SAMPLES: User selection of 64, 256, 512, 1024, 2048, 4096, or 8192 conversions. WINDOW: Used in the Power Spectrum Window to calculate the FFT. Windowing algorithms include the Blackman, Blackman-Harris, Hann, 5-term Hodie, and 7-term Hodie. The 5-term Hodie and 7term Hodie are windowing algorithms developed at Crystal Semiconductor. If information concerning these algorithms is needed, call technical support. AVERAGE: Sets the number of consecutive FFT's to perform and average. LIMITED NOISE BANDWIDTH: Limits the amount of noise in the converters bandwidth. Default is 0 Hz. OK: Accept the change MAGNITUDE: Displays the y-axis value of the cursor on the Histogram. MAXIMUM: Indicator for the maximum value of the collected data set. MEAN: Indicator for the mean of the data sample set. MINIMUM: Indicator for the minimum value of the collected data set. OUTPUT: Control that calls a pop-up menu. This menu controls three options: 1) save current data set to a file with the CDBCAPTURE format, 2) print current screen, or 3) print current graph. RESTORE: Restores the display of the graph after zoom has been entered. STD. DEV.: Indicator for the Standard Deviation of the collected data set. TEST: Quick access control icon, similar to the hot keys, to allow user to quickly switch between a time domain, a frequency domain, or a histogram display. VARIANCE: Indicates the Variance for the current data set.
38
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ZOOM: Control icon that allows the operator to zoom in on a specific portion of the current graph. To zoom, click on the ZOOM icon, then click on the graph to select the first point (the 1st point is the top left corner of the zoom box). Then click on the graph again to select the second point (the 2nd point is the bottom right corner of the zoom box). Once an area has been zoomed in to, the OUTPUT functions can be used to print a hard copy of that region. Click on RESTORE when done with the zoom function. ZOOM: See description in Histogram Window Overview. # of AVG: Displays the number of FFT's averaged in the current display.
Time Domain Window Overview
The following controls and indicators are associated with the Time Domain Window. CANCEL: See description in Histogram Window Overview. COLLECT: See description in Histogram Window Overview. CONFIG: See description in Histogram Window Overview. COUNT: Displays current x-position of the cursor on the time domain display. MAGNITUDE: Displays current y-position of the cursor on the time domain display. MAXIMUM: Indicator for the maximum value of the collected data set. MINIMUM: Indicator for the minimum value of the collected data set. OUTPUT: See description in Histogram Window Overview. TEST: See description in Histogram Window Overview. ZOOM: See description in Histogram Window Overview.
Frequency Domain Window (i.e. FFT)
The following describe the controls and indicators associated with the Frequency Domain Window. CANCEL: See description in Histogram Window Overview. COLLECT: See description in Histogram Window Overview. CONFIG: See description in Histogram Window Overview. FREQUENCY: Displays the x-axis value of the cursor on the FFT display. MAGNITUDE: Displays the y-axis value of the cursor on the FFT display. OUTPUT: See description in Histogram Window Overview. S/D: Indicator for the Signal-to-Distortion Ratio, 4 harmonics are used in the calculations (decibels). S/N+D: Indicator for the Signal-to-Noise + Distortion Ratio (decibels). SNR: Indicator for the Signal-to-Noise Ratio, first 4 harmonics are not included (decibels). S/PN: Indicator for the Signal-to-Peak Noise Ratio (decibels). TEST: See description in Histogram Window Overview.
Trouble Shooting the Evaluation Board
This section describes special test modes incorporated in the microcontroller software to diagnose hardware problems with the evaluation board.
Note: To enter these modes, set the test switches to the appropriate position and reset the evaluation board. To reenter the normal operation mode, set the switches back to binary zero and reset the board again.
Test Mode 0, Normal Mode: This is the default mode of operation. To enter this mode, set the test
DS202DB5 39
CDB5525 CDB5526
switches to 000 and reset the board. The evaluation board allows normal read/writes to the ADC's registers. All the LED's toggle on then off after reset, and then only when communicating with the PC. Test Mode 1, Loop Back Test: This test mode checks the microcontroller's on-chip UART. To enter this mode, set test switches to 001, set HDR7 for loop back, and then reset the board. If the communication works, all the LED's toggle. Otherwise, only 1/2 of the LED's toggle to indicate a communication problem. Test Mode 2, Read/Write to ADC: This test mode tests the microcontroller's ability to read and write to the ADC. To enter this mode, set the switches to 010 and reset the board. In this test mode, the ADC's configuration, offset, and gain registers are written to and then read from. If the correct data is read back, all the LED's toggle. Otherwise, only half of them toggle to indicate an error. Test Mode 3, Continuously Acquire Single Conversion: This test mode repetitively acquires a single conversion. To enter this mode, set the test switches to 011 and press reset. A binary three is indicated on the LED's. By probing HDR6 and using CS as a triggering pin, an oscilloscope or logic analyzer will display in real-time how the microcontroller reads conversion data. Test Mode 4: Reserved for future modifications. Test Mode 5, Continuously Read Gain Register: This test mode repetitively acquires the gain registers default contents (0x800000 HEX). To enter this mode, set the test switches to 101 and press reset. The LED's should indicate a binary five. By probing HDR6 and using CS as a triggering pin, an oscilloscope or logic analyzer will display in realtime how the microcontroller acquires a conversion. Test Mode 6, PC to Microcontroller RS-232 Communication Link Test: This test mode tests the ability of the PC to communicate to the evaluation board. It consists of two subtests: 1) test the link between the PC and the RS-232 interface circuitry; and 2) test the RS-232 link between the PC and the microcontroller. HDR7 distinguishes these two subtests. Set HDR7 to Normal to test the complete communication link. Or set HDR7 to Loop Back to test the link between the RS-232 Circuitry and the PC. Then, set the test switches to 110 and reset the evaluation board. The LED's should indicate a binary six signifying that the hardware is ready to initiate the test. To complete the test, the user must initialize the PC. First, use the SETUP menu to select a communications port and then select the TESTRS232 option. From there, user prompts navigate the user through the test. The PC indicates if the test passes or fails. Once either test is complete, the LED's toggle to indicate that the test mode is complete. Test Mode 7, Toggle LED's: This test mode tests the evaluation board LED's. To enter this mode, set the test switches to 111 and reset the board. If the mode passes, the LED's toggle.
Note: Remember, to return to the normal operating mode, set the test switches to binary zero, return HDR7 to Normal, and reset the evaluation board.
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Figure 4. Main Menu
Figure 5. Input/Output Window
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Figure 6. Frequency Domain Analysis
Figure 7. Configuration Menu
42
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Figure 8. Time Domain Analysis
Figure 9. Histogram Analysis
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Figure 10. CDB5525/26 Component Side Silkscreen
44
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Figure 11. CDB5525/26 Component Side (top)
DS202DB5
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CDB5525 CDB5526
Figure 12. CDB5525/26 Solder Side (bottom)
46
DS202DB5
* Notes *

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Price & Availability of 5525

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