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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES +2.5 V to +5.5 V Supply Operation 50MHz Serial Interface 8-Bit (Byte Load) serial interface, 6MHz Update Rate 10MHz Multiplying Bandwidth 10V Reference Input 10-Lead SOIC Package Guaranteed Monotonic Four Quadrant Multiplication Power On Reset LDAC function 5A typical Power Consumption
High Bandwidth, CMOS 8-Bit Serial Interface Multiplying DAC AD5425*
FUNCTIONAL BLOCK DIAGRAM
VDD VREF R 8 BIT R-2R DAC RFB IOUT1 IOUT2
AD5425
LDAC Power On Reset
DAC REGISTER
INPUT LATCH
APPLICATIONS Portable Battery Powered Applications Waveform Generators Analog Processing Instrumentation Applications Programmable Amplifiers and Attenuators Digitally-Controlled Calibration Programmable Filters and Oscillators Composite Video Ultrasound Gain, offset and Voltage Trimming
SYNC SCLK SDIN
CONTROL LOGIC & INPUT SHIFT REGISTER
GND
GENERAL DESCRIPTION
The AD5425 is a CMOS 8-bit current output digital-toanalog converter which operates from a +2.5 V to 5.5 V power supply, making it suited to battery powered applications and many other applications. This DAC utilizes a double buffered 3-wire serial interface that is compatible with SPITM, QSPITM, MICROWIRETM and most DSP interface standards. In addition, an LDAC pin is provided which allows simultaneous update in multi DAC configuration. On power-up, the internal shift register and latches are filled with zeros and the DAC outputs are at 0V. As a result of processing on a CMOS sub micron process, this DAC offers excellent four quadrant multiplication characteristics, with large signal multiplying bandwidths of 10MHz.
*US Patent Number 5,689,257 SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.
The applied external reference input voltage (VREF) determines the full scale output current. An integrated feedback resistor (RFB) provides temperature tracking and full scale voltage output when combined with an external I-toV precision amplifier. The AD5425 DAC is available in a small 10-lead SOIC package.
PRODUCT HIGHLIGHTS
1. 2. 3.
10MHz Multiplying Bandwidth 3mm x 5mm 10-lead SOIC package Low Voltage, Low Power Current Output DAC.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
AD5425-SPECIFICATIONS1 T (V = 2.5 V to 5.5 V, V = +10 V, I x = O V. All specifications
DD REF OUT
MIN
to TMAX unless otherwise noted. DC performance measured with
Units Conditions
OP1177, AC performance with AD811 unless otherwise noted.)
Parameter
STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temp Coefficient2 Output Leakage Current Output Voltage Compliance Range REFERENCE INPUT Reference Input Range VREF Input Resistance DIGITAL INPUTS/OUTPUT Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIL Input Capacitance DYNAMIC PERFORMANCE2 Reference Multiplying BW Output Voltage Settling Time Slew Rate Digital to Analog Glitch Impulse Multiplying Feedthrough Error Output Capacitance Digital Feedthrough Total Harmonic Distortion Output Noise Spectral Density SFDR performance Intermodulation Distortion POWER REQUIREMENTS Power Supply Range IDD Power Supply Sensitivity 2 2.5 10 TBD 30 100 3 -75 2 4 5 -85 -85 25 72 TBD 5.5 10 0.001 TBD
2 2
Min
Typ
Max
8 0.5 1 2
5 10 50 TBD 10 10
Bits LSB LSB Guaranteed Monotonic mV ppm FSR/C nA Data = 0000H, TA = 25C, I OUT1 nA Data = 0000H, IOUT1 V V k V V V A pF MHz MHz ns V/s nV-s dB pF pF nV-s dB dB nV/Hz dB dB V A %/%
8 1.7
12
Input resistance TC = -50ppm/C VDD = 2.5 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.5 V to 2.7 V
0.8 0.7 1 10
VREF = 100 mV rms, DAC loaded all 1s VREF = 6 V rms, DAC loaded all 1s Measured to 1/2 LSB. RLOAD = 100, CLOAD = 15pF. DAC latch alternately loaded with 0s and 1s. 1 LSB change around Major Carry DAC latch loaded with all 0s. Reference = 10kHz. DAC Latches Loaded with all 0s DAC Latches Loaded with all 1s Feedthrough to DAC output with SYNC high and Alternate Loading of all 0s and all 1s. VREF = 6 V rms, All 1s loaded, f = 1kHz VREF = 5 V, Sinewave generated from digital code. @ 1kHz
Logic Inputs = 0 V or VDD VDD = 5%
NOTES 1 Temperature range is as follows: B Version: -40C to +105C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA Single Supply Operation (Biased Mode)
Parameter
STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temp Coefficient2 Output Leakage Current Output Voltage Compliance Range REFERENCE INPUT Reference Input Range VREF Input Resistance DIGITAL INPUTS/OUTPUT Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIL Input Capacitance DYNAMIC PERFORMANCE2 Reference Multiplying BW Output Voltage Settling Time Slew Rate Digital to Analog Glitch Impulse Multiplying Feedthrough Error Output Capacitance Digital Feedthrough Total Harmonic Distortion Output Noise Spectral Density SFDR performance Intermodulation Distortion POWER REQUIREMENTS Power Supply Range IDD Power Supply Sensitivity 2 2.5 10 TBD 20 100 3 -75 2 4 5 -85 -85 25 72 TBD 5.5 10 0.001 TBD
2 2
AD5425
(VDD = 2.5 V to 5.5 V, VREF = + 2V, IOUT2 = +1 V. All specifications TMIN to TMAX unless otherwise noted. DC performance measured with OP1177, AC performance with AD811 unless otherwise noted.)
Min Typ Max
8 0.5 1 2 5 10 50 TBD tbd 10
Units
Conditions
Bits LSB LSB Guaranteed Monotonic mV ppm FSR/C nA Data = 0000H, TA = 25C, I OUT1 nA Data = 0000H, IOUT1 V V k V V V A pF MHz MHz ns V/s nV-s dB pF pF nV-s dB dB nV/Hz dB dB V A %/%
8 1.7
12
Input resistance TC = -50ppm/C VDD = 2.5 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.5 V to 2.7 V
0.8 0.7 1 10
VREF = 100 mV rms, DAC loaded all 1s VREF = 2 V p-p, 1 V Bias, DAC loaded all 1s Measured to 1/2 LSB. RLOAD = 100, CLOAD = 15pF. VREF = 0V,DAC latch alternately loaded with 0s & 1s. 1 LSB change around Major Carry DAC latch loaded with all 0s. Reference = 10kHz. DAC Latches Loaded with all 0s DAC Latches Loaded with all 1s Feedthrough to DAC output with SYNC high and Alternate Loading of all 0s and all 1s. VREF = 2 Vp-p, 1 V Bias, All 1s loaded, f = 1kHz VREF = 2 V, Sinewave generated from digital code. @ 1kHz
Logic Inputs = 0 V or VDD VDD = 5%
NOTES 1 Temperature range is as follows: B Version: -40C to +105C. 2 Guaranteed by design and characterisation, not subject to production test. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA
AD5425-SPECIFICATIONS1 (V = 2.5 V to 5.5 TIMING CHARACTERISTICS1,2otherwise noted.) V, V
DD
REF
= +5 V, IOUT2 = O V. All specifications TMIN to TMAX unless
Parameter fSCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11
Limit at TMIN, TMAX 50 20 8 8 13 5 4 5 30 0 12 10
Units MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min
Conditions/Comments Max Clock Frequency SCLK Cycle time SCLK High Time SCLK Low Time SYNC falling edge to SCLK falling edge setup time Data Setup Time Data Hold Time SYNC Rising edge to SCLK falling edge Minimum SYNC high time SCLK Falling edge to LDAC falling edge LDAC pulse width SCLK Falling edge to LDAC rising edge
NOTES 1 See Figure 1. Temperature range is as follows: B Version: -40C to +105C. Guaranteed by design and characterisation, not subject to production test. 2 All input signals are specified with tr =tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Specifications subject to change without notice.
t1 SCLK t2 t8 t4 SYNC t6 t5 DIN DB7 DB0 t10 t9 LDAC1 t11 t3 t7
LDAC2
NOTES 1. ASYNCHRONOUS LDAC UPDATE MODE 2. SYNCHRONOUS LDAC UPDATE MODE
Figure 1. Timing Diagram.
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PRELIMINARY TECHNICAL DATA AD5425
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise noted)
VDD to GND -0.3 V to +7 V VREF, RFB to GND -12 V to +12 V IOUT1, IOUT2 to GND -0.3 V to +7 V -0.3V to VDD +0.3 V Logic Inputs & Output2 Operating Temperature Range Industrial (B Version) -40C to +105C Storage Temperature Range -65C to +150C Junction Temperature +150C 10 lead SOIC JA Thermal Impedance 206C/W Lead Temperature, Soldering (10seconds) 300C IR Reflow, Peak Temperature (<20 seconds) +235C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at SCLK, SYNC, DIN and LDAC will be clamped by internal diodes. Current should be limited to the maximum ratings given.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5425 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Model AD5425BRM
Temperature Range -40 oC to +105 oC
Package Description SOIC
Branding D00
Package Option RM-10
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PRELIMINARY TECHNICAL DATA AD5425
PIN FUNCTION DESCRIPTION
Pin 1 2 3 4 5 6
Mnemonic IOUT1 IOUT2 GND SCLK SDIN SYNC
Function DAC Current Output. DAC Analog Ground. This pin should normally be tied to the analog ground of the system. Digital Ground Pin. Serial Clock Input. Data is clocked into the input shift register on each falling edge of the serial clock input. These devices can accomodate serial input rates of up to 50MHz. Serial Data Input. Data is clocked into the 8-bit input register on each falling edge of the serial clock input. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and the input shift register is enabled. Data is transferred on each falling edge of the following clocks. Load DAC input. Updates the DAC output. The DAC is updated when this signal goes low or alternatively if this line is held permanently low, an automatic update mode is selected whereby the DAC is updated on the 8th clock falling edge. Positive power supply input. These parts can be operated from a supply of +2.5 V to +5.5 V. DAC reference voltage input terminal. DAC feedback resistor pin. Establish voltage output for the DAC by connecting to external amplifier output.
7
LDAC
8 9 10
VDD VREF RFB
PIN CONFIGURATION SOIC
IOUT1 1 IOUT2 2 GND 3 AD5425 (Not to Scale)
10 RFB 9 VREF 8 VDD 7 LDAC 6 SYNC
SCLK 4 SDIN 5
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PRELIMINARY TECHNICAL DATA AD5425
TERMINOLOGY Relative Accuracy Intermodulation Distortion
Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally expressed in LSBs or as a percentage of full scale reading.
Differential Nonlinearity
The DAC is driven by two combinded sine waves references of frequencies fa and fb. Distortion products are produced at sum and difference frequencies of mfanfb where m, n = 0, 1, 2, 3... Intermodulation terms are those for which m or n is not equal to zero. The second order terms include (fa +fb) and (fa - fb) and the third order terms are (2fa + fb), (2fa -fb), (f+2fa + 2fb) and (fa 2fb). IMD is defined as IMD = 20log (rms sum of the sum and diff distortion products)
rms amplitude of the fundamental
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB max over the operating temperature range ensures monotonicity.
Gain Error
Compliance Voltage Range
Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is VREF - 1 LSB. Gain error of the DACs is adjustable to zero with external resistance.
Output Leakage Current
The maximum range of (output) terminal voltage for which the device will provide the specified current-output characteristics.
GENERAL DESCRIPTION DAC Section
Output leakage current is current which flows in the DAC ladder switches when these are turned off. For the IOUT1 terminal, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current will flow in the IOUT2 line when the DAC is loaded with all 1s
Output Capacitance
Capacitance from IOUT1 or IOUT2 to AGND.
Output Current Settling Time
The AD5425 is an 8 bit current output DAC consisting of a standard inverting R-2R ladder configuration. A simplified diagram is shown in Figure 2. The feedback resistor RFB has a value of R. The value of R is typically 10k (minimum 8k and maximum 12k). If IOUT1 and IOUT2 are kept at the same potential, a constant current flows in each ladder leg, regardless of digital input code. Therefore, the input resistance presented at VREF is always constant.
R
VREF
This is the amount of time it takes for the output to settle to a specified level for a full scale input change. For these devices, it is specifed with a 100 resistor to ground.
Digital to Analog Glitch lmpulse
R
2R S2
R
2R S3
2R S1
2R S8
2R
R
RFB A IOUTA IOUT B
The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage signal.
Digital Feedthrough
DAC DATA LATCHES AND DRIVERS
Figure 2. Simplified Ladder
When the device is not selected, high frequency logic activity on the device digital inputs is capacitivelly coupled through the device to show up as noise on the IOUT pins and subsequently into the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
Access is provided to the VREF, RFB, IOUT1 and IOUT2 terminals of the DAC, making the device extremely versatile and allowing it to be configured in several different operating modes, for example, to provide a unipolar output, bipolar output or in single supply modes of operation. in unipolar mode or four quadrant multiplication in bipolar mode.
Unipolar Mode
This is the error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal, when all o0s are loaded to the DAC.
Harmonic Distortion
Using a single op amp, these devices can easily be configured to provide 2 quadrant multiplying operation or a unipolar output voltage swing as shown in Figure 3. When an output amplifier is connected in unipolar mode, the output voltage is given by: VOUT = -D x VREF Where D is the fractional representation of the digital word loaded to the DAC.
The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower order harmonices are included, such as second to fifth. THD = 20log (V22 + V32 + V42 + V52)
V1
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PRELIMINARY TECHNICAL DATA AD5425
VDD R2
Table II. shows the relationship between digital code and the expected output voltage for bipolar operation.
C1
Table II. Bipolar Code Table
VDD VREF R1 VREF AD5426/32/43
RFB IOUT1 IOUT2 VOUT = -D VREF
Digital Input
A1
Analog Output (V) +V REF (127/128) 0 -V REF (127/128) -V REF (128/128)
SYNC SCLK SDIN
GND
1111 1000 0000 0000
1111 0000 0001 0000
uController
AGND
NOTES: 1R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2C1 PHASE COMPENSATION (10pF-15pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
SERIAL INTERFACE
Figure 3. Unipolar Operation
The AD5425 has a simple 3-wire interface which is compatible with SPI/QSPI/MicroWire and DSP interface standards. Data is written to the device in 8 bit words. This 8-bit word consists 8 data bits as shown in Figure 3.
DB7 (MSB) DB0 (LSB) DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4
With a fixed 10 V reference, the circuit shown above will give an unipolar 0V to -10V output voltage swing. When VIN is an ac signal, the circuit performs two-quadrant multiplication. The following table shows the relationship between digital code and expected output voltage for unipolar operation.
Table I. Unipolar Code Table
DATA BITS
Figure 3. 8 bit Input Shift Register Contents
Digital Input 1111 1000 0000 0000 1111 0000 0001 0000
Analog Output (V) -V REF (255/256) -VREF (128/256) = -VREF/2 -V REF (1/256) -VREF (0/256) = 0
Bipolar Operation
In some applications, it may be necessary to generate full 4-Quadrant multplying operation or a bipolar output swing. This can be easily accomplished by using another external amplifier and some external resistors as shown in Figure 4. When VIN is an ac signal, the circuit performs fourquadrant multiplication.
SYNC is an edge-triggered input that acts as a frame synchronization signal and chip enable. Data can only be transferred into the device while SYNC is low. To start the serial data transfer, SYNC should be taken low observing the minimum SYNC falling to SCLK falling edge setup time, t4. After loading 8 data bits to the shift register, the SYNC line is brought high. The contents of the DAC register and the output will be updated by bringing LDAC low any time after the 8 bit data transfer is complete as can be seen in the timing diagram of Figure 1. LDAC may be tied permanently low if required. In order for another serial transfer to take place the interface must be enabled by another falling edge of SYNC.
Low Power Serial Interface
To minimize the power consumption of the device, the interface only powers up fully when the device is being written to, i.e., on the falling edge of SYNC. The SCLK and DIN input buffers are powered down on the rising edge of SYNC.
R3 10k VDD VDD VREF AD5426/32/43 SYNC SCLK SDIN RFB IOUT1 IOUT2 R2 C1 A1 R4 10k A2 VOUT = -VREF to +VREF R5 20k
R1 VREF 10V
GND
uController
AGND NOTES: 1R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC. 2MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 3C1 PHASE COMPENSATION (10pF-15pF) MAY BE REQUIRED IF A1/A2 IS A HIGH SPEED AMPLIFIER.
Figure 4. Bipolar Operation (4 Quadrant Multiplication)
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PRELIMINARY TECHNICAL DATA AD5425
Overview of AD54xx devices Part No Resolution #DACs INL AD5424 AD5425 AD5426 AD5432 AD5433 AD5443 AD5445 8 8 8 10 10 12 12 1 1 1 1 1 1 1 0.5 0.5 0.5 1 1 2 2 Settling Time Interface Package 20ns 20ns 20ns 25ns 25ns 30ns 30ns Parallel Serial Serial Serial Parallel Serial Parallel Features
RU-16, CP-20 10 MHz, 10 ns CS Pulse Width RM-10 Byte Load,10 MHz BW, 50 MHz Serial RM-10 10 MHz BW, 50 MHz Serial RM-10 10 MHz BW, 50 MHz Serial RU-20, CP-20 10 MHz, 10 ns CS Pulse Width RM-10 10 MHz BW, 50 MHz Serial RU-20, CP-20 10 MHz, 10 ns CS Pulse Width
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
10 Lead SOIC (RM-10)
0.122 (3.10) 0.114 (2.90)
10
6
0.122 (3.10) 0.114 (2.90)
1 5
0.199 (5.05) 0.187 (4.75)
PIN 1 0.0197 (0.50) BSC 0.120 (3.05) 0.112 (2.85) 0.043 (1.10) MAX 0.028 (0.70) 0.016 (0.40) 0.120 (3.05) 0.112 (2.85)
0.037 (0.94) 0.031 (0.78)
6 0.006 (0.15) 0.012 (0.30) SEATING 0 PLANE 0.009 (0.23) 0.002 (0.05) 0.006 (0.15) 0.005 (0.13)
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