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74LCX646
LOW VOLTAGE CMOSOCTAL BUSTRANSCEIVER/REGISTER (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS
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5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED: tPD = 7.0 ns (MAX.) at VCC = 3V POWER-DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) PCI BUS LEVELS GUARANTEED AT 24mA BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2.0V to 3.6V (1.5V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 646 LATCH-UP PERFORMANCE EXCEEDS 500mA ESD PERFORMANCE: HBM >2000V; MM > 200V
M (Micro Package)
T (TSSOP Package)
ORDER CODES : 74LCX646M 74LCX646T This device consists of bus transceiver circuits with 3-state outputs, D type flip-flops, and control circuitry arranged for multiplexed trasmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into registers on the low-to high transition of the appropriate clock pin (clock AB or clock BA). Enable (G) and direction (DIR) pins are provided to control the transceiver functions. In the transceiver mode, data present at the high impedance port may be stored in either register or in both. The selected controls (Select AB Select BA) can multiplex stored and real time (transparent mode) data. The direction control determines which bus
DESCRIPTION The LCX646 is a low voltage CMOS OCTAL BUS TRANSCEIVER AND REGISTER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs. PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1999
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will receive data when enable G is active (low). In the isolation mode (enable G high), "A" data may be stored in one register and/or "B" data may be stored in the other register. When an output bus is disabled, the input bus is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. INPUT AND OUTPUT EQUIVALENT CIRCUIT It has same speed performance at 3.3V than 5V, AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
PIN DESCRIPTION
PIN No 1 2 3 4, 5, 6, 7, 8, 9, 10, 11 20, 19, 18, 17, 16, 15, 14, 13 21 22 23 12 24 SYMBOL CAB SAB DIR A1 to A8 B1 to B8 G SBA CBA GND VCC NAME AND FUNCTION A to B Clock Input (LOW to HIGH, Edge-Trigged) Select A to B Source Input Direction Control Input A Data Inputs/Outputs B Data Inputs/Outputs Output Enable Input (Active LOW) Select B to A Source Input B to A Clock Input (LOW to HIGH, Edge-Triggered) Ground (0V) Positive Supply Voltage
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LOGIC DIAGRAM
TIMING CHART
CAB CBA
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TRUTH TABLE
G DIR CAB CBA SAB SBA A INPUTS X H X X X X X X Z INPUTS B INPUTS Z INPUTS FUNCTIO N Both the A bus and the B bus are inputs The output functions of the A and B bus are disabled Both the A and B bus are used as inputs to the internal flip-flops. Data on the bus will be stored on low to high transition of the clock inputs The data at the A bus are displayed on the B bus The data on the A bus are displayed on the B bus. The data on the A bus are stored in the A internal flip-flop on low to high transition of th clock pulse. The data stored to the internal flip-flop are dispayed on the B bus The data on the A bus are stored in the A internal flip-flop on low to high transition of the clock pulse. The states of the A internal flip-flops propagate directly to the B bus The B bus are inputs and the A bus are outputs The data on the B bus are displayed on the A bus The data on the B bus are displayed on the A bus. The data on the B bus are stored on the B internal flip-flop on low to high transition of the clock pulse The data stored in the B internal flip-flops are displayed on the A bus The data on the B bus are stored in the B internal flipflop on low to high transition of the clock pulse. The states of the B internal flip-flops propagate output directly to the A bus
INPUTS X X* X* L H X X* X* H H X X L L X X L H L H X L H
OUTPUTS The A bus are inputs and the B bus are outputs L H L H Qn L H
OUTPUTS X* X* L L X* x* X X X H H Qn L H X X X L L L H L H
INPUTS L H L H X L H
X Z Qn *
: DON'T CARE : HIGHIMPEDANCE : THE DATA STORED TO THE INTERNALFLIP-FLOPS BY MOST RECENTLOW TO HIGH TRANSITION OF THE CLOCK INPUTS : THE DATA AT THE A AND B BUS WILLBE STORED TOTHE INTERNALFLIP-FLOPS ON EVERYLOW TO HIGH TRANSITION OF
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ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO VO IIK IOK IO ICC IGND Tstg TL Supply Voltage DC Input Voltage DC Output Voltage (OFF state) DC Output Voltage (High or Low State) (note1) DC Input Diode Current DC Output Diode Current (note2) DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Supply Pin Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to + 7.0 -0.5 to + 7.0 -0.5 to + 7.0 -0.5 to VCC + 0.5 - 50 50 50 100 100 -65 to +150 300 Unit V V V V mA mA mA mA mA
o o
C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. 1) IO absolute maximum rating must be observed 2) VO < GND, VO > VCC
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO VO IOH, IOL IOH, IOL Top dt/dv Input Voltage Output Voltage (OFF state) Output Voltage (High or Low State) High or Low Level Output Current (VCC = 3.0 to 3.6V) High or Low Level Output Current (VCC = 2.7 to 3.0V) Operating Temperature: Input Transition Rise or Fall Rate (V CC = 3.0V) (note 2) Parameter Supply Voltage (note 1) Value 2.0 to 3.6 0 to 5.5 0 to 5.5 0 to VCC 24 12 -40 to +85 0 to 10 Unit V V V V mA mA
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1) Truth Table guaranteed: 1.5V to3.6V 2) VIN from0.8V to 2.0V
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DC SPECIFICATIONS
Symb ol Parameter V CC (V) VIH VIL VOH High Level Input Voltage Low Level Input Voltage High Level Output Voltage 2.7 to 3.6 2.7 to 3.6 2.7 3.0 VOL Low Level Output Voltage 2.7 to 3.6 2.7 3.0 3.0 II IOZ Ioff ICC Input Leakage Current 3 State Output Leakage Current Power Off Leakage Current Quiescent Supply Current 2.7 to 3.6 2.7 to 3.6 0 2.7 to 3.6 VI = VI H or V IL Test Co nditi ons Value -40 to 85 o C Min. 2.0 0.8 IO=-100 A V CC -0.2 IO=-12 mA IO=-18 mA IO=-24 mA VI = VI H or V IL IO=100 A IO=12 mA IO=16 mA IO=24 mA VI = 0 to 5.5 V VI = VIH or VIL VO = 0 to 5.5V VI or VO = 5.5V VI = VCC or GND VI or VO = 3.6 to 5.5V ICC ICC incr. per input 2.7 to 3.6 VIH = VCC -0.6V 2.2 2.4 2.2 0.2 0.4 0.4 0.55 5 5 100 10 10 500 A A A A A V V Max. V V Un it
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol Parameter V CC (V) VOLP VOLV Dynamic Low Voltage Quiet Output (note 1) 3.3 C L = 50 pF V IL = 0 V V IH = 3.3V Test Con dition s Min . Value T A = 25 o C T yp. 0.8 -0.8 V Max. Un it
1) Number ofoutputs defined as "n". Measured with"n-1" outputs switching from HIGH to LOW or LOW t o HIGH. The remaining output is measured in the LOW state.
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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = tf = 2.5 ns)
Symb ol Parameter V CC (V) tPLH tPHL tPLH tPHL tPLH tPHL tPZL tPZH tPLZ tPHZ ts th tw fMAX tOSLH tOSHL Propagation Delay Time CAB or CBA to An or Bn Propagation Delay Time An to Bn or Bn to An Propagation Delay Time SAB or SBA to An or Bn Output Enable Time G, DIR to An, Bn Output Disable Time G, DIR to An, Bn Setup Time, HIGH or LOW Level Data to CAB, CBA Hold Time, HIGH or LOW Level Data to CAB, CBA CAB, CBA Pulse Width, HIGH or LOW Clock Pulse Frequency Output to Output Skew Time (note 1, 2) 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 Test Con dition Waveform Value -40 to 85 o C Min. Max. 1.5 9.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 2.5 1.5 1.5 4.0 3.3 150 1.0 8.5 8.0 7.0 9.5 8.5 9.5 8.5 9.5 8.5 Un it
3 1 1 2 2 3 3 4 3
ns ns ns ns ns ns ns ns MHz ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tpHLn|) 2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
Symb ol Parameter V CC (V) C IN C i/o CPD Input Capacitance I/O Capacitance Power Dissipation Capacitance (note 1) 3.3 3.3 3.3 VIN = 0 to VCC VIN = 0 to VCC fIN = 10MHz VIN = 0 or VCC Test Co nditi ons Min. Valu e T A = 25 C T yp. 6 10 37 Max. pF pF pF
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Un it
1) CPD isdefined as the value of the IC'sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. Average operting current can be obtained by the following equation. I CC(opr) = CPD * VCC * fIN + ICC/8 (per circuit)
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TEST CIRCUIT
T EST tPLH , tPHL tPZL , tPLZ tPZH , tPHZ
CL = 50 pF or equivalent (includes jigand probe capacitance) RL = R1 = 500 orequivalent RT = ZOUT of pulse generator (typically 50)
SW IT CH Open 6V GND
WAVEFORM 1: PROPAGATION DELAYS, SAB, SBA, An, Bn TIMES (f=1MHz; 50% duty cycle)
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WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
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WAVEFORM 3: PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 4: PULSE WIDTH
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SO-24 MECHANICAL DATA
mm MIN. A a1 a2 b b1 C c1 D E e e3 F L S 7.40 0.50 15.20 10.00 1.27 13.97 7.60 1.27 8 (max.) 0.291 0.19 15.60 10.65 0.35 0.23 0.50 45 (typ.) 0.598 0.393 0.05 0.55 0.299 0.050 0.614 0.420 0.10 TYP. MAX. 2.65 0.20 2.45 0.49 0.32 0.013 0.009 0.020 0.004 MIN. inch TYP. MAX. 0.104 0.007 0.096 0.019 0.012
DIM.
L C c1
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P013T
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74LCX646
TSSOP24 MECHANICAL DATA
mm MIN. A A1 A2 b c D E E1 e K L 0o 0.50 0.05 0.85 0.19 0.09 7.7 6.25 4.3 7.8 6.4 4.4 0.65 BSC 4o 0.60 8o 0.70 0o 0.020 0.10 0.9 TYP. MAX. 1.1 0.15 0.95 0.30 0.2 7.9 6.5 4.48 0.002 0.335 0.0075 0.0035 0.303 0.246 0.169 0.307 0.252 0.173 0.0256 BSC 4o 0.024 8o 0.028 0.004 0.354 MIN. inch TYP. MAX. 0.433 0.006 0.374 0.0118 0.0079 0.311 0.256 0.176
DIM.
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A2 A1 b e K c L E
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PIN 1 IDENTIFICATION
1
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com .
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