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Final Electrical Specifications
LT3150 Fast Transient Response, Low Input Voltage, Very Low Dropout Linear Regulator Controller August 2002 DESCRIPTION
The LT(R)3150 drives a low cost external N-channel MOSFET as a source follower to produce a fast transient response, very low dropout voltage linear regulator. Selection of the N-channel MOSFET RDS(ON) allows dropout voltages below 300mV for low VIN to low VOUT applications. The LT3150 includes a fixed frequency boost regulator that generates gate drive for the N-channel MOSFET. The internally compensated current mode PWM architecture combined with the 1.4MHz switching frequency permits the use of tiny, low cost capacitors and inductors. The LT3150's transient load performance is optimized with ceramic output capacitors. A precision 1.21V reference accommodates low voltage supplies. Protection includes a high side current limit amplifier that activates a fault timer circuit. A multifunction shutdown pin provides either current limit time-out with latchoff, overvoltage protection or thermal shutdown. Independent shutdown control of the boost converter provides on/off and sequencing control of the LDO output voltage.
FEATURES
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Fast Transient Response Optimized with Ceramic Output Capacitors FET RDS(ON) Defines Dropout Voltage 1% Reference Tolerance Over Temperature Multifunction LDO Shutdown Pin with Latchoff Fixed Frequency 1.4MHz Boost Converter Generates MOSFET Gate Drive Internally Compensated Current Mode PWM Boost Converter Uses Tiny Capacitors and Inductor Independent Boost Converter Shutdown Control Permits LDO Output Voltage Supply Sequencing 16-Lead SSOP Package
APPLICATIONS
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Microprocessor, ASIC and I/O Supplies Very Low Dropout Input-to-Output Conversion Logic Termination Supplies
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATION
1.8V to 1.5V, 4A Very Low Dropout Linear Regulator (Typical Dropout Voltage = 65mV at IOUT = 4A)
L1 10H D1 MBR0520L R2 6.19k 1% LT3150 SW FB1 SWGND GND1 VIN1 SHDN1 SHDN2 IPOS VIN2 INEG GND2 GATE NC NC FB2 COMP R1 1.37k 1%
+
C1 4.7F
50mV/DIV
RG 5.1
VIN 1.8V Q1 Si4410
R5 243 1% R6 1020 1%
2A/DIV
VOUT 1.5V 4A
+
C3 50pF
R4 1.5k C2 6800pF
COUT 2.2F x10 X5R CERAMIC 0805 CASE
CIN 220F 2.5V x2
3150 TA01
CIN: PANASONIC SP SERIES EEFUE0E221R 20% C1: AVX TAJA475M020R 20V 20% L1: MURATA LQH32CN100K11 OR SUMIDA CDRH3D16100
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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Transient Response for 0.1A to 4A Output Load Step
20s/DIV
3150 TA02
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LT3150
ABSOLUTE
(Note 1)
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PACKAGE/ORDER I FOR ATIO
TOP VIEW SW SWGND VIN1 SHDN2 VIN2 GND NC FB2 1 2 3 4 5 6 7 8 16 FB1 15 GND 14 SHDN1 13 IPOS 12 INEG 11 GATE 10 NC 9 COMP
VIN1, SHDN1 Voltage .............................................. 10V SW Voltage .............................................. - 0.4V to 36V FB1 Voltage ................................................ VIN1 + 0.3V Current into FB1, FB2 Pin .................................... 1mA VIN2, IPOS, INEG ....................................................... 22V SHDN2 .................................................................... VIN2 Operating Ambient Temperature Range ..... 0C to 70C Junction Temperature (Note 2) ........................... 125C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER LT3150CGN
GN PART MARKING 3150
GN PACKAGE 16-LEAD PLASTIC SSOP
TJMAX = 125C, JA = 130C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN1 = 1.5V, VSHDN1 = VIN1, VIN2 = 12V, GATE = 6V, IPOS = INEG = 5V, VSHDN2 = 0.75V unless otherwise noted.
SYMBOL PARAMETER VIN1 Minimum Operating Voltage VIN1 Maximum Operating Voltage VFB1 IQ1 FB1 Reference Voltage FB1 Input Bias Current VIN1 Quiescent Current VIN1 Quiescent Current in Shutdown FB1 Reference Line Regulation Switching Frequency Maximum Duty Cycle Switch Current Limit Switch VCESAT Switch Leakage Current SHDN1 Input Voltage High SHDN1 Input Voltage Low SHDN1 Input Bias Current Linear Regulator Controller IQ2 VFB2 VIN2 Quiescent Current FB2 Reference Voltage
q q q
CONDITIONS
MIN
TYP 0.9
MAX 1.1 10 1.255 80 4.5 0.5 1.0 0.2 1.9
UNITS V V V nA mA A A %/V MHz % mA
Boost Switching Regulator
1.20
1.23 27 3 0.01 0.01 0.02
Current Flows into Pin VSHDN1 = 1.5V VSHDN1 = 0V, VIN1 = 2V VSHDN1 = 0V, VIN1 = 5V 1.5V VIN1 10V
q
q q
1 82 550
1.4 86 800 300 0.01
(Note 3) ISW = 300mA VSW = 5V
350 1 0.3
1 VSHDN1 = 3V, Current Flows into Pin VSHDN1 = 0V, Current Flows into Pin 5 1.203 1.198 25 0.01 12 1.210 1.210 0.01 -0.6 50 0.1 19 1.217 1.222 0.03 -4
FB2 Line Regulation FB2 Input Bias Current
10V VIN2 20V FB2 = VFB2, Current Flows out of Pin
q q
2
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mV A V V A A mA V V %/V A
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LT3150
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN1 = 1.5V, VSHDN1 = VIN1, VIN2 = 12V, GATE = 6V, IPOS = INEG = 5V, VSHDN2 = 0.75V unless otherwise noted.
SYMBOL AVOL VOL VOH PARAMETER Large-Signal Voltage Gain GATE Output Swing Low (Note 4) GATE Output Swing High IPOS + INEG Supply Current Current Limit Threshold Voltage
q
CONDITIONS VGATE = 3V to 10V IGATE = 0mA IGATE = 0mA 3V IPOS 20V
q q q q
MIN 69 VIN2 - 1.6 0.3 42 37
TYP 84 2.5 VIN2 - 1 0.625 50 50 - 0.20
MAX 3
UNITS dB V V
1 58 63 - 0.50 8.0 - 23 0.25 2.20 1.240 150
mA mV mV %/V A A V V V mV
Current Limit Threshold Voltage Line Regulation SHDN2 Sink Current SHDN2 Source Current SHDN2 Low Clamp Voltage SHDN2 High Clamp Voltage SHDN2 Threshold Voltage SHDN2 Threshold Hysteresis
3V IPOS 20V Current Flows Into Pin Current Flows Out of Pin
q q q q q q q
2.5 -8 1.50 1.18 50
5.0 - 15 0.1 1.85 1.21 100
Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD * 130C/W)
Note 3: Switch current limit is guaranteed by design and/or correlation to static test. Note 4: The VGS(th) of the external MOSFET must be greater than 3V - VOUT.
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LT3150 TYPICAL PERFOR A CE CHARACTERISTICS
Boost Switching Regulator
Switch VCESAT vs Switch Current
700 600 500 TA = 25C
SWITCHING FREQUENCY (MHz)
SHDN1 INPUT BIAS CURRENT (A)
VCESAT (mV)
400 300 200 100 0 0 100 200 300 400 500 SWITCH CURRENT (mA) 600 700
Switch Current Limit vs Duty Cycle
1000 900
SWITCH CURRENT LIMIT (mA)
FB1 REFERENCE VOLTAGE (V)
800 70C 700 600 500 400 300 200 10 20 30 40 50 60 DUTY CYCLE (%) 70 80 -40C 25C
Linear Regulator Controller
VIN2 Quiescent Current vs Temperature
19 18 17 16 15 VIN = 12V 14 VIN = 20V 13 12 VIN = 8V 11 10 9 8 7 6 5 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3150 G06
VIN2 QUIESCENT CURRENT (mA)
FB2 INPUT BIAS CURRENT (A)
FB2 REFERENCE VOLTAGE (V)
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Oscillator Frequency vs Temperature
2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 -50 VIN = 1.5V VIN = 5V 50
SHDN1 Input Bias Current vs VSHDN1
TA = 25C
40
30
20
10
0 -25 0 25 50 TEMPERATURE (C) 75 100
3150 G02
0
1
2 3 4 SHDN1 PIN VOLTAGE (V)
5
3150 G03
3150 G01
FB1 Reference Voltage vs Temperature
1.25
1.24 VOLTAGE 1.23
1.22
1.21
1.20 -50
-25
0 25 50 TEMPERATURE (C)
75
100
3150 G05
3150 G04
FB2 Reference Voltage vs Temperature
1.222 1.220 1.218 1.216 1.214 1.212 1.210 1.208 1.206 1.204 1.202 1.200 1.198 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3150 G07
FB2 Input Bias Current vs Temperature
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 VIN = 20V VIN = 12V VIN = 8V
0 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3150 G08
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LT3150 TYPICAL PERFOR A CE CHARACTERISTICS
FB2 Line Regulation vs Temperature
0.030 0.025 0.020 0.015 0.010 0.005 0 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3150 G09
ERROR AMPLIFIER GAIN (dB) AND PHASE (DEG)
LARGE-SIGNAL VOLTAGE GAIN (dB)
FB2 LINE REGULATION (%/V)
Gate Output Swing Low vs Temperature
3.00 2.75 ILOAD = 50mA GATE OUTPUT SWING HIGH (V)
2.5 2.0 1.5 1.0 3.0
2.50 NO LOAD 2.25 2.00 1.75 1.50 1.25 1.00 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3150 G12
IPOS + INEG SUPPLY CURRENT (A)
GATE OUTPUT SWING LOW (V)
Current Limit Threshold Voltage vs Temperature
CURRENT LIMIT THRESHOLD VOLTAGE (mV)
65 60 55 50 IPOS = 20V 45 40 35 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3150 G15
CURRENT LIMIT THRESHOLD VOLTAGE LINE REGULATION (%/V)
SHDN2 SINK CURRENT (A)
IPOS = 5V IPOS = 3V
UW
Linear Regulator Controller
Error Amplifier Large-Signal Voltage Gain vs Temperature
120 115 110 105 100 95 90 85 80 75 70 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3150 G10
Gain and Phase vs Frequency
200
150 PHASE 100 GAIN 50
0 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M
3150 G11
Gate Output Swing High (VIN2 - VGATE) vs Temperature
1000 900 800 700 600 500 400
IPOS + INEG Supply Current vs Temperature
ILOAD = 50mA
IPOS = INEG = 5V IPOS = INEG = 12V IPOS = INEG = 20V IPOS = INEG = 3V
NO LOAD 0.5 0 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3150 G13
300 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3150 G14
Current Limit Threshold Voltage Line Regulation vs Temperature
0 7.5 7.0 - 0.1 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 - 0.5 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3150 G16
SHDN2 Sink Current vs Temperature
- 0.2
- 0.3
- 0.4
2.5 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3150 G17
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LT3150 TYPICAL PERFOR A CE CHARACTERISTICS
SHDN2 Source Current vs Temperature
-10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3150 G18
SHDN2 LOW CLAMP VOLTAGE (V)
SHDN2 SOURCE CURRENT (A)
SHDN2 High Clamp Voltage vs Temperature
2.1
SHDN2 HIGH CLAMP VOLTAGE (V)
2.0
SHDN2 HYSTERESIS (mV)
1.9 1.8 1.7 1.6 1.5 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3150 G20
PI FU CTIO S
SW (Pin 1): Boost Converter Switch Pin. Connect inductor/diode here. Minimize trace area at this pin to keep EMI down. SWGND (Pin 2): Switch Ground. Tie directly to the local ground plane and the GNDs at Pins 6 and 15. VIN1 (Pin 3): Boost Converter Input Supply Pin. Must be locally bypassed. SHDN2 (Pin 4): This is a multifunction shutdown pin that provides GATE drive latchoff capability. A 15A current source, that turns on when current limit is activated, charges a capacitor placed in series with SHDN2 to GND and performs a current limit time-out function. The pin is also the input to a comparator referenced to VREF (1.21V). When the pin pulls above VREF, the comparator latches the gate drive to the external MOSFET off. The comparator typically has 100mV of hysteresis and the SHDN2 pin can be pulled low to reset the latchoff function. This pin provides overvoltage protection or thermal shutdown protection when driven from various resistor divider schemes.
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Linear Regulator Controller
SHDN2 Low Clamp Voltage vs Temperature
0.25
0.20
0.15
0.10
0.05
0 - 75 - 50 - 25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3150 G19
SHDN2 Hysteresis vs Temperature
150 140 130 120 110 100 90 80 70 60 50 -75 - 50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3150 G21
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LT3150
PI FU CTIO S
VIN2 (Pin 5): This is the input supply for the linear regulator control circuitry and provides sufficient gate drive compliance for the external N-channel MOSFET. The maximum operating VIN2 is 20V and the minimum operating VIN2 is set by VOUT + (VGS of the MOSFET at max IOUT) + 1.6V (worst-case VIN2 to GATE output swing). GND (Pin 6): Analog Ground. This pin is also the negative sense terminal for the internal 1.21V reference. Connect the LDO regulator external feedback divider network and frequency compensation components that terminate to GND directly to this pin for best regulation and performance. NC (Pins 7, 10): No Connect. FB2 (Pin 8): This is the inverting input of the error amplifier for the linear regulator. The noninverting input is tied to the internal 1.21V reference. Input bias current for this pin is typically 0.6A flowing out of the pin. Tie this pin to a resistor divider network to set output voltage. Tie the top of the external resistor divider directly to the output load for best regulation performance. COMP (Pin 9): This is the high impedance gain node of the error amplifier and is used for external frequency compensation. The transconductance of the error amplifier is 15 millimhos and open-loop voltage gain is typically 84dB. Frequency compensation is generally performed with a series RC + C network to ground. GATE (Pin 11): This is the output of the error amplifier that drives N-channel MOSFETs with up to 5000pF of "effective" gate capacitance. The typical open-loop output impedance is 2. When using low input capacitance MOSFETs (< 1500pF), a small gate resistor of 2 to 10 dampens high frequency ringing created by an LC resonance due to the MOSFET gate's lead inductance and input capacitance. The GATE pin delivers up to 50mA for a few hundred nanoseconds when slewing the gate of the N-channel MOSFET in response to output load current transients. INEG (Pin 12): This is the negative sense terminal of the current limit amplifier. A small sense resistor is connected in series with the drain of the external MOSFET and is connected between the IPOS and INEG pins. A 50mV threshold voltage in conjunction with the sense resistor value sets the current limit level. The current sense resistor can be a low value shunt or can be made from a piece of PC board trace. If the current limit amplifier is not used, tie the INEG pin to IPOS to defeat current limit. An alternative is to ground the INEG pin. This action disables the current limit amplifier and additional internal circuitry activates the timer circuit on the SHDN2 pin if the GATE pin swings to the VIN rail. This option provides the user with a No RSENSETM current limit function. IPOS (Pin 13): This is the positive sense terminal of the current limit amplifier. Tie this pin directly to the main input voltage from which the output voltage is regulated. SHDN1 (Pin 14): Boost Regulator Shutdown Pin. Tie to 1V or more to enable device. Ground to shut down. This pin must not float for proper operation. Connect SHDN1 externally as it does not incorporate an internal pull-up or pull-down. GND (Pin 15): Boost Converter Analog Ground. This pin is also the negative sense terminal for the FB1 1.23V reference. Connect the external feedback divider network, which sets the VIN2 supply voltage and terminates to GND, directly to this pin for best regulation and performance. Also, tie this pin directly to SWGND (Pin 2) and GND (Pin 6). FB1 (Pin 16): Boost Regulator Feedback Pin. Reference voltage is 1.23V. Connect resistive divider tap here. Minimize trace area at FB1. Set VOUT = VIN2 according to VOUT = 1.23V(1 + R1/R2).
No RSENSE is a trademark of Linear Technology Corporation.
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LT3150
BLOCK DIAGRA S
Boost Switching Regulator
VIN1 3 R5 40k VIN2 R1 (EXTERNAL) FB1 Q1 FB1 16 R2 (EXTERNAL) Q2 x10 R3 30k R4 140k R6 40k VIN1 gm = 77mhos
A1
-
CC 40pF
1.4MHz OSCILLATOR SHDN1 14 SHUTDOWN
GND 15
Linear Regulator Controller
I1 15A SW1 SHDN2 4 R10 5k NORMALLY OPEN OR1 D1 VTH1 50mV IPOS 13 INEG 12
+
COMP1 I2 5A SW2 NORMALLY CLOSED Q9
-
100mV HYSTERESIS
OR2
VIN2 5 GND VOUT 6 START-UP VREF
1.21V
COMP3
R7 (EXTERNAL) FB2 FB2 8 I3 100A Q4 R9 50k Q5
+
ERROR AMP
-
COMP 9 Q7 Q6
3150 BD02
R8 (EXTERNAL)
8
-
+
+
RC 100k
RAMP GENERATOR
-
W
+
1 SW COMPARATOR FF S DRIVER Q Q3
A2
R
+
ILIM1 0.15
-
2 SWGND
3150 BD1
+
ILIM2 AMP
+ -
-
D2 COMP2
- +
VTH2 1V
+ -
GATE 11 Q8
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APPLICATIO S I FOR ATIO
Introduction
With each new generation of computing systems, total power increases while system voltages fall. CPU core, logic and termination supplies below 1.8V are now common. Power supplies must not only regulate low output voltages, but must also operate from low input voltages. A low voltage, very low dropout linear regulator is an attractive conversion option for applications with output current in the range of several amperes. Component count and cost are low in comparison with switching regulator solutions and with low input-to-output differential voltages, efficiencies are comparable. In addition to low input-to-output voltage conversion, these systems require stringent output voltage regulation. The output voltage specification includes input voltage change, output load current change, temperature change and output load current transient response. Total tolerances as low as 2% are now required. For a 1.5V output voltage, this amounts to a mere 30mV. Transient load current response is the most critical component as output current can cycle from zero to amps in tens of nanoseconds. These requirements mandate the need for a very accurate, very high speed regulator. Historically employed solutions include monolithic 3-terminal linear regulators, PNP transistors driven by low cost control circuits and simple buck converter switching regulators. The 3-terminal regulator provides high integration, the PNP driven regulator provides low dropout performance and the switching regulator provides high electrical efficiency. However, these solutions manifest a common trait of transient response measured in many microseconds. This fact translates to a regulator output decoupling capacitor scheme requiring several hundred microfarads of very low ESR bulk capacitance using multiple capacitors in parallel. This required bulk capacitance is in addition to the ceramic decoupling capacitor network that handles the transient
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load response during the first few hundred nanoseconds as well as providing high frequency noise immunity. The combined cost of all capacitors is a significant percentage of the total power supply cost. The LT3150 controller IC is a unique, easy-to-use device that drives an external N-channel MOSFET as a source follower and realizes an extremely low dropout, ultrafast transient response regulator. The circuit achieves superior regulator bandwidth and transient load performance by eliminating expensive special polymer, tantalum or bulk electrolytic capacitors in the most demanding applications. Performance is optimized around the latest generation of low cost, low ESR, readily available ceramic capacitors. Users benefit directly by saving significant cost as all bulk capacitance is removed. Additional savings include insertion cost, purchasing/inventory cost and board space. The precision-trimmed adjustable voltage LT3150 accommodates most power supply voltages. Proper selection of the N-channel MOSFET RDS(ON) allows user-settable dropout voltage performance. Transient load step performance is optimized for ceramic output capacitor networks allowing the regulator to respond to transient load changes in a few hundred nanoseconds. The output capacitor network typically consists of multiple 1F to 10F ceramic capacitors in parallel depending on the power supply requirements. The LT3150 also incorporates current limiting, on/off control for power supply sequencing and overvoltage protection or thermal shutdown with simple external components. The LT3150 combines the benefits of low input voltage operation, very low dropout voltage performance, precision regulation and fast transient response. With low input/output differential voltage applications becoming the norm, an LT3150-based solution is a practical alternative to switching regulators providing comparable efficiency performance at an appreciable cost savings.
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APPLICATIO S I FOR ATIO
Block Diagram Operation
Gate drive for the external N-channel MOSFET in the linear regulator loop is provided by a current mode, internally compensated, fixed frequency step-up switching regulator. Referring to the Block Diagram, Q1 and Q2 form a bandgap reference core whose loop is closed around the output of the regulator. The voltage drop across R5 and R6 is low enough such that Q1 and Q2 do not saturate, even when VIN1 is 1V. When there is no load, FB1 rises slightly above 1.23V, causing VC (the error amplifier's output) to decrease. Comparator A2's output stays high, keeping switch Q3 in the off state. As increased output loading causes the FB1 voltage to decrease, A1's output increases. Switch current is regulated directly on a cycle-by-cycle basis by the VC node. The flip flop is set at the beginning of each switch cycle, turning on the switch. When the summation of a signal representing switch current and a ramp generator (introduced to avoid subharmonic oscillations at duty factors greater than 50%) exceeds the VC signal, comparator A2 changes state, resetting the flip flop and turning off the switch. More power is delivered to the output as switch current is increased. The output voltage, attenuated by external resistor divider R1 and R2, appears at the FB1 pin, closing the overall loop. Frequency compensation is provided internally by RC and CC. Transient response can be optimized by the addition of a phase lead capacitor CPL in parallel with R1 in applications where large value or low ESR output capacitors are used. As the load current is decreased, the switch turns on for a shorter period each cycle. If the load current is further decreased, the converter will skip cycles to maintain output voltage regulation. The linear regulator controller section of the LT3150 Block Diagram consists of a simple feedback control loop and multiple protection functions. Examining the Block Diagram for the LT3150, a start-up circuit provides controlled start-up, including the precision-trimmed bandgap reference, and establishes all internal current and voltage biasing. Reference voltage accuracy at the FB2 pin is specified as 0.6% at room temperature and as 1% over the full operating temperature range. This places the LT3150 among a select group of regulators with a very tightly
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specified reference voltage tolerance. The 1.21V reference is tied to the noninverting input of the main error amplifier in the feedback control loop. The error amplifier consists of a single high gain gm stage with a transconductance equal to 15 millimhos. The inverting terminal is brought out as the FB2 pin. The gm stage provides differential-to-single ended conversion at the COMP pin. The output impedance of the gm stage is about 1M and thus, 84dB of typical DC error amplifier open-loop gain is realized along with a typical 75MHz uncompensated unity-gain crossover frequency. Note that the overall feedback loop's DC gain decreases from the gain provided by the error amplifier by the attenuation factor in the resistor divider network which sets the DC output voltage. External access to the high impedance gain node of the error amplifier permits typical loop compensation to be accomplished with a series RC + C network to ground. A high speed, high current output stage buffers the COMP node and drives up to 5000pF of "effective" MOSFET gate capacitance with almost no change in load transient performance. The output stage delivers up to 50mA peak when slewing the MOSFET gate in response to load current transients. The typical output impedance of the GATE pin is typically 2. This pushes the pole due to the error amplifier output impedance and the MOSFET input capacitance well beyond the loop crossover frequency. If the capacitance of the MOSFET used is less than 1500pF, it may be necessary to add a small value series gate resistor of 2 to 10. This gate resistor helps damp the LC resonance created by the MOSFET gate's lead inductance and input capacitance. In addition, the pole formed by this resistance and the MOSFET input capacitance can be fine tuned. Because the MOSFET pass transistor is connected as a source follower, the power path gain is much more predictable than designs that employ a discrete PNP transistor as the pass device. This is due to the significant production variations encountered with PNP Beta. MOSFETs are also very high speed devices which enhance the ability to produce a stable wide bandwidth control loop. An additional advantage of the follower topology is inherently good line rejection. Input supply disturbances
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LT3150
APPLICATIO S I FOR ATIO
do not propagate through to the output. The feedback loop for a regulator circuit is completed by providing an error signal to the FB2 pin. A resistor divider network senses the output voltage and sets the regulated DC bias point. In general, the LT3150 regulator feedback loop permits a loop crossover frequency on the order of 1MHz while maintaining good phase and gain margins. This unity-gain frequency is a factor of 20 to 30 times the bandwidth of currently implemented regulator solutions for microprocessor power supplies. This significant performance benefit is what permits the elimination of all bulk output capacitance. Several other unique features are included in the design that increase its functionality and robustness. These functions comprise the remainder of the Block Diagram. A high side sense, current limit amplifier provides active current limiting for the regulator. The current limit amplifier uses an external low value shunt resistor connected in series with the external MOSFET's drain. This resistor can be a discrete shunt resistor or can be manufactured from a Kelvin-sensed section of "free" PC board trace. All load current flows through the MOSFET drain and thus, through the sense resistor. The advantage of using high side current sensing in this topology is that the MOSFET's gain and the main feedback loop's gain remain unaffected. The sense resistor develops a voltage equal to IOUT(RSENSE). The current limit amplifier's 50mV threshold voltage is a good compromise between power dissipation in the sense resistor, dropout voltage impact and noise immunity. Current limit activates when the sense resistor voltage equals the 50mV threshold. Two events occur when current limit activates: the first is that the current limit amplifier drives Q5 in the Block Diagram and clamps the positive swing of the COMP node in the main error amplifier to a voltage that provides an output load current of 50mV/RSENSE. This action continues as long as the output current overload persists. The second event is that a timer circuit activates at the SHDN2 pin. This pin is normally held low by a 5A active pull-down that limits to 100mV above ground. When current limit activates, the 5A pull-down turns off and a 15A pull-up current source turns on. Placing a capacitor in series with
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the SHDN2 pin to ground generates a programmable time ramp voltage. The SHDN2 pin is also the positive input of COMP1. The negative input is tied to the internal 1.21V reference. When the SHDN2 pin ramps above VREF, the comparator drives Q7 and Q8. This action pulls the COMP and GATE pins low and latches the external MOSFET drive off. This condition reduces the MOSFET power dissipation to zero. The time period until the latched-off condition occurs is typically equal to CSHDN2(1.11V)/15A. For example, a 1F capacitor on the SHDN2 pin yields a 74ms ramp time. In short, this unique circuit block performs a current limit time-out function that latches off the regulator drive after a predefined time period. The time-out period selected is a function of system requirements including start-up and safe operating area. The SHDN2 pin is internally clamped to typically 1.85V by Q9 and R10. The comparator tied to the SHDN2 pin has 100mV of typical hysteresis to provide noise immunity. The hysteresis is especially useful when using the SHDN2 pin for thermal shutdown. Restoring normal operation after the load current fault is cleared is accomplished in two ways. One option is to recycle the VIN2 LT3150 supply voltage as long as an external bleed path for the SHDN2 pin capacitor is provided. The second option is to provide an active reset circuit that pulls the SHDN2 pin below VREF. Pulling the SHDN2 pin below VREF turns off the 15A pull-up current source and reactivates the 5A pull-down. If the SHDN2 pin is held below VREF during a fault condition, the regulator continues to operate in current limit into a short. This action requires being able to sink 15A from the SHDN2 pin at less than 1V. The 5A pull-down current source and the 15A pull-up current source are designed low enough in value so that an external resistor divider network can drive the SHDN2 pin to provide overvoltage protection or to provide thermal shutdown with the use of a thermistor in the divider network. Diode-ORing these functions together is simple to accomplish and provides multiple functionality for one pin. If the current limit amplifier is not used, two choices present themselves. The simplest choice is to tie the INEG pin directly to the IPOS pin. This action defeats current limit
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LT3150
APPLICATIO S I FOR ATIO
and provides the simplest, no frills circuit. Applications in which the current limit amplifier is not used are where extremely low dropout voltages must be achieved and the 50mV threshold voltage cannot be tolerated. However, a second available choice permits a user to provide short-circuit protection with no external sensing. This technique is activated by grounding the INEG pin. This action disables the current limit amplifier because Schottky diode D1 clamps the amplifier's output and prevents Q5 from pulling down the COMP node. In addition, Schottky diode D2 turns off pull-down transistor Q4. Q4 is normally on and holds internal comparator COMP3's output low. This comparator circuit, now enabled, monitors the GATE pin and detects saturation at the positive rail. When a saturated condition is detected, COMP3 activates the shutdown timer. Once the time-out period occurs, the output is shut down and latched off. The operation of resetting the latch remains the same. Note that this technique does not limit the FET current during the time-out period. The output current is only limited by the input power supply and the input/output impedance. Setting the timer to a short period in this mode of operation keeps the external MOSFET within its SOA (safe operating area) boundary and keeps the MOSFET's temperature rise under control.
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Unique circuit design incorporated into the LT3150 alleviates all concerns about power supply sequencing. The issue of power supply sequencing is an important topic as the typical LT3150 application has two separate power supply inputs, VIN1 and VIN2. If the VIN2 supply voltage is slow in ramping up or is held off by SHDN1, insufficient MOSFET gate drive exists and therefore, the output voltage does not come up. If VIN2 is present, but the VIN1 supply voltage tied to the IPOS pin is slow in ramping, then the feedback loop wants to drive the GATE pin to the positive VIN2 rail. This results in a large current as the VIN1 supply ramps up. However, undervoltage lockout circuit COMP2, which monitors the IPOS supply voltage, holds Q6 on and pulls the COMP pin low until the IPOS voltage increases to greater than the internal 1.21 reference voltage. The undervoltage lockout circuit then smoothly releases the COMP pin and allows the output voltage to come up in dropout from the input supply voltage. An additional benefit derived from the speed of the LT3150 feedback loop is that turn-on overshoot is virtually nonexistent in a properly compensated system.
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LT3150
TYPICAL APPLICATIO S
Setting the Linear Regulator Output Voltage
VOUT R2 FB2 R1
SHDN2 IPOS CT INEG GATE Q1 C1 10F
VOUT = 1.21V(1 + R2/R1)
3150 TA03
Setting Current Limit
IPOS VIN1 RSENSE* INEG GATE Q2
VOUT *ILIM = 50mV/RSENSE RSENSE = DISCRETE SHUNT RESISTOR OR RSENSE = KELVIN-SENSED PC BOARD TRACE ACTIVATING CURRENT LIMIT ALSO ACTIVATES THE SHDN2 PIN TIMER 3150 TA05
Shutdown Time-Out with Reset
SHDN2 RESET 0V TO 5V R1 100k Q1 VN2222L C1*
*C1 = 15A(t)/1.11V t = SHUTDOWN LATCHOFF TIME
Shutdown Time-Out with Reset
R2 100k R3 100k SHDN2 Q2 2N3904 C2*
RESET 0V TO 5V
*C2 = 15A(t)/1.11V t = SHUTDOWN LATCH-OFF TIME
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Using No RSENSE Current Limit
D1 MBR0520L VIN1
VOUT
3150 TA04
Current Limit with Foldback Limiting Example
IPOS R5 INEG D1 1N4148 D2 1N4148 R6
3150 TA06
VIN1 R4
IOUT Q3 VOUT
GATE
SET R5 << R6
R6 R5 - (VIN1 - VOUT - 2VF) IOUT = 50mV R4 R5 + R6 R5 + R6 R4
(
)
(
)
Basic Thermal Shutdown
VIN1 RT1 10k NTC SHDN2
RT1 = DALE NTHS-1206N02 THERMALLY MOUNT RT1 IN CLOSE PROXIMITY TO THE EXTERNAL N-CHANNEL MOSFET *CHOOSE R4 BASED ON VIN1 AND REQUIRED THERMAL SHUTDOWN TEMPERATURE
3150 TA08
3150 TA07
R4*
Overvoltage Protection
VOUT R6 SHDN2 R5
3150 TA09
3150 TA10
VOUT(uth) = 1.21(R6/R5) + 5A(R6) VOUT(lth) = 1.11(R6/R5) - 15A(R6)
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LT3150
TYPICAL APPLICATIO S
1.5V to 1.2V, 4A Very Low Dropout Linear Regulator
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L1 10H
D1 MBR0520L R2 5.9k 1% LT3150 R1 1.37k 1%
+
C1 4.7F
SW FB1 SWGND GND1 VIN1 SHDN1 SHDN2 IPOS INEG VIN2 GND2 GATE NC NC FB2 COMP
RG 5.1
VIN 1.5V Q1 Si4410
C3 50pF
R4 1.5k C2 6800pF
VOUT 1.2V 4A
+
CIN 220F 2.5V x2
COUT 2.2F x10 X5R CERAMIC 0805 CASE
3150 TA11
CIN: PANASONIC SP SERIES EEFUE0E221R 20% C1: AVX TAJA475M020R 20V 20% L1: MURATA LQH32CN100K11 OR SUMIDA CDRH3D16100
2.5V to 1.8V, 1.7A Low Dropout Linear Regulator
L1 10H
D1 MBR0520L R2 6.65k 1% LT3150 R1 1.37k 1%
+
C1 4.7F
SW FB1 SWGND GND1 VIN1 SHDN1 SHDN2 IPOS INEG VIN2 GND2 GATE NC NC FB2 COMP
RG 5.1
VIN 2.5V Q1 Si4410
R5 499 1% R6 1020 1%
C3 50pF
R4 1.5k C2 6800pF
VOUT 1.8V 1.7A
+
CIN 220F 4V x2
COUT 2.2F x 6 X5R CERAMIC 0805 CASE
3150 TA11a
CIN: PANASONIC SP SERIES EEFUE0G221R 20% C1: AVX TAJA475M020R 20V 20% L1: MURATA LQH32CN100K11 OR SUMIDA CDRH3D16100
3150I
LT3150
PACKAGE DESCRIPTIO
0.007 - 0.0098 (0.178 - 0.249) 0.016 - 0.050 (0.406 - 1.270)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
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GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
0.189 - 0.196* (4.801 - 4.978) 16 15 14 13 12 11 10 9 0.009 (0.229) REF 0.229 - 0.244 (5.817 - 6.198) 0.150 - 0.157** (3.810 - 3.988) 1 0.015 0.004 x 45 (0.38 0.10) 0 - 8 TYP 0.053 - 0.068 (1.351 - 1.727) 23 4 56 7 8 0.004 - 0.0098 (0.102 - 0.249) 0.008 - 0.012 (0.203 - 0.305) 0.0250 (0.635) BSC
GN16 (SSOP) 1098
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LT3150
TYPICAL APPLICATIO
1.8V to 1.5V, 4A Very Low Dropout Linear Regulator with No RSENSE Current Limiting and Shutdown
SHDN2 C4 0.01F
RELATED PARTS
PART NUMBER LT1573 LT1575/LT1577 LT1761 DESCRIPTION UltraFast Transient Response Low Dropout Regulator PNP Driver, Up to 5A UltraFast Transient Response Low Dropout Regulator MOSFET Driver, Up to 10A 100mA, Low Noise Micropower, LDO COMMENTS VIN = 2.8V to 10V, VOUT = 1.265V, IOUT = 0.35V, IQ = 1.7mA, ISD = 200A Requires External PNP Transistor, S8 Package VIN = 1.5V to 22V, VOUT = 1.21V, IOUT = 0.15V, IQ = 12mA, ISD = 5A LT1577 is Dual Version, N8, S8 Packages VIN = 1.8V to 20V, VOUT = 1.22V, IOUT = 0.30V, IQ = 20A, ISD = <1A Low Noise <20VRMS P-P, Stable with 1F Ceramic Capacitors, ThinSOT Package VIN = 1.8V to 20V, VOUT = 1.22V, IOUT = 0.30V, IQ = 25A, ISD = <1A Low Noise <20VRMS P-P, MS8 Package VIN = 1.8V to 20V, VOUT = 1.22V, IOUT = 0.30V, IQ = 30A, ISD = <1A Low Noise <20VRMS P-P, S8 Package VIN = 2.7V to 20V, VOUT = 1.21V, IOUT = 0.34V, IQ = 1mA, ISD = <1A Low Noise <40VRMS P-P, "A" Version Stable with Ceramic Capacitors, DD, TO220-5 Packages VIN = 1.8V to 20V, VOUT = 1.22V, IOUT = 0.27V, IQ = 30A, ISD = <1A Low Noise <20VRMS P-P, MS8 Package VIN = 2.1V to 20V, VOUT = 1.21V, IOUT = 0.34V, IQ = 1mA, ISD = <1A Low Noise <40VRMS P-P, "A" Version Stable with Ceramic Capacitors DD, T0220-5, SOT-223, S8 Packages 95% Efficiency, VIN = 2.5V to 5.5V, IOUT = 1.25A, IQ = 0.8V, ISD = <1A, MS Package 95% Efficiency, VIN = 2.5V to 5.5V, IOUT = 2.5A, IQ = 0.8V, ISD = <1A, TSSOP16E Package
3150I LT/TP 0802 1.5K * PRINTED IN THE USA
LT1762 LT1763
150mA, Low Noise Micropower, LDO 500mA, Low Noise Micropower, LDO
LT1764/LT1764A 3A, Low Noise, Fast Transient Response, LDO
LT1962
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LTC3411 LTC3412
1.25A(IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 2.5A(IOUT), 4MHz, Synchronous Step-Down DC/DC Converter
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
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L1 10H D1 MBR0520L R2 6.19k 1% LT3150 SW SWGND VIN1 SHDN2 VIN2 GND2 NC FB2 FB1 GND1 SHDN1 IPOS INEG GATE NC COMP R1 1.37k 1%
+
C1 4.7F SHDN1 R3 10k VIN 1.8V
C5 10F
D2 BAT54 RG 5.1
Q1 Si4410
R5 243 1% R6 1020 1%
C3 50pF
R4 1.5k C2 6800pF
VOUT 1.5V 4A
+
CIN 220F 2.5V x2
COUT 2.2F x10 X5R CERAMIC 0805 CASE
3150 TA12
CIN: PANASONIC SP SERIES EEFUE0E221R 20% C1: AVX TAJA475M020R 20V 20% L1: MURATA LQH32CN100K11 OR SUMIDA CDRH3D16100
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2002

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