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| PRELIMINARY TECHNICAL DATA = Preliminary Technical Data Three Phase Multi-Function Energy Metering IC with Serial Port ADE7754* The ADE7754 provides different solutions to measure Active and Apparent Energy from the six analog inputs thus enabling the use of the ADE7754 in various Power meter services as 3-phase 4-wire, 3-phase 3-wire but also 4-wire delta. In addition to RMS calculation, Real and Apparent power informations, the ADE7754 provides system calibration features for each phase, i.e., channel offset correction, phase calibration and power calibration. The CF logic output gives instantaneous real power information. The ADE7754 has a waveform sample register which enables access to ADC outputs. The part also incorporates a detection circuit for short duration low or high voltage variations. The voltage threshold levels and the duration (no. of half line cycles) of the variation are user programmable. A zero crossing detection is synchronized which the zero crossing point of the line voltage of each of the three phases. This information is used to measure each line's Period. It is also used internally to the chip in the Line Active Energy and Line Apparent Energy accumulation modes. This permits faster and more accurate calibration of the power calculations. This signal is also useful for synchronization of relay switching. Data is read from the ADE7754 via the SPI serial interface. The interrupt request output (143) is an open drain, active low logic output. The IRQ output will go active low when one or more interrupt events have occurred in the ADE7754. A status register will indicate the nature of the interrupt. The ADE7754 is available in a 24-lead SOIC package. RESET 17 FEATURES High Accuracy, supports IEC 687/1036 Compatible with 3-phase/3-wire, 3-phase/4-wire and any type of 3-phase services Less than 0.1% error over a dynamic range of 500 to 1 The ADE7754 supplies Active Energy, Apparent Energy, Voltage rms, Current rms and Sampled Waveform Data. Digital Power, Phase & Input Offset Calibration. An On-Chip temperature sensor (3C typ. after calibration) On-Chip user Programmable thresholds for line voltage SAG and overdrive detections. A SPI compatible Serial Interface with Interrupt Request line (IRQ). A pulse output with programmable frequency Proprietary ADCs and DSP provide high accuracy over large variations in environmental conditions and time. Reference 2.5V8% (Drift 30 ppm/C typical) with external overdrive capability Single 5V Supply, Low power (15mW typical) GENERAL DESCRIPTION The ADE7754 is a high accuracy three-phase electrical energy measurement IC with a serial interface and a pulse output. The ADE7754 incorporates second order sigmadelta ADCs, reference circuitry, temperature sensor, and all the signal processing required to perform Active Energy measurement, Apparent Energy measurement and rms calculation. FUNCTIONAL BLOCK DIAGRAM AVDD 4 AVGAIN AVRMSOS AIRMSOS AVAG Power Supply Monitor ADE7754 PGA1 AAPGAIN HPF IAP 5 IAN 6 VAP 16 PGA2 ADC LPF2 AAPOS ADC APHCAL BVGAIN BVRMSOS AWG BIRMSOS BVAG PGA1 BAPGAIN HPF LPF2 CVRMSOS BAPOS CFNUM IBP 7 IBN 8 VBP 15 PGA2 ADC BWG DFC CFDEN 1 CF ADC BPHCAL CVGAIN CIRMSOS 3 2 CVAG 19 PGA1 ICP ICN 10 PGA2 VCP 14 VN 13 2.5V REF 11 CAPGAIN HPF LPF2 20 DVDD DGND CLKIN CLKOUT ADC CAPOS WDIV VADIV ADC CPHCAL CWG TEMP SENSOR 4k 12 ADC ADE7754 REGISTERS & SERIAL INTERFACE * Patents pending. REV. PrD 08/01 22 24 23 21 18 AGND REF IN/OUT DIN DOUT SCLK CS IRQ Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000 PRELIMINARY TECHNICAL DATA ADE7754-SPECIFICATIONS Parameters ACCURACY Measurement Error (per phase) Phase Error Between Channels (PF=0.8 capacitive) (PF=0.5 inductive) AC Power Supply Rejection1 Output Frequency Variation DC Power Supply Rejection1 Output Frequency Variation ANALOG INPUTS Maximum Signal Levels Input Impedance (DC) Bandwidth (-3dB) ADC Offset Error1 Gain Error 1 Gain Error Match1 REFERENCE INPUT REFIN/OUT Input Voltage Range Input Impedance Input Capacitance TEMPERATURE SENSOR ON-CHIP REFERENCE Reference Error Temperature Coefficient CLKIN Input Clock Frequency LOGIC INPUTS 4-5-6, DIN, SCLK CLKIN and +5 Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS CF, 143, DOUT and CLKOUT Output High Voltage, VOH Output Low Voltage, VOL POWER SUPPLY AVDD DVDD AIDD DIDD 0.1 0.05 0.05 0.01 0.01 500 400 3.5 10 4 3 2.7 2.3 4 10 2 200 30 typ 15 5 Units % typ max max % typ % typ mV max k min kHz typ mV max % typ % typ V max V min kW min pF max C mV max ppm/C MHz max MHz min (AVDD = DVDD = 5V5%, AGND = DGND = 0V, On-Chip Reference, CLKIN=10MHz, TMIN to TMAX = -40C to +85C) Test Conditions/Comments Over a dynamic range of 500 to 1 Line Frequency = 45Hz to 65Hz Phase Lead 37 Phase Lag 60 V1P = V2P = V3P = 100mV rms V1P = V2P = V3P = 100mV rms Differential input Uncalibrated error, see Terminology for detail External 2.5V reference External 2.5V reference 2.5V +8% 2.5V -8% Calibrated DC offset 2.4 0.8 3 10 V min V max mA max pF max DVDD=5V 5% DVDD=5V 5% Typical 10nA, Vin=0V to DVDD 4 1 V min V max DVDD=5V 5% DVDD=5V 5% For specified performance 4.75 5.25 4.75 5.25 TBD TBD V min V max V min V max mA max mA max 5V 5V 5V 5V - 5% +5% - 5% +5% NOTES: 1. See Terminology section for explanation of specifications. 2. See plots in Typical Performance Graph. 3. Specification subject to change without notice. MODEL ORDERING GUIDE PACKAGE OPTION SO-24 ADE7754 Evaluation Board ADE7754AR EVAL-ADE7754EB REV. PrD 08/01 -2- PRELIMINARY TECHNICAL DATA ADE7754 ADE7754 TIMING CHARACTERISTICS1,2 Parameter Write timing t1 t2 t3 t4 t5 t6 t7 t8 Read timing t9 t10 t113 t124 t134 50 50 50 10 5 900 50 100 1 50 30 100 10 100 10 Units ns ns ns ns ns ns ns ns (min) (min) (min) (min) (min) (min) (min) (min) (AVDD = DVDD = 5V 5%, AGND = DGND = 0V, On-Chip Reference, CLKIN = 10MHz XTAL, TMIN to TMAX = -40C to +85C) Test Conditions/Comments CS falling edge to first SCLK falling edge SCLK logic high pulse width SCLK logic low pulse width Valid Data Set up time before falling edge of SCLK Data Hold time after SCLK falling edge Minimum time between the end of data byte transfers. Minimum time between byte transfers during a serial write. CS Hold time after SCLK falling edge. Minimum time between read command (i.e. a write to Communication Register) and data read. Minimum time between data byte transfers during a multibyte read. Data access time after SCLK rising edge following a write to the Communications Register Bus relinquish time after falling edge of SCLK. Bus relinquish time after rising edge of +5. s (min) ns (min) ns (min) ns ns ns ns (max) (min) (max) (min) NOTES Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5ns (10% to 90%) and timed from a voltage level of 1.6V. 2 See timing diagram below and Serial Interface section of this data sheet. 3 Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8V or 2.4V. 4 Derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit in Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 1 IOL 200 A TO OUTPUT PIN +2.1V CL 50pF 1.6 mA IOH Figure 1 - Load Circuit for Timing Specifications Serial Write Timing t8 CS t1 t2 t3 t7 t4 t5 DB7 DB0 DB7 DB0 t7 t6 SCLK DIN 1 0 A5 A4 A3 A2 A1 A0 Command Byte Most Significant Byte Least Significant Byte Serial Read Timing CS t1 t9 t10 t14 SCLK DIN DOUT Command Byte 0 0 A5 A4 A3 A2 A1 A0 t11 DB7 t12 DB0 DB7 t13 DB0 Most Significant Byte Least Significant Byte REV. PrD 08/01 -3- PRELIMINARY TECHNICAL DATA ADE7754 ABSOLUTE MAXIMUM RATINGS* (T A = +25C unless otherwise noted) AVDD to AGND . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V DV DD to DGND . . . . . . . . . . . . . . . . . . . . -0.3V to +7V DV DD to AV DD . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Analog Input Voltage to AGND I AP ,I AN ,I BP ,I BN ,I CP ,I CN ,V AP ,V BP ,V CP ,V N . -6V to +6V Reference Input Voltage to AGND -0.3V to AVDD+0.3V Digital Input Voltage to DGND . -0.3V to DV DD+0.3V Digital Output Voltage to DGND -0.3V to DV DD+0.3V Operating Temperature Range Industrial . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C 24-Lead SOIC, Power Dissipation . . . . . . . . . TBD mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 53C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADE7754 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE Terminology MEASUREMENT ERROR The error associated with the energy measurement made by the ADE7754 is defined by the following formula: Percentage Error = Energy registered by ADE 7754 - True Energy x 100% True Energy PHASE ERROR BETWEEN CHANNELS Any error introduced is again expressed as a percentage of reading. ADC OFFSET ERROR The HPF (High Pass Filter) in the current channel has a phase lead response. To offset this phase response and equalize the phase response between channels a phase correction network is also placed in the current channel. The phase correction network ensures a phase match between the current channels and voltage channels to within 0.1 over a range of 45Hz to 65Hz and 0.2 over a range 40Hz to 1kHz. This phase mismatch between the voltage and the current channels can be further reduced with the phase calibration register in each phase. POWER SUPPLY REJECTION This refers to the DC offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection - see characteristic curves. However, when HPFs are switched on the offset is removed from the current channels and the power calculation is not affected by this offset. GAIN ERROR The gain error in the ADE7754 ADCs, is defined as the difference between the measured ADC output code (minus the offset) and the ideal output code - see Current Channel ADC & Voltage Channel ADC. The difference is expressed as a percentage of the ideal code. GAIN ERROR MATCH This quantifies the ADE7754 measurement error as a percentage of reading when the power supplies are varied. For the AC PSR measurement a reading at nominal supplies (5V) is taken. A second reading is obtained with the same input signal levels when an ac (175mVrms/100Hz) signal is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading--see Measurement Error definition above. For the DC PSR measurement a reading at nominal supplies (5V) is taken. A second reading is obtained with the same input signal levels when the power supplies are varied 5%. -4- The Gain Error Match is defined as the gain error (minus the offset) obtained when switching between a gain of 1, 2 or 4. It is expressed as a percentage of the output ADC code obtained under a gain of 1. REV. PrD 08/01 PRELIMINARY TECHNICAL DATA ADE7754 PIN FUNCTION DESCRIPTION Pin No. 1 MNEMONIC CF DESCRIPTION Calibration Frequency logic output. The CF logic output gives Active Power information. This output is intended to be used for operational and calibration purposes. The full-scale output frequency can be scaled by writing to the CFNUM and CFDEN registers. This provides the ground reference for the digital circuitry in the ADE7754, i.e. multiplier, filters and digital-to-frequency converter. Because the digital return currents in the ADE7754 are small, it is acceptable to connect this pin to the analog ground plane of the whole system. However high bus capacitance on the DOUT pin may result in noisy digital current which could affect performance. Digital power supply. This pin provides the supply voltage for the digital circuitry in the ADE7754. The supply voltage should be maintained at 5V 5% for specified operation. This pin should be decoupled to DGND with a 10F capacitor in parallel with a ceramic 100nF capacitor. Analog power supply. This pin provides the supply voltage for the analog circuitry in the ADE7754. The supply should be maintained at 5V 5% for specified operation. Every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling. The typical performance graphs in this data sheet show the power supply rejection performance. This pin should be decoupled to AGND with a 10F capacitor in parallel with a ceramic 100nF capacitor. Analog inputs for current channel. This channel is intended for use with the current transducer and is referenced in this document as the current channel. These inputs are fully differential voltage inputs with maximum differential input signal levels of 0.5V, 0.25V and 0.125V, depending on the gain selections of the internal PGA -See Analog Inputs. All inputs have internal ESD protection circuitry, and in addition an overvoltage of 6V can be sustained on these inputs without risk of permanent damage. This pin provides the ground reference for the analog circuitry in the ADE7754, i.e. ADCs, temperature sensor, and reference. This pin should be tied to the analog ground plane or the quietest ground reference in the system. This quiet ground reference should be used for all analog circuitry, e.g. anti aliasing filters, current and voltage transducers etc. In order to keep ground noise around the ADE7754 to a minimum, the quiet ground plane should only connected to the digital ground plane at one point. It is acceptable to place the entire device on the analog ground plane. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.5V 8% and a typical temperature coefficient of 30ppm/C. An external reference source may also be connected at this pin. In either case this pin should be decoupled to AGND with a 1F ceramic capacitor. Analog inputs for the voltage channel. This channel is intended for use with the voltage transducer and is referenced as the voltage channel in this document. These inputs are single-ended voltage inputs with maximum signal level of 0.5V with respect to VN for specified operation. These inputs are voltage inputs with maximum differential input signal levels of 0.5V, 0.25V and 0.125V, depending on the gain selections of the internal PGA - see Analog Inputs. All inputs have internal ESD protection circuitry, and in addition an over voltage of 6V can be sustained on these inputs without risk of permanent damage. 2 DGND 3 D V DD 4 AVDD 5,6; 7,8; 9,10 IAP, IAN; IBP, IBN; ICP, ICN 11 AGND 12 REFIN/OUT 13, 14 15, 16 VN, VCP, VBP, VAP 17 18 RESET IRQ Reset pin for the ADE7754. A logic low on this pin will hold the ADCs and digital circuitry (including the Serial Interface) in a reset condition. Interrupt Request Output. This is an active low open drain logic output. Maskable interrupts include: Active Energy Register at half level, Apparent Energy Register at half level, and waveform sampling up to 26kSPS. See ADE7754 Interrupts. REV. PrD 08/01 -5- PRELIMINARY TECHNICAL DATA ADE7754 Pin No. 19 MNEMONIC CLKIN DESCRIPTION Master clock for ADCs and digital signal processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7754. The clock frequency for specified operation is 10MHz. Ceramic load capacitors of between 22pF and 33pF should be used with the gate oscillator circuit. Refer to crystal manufacturers data sheet for load capacitance requirements A crystal can be connected across this pin and CLKIN as described above to provide a clock source for the ADE7754. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used. Chip Select. Part of the four wire Serial Interface. This active low logic input allows the ADE7754 to share the serial bus with several other devices. See ADE7754 Serial Interface. Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK--see ADE7754 Serial Interface. Serial Clock Input for the synchronous serial interface. All Serial data transfers are synchronized to this clock--see ADE7754 Serial Interface. The SCLK has a Schmidt-trigger Input for use with a clock source which has a slow edge transition time, e.g., opto-isolator outputs etc. Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK. This logic output is normally in a high impedance state unless it is driving data onto the serial data bus--see ADE7754 Serial Interface. 20 CLKOUT 21 CS . 22 23 DIN SCLK 24 DOUT PIN CONFIGURATION SOIC Package CF 1 DGND 2 DVDD 3 24 DOUT 23 SCLK 22 DIN 21 CS AVDD 4 IAP 5 ADE7754 20 CLKOUT IAN 6 19 CLKIN TOP VIEW IBP 7 (Not to Scale) 18 IRQ 17 RESET 16 VAP 15 VBP 14 VCP 13 VN IBN 8 ICP 9 ICN 10 AGND 11 REFIn/Out 12 -6- REV. PrD 08/01 PRELIMINARY TECHNICAL DATA ADE7754 ACCESSING THE ADE7754 ON-CHIP REGISTERS All ADE7754 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the communications register and then transferring the register data. For a full description of the serial interface protocol, see Serial Interface section of this data sheet. Communications Register The Communications register is an eight bit, write-only register which controls the serial data transfer between the ADE7754 and the host processor. All data transfer operations must begin with a write to the communications register. The data written to the communications register determines whether the next operation is a read or a write and which register is being accessed. Table I below outlines the bit designations for the Communications register. Table VII : Communications Register Bit Location 0 to 5 6 7 Bit Mnemonic A0 to A5 RESERVED W/ R Description The five LSBs of the Communications register specify the register for the data transfer operation. Table II lists the address of each ADE7754 on-chip register. This bit is unused and should be set to zero. When this bit is a logic one the data transfer operation immediately following the write to the Communications register will be interpreted as a write to the ADE7754. When this bit is a logic zero the data transfer operation immediately following the write to the Communications register will be interpreted as a read operation. DB7 W/R DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 A5 A4 A3 A2 A1 A0 REV. PrD 08/01 -7- PRELIMINARY TECHNICAL DATA ADE7754 Table VIII. ADE7754 REGISTER LIST Address [A5:A0] Name 00h 01h Reserved AENERGY R/W* R Length 24 Default Value 0 Description Reserved. Active Energy register. Active power is accumulated over time in this read-only register. The AENERGY register can hold a minimum of 5 seconds of active energy information with full-scale analog inputs before it overflows - See Energy Calculation. Bit 7 to 3 of the WATMODE register determine how the Active energy is processed from the 6 Analog inputs. Same as the AENERGY register, except that the register is reset to zero following a read operation. Line Accumulation Active Energy register. The instantaneous active power is accumulated in this read-only register over the LINCYC number of half line cycles. Bit 2 to 0 of the WATMODE register determines, how the Line Accumulation Active energy is processed from the 6 Analog inputs. VA Energy register. Real power is accumulated over time in this read-only register. Bit 7 to 3 of the VAMODE register determines, how the Apparent energy is processed from the 6 Analog inputs. Same as the VAENERGY register except that the register is reset to zero following a read operation. Real Energy register. The instantaneous real power is accumulated in this read-only register over the LINCYC number of half line cycles. Bit 2 to 0 of the VAMODE register determines how the Apparent energy is processed from the 6 Analog inputs. Period of the line input estimated by Zero-crossing processing. Data bits 0 to 1 of the MMODE register determines the voltage channel used for Period calculation. Temperature register. This register contains the result of the latest temperature conversion. Please refer to Temperature Measurement section on this datasheet for details on how to interpret the content of this register. Waveform register. This register contains the digitized waveform of one of the six analog inputs. The source is selected by data bits 0 to 2 in the WAVMode register. Operational Mode Register. This register defines the general configuration of the ADE7754. See OPMode Register. Measurement Mode register. This register defines the channel used for Period and Peak detection measurements. See MMode Register. Waveform Mode register. This register defines the channel and the sampling frequency used in Waveform sampling mode. See WAVMode Register. This register configures the formula applied for the Active Energy and Line active energy measurements. See WATMode Register. This register configures the formula applied for the Apparent Energy and Line Apparent Energy measurements. See VAMode Register. IRQ Mask register. It determines if an interrupt event will generate an active-low output at 143 pin - see ADE7754 Interrupts. IRQ Status register. This register contains information regarding the source of ADE7754 interrupts - see ADE7754 Interrupts. Same as the STATUS register. Except that its contents are reset to zero (all flags cleared) after a read operation. 02h 03h RAENERGY LAENERGY R R 24 24 0 0 04h VAENERGY R 24 0 05h 06h RVAENERGY R LVAENERGY R 24 24 0 0 07h PERIOD R 15 0 08h TEMP R 8 0 09h WFORM R 24 0 0Ah 0Bh OPMODE MMODE R/W R/W 8 8 4 70h 0Ch WAVMODE R/W 8 0 0Dh 0Eh WATMODE VAMODE R/W R/W 8 8 3Fh 3Fh 0Fh 10h 11h MASK STATUS RSTATUS R/W R R 16 16 16 0 0 0 -8- REV. PrD 08/01 PRELIMINARY TECHNICAL DATA ADE7754 Address [A5:A0] Name 12h ZXTOUT R/W* R/W Length 16 Default Value FFFFh Description Zero Cross Time Out register. If no zero crossing is detected within a time period specified by this register the interrupt request line (IRQ) will go active low for the corresponding line voltage. The maximum time -out period is 2.3 seconds - see Zero Crossing Detection. Line Cycle register. The content of this register sets the number of half line cycles while the active energy and the apparent energy are accumulated in the LAENERGY and LVAENERGY registers - See Energy Calibration. Sag Line Cycle register. This register specifies the number of consecutive half-line cycles where voltage channel input falls below a threshold level. This register is common to the three line voltage SAG detection. The detection threshold is specified by SAGLVL register - See Voltage SAG Detection. SAG Voltage Level. This register specifies the detection threshold for SAG event. This register is common to the three line voltage SAG detection. See the description of SAGCYC register for details. Voltage Peak Level. This register sets the level of the voltage peak detection. If the selected voltage phase exceeds this level, the PKV flag in the status register is set. Current Peak Level. This register sets the level of the current peak detection. If the selected current phase exceeds this level, the PKI flag in the status register is set. PGA Gain register. This register is used to adjust the gain selection for the PGA in current and voltage channels - See Analog Inputs. Phase A Active Power Gain register. This register calculation can be calibrated by writing to this register. The calibration range is 50% of the nominal full scale active power. The resolution of the gain adjust is 0.0244% / LSB. Phase B Active Power Gain Phase C Active Power Gain VA Gain register. This register calculation can be calibrated by writing this register. The calibration range is 50% of the nominal full scale real power. The resolution of the gain adjust is 0.02444% / LSB. Phase B VA Gain Phase C VA Gain Phase A Phase Calibration Register Phase B Phase Calibration Register Phase C Phase Calibration Register Phase A Power Offset Calibration Register Phase B Power Offset Calibration Register Phase C Power Offset Calibration Register CF Scaling Numerator register. The content of this register is used in the numerator of CF output scaling. CF Scaling Denominator register. The content of this register is used in the denominator of CF output scaling. Active Energy register divider Apparent Energy register divider Phase A Current channel RMS register. The register contains the RMS component of one input of the current channel. The source is selected by data bits in the mode register. Phase B Current channel RMS register. Phase C Current channel RMS register. Phase A Voltage channel RMS register. Phase B Voltage channel RMS register. Phase C Voltage channel RMS register. -9- 13h LINCYC R/W 16 FFFFh 14h SAGCYC R/W 8 FFh 15h SAGLVL R/W 8 0 16h VPEAK R/W 8 FFh 17h IPEAK R/W 8 FFh 18h GAIN R/W 8 0 19h AWG R/W 12 0 1Ah 1Bh 1Ch BWG CWG AVAG R/W R/W R/W 12 12 12 0 0 0 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h BVAG CVAG APHCAL BPHCAL CPHCAL AAPOS BAPOS CAPOS CFNUM CFDEN WDIV VADIV AIRMS R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R 12 12 6 6 6 12 12 12 12 12 8 8 24 0 0 0 0 0 0 0 0 3Fh 3Fh 0 0 0 2Ah 2Bh 2Ch 2Dh 2Eh BIRMS CIRMS AVRMS BVRMS CVRMS R R R R R 24 24 24 24 24 0 0 0 0 0 REV. PrD 08/01 PRELIMINARY TECHNICAL DATA ADE7754 Address [A5:A0] Name 2Fh 30h 31h 32h 33h 34h 35h AIRMSOS BIRMSOS CIRMSOS AVRMSOS BVRMSOS CVRMSOS AAPGAIN R/W* R/W R/W R/W R/W R/W R/W R/W Length 12 12 12 12 12 12 12 Default Value 0 0 0 0 0 0 0 Description Phase A Current RMS offset correction register. Phase B Current RMS offset correction register. Phase C Current RMS offset correction register. Phase A Voltage RMS offset correction register. Phase B Voltage RMS offset correction register. Phase C Voltage RMS offset correction register. Phase A Active Power Gain Adjust. The Active Power accumulation of the phase A can be calibrated by writing to this register. The calibration range is 50% of the nominal full scale of the Active Power. The resolution of the gain is 0.0244% / LSB - see Current channel Gain Adjust Phase B Active Power Gain Adjust Phase C Active Power Gain Adjust Phase A voltage RMS gain. The Apparent Power accumulation of the phase A can be calibrated by writing to this register. The calibration range is 50% of the nominal full scale of the Apparent Power. The resolution of the gain is 0.0244% / LSB - see Voltage RMS Gain Adjust Phase B voltage RMS gain Phase C voltage RMS gain Reserved CHKSUM R 8 Check sum register. The content of this register represents a XOR of each bytes of the latest register read from the SPI port. Version of the Die 36h 37h 38h BAPGAIN CAPGAIN AVGAIN R/W R/W R/W 12 12 12 0 0 0 39h 3Ah 3Bh 3Dh 3Eh BVGAIN CVGAIN R/W R/W 12 12 0 0 3Fh VERSION R 8 *R/W: Read/Write capability of the register. R: Read only register. R/W: Register that can be both read and written. -10- REV. PrD 08/01 PRELIMINARY TECHNICAL DATA ADE7754 Operational Mode Register (0Ah) The general configuration of the ADE7754 is defined by writing to the OPMODE register. Table III below summarizes the functionality of each bit in the OPMODE register . Table IX OPMode Register Bit Location 0 1 2 3-5 Bit Mnemonic DISHPF DISLPF DISCF DISMOD Default Value 0 0 1 0 Description The HPF (High Pass Filter) in all current channel inputs are disabled when this bit is set. The LPFs (Low Pass Filter) in all current channel inputs are disabled when this bit is set. The Frequency output CF is disabled when this bit is set. By setting these bits, ADE7754's A/D converters can be turned off. In normal operation, these bits should be left at logic zero. DISMOD2 DISMOD1 DISMOD0 0 1 0 0 0 0 Normal operation Normal operation, by setting this bit to logic 1 the analog inputs to current channel are connected to the ADC for voltage channel and the analog inputs to voltage channel are connected to the ADC for current channel Current channel A/D converters OFF Current channel A/D converters OFF + chan nels swapped Voltage Channel A/D converters OFF Voltage Channel A/D converters OFF + chan nels swapped ADE7754 in Sleep Mode ADE7754 powered down 0 0 0 1 0 1 6 7 SWRST 0 0 0 1 1 1 1 1 1 0 0 1 1 Software chip reset. A data transfer to the ADE7754 should not take place for at least 18s after a software reset. This is intended for factory testing only and should be left at zero. RESERVED - REV. PrD 08/01 -11- PRELIMINARY TECHNICAL DATA ADE7754 Measurement Mode Register (0Bh) The configuration of the period and Peak measurements made by the ADE7754 are defined by writing to the MMODE register. Table IV below summarizes the functionality of each bit in the MMODE register . Table X MMode Register Bit Location 0-1 Bit Mnemonic PERDSEL Default Value 0 Description These bits are used to select the source of the measurement of the voltage line period. PERDSEL1 PERDSEL0 0 0 1 1 0 1 0 1 Source Phase A Phase B Phase C Reserved 2-3 PEAKSEL 0 These bits select the line voltage and current phase used for the PEAK detection. If the selected line voltage is above the level defined in the PKVLVL register, the PKV flag in the Interrupt Status register is set. If the selected current input is above the level defined in the PKILVL register, the PKI flag in the Interrupt Status register is set. PEAKSEL1 0 0 1 1 0 1 0 1 PEAKSEL0 Source Phase A Phase B Phase C Reserved 4-6 ZXSEL 7 These bits select the phases used for counting the number of zero crossing in the Line Active and Apparent accumulation modes. bit 4, 5 and 6 select Phase A, Phase B and Phase C respectively. Reserved 7 Waveform Mode Register (0Ch) The Waveform sampling mode of the ADE7754 is defined by writing to the WAVMODE register. Table V below summarizes the functionality of each bit in the WAVMODE register . Table XI WAVMode Register Bit Location 0-2 Bit Mnemonic WAVSEL Default Value 0 Description These bits are used to select the source of the Waveform sample WAVSEL2 0 0 0 0 1 1 1 WAVSEL1 WAVSEL0 0 0 1 1 0 0 1 DTRT0 0 1 0 1 0 1 0 1 0 1 0 or 1 Update rate 26.0ksps (CLKIN/3/128) 13.0ksps (CLKIN/3/256) 6.5ksps (CLKIN/3/512) 3.3ksps (CLKIN/3/1024) Source Voltage Phase A Voltage Phase B Voltage Phase C Current Phase A Current Phase B Current Phase C Reserved 3-4 DTRT 0 These bits are used to select the Waveform sampling update rate DTRT1 0 0 1 1 5 6-7 LVARSEL 0 This bit is used to enable the accumulation of the sign of the Line VAR energy into the LAENERGY register. Reserved -12- REV. PrD 08/01 PRELIMINARY TECHNICAL DATA ADE7754 Watt Mode Register (0Dh) The phases involved in the Active Energy measurement of the ADE7754 are defined by writing to the WATMODE register. Table VI below summarizes the functionality of each bit in the WATMODE register . Table XII WATMode Register Bit Location 7-6 Bit Mnemonic Default Value Description These bits are used to select the formula used for Active Energy calculation WATMOD1 WAVMOD0 Active Energy calculation 0 0 1 1 0 1 0 1 VAxIA + VBxIB 0 0 + + + VCxIC VCx(IC-IB) VCxIC VAx(IA-IB) + VAx(IA-IB) + Reserved WATMOD 0 5-3 WATSEL 7 These bits are used to select separately each part of the formula, depending on the Active Energy measurement method. Setting bit 5 to logic one selects the first term of the formula (VAxIA or VAx(IA-IB)). Setting bit 4 to logic one selects the second term of the formula (VBxIB or 0 depending on WATMOD configuration). Setting bit 3 to logic one selects the last term of the formula (VCxIC or VC(IC-IB)). Any combination of these bits are possible to address calibration and operational needs. These bits are used to select separately each part of the formula, depending on the Line Active Energy measurement method. The behavior of these bits is the same as WATSEL bits. Bit 2 selects the first term of the formula and so on. 2-0 LWATSEL 7 VA Mode Register (0Eh) The phases involved in the Apparent Energy measurement of the ADE7754 are defined by writing to the VAMODE register. Table VII below summarizes the functionality of each bit in the VAMODE register . Table XIII VAMode Register Bit Location 7-6 Bit Mnemonic VAMOD Default Value 0 Description These bits are used to select the formula used for Active Energy calculation VAMOD1 0 0 1 1 VAMOD0 0 1 0 1 Apparent Energy calculation VArmsxIArms+VBrmsxIBrms+VCrmsxICrms VArmsxIArms+(VArms+VCrms)/2xIBrms+VCrmsxICrms VArmsxIArms+VArmsxIBrms+VCrmsxICrm Reserved 5-3 VASEL 7 These bits are used to select separately each part of the formula, depending on the Apparent Energy measurement method. Setting bit 5 to logic one selects the first term of the formula (VArmsxIArms). Setting bit 4 to logic one selects the second term of the formula (VBrmsxIBrms or (VArms+VCrms)/2xIBrms or VArmsxIBrms depending on VAMOD configuration). Setting bit 3 to logic one selects the first term of the formula (VCrmsxICrms). Any combination of these bits are possible to address calibration and operational needs. These bits are used to select separately each part of the formula, depending on the Line Apparent Energy measurement method. The behavior of these bits is the same as VASEL bits. Bit 2 selects the first term of the formula and so on. 2-0 LVASEL 7 REV. PrD 08/01 -13- PRELIMINARY TECHNICAL DATA ADE7754 Interrupt Mask Register (0Fh) When an interrupt event occurs in the ADE7754, the IRQ logic output goes active low if the mask bit for this event is logic one in this register. The IRQ logic output is reset to its default collector open state when the RSTATUS register is read. The following describes the function of each bit in the Interrupt Mask Register. Bit Location 0 1 2 3 4 5 6 7 8 9 Ah Bh Ch Dh Eh Fh PKV PKI WFSM VAEHF 0 0 0 0 Interrupt Flag AEHF SAGA SAGB SAGC ZXTOA ZXTOB ZXTOC ZXA ZXB ZXC Default Value 0 0 0 0 0 0 0 0 0 0 Description Enables an interrupt when there is a 0 to 1 transition of the MSB of the AENERGY register (i.e. the AENERGY register is half-full) Enables an interrupt when there is a SAG on the line voltage of the Phase A Enables an interrupt when there is a SAG on the line voltage of the Phase B Enables an interrupt when there is a SAG on the line voltage of the Phase C Enables an interrupt when there is a zero crossing time out detection on Phase A Enables an interrupt when there is a zero crossing time out detection on Phase B Enables an interrupt when there is a zero crossing time out detection on Phase C Enables an interrupt when there is a zero crossing in voltage channel of the phase A --Zero Crossing Detection Enables an interrupt when there is a zero crossing in voltage channel of the phase B --Zero Crossing Detection Enables an interrupt when there is a zero crossing in voltage channelof the phase C --Zero Crossing Detection Enables an interrupt when the LAENERGY and LVAENERGY accumulations over LINCYC are finished Reserved Enables an interrupt when the voltage input selected in the MMODE register is above the value in the PKVLVL register Enables an interrupt when the current input selected in the MMODE register is above the value in the PKILVL register. Enables an interrupt when a data is present in the Waveform Register. Enables an interrupt when there is a 0 to 1 transition of the MSB of the VAENERGY register (i.e. the VAENERGY register is half-full) INTERRUPT MASK REGISTER* F E D C B A 9 8 7 6 5 4 3 2 1 0 LENERGY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR: 0Fh VAEHF (Apparent Energy Register Half Full) WFMP (New Waveform Sample Ready) PKI (Current channel Peak detection) PKV (Voltage channel Peak detection) Reserved LENERGY (End of the LAENERGY and LVAENERGY accumulation) *Register contents show power on defaults AEHF (Active Energy Register Half Full) SAG (SAG Event Detect) ZX (Zero Crossing Time out Detection) ZX (Zero Crossing Detection) -14- REV. PrD 08/01 PRELIMINARY TECHNICAL DATA ADE7754 Interrupt Status Register (10h) / Reset Interrupt Status Register (11h) The Interrupt Status Register is used to determine the source of an interrupt event. When an interrupt event occurs in the ADE7754, the corresponding flag in the Interrupt Status Register is set logic high. The 143 pin will go active low if the corresponding bit in the Interrupt Mask register is set logic high. When the MCU services the interrupt, it must first carry out a read from the Interrupt Status Register to determine the source of the interrupt. All the interrupts in the Interrupt Status Register stay at their logic high state after an event occurs. The state of the interrupt bit in the Interrupt Status register is reset to its default value once the Reset Interrupt Status register is read. Bit Location 0 1 2 3 4 5 6 7 8 9 Ah Bh Ch Dh Eh Fh Interrupt Flag AEHF SAGA SAGB SAGC ZXTOA ZXTOB ZXTOC ZXA ZXB ZXB Default Value 0 0 0 0 0 0 0 0 0 0 Event Description Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the AENERGY register (i.e. the AENERGY register is half-full) Indicates that an interrupt was caused by a SAG on the line voltage of the Phase A Indicates that an interrupt was caused by a SAG on the line voltage of the Phase B Indicates that an interrupt was caused by a SAG on the line voltage of the Phase C Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase A Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase B Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase C Indicates a detection of zero crossing in the voltage channel of the phase A Indicates a detection of zero crossing in the voltage channel of the phase B Indicates a detection of zero crossing in the voltage channel of the phase C In Line energy accumulation, it indicates the end of an integration over an integer number of half line cycles (LINCYC) --see Energy Calibration Indicates that the 5V power supply is below 4V Indicates that an interrupt was caused when the selected voltage input is above the value in the PKVLV register. Indicates that an interrupt was caused when the selected current input is above the value in the PKILV register. Indicates that new data is present in the Waveform Register. Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the VAENERGY register (i.e. the VAENERGY register is half-full) INTERRUPT STATUS REGISTER* F E D C B A 9 8 7 6 5 4 3 2 1 0 LENERGY 0 RESET PKV PKI WFSM VAEHF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR: 10h VAEHF (Apparent Energy Register Half Full) WFMP (New Waveform Sample Ready) PKI (Current channel Peak detection) PKV (Voltage channel Peak detection) RESET LENERGY (End of the LAENERGY and LVAENERGY accumulation) *Register contents show power on defaults AEHF (Active Energy Register Half Full) SAG (SAG Event Detect) ZX (Zero Crossing Time out Detection) ZX (Zero Crossing Detection) REV. PrD 08/01 -15- PRELIMINARY TECHNICAL DATA ADE7754 NOTE For a complete datasheet of the ADE7754, please contact us on our website at: http://forms.analog.com/Form_Pages/energymeter/ contact.asp OUTLINE DIMENSIONS Dimensions shown in inches and (mm) 24-LEAD SOIC (R-24) 0.6141 (15.60) 0.5985 (15.20) 24 13 0.2992 (7.60) 0.2914 (7.40) 1 12 0.4193 (10.65) 0.3937 (10.00) PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) 0.0098 (0.25) 45 0.0118 (0.30) 0.0500 0.0040 (0.10) (1.27) BSC 8 0 0.0192 (0.49) SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) -16- REV. PrD 08/01 |
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