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Ordering number:ENN4490A
CMOS IC
LC74780, LC74780M
On-Screen Video Display Controllers for VCRs
Overview
The LC74780 and LC74780M are CMOS, video display controllers for superimposing text and low-level graphics onto an NTSC, PAL or PAL-M compatible television receiver. Up to 288, 12 x 18-pixel characters can be displayed under microprocessor control on a 24-character by 12-line display. The LC74780 and LC74780M feature selectable pixel width and height, and 64 vertical and 64 horizontal display start positions. It also features a flashing enable bit for each character position. The LC74780 and LC74780M operate from a 5V supply. The LC74780 is available in 24-pin DIPs, and the LC74780M, in 24-pin MFPs.
Package Dimensions
unit:mm 3067A-DIP24S
[LC74780]
21.0
24
13
7.62 6.4
1
0.9
12
Features
* Complete text and graphics vide overlay circuitry. * 128-character internal character generator ROM. * 12 x 18-pixel characters. * Three pixel widths and three pixel heights. * Selectable background color. * 8 colors at 4fSC (NTSC/PAL/PAL-M) * 4 colors at 2fSC (NTSC) * Built-in synchronization check and separation circuitry. * Approximately 0.5 or 1 s period character flashing option. * Screen blanking. * NTSC, PAL and PAL-M format compatibility. * 8-bit serial input format. * 5V supply. * 24-pin plastic DIP and 24-pin plastic MFP.
(0.71)
1.78
0.48
0.95
0.51min
unit:mm 3045B-MFP24
[LC74780M]
24 13
3.3 3.9max
(3.25)
SANYO : DIP24S
15.3
0.35
1.27
0.67
0.1
SANYO : MFP24
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O1001TN (KT)/D1694TH(ID)/N1293JN No.4490-1/14
2.5max
0.15
2.15
0.75
1
12
9.0 10.5
7.9
0.25
LC74780, 74780M
Block Diagram
No.4490-2/14
LC74780, 74780M
Pin Functions
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name VSS1 XIN XOUT CTRL1 CSYNOUT OSCIN OSCOUT SYNC CS SCLK SIN VDD2 CVOUT NC CVIN VDD1 SYNCIN SEPC SEPOUT SEPIN CTRL2 CTRL3 RST VDD1 Ground Internal sync signal crystal oscillator capacitor connections or external clock input (2fSC or 4fSC). Clock input mode select. HIGH for external clock input mode, and LOW for crystal oscillator mode. Composite synchronization signal output. During reset (RST LOW), crystal oscillator clock is output. No output for internal reset command. LC oscillator input. LC circuit for pixel clock generation character output. LC oscillator output. LC circuit for pixel clock generation character output. External synchronization signal check output. HIGH when sync is detected. During reset (RST LOW), pixel clock is output. No output for internal reset command. Serial data input enable when LOW, with pull-up resistance (hysteresis input). Clock input for serial data input, with pull-up resistance (hysteresis input). Serial data input, with pull-up resistance (hysteresis input). Power supply for composite video image signal level modulation (for analog system). Composite video image signal output. No connection. Composite video image signal input. 5V power supply for digital system. Synchronization separation circuit input. If internal sync separation circuit is not used, use SYNCIN to input an external horizontal or composite synchronization signal. Synchronization separation circuit modulator capacitor connection. Leave open if not used. Composite synchronization separation circuit output. Outputs SYNCIN signal if internal sync separation is not used. Vertical synchronization signal input. Tie to VDD1 if not used. NTSC/PAL/PAL-M sync signal generation method select input. PAL-M when HIGH. NTSC/PAL/PAL-M selected by command when LOW. SEPIN input control. VSYNC input signal when LOW, and not input when HIGH. System reset input, with pull-up resistance (hysteresis input). 5V power supply for digital system. Description
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter VDD1 and VDD2 supply voltage Input voltage range for all inputs CSYNOUT, SYNC and SEPOUT output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN max VOUT max Pd max Ta=25C Topr Tstg Conditions Ratings
VSS- 0.3 to VSS+7.0 VSS- 0.3 to VDD+0.3
VSS- 0.3 to VDD+0.3 350
Unit V V V mW
- 30 to +70 - 40 to +125
C C
Allowable Operating Ranges at Ta = -30 to +70C
Parameter Logic supply voltage Analog supply voltage Logic supply voltage range Analog supply voltage range Symbol VDD1 VDD2 VDD1 VDD2 Conditions Ratings 5.0 5.0 4.5 to 5.5 4.5 to 1.27VDD1 Unit V V V V
Pin Assignment
No.4490-3/14
LC74780, 74780M
Electrical Characteristics at Ta = -30 to +70C, VDD1 = 5V, unless otherwise noted
Parameter VDD1 logic supply current VDD2 analog supply current CVIN input leakage current CVOUT output leakage current CTRL1, CTRL2, CTRL3 and OSCIN LOW-level input current RST, CS, SIN, SCLK, CTRL1, SEPIN, CTRL2 and CTRL3 HIGH-level input current RST, CS, SIN and SCLK LOW-level input voltage CTRL1, CTRL2, CTRL3 and SEPIN LOW-level input voltage RST, CS, SIN and SCLK HIGH-level input voltage CTRL1, CTRL2, CTRL3 and SEPIN HIGH-level input voltage CVIN composite video input voltage SYNCIN composite video input voltage XIN input voltage CSYNOUT, SYNC and SEPOUT LOW-level output voltage CSYNOUT, SYNC and SEPOUT HIGH-level output voltage CVOUT sync voltage CVOUT pedestal voltage CVOUT LOW-level color burst voltage CVOUT HIGH-level color burst voltage CVOUT LOW-level background color voltage CVOUT HIGH-level background color voltage CVOUT border voltage CVOUT character voltage RST, CS, SIN and SCLK pull-up resistance Symbol IDD1 IDD2 Ileak1 Ileak2 IIL IIH VIL1 VIL2 VIH1 VIH2 VIN1 VIN2 VIN3 VOL1 VOH1 VSN VPD VCBL VCBH VRSL VRSH VBK VCHA RPU External clock input, fIN=2fSC or 4fSC VDD1=4.5V, IOL=1.0 mA VDD1=4.5V, IOH=-1.0 mA See note 1. See note 2. See note 1. See note 2. See note 1. See note 2. See note 1. See note 2. See note 1. See note 2. See note 1. See note 2. See note 1. See note 2. See note 1. See note 2. Depends on optional settings at pins NTSC (2fSC) NTSC (4fSC) PAL (4fSC) PAL-M (4fSC) OSCIN and OSCOUT oscillator frequency fOSC2 LC oscillator 5 3.5 0.70 0.95 1.30 1.54 1.00 1.25 1.62 1.85 1.45 1.69 1.98 2.21 1.52 1.66 2.63 2.79 25 0.82 1.07 1.42 1.66 1.12 1.37 1.74 1.97 1.57 1.81 2.10 2.33 1.64 1.78 2.75 2.91 50 7.159 14.318 17.734 14.302
10 0.94 1.19
Conditions All outputs open, 7.159MHz crystal oscillator, 8MHz LC oscillator VDD2=5V
Ratings min typ max 15 20
1 1
Unit mA mA A A A 1 A V V V V VP-P
VIN=VSS1 VIN=VDD1
-1
VSS-0.3 VSS-0.3
0.8VDD1 0.7VDD1
0.2VDD1 0.3VDD1
VDD1+0.3 VDD1+0.3
2.0 2.0 0.20
2.5 5.0 1.0
VP-P VP-P V V V V V V V V V V V V V V V V V V K MHz MHz MHz MHz MHz
1.54 1.78 1.24 1.49 1.86 2.09 1.69 1.93 2.22 2.45 1.76 1.90 2.87 3.03
90
XIN and XOUT oscillator frequency
fOSC1
Notes 1. CVOUT at VDD1=VDD2=5.0V, 0.8V sync level 2. CVOUT at VDD1=VDD2=5.0V, 1.0V sync level Timing Characteristics at Ta = -30 to +70C, VDD1 = 5 0.5V
Parameter SCLK input pulsewidth CS HIGH-level input pulsewidth CS input setup time SIN data input setup time CS input hold time SIN data input hold time 8-bit data word write time RAM data write time Symbol tW(SCLK) tW(CS) tSU(CS) tSU(SIN) tH(CS) tH(SIN) tWORD tWT Conditions Ratings min 200 1 200 200 2 200 4.2 1 typ max Unit ns s ns ns s ns s s
No.4490-4/14
LC74780, 74780M
Serial Data Input Timing
Display Control Features and Characteristics
Display Control Command Structure The display control commands, COMMAND0 to COMMAND7, are shifted in 8-bit serial units. The first byte of a command consists of an identification code and data. The second byte consists of data only. Once the command identification code in byte 1 has been written, it is saved until Display Control Command Data
First byte Command 7
COMMAND0 Display memory (VRAM) write address setting command COMMAND1 Display character data write command COMMAND2 Vertical display position and character size setting command COMMAND3 Horizontal display position and character size setting command COMMAND4 Display control setting command COMMAND5 Display control setting command COMMAND6 Synchronization signal control setting command COMMAND7 Display control setting command
the next time the first byte is written. If COMMAND1 is written, the display character write mode begins and the first byte does not change. When CS is HIGH, COMMAND0 is set.
Second byte Data or register storing data 7 0 6 0 5 0 4 H4 3 H3 2 H2 1 H1 0 H0 2 V2 1 V1 0 V0
Command code 6 0 5 0 4 0
Data or register storing data 3 V3
1
1
0
0
1
0
0
0
0
at
C6
C5
C4
C3
C2
C1
C0
1
0
1
0
VS21 VS20
VS11 VS10
0
FS
VP5
VP 4
VP 3
VP 2
VP 1
VP0
1
0
1
1
HS21 HS20
HS11 HS10
0
LC
HP 5
HP4
HP3
HP 2
HP1
HP0
1
1
0
0
TST MOD NP1
RAM ERS NP 0
OSC STP NON DIS LIN EX 0
SYS RST INT
0
BLK2
BLK1 BLK0
BK 1
BK 0
RV
DSP ON PH0
1
1
0
1
0
0
0
BCL
CB
PH2
PH 1
1
1
1
0
MOD1 MOD0
MUT
0
RN 2
RN1
RN0
SN3
SN 2
SN1
SN0
1
1
1
1
EX1
PD1
PD0
No.4490-5/14
LC74780, 74780M
COMMAND0: Display Memory Write Address Setting Command COMMAND0: first byte
DA0 to DA7 0 1 2 3 4 5 6 7 Register name V0 V1 V2 V3 Register Contents Status 0 1 0 1 0 1 0 1 0 0 0 1 Display memory line address 0 to BH Function Remarks
COMMAND0 identification code
COMMAND0: second byte
DA0 to DA7 0 1 2 3 4 5 6 7 Register name H0 H1 H2 H3 H4 Register Contents Status 0 1 0 1 0 1 0 1 0 1 0 0 0 Display memory address 0 to 17H Function Remarks
Second byte identification bit
Note On system reset with RST, the status of all registers is set to 0. COMMAND1: Display Character Data Write Command COMMAND1: first byte
DA0 to DA7 0 1 2 3 4 5 6 7 Register name Register Contents Status 0 0 0 0 1 0 0 1 Function Remarks
COMMAND1 identification code
After command is input, display character data write mode is set until CS is set HIGH
No.4490-6/14
LC74780, 74780M
COMMAND1: second byte
DA0 to DA7 0 1 2 3 4 5 6 7 Register name C0 C1 C2 C3 C4 C5 C6 at Register Contents Status 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Remarks
Character code 0 to 7FH
Character attribute OFF Character attribute ON
Note On system reset with RST, the status of all registers is set to 0. COMMAND2: Vertical Display Position and Character Size Setting Command COMMAND2: first byte
DA0 to DA7 0 Register name Register Contents Status 0 VS10 1 0 1 VS11 1 0 2 VS20 1 0 3 4 5 6 7 VS21 1 0 1 0 1 VS11 0 0 1 1 VS10 0 1 0 1 Function Height 1H/pixel 2H/pixel 3H/pixel 1H/pixel First line vertical character size Remarks
VS21 0 0 1 1
VS20 0 1 0 1
Height 1H/pixel 2H/pixel 3H/pixel 1H/pixel Second line vertical character size
COMMAND2 identification code
No.4490-7/14
LC74780, 74780M
COMMAND2: second byte
DA0 to DA7 Register name Register Contents Status 0 0 VP0 (LSB) 1 0 1 VP1 1 0 2 VP2 1 0 3 VP3 1 0 4 VP4 1 0 5 VP5 (MSB) 1 6 7 FS 0 1 0 2fSC crystal oscillator frequency 4fSC crystal oscillator frequency Second byte identification bit The initial vertical coordinate position is set in 6 bits, VP0 to VP5, where the LSB, VP0, corresponds to 2H where H is the horizontal synchronization pulse period Function Initial vertical coordinate position determined by Remarks
Note On system reset with RST, the status of all registers is set to 0. COMMAND3: Horizontal Display Position and Character Size Setting Command COMMAND3: first byte
DA0 to DA7 0 Register name Register Contents Status 0 HS10 1 0 1 HS11 1 0 2 HS20 1 0 3 4 5 6 7 HS21 1 1 1 0 1 HS11 0 0 1 1 HS21 0 0 1 1 HS10 0 1 0 1 HS20 0 1 0 1 Function Width 1TC/pixel 2TC/pixel 3TC/pixel 1TC/pixel Width 1TC/pixel 2TC/pixel 3TC/pixel 1TC/pixel Second line horizontal character size First line horizontal character size Remarks
COMMAND3 identification code
No.4490-8/14
LC74780, 74780M
COMMAND3: second byte
DA0 to DA7 0 1 2 3 4 5 Register name HP0 (LSB) HP1 HP2 HP3 HP4 HP5 (MSB) Register Contents Status 0 1 0 1 0 1 0 1 0 1 0 1 0 6 7 LC 1 0 Crystal oscillator dot clock Second byte identification bit LC oscillator dot clock Selects the dot clock used for the character display transverse direction where TC is the OSCIN and OSCOUT operation mode oscilation period The initial horizontal coordinate position is given by The initial horizontal coordinate position is set in 6 bits, HP0 to HP5, where the LSB, HP0, corresponds to 2TC Function Remarks
Note On system reset with RST, the status of all registers is set to 0. COMMAND4: Display Control Setting Command COMMAND4: first byte
DA0 to DA7 0 1 2 3 4 5 6 7 Register name SYSRST OSCSTP RAMERS TSTMOD Register Contents Status 0 1 0 1 0 1 0 1 0 0 1 1 Resets all registers and turns the display OFF Crystal and LC oscillator stop disable Crystal and LC oscillator circuitry stop enable Erases display RAM (set to 7FH) Normal operating mode Test mode Function Remarks A system reset also occurs when CS goes LOW External sync mode character display Approximately 500 s are required to erase RAM (with display OFF) Test mode should not be selected during normal operation
COMMAND4 identification code
COMMAND4: second byte
DA0 to DA7 0 1 Register name DSPON RV Register Contents Status 0 1 0 1 0 2 BK0 1 3 BK1 0 1 0 4 BLK0 1 0 5 BLK1 1 6 7 BLK2 0 1 0 Blinking ON Blinking period approximately 0.5 s Blinking period approximately 1.0 s
BLK1 0 0 1 1 BLK0 0 1 0 1 Blanking select Blanking OFF Character size Border size Full size
Function Character display OFF Character display ON Reverse characters OFF Reverse characters ON Blinking OFF
Remarks
When blinking inverse characters, characters alternate between normal and inverse Selects blinking period
Selects the blanking area size
Character display Video display Second byte identification bit
Full size selection
Note On system reset with RST, the status of all registers is set to 0.
No.4490-9/14
LC74780, 74780M
COMMAND5: Display Control Setting Command COMMAND5: first byte
DA0 to DA7 0 1 Register name INT NON Register Contents Status 0 1 0 1 0 2 NP0 1 0 3 4 5 6 7 NP1 1 1 0 1 1 External synchronization Internal synchronization Interfaced Non-interfaced NP1 0 0 1 1 NP0 0 1 0 1 Mode select NTSC PAL-M PAL NTSC Switches between NTSC, PAL and PAL-M modes Function Remarks Switches between external and internal synchronization Switches between interlaced and non-interlaced
COMMAND5 identification code
COMMAND5: second byte
DA0 to DA7 Register name Register Contents Status 0 0 PH0 1 Function Remarks
PH2 0
0
PH1 0 0 1 1 0 0 1 1
PH0 0 1 0 1 0 1 0 1
Background color phase NTSC /2* In phase* 3/2* * 3/4 /4 7/4 5/4 PAL /2 In phase /2 3/4 /4 /4 3/4
PAL color burst, background color phase diagram
0 0 0 1 1 1 1
1
PH1 1 0
2
PH2 1
3 4 5 6 7
CB BCL
0 1 0 1 0 0 0
* NTSC at 2fSC Color burst signal is output Color burst signal output is halted Background color present Background color not present (background level only is set)
Applies when BCL=1 Applies for internal synchronization only
Second byte identification bit
Note On system reset with RST, the status of all registers is set to 0. COMMAND6: Synchronization Signal Control Setting Command COMMAND6: first byte
DA0 to DA7 0 1 2 3 4 5 6 7 Register name MUT DISLIN MOD0 MOD1 Register Contents Status 0 1 0 1 0 1 0 1 0 1 1 1 COMMAND6 identification code Normal output CVIN is cut and CVOUT is fixed at the pedestal level 12 lines 10 lines Composite sync signal Character and border OR-signal output Composite synchronization separation signal HIGH-level output for internal sync Function Remarks Switches CVOUT Selects the number of display lines Switches CSYNOUT Switches SEPOUT
No.4490-10/14
LC74780, 74780M
COMMAND6: second byte
DA0 to DA7 0 1 2 3 4 5 6 7 Register name SN0 SN1 SN2 SN3 RN0 RN1 RN2 Register Contents Status 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Second byte identification bit RN2 0 0 0 1 RN1 0 0 1 0 RN0 0 1 0 0 Detection frequency 0 times 4 times 8 times 16 times External sync signal detection control determines when the signal goes from OFF to ON. Selects the sampling period, in units of the horizontal sync signal cycle (1H), for which the sync continues and can be detected.
SN3 0 0 0 0 1 SN2 0 0 0 1 0 SN1 0 0 1 0 0 SN0 0 1 0 0 0 Detection frequency No detection 32 times 64 times 128 times 256 times
Function
Remarks
External sync signal detection control determines when the signal goes from ON to OFF. Selects the sampling period, in units of the horizontal sync signal cycle (1H), for which the sync continues and cannot be detected.
Note On system reset with RST, the status of all registers is set to 0.
COMMAND7: Display Control Setting Command COMMAND7: first byte
DA0 to DA7 0 1 2 3 4 5 6 7 Register name PD0 EX0 PD 1 EX1 Register Contents Status 0 1 0 1 0 1 0 1 1 1 1 1 COMMAND7 identification code LOW-level output HIGH-level output MODE0 settings output PORT DATA0 settings output LOW-level output HIGH-level output MODE1 settings output PORT DATA1 settings output Switches SEPOUT Switches CSYNOUT Function Remarks
Note On system reset with RST, the status of all registers is set to 0.
No.4490-11/14
LC74780, 74780M
Display Configuration The display is 24 characters by 12 rows large. Up to 288 characters can be displayed, unless the character size is expanded. The display memory address is set as a row ad-
dress in the range 0 to 11 and a column address in the range 0 to 23.
No.4490-12/14
LC74780, 74780M
Composite Video Output CVOUT Output Waveform (VDD2=5.00V)
Output voltage level Character HIGH-level background color HIGH-level color burst LOW-level background color Border Pedestal LOW-level color burst Sync
Symbol VCHA VRSH VCBH VRSL VBK VPD VCBL VSN
Output voltage at 0.8V sync (V) 2.75 2.10 1.74 1.57 1.64 1.42 1.12 0.82
Output voltage at 1.0V sync (V) 2.91 2.33 1.97 1.81 1.78 1.66 1.37 1.07
Note VDD2=5.00V
No.4490-13/14
LC74780, 74780M
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of October, 2001. Specifications and information herein are subject to change without notice.
PS No.4490-14/14

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