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HCF40110B
DECADE UP/DOWN COUNTER/DECODER/LATCH/DRIVER
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SEPARATE CLOCK-UP AND CLOCK-DOWN LINES CAPABLE OF DRIVING COMMON CATHODE LEDS AND OTHER DISPLAYS DIRECTLY ALLOWS CASCADING WITHOUT ANY EXTERNAL CIRCUITRY MAXIMUM INPUT CURRENT OF 1 A AT 18 V (full package-temperature range) QUIESCENT CURRENT SPECIFIED UP TO 20V STANDARDIZED, SYMMETRICAL OUTPUT CHARACTERISTCS 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
ORDER CODES
PACKAGE DIP TUBE HCF40110BEY T&R
DESCRIPTION HCF40110B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP package. HCF40110B is a dual-clocked up/down counter with a special preconditioning circuit that allows the counter to be clocked, via positive going inputs, up or down regardless of the states or PIN CONNECTION
timing (within 100 ns typ.) of the other clock line. The clock signal is fed into the control logic and Johnson counter after it is preconditioned. The outputs of the Johnson counter (which include anti-lock gating to avoid being locked at an illegal state) are fed into a latch. This data can be fed directly to the decoder through the latch or can be strobed to hold a particular count while the Johnson counter continues to be clocked. The decoder feeds a seven-segment bipolar output driver which can source up to 25mA to drive LEDs and other displays such as low-voltage fluorescent and incandescent lamps. A short duration negative-going pulse appears on the BORROW output when the count changes from 0
October 2002
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to 9 or the CARRY output when the count changes from 9 to 0. At other times the BORROW and BORROW outputs can be tied directly to the INPUT EQUIVALENT CIRCUIT
clock-up and clock-down lines, respectively, of another HCF40110B for easy cascading of several counters. PIN DESCRIPTION
PIN No 1, 15, 14, 13, 12, 3, 2 4 5 6 7 9 10 11 8 16 SYMBOL a, b, c, d, e, f, g Toggle Enable Reset Latch Enable Clock Down Clock Up Carry Borrow VSS VDD NAME AND FUNCTION 7 Segment Outputs Enable Johnson Counter Reset Input Latch Enable Clock Down Clock Up Carry Output Borrow Output Negative Supply Voltage Positive Supply Voltage
FUNCTIONAL DIAGRAM (One Half)
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TRUTH TABLES
CLOCK UP* CLOCK DOWN* X X LATCH TOGGLE ENABLE ENABLE L L X X X X X X X X X H H L L X X H L L RESET L L L H L L L COUNTER Increments by 1 Decrements by 1 No Change Goes to 00000 Inhibited Increments by 1 Decrements by 1 DISPLAY Follows Counter Follows Counter No Change Follow Counter (Display = 0) Remains Fixed Remains Fixed Remains Fixed
X : Don't Care * : Typically 100 ns between clock-up and clock-down positive transitions are required to ensure proper counting
LOGIC DIAGRAM
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LOGIC DIAGRAM
DISPLAY SEGMENTS
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ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C
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DC SPECIFICATIONS
Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 0.4 0.5 1.5 VO (V) |IO| VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 5 10 15 18 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 1.74 4.42 11.56 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 4 10.4 27.2 1 2.6 6.8 10-5 10-4 5 -1.1 -0.36 -0.9 -2.4 1.43 3.74 9.52 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 1.43 3.74 9.52 0.36 0.9 2.4 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit
IL
Quiescent Current
A
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current Q Output Sink Current Input Leakage Current 3-State Output Leakage Current Input Capacitance
IOL
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/5 0/10 0/15 0/18 0/18
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
mA
mA
mA
II
Any Input Any Input Any Input
0.1 0.4
7.5
1 12
1 12
A A
pF
IOZ CI
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
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DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) Min. Value (*) Typ. Max. Unit
CLOCK UP/CLOCK DOWN tW Pulse Width 5 10 15 5 10 15 5 10 15 5 10 15 85 35 15 2.5 5 8 225 100 70 260 110 80 ns
fCL
Maximum Frequency
MHz
tWC
Carry Pulse Width
ns
tWB
Borrow Pulse Width
ns
RESET tPLH tPHL Propagation Delay Time Reset to Clock Delay from Reset to First Allowable Clock tW Pulse Width 5 10 15 5 10 15 5 10 15 750 285 200 300 125 75 150 60 40 ns
ns
ns
(*) Typical temperature coefficient for all VDD value is 0.3 %/C. NOTE : Measured at the point of 10% change in output load of 50pF, RL = 1K to VDD for tPZL, tPLZ and RL = 1K to VSS for tPHZ
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
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WAVEFORM : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
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Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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