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| PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN PM5372 TSE TRANSMISSION SWITCHING ELEMENT CORE CARD REFERENCE DESIGN PRELIMINARY ISSUE 1: MARCH 2000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN PUBLIC REVISION HISTORY Issue No. 1 Issue Date Details of Change February 2000 Document Created PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN CONTENTS 1 2 3 4 5 DEFINITIONS .......................................................................................... 1 FEATURES .............................................................................................. 2 APPLICATIONS ....................................................................................... 3 REFERENCES......................................................................................... 4 APPLICATION EXAMPLES ..................................................................... 5 5.1 5.2 5.3 6 7 ADD/DROP MULTIPLEXER.......................................................... 5 BROADBAND DIGITAL CROSS CONNECT................................. 6 TERMINAL MULTIPLEXER........................................................... 7 BLOCK DIAGRAM ................................................................................... 8 FUNCTIONAL DESCRIPTION................................................................. 9 7.1 7.2 PM5372 TSE ................................................................................. 9 CPLD............................................................................................. 9 7.2.1 CPCI INTERFACE .............................................................11 7.2.2 CONFIGURATION REGISTER .........................................11 7.2.3 SYSCLK CONTROL ......................................................... 12 7.3 CHESS SYSTEM SIGNALS........................................................ 14 7.3.1 SYSCLK DISTRIBUTION ................................................. 14 7.3.2 FRAME PULSE (FP) ........................................................ 15 7.3.3 XCMP, RWSEL ................................................................. 16 7.4 SYSTEM INTERFACE ................................................................ 17 7.4.1 LVDS TERMINATION ....................................................... 18 7.5 COMPACT PCI INTERFACE....................................................... 19 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE i PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 7.5.1 INTERFACE AND BRIDGE HARDWARE......................... 19 7.5.2 HOT SWAP FEATURES................................................... 20 7.6 POWER SUPPLY........................................................................ 21 7.6.1 VOLTAGE REGULATORS ............................................... 22 7.6.2 HOT SWAP CONTROLLER ............................................. 22 8 IMPLEMENTATION DESCRIPTION ...................................................... 25 8.1 8.2 8.3 ROOT DRAWING........................................................................ 25 TSE BLOCK SHEETS 2,3,4........................................................ 25 CPLD BLOCK.............................................................................. 25 8.3.1 VHDL PROGRAMMING CODE ........................................ 26 8.4 CLOCK BLOCK........................................................................... 26 8.4.1 PECL TERMINATION ....................................................... 26 8.5 8.6 SYSTEM INTERFACE ................................................................ 27 COMPACT PCI BLOCK............................................................... 29 8.6.1 LAYOUT CONSIDERATIONS........................................... 29 8.7 9 10 POWER BLOCK ......................................................................... 30 SCHEMATICS........................................................................................ 31 BILL OF MATERIALS............................................................................. 32 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE ii PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN LIST OF FIGURES FIGURE 1 - ADD/DROP MULTIPLEXER........................................................... 5 FIGURE 2 - DIGITAL CROSS CONNECT (PARTIALLY POPULATED) ............ 6 FIGURE 3 - CPLD FUNCTIONAL BLOCK DIAGRAM..................................... 10 FIGURE 4 - LOGIC OF SYSCLK DISTRIBUTION CONTROL........................ 13 FIGURE 5 - SYSCLK SWITCHOVER TIMING................................................ 14 FIGURE 6 - SYSCLK INTER-BOARD DISTRIBUTION................................... 15 FIGURE 7 - FRAME PULSE (FP) INTER-BOARD DISTRIBUTION................ 16 FIGURE 8 - XCMP AND RWSEL INTER-BOARD DISTRIBUTION................. 17 FIGURE 9 - CONNECTION MAP TO BACKPLANE........................................ 18 FIGURE 10- CPCI BLOCK DIAGRAM. ............................................................ 19 FIGURE 11 - POWER SUPPLY BOARD SYSTEM BLOCK.............................. 21 FIGURE 12- CPCI HOT SWAP CIRCUIT......................................................... 23 FIGURE 13- PECL TERMINATION FOR CLOCK DISTRIBUTION .................. 27 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE iii PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 - ADDRESS BIT ALLOCATION.......................................................11 - CONFIGURATION REGISTER.....................................................11 - TSE CORE CARD POWER CONSUMPTION............................. 21 - PINOUT OF BACKPLANE CONNECTION (J4,J5,J6) ................. 27 - BILL OF MATERIALS .................................................................. 32 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE iv PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 1 DEFINITIONS ADM CHESS CPLD LVDS POS P-TCB RWSEL SCOEB SDEN S-TCB xCMP Add Drop Multiplexer Channelizer Engine for SONET/SDH Complex Programmable Logic Device Low Voltage Differential Signaling Packet over SONET Parallel Telecombus at 77.76 MHz Read Working Link Select SYSCLK Output Enable Bar SYSCLK Distribution Enable Serial Telecombus at 777.6 MHz Grouped Connection Memory Page signals PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 2 FEATURES The TSE Core Card Reference Design belongs to the CHESS Set Reference Design and has the following features: * Demonstrates a non-blocking cross-connect (switch matrix building block) with STS-1 granularity and scalability from 40 Gb/s to 160 Gb/s in a single stage, and up to 2.5 Tb/s in multi-stage fabrics. Highlights a single PM5372 TSE Transmission Switch Element device with backplane access to all 64 ingress and 64 egress STS-12 equivalent S-TCB ports. 777.6 MHz LVDS serial telecombus (S-TCB) links to 16, OC-48 load devices through CHESS Set Backplane. Supports extension to redundant and expanded bandwidth fabrics using multiple cards. A single card supports 40Gb/s. Transparent support for UPSR, 2-BLSR, 4-BLSR architectures. Generates CHESS Set specific signaling for backplane distribution and manages generation between multiple cards. Provides a total of 9 differential PECL SYSCLK pairs to backplane for system side timing. Host control and monitoring through 32bit 33MHz CompactPCI interface. On-board power regulation provides required 1.8V and 3.3V from cPCI bus. Supports hot swapping. * * * * * * * * * PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 2 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 3 APPLICATIONS * * * Multiservice Add/Drop Mulitplexer Digital Cross Connect Terminal Multiplexer PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 3 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 4 REFERENCES PMC-Sierra, Inc., PMC-1990713, " Transmission Switch Element Data Sheet", Issue 2, January 2000. PMC-Sierra, Inc., PMC-200-0021, "CHESS Reference Design Hardware Manual", Issue 1, March 2000. PMC-Sierra, Inc., PMC-1991797, "CHESS User's Guide", Issue 1, March 2000. Bell Communication Research - SONET Transport Systems: Common Generic Criteria, GR-253-CORE, Issue 2, December 1995. PICMG, "Compact PCI Specification", Version 2.0 R2.1 Sept, 1997. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 4 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 5 APPLICATION EXAMPLES The TSE Core Card Reference Design is a building block for scalable and redundant SONET/SDH switch fabrics. It is applicable for use with any combination of line and service cards as bandwidth and ports permit. The general configuration sees a TBS device (or function) on line or service cards to connect to the ingress and egress ports on the TSE Core Card. This design finds application in typical SONET network elements: multiservice Add/Drop multiplexer, broadband digital crossconnect and terminal multiplexer. 5.1 Add/Drop Multiplexer In a multiservice Add/Drop Multiplexer (ADM), the TSE Core Card acts to route the different traffic types the SONET line may contain such as POS, voice, or video, to the appropriate service cards. In this way, the TSE decouples line-side PHY devices of SONET rings from multi-service system cards. Figure 1 is an example configuration for an ADM with a maximum switch bandwidth of 80Gb/s. A 40Gb/s fabric with 1:1 redundancy is formed from this configuration by adding two additional links to each TSE card from each line card. Figure 1 - Add/Drop Multiplexer SONET Ring Multi-Service STS-48 Load Card 1 2 2 ATM Processing Card 2 TSE Core Card 2 STS-48 Load Card 2 2 2 POS Processing Card 2 2 TSE Core Card LVDS Backplane PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 5 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN In Figure 1, each line represent both transmit and receive STS-12 bidirectional links. The TSE Core Card completes the SONET ring, routes the drop traffic to the desired processing card, and routes the add traffic to the appropriate line card. Through traffic connects from ingress line card to egress line card through the TSE Core Card. This provides an opportunity for channel spying, redundancy switchovers and traffic grooming. Add traffic is routed to a single ring or to multiple rings using multicast. The TSE Core Card plays an important role in any UPSR, 2-BLSR, or 4-BLSR ring architecture and does not require additional configuration in any case. The architectural details are accomplished within the switch settings of the TSE device. See the CHESS User's Guide (PMC-1991797) for information on implementing ring architectures. 5.2 Broadband Digital Cross Connect Figure 2 - Digital Cross Connect (Partially Populated) 1 OC-12 Line Card OC-12Line Card OC-12 Line Card OC-12 Line Card OC-48 Line Card OC-48 Line Card 4 1 4 OC-48 Line Card TSE Core Card 1 1 4 A broadband digital cross-connect (DCC) with grooming for (12 x 64=) 768, STS1 streams (40Gb/s throughput) is formed with a single TSE Core Card. The system bandwidth is scalable (as in any application of the TSE Reference Card) to the desired bandwidth and port count with the use of additional Core Cards. In the DCC, the TSE Card consolidates or segregates STS-1 traffic between the STS-12 equivalent flows found at each port. OC-48 and OC-192 devices are interfaced by aggregating 4 and 16 flows respectively. A cross connect using only one eighth of the TSE Core Card ports with simple uni-directional connectivity is drawn in Figure 2. Any STS-1 from an ingress card or port can be switched to any STS-1 timeslot on any egress card or port. The number on each line indicates count of uni-directional S-TCB STS-12 streams. Bi-directional connections can be simultaneously added, greatly increasing the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 6 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN switch possibilities. Additionally, a one-to-one ratio of ingress to egress is implied here but not necessary. Multicast is supported as an output can sample data from any input. 5.3 Terminal Multiplexer A terminal multiplexer using the TSE Core Card does not differ significantly from the ADM or DCC applications since the same decoupling is provided between the line and service cards. Note that in all applications using the TSE Reference Design (or the PM5372) discussed here, the bandwidth is scalable with the addition of planes and stages. It is also important to note that redundancy (whether 1:1 or 1:n) can be accomplished for any fabric composition. The CHESS User's Guide (PMC1991797) describes these issues in greater detail. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 7 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 6 BLOCK DIAGRAM Power Supply 3.3V 1.8V LD[15:0] LA[15:2] LA[21:16] LINT# ADS# LW/R# READY# LRESETo# LHOLD PCI Bus LHOLDA# LCLK ACTIVE_LED XCMP_LED RWSEL_LED SCLK_TTL CLK_EN SYSCLKo SYSCLKi2 SYSCLKi1 D[15:0] A[12:0] INTB SYSCLK 77.76MHz TTL Clock PLX PCI9054 CPLD ACTIVE SDEN SDENOUT RSTB CSB WRB RDB CMP RWSEL xCMP FP RJOFP TJ0FP TSE PM5372 PECL to TTL TTL to PECL SSDEN FPDEN EN PECL Clock Distribution RN RP EN TTL Driver 64 64 64 64 cPCI Bus SYSCLK Distribution Control Signals CHESS System Signals 777.6 Mb/s LVDS S-TCB TN TP PECL SYSTEM CLOCKS cPCI Connector, J1 HS-3 Backplane Connectors J4,J5,J6 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 8 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 7 FUNCTIONAL DESCRIPTION This design provides an example implementation of the TSE Transmission Switching Element device and CHESS signalling (xCMP, RWSEL, SYSCLK, FP). A CPLD is used for signalling control, and a Compact PCI bus is used for the host interface. The TSE Core Card Reference Design belongs to the CHESS Reference Design. 7.1 PM5372 TSE The PM5372 Transmission Switch Element is a time-space-time switch fabric with 40 Gb/s bandwidth. It performs non-blocking permutation switching with STS-1 granularity on 64, STS-12 ingress ports. Each port supports streams formed by any combination of STS-1, STS-3, STS-3c, STS-12, or STS-12c. STS-48 and STS-192 flows are supported by aggregating 4 and 16 STS-12 streams. There are a total of 64 ingress and 64 egress STS-12 ports using 10B/8B encoded 777.76MHz LVDS. All of the TSE ports are available at the backplane connector. The TSE device switches the STS-12 aligned data streams at STS-1 granularity through ingress Time, Space, and then egress Time switch stages. The time switch stages perform timeslot interchange on each STS-12 data stream. The space switch stage switches data from one STS-12 pipe to another. Each STS-1 timeslot is switched independently in the Space switch stage. The egress time switch stage then provides for an additional timeslot interchange. The result is a reconfigurably non-blocking fabric of STS-1 granularity. The ports are aligned and framed by the framing pulse (FP) applied to the RJ0FP pin. The TSE device decodes the 8B/10B J0 frame alignment control code found within each STS-12 stream to align the 10B characters. If the alignment criteria is met, SYNC state is entered and each stream will be aligned at the space switch boundary. The write pointers of the 64 ingress FIFOs (buffer the differences between internal timing and the LVDS interface) are reset when the J0 byte is received as expected. This provides the necessary port alignment and framing at switch boundaries. 7.2 CPLD A complex programmable logic device (CPLD) is used to perform two functions within the TSE Core Card: 1) interface between the PM5372 TSE device and the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 9 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN cPCI interface device, and 2) generation and control of CHESS system signals (xCMP, FP, RWSEL and SYSCLK). Figure 3 - CPLD Functional Block Diagram RESET_BUTTON LRESETo# RSTB ADS# LW/R# READY# LHOLD LHOLDA# Bus Request/ Grant Read/Write Control CSB RDB WRB LCLK /n FPIN FP Generator OK FPOUT LA[15..13] LD[7..0] Function Instruction Register andDecoder xCMP Register xCMPO RWSEL Register RWSELO Driver Enable Note 1 SCOEB ACTIVE Active/ Register ACTIVE_LED xCMPLED RWSEL_LED SYSCLKi1 SYSCLKi2 SDEN SYSCLK Control SYSCLKo SDENOUT Note 1 Not Implemented PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 10 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 7.2.1 cPCI Interface The interface to the cPCI interface chip can be summarized as follows: added signaling (LHOLD, LHOLDA#, ADS#, READY#) not support by the microprocessor interface and decoding for interface signals (RDB, WRB and CSB). Timing for the signals to the TSE device is achieved using counts of SYSCLK. 7.2.1.1 Address Space of Card The LA<32..2> address space is allocation according to Table 1. Table 1 - Address Bit Allocation Function TSE Normal Registers TSE Test Registers CPLD Configuration Register Unused bits LA<32..2> bits 13..2 14..2 15 32..16 7.2.2 Configuration Register The CPLD provides a register for control of CHESS system signalling. Access to the register is through the cPCI interface when LA[15] = 1. The CSB pin of the TSE device is deselected and LD[7..0] is written to the register. Table 2 Bit 0 1 2 3 4 - Configuration Register Function CMP pin value RWSEL pin value FP driver enable xCMP/RWSEL driver enable A/B Default 1 1 1 1 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 11 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN Bit 5 6 7 Function Master Reset Reserved Default 0 0 0 7.2.2.1 A/B Jumpers The A/B jumper can be set to differentiate between two TSE Core Cards with Configuration Bit 4. The setting of the jumper is logically XORed with Configuration Bit 4 to determine the active card. 7.2.3 SYSCLK Control The TSE Core Card generates and distributes the 77.76 MHz CHESS system timing signal, SYSCLK. This signal is important to the timing of the S-TCB (LVDS) interface and the digital switch core timing. It is common for all devices using the S-TCB to avoid FIFO over and under runs. Essentially, frequency is the only consideration for SYSCLK as the system is not sensitive to skew. With this in mind, a centralized SYSCLK source has been implemented. It was conceived that the source of SYSCLK be switched between two installed TSE Core Cards at specific events. For instance, this may be desired if using a redundant TSE configuration when a change from receiving Working to Protection channels is made (CHESS chipset signal RWSEL change) after the Working data stream is interrupted or has accumulated significant errors. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 12 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN Figure 4 - Logic of SYSCLK Distribution Control to ENbar of 100LVEL14 clock distribution IC D Q SDENOUT SDENOUT Q D to ENbar of 100LVEL14 clock distribution IC SYSCLK_TTL SELECT SDEN SDEN SYSCLK_TTL SELECT logic and signals found on TSE Core Card A Backplane logic and signals found on TSE Core Card B The logic in Figure 4 is used to control the switch between the unique clock sources. This configuration will avoid runt or otherwise glitched clock distribution during the switchover with minimized clock gap. With a change on SELECT, the driving board will hold SYSCLK low on a falling edge. The other card will be enabled once the SDENOUT flip-flop is clocked and will begin SYSCLK distribution on a falling edge of its SYSCLK. SYSCLK distribution is ultimately controlled using the synchronous ENbar of the MC100LVEL14 1:5 clock distribution device. ENbar is set as described in Figure 4. The clock driver can be disabled by the CPU (via the CPLD) if a second TSE Core Card is used, or an alternate source is desired. The Active A and Active B bits of the Configuration Register holds this status. Representative timing waveforms drawn in Figure 5 show the cessation of clock A, the resultant lost pulse (low), and the initiation of clock B. Clock B has been drawn with worst case phase. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 13 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN Figure 5 - SYSCLK Switchover Timing SELECT clock on Card A clock on Card B SDENOUT CARD A SDEN CARD A SYSCLK clock A clock B For the TSE Core Card not distributing timing to the backplane, SYSCLK is sampled from the backplane for TSE device timing and for redundant timing of FP. Alignment of the frame pulse (FP) counter between TSE Core Cards is accomplished similarly, as FP is always sampled from the backplane and used to reset the local frame pulse counter. 7.3 CHESS System Signals 7.3.1 SYSCLK Distribution SYSCLK is distributed within the CHESS Reference Design cards as described in Figure 6. Only one SYSCLK source drives at one time (as described above in Figure 4), hence the OR gate selects the active clock source. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 14 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN Figure 6 - SYSCLK Inter-Board Distribution TSE CORE CARD SYSCLK TSE CORE CARD SYSCLK Clock Clock SYSCLK LINE CARD SYSCLK LINE CARD SYSCLK LINE CARD 7.3.2 Frame Pulse (FP) The frame pulse (FP) indicates the STS-12 frame boundaries at the J0 byte. This signal provides synchronization between all CHESS devices to ensure alignment of frames at space and time switch fabric interfaces. It is asserted high for a full SYSCLK period once every 9720 counts of SYSCLK (125s). FP is not required at every frame as all CHESS devices maintain framing counts, but synchronization must occur at the initialization of operation. FP can be disabled by setting Configuration Register Bit 2 = 0 on both cards. The OK signal is used to signal the update of XCMP and RWSEL at the end of each frame. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 15 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN The CPLD is used for counting SYSCLK cycles for FP and for enabling the 49FCT3805 1:4 output driver used in its distribution. Consult the CHESS User's Guide (PMC-1991797) for additional information on frame alignment and the system effects of the frame pulse. Figure 7 - Frame Pulse (FP) Inter-board Distribution TSE CORE CARD FP gen TSE CORE CARD FP gen EN EN LINE CARD LINE CARD LINE CARD 7.3.3 xCMP, RWSEL The system host determines the CHESS system signals', xCMP and RWSEL, respective states. Each TSE Core Card generates identical versions but only one drives the backplane as set in Configuration Register Bit 3. As xCMP and RWSEL are sampled at FP, changing their respective states is reserved until immediately before the frame pulse. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 16 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN Figure 8 - xCMP and RWSEL Inter-board Distribution xCMP xCMP xCMP, RWSEL gen RWSEL RWSEL xCMP, RWSEL gen TSE CORE CARD TSE CORE CARD xCMP LINE CARD RWSEL xCMP LINE CARD RWSEL xCMP LINE CARD RWSEL 7.4 System Interface The S-TCB is an 777.6 Mb/s LVDS link. In a normal configuration, the TSE Core Card will connect through the S-TCB backplane to SONET/SDH framer cards with S-TCB interfaces (provided by the PM5315 TBS device). For multi-stage fabrics, one TSE Core Card (or device) would connect to another TSE Core Card (or device). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 17 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN Figure 9 - Connection Map to Backplane CPLD Control ACTIVE CLKCOUT CLKCIN System Signals LVDS S-TCB SYS CLK SYSCLK[1:7] SYSCLKIN Rows 7-10 Rows 1-6 Backplane HS3 Connector The separation of the backplane connection into Rows 7-10 and Rows 1-6 was made to enable the optional use of a 6 Row connector or a 10 Row connector. All non-LVDS backplane signaling resides within Rows 1-6, and Rows 7-10 contain only LVDS channels as described in Figure 9. Note: the pin-out of the HS-3 connector in Table 4 labels the rows as letters (A, B, C,... with 1 being Row A) to be consistent with AMP documentation. 7.4.1 LVDS Termination The LVDS receive signals RN/P[1..64] are terminated with 100 internally to the TSE device. No additional termination is normally required. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RP[41:64] RN[41:64] TP[41:64] TN[41:64] RP[1:40] RN[1:40] TP[1:40] TN[1:40] RWSEL GFP xCMP TJ0FP 18 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 7.5 Compact PCI Interface The PM5372 TSE includes a microprocessor interface to provide read/write access to normal and test mode registers as described within the TSE Data Sheet. This design connects a CompactPCI bus to this microprocessor interface. A block diagram of the cPCI interface and bridge is shown below in Figure 10. Figure 10 - cPCI Block Diagram. LA<31..2> LD<31..0> CONTROL LA<31..2> LD<31..0> CONTROL AD<31:0> C/BE<3:0> CONTROL CPCI J1 LOCAL BUS PLX 9054 PCI BRIDGE PCI BUS RESET\ EEPROM EECS EESK EEDI/O +12V -12V +5V +3.3V 7.5.1 Interface and Bridge Hardware The PCI9054 is a 3.3V/5V compliant PCI v2.2 32-bit, 33MHz Bus Master Interface Controller, that provides flexible local bus configurations and Hot Swap capability. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 19 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN The 32 bit multiplexed address/data bus and associated control lines connect directly from the CPCI J1 connector to the PLC PCI9054 bridge device. The bus and control lines are terminated with 10 ohm stub resistance that should be placed close to the J1 connector pins. For this reference design the PCI 9054 operates with a 32-bit non-multiplexed bus (C-mode) on the local bus side. Address lines LA<31...2> provide 32-bit word addressing. The lower two bits of the address lines are used for 16 or 8 bit byte access but are unused in this application. The CPLD (Section 7.2.1) implements the local bus glue logic. A serial EEPROM is required for device configuration after reset or upon powerup. PLX Technology recommends Fairchild Semiconductor the 93CSX6L family serial EEPROMs. The PCI9054 can also be configured by an on board microprocessor/controller if desired. 7.5.2 Hot Swap Features In addition to the local and PCI bus interfaces, the cPCI block provides some of the hardware required for hot swap. The hot swap specification outlines a hardware and software solution to allow cPCI boards to be safely plugged in or removed from an active PCI backplane. Note that this block does not provide the minimum Hot Swap requirements for safe insertion and extraction. An additional Hot Swap controller is required to safely power up and power down the board. The cPCI block provides 1V precharge voltage to cPCI bus pins to reduce pin bounce during connection or removal. Most cPCI pins are pulled up to 1V with 4 other pins (RST#, ENUM#, INTA#, and REQ#) precharged to V(I/O) to provide a stable clock prior to bus contact. The PCI9054 provides control circuitry for a blue hot swap LED placed on the front panel of the board. This LED is illuminated when it is safe to extract a board from the backplane. As the user presses the ejector switch to remove a board from the backplane, the LED indicates that system software has been placed in a safe state for extraction. There is no indication as to the hardware integrity. Upon insertion, the LED will remain illuminated until the hardware connection process completes. It will remain off until illuminated by software to indicate extraction is safe. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 20 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 7.6 Power Supply Figure 11 - Power Supply Board System Block. +5V +3.3V +5V_PCI +3.3V_PCI +12V_PCI -12V_PCI GND BD_SEL# HEALTHY# PCI_RST# Hot Swap Controller LT1643L +12V -12V 1.8VA +5V 1.8V Regulator 1.8V +3.3V 1.8V Regulator The Power Block provides stable voltage supplies delivered over the CompactPCI backplane from a centralized power supply. Voltage levels of +5V, +3.3V, +12V, -12V and regulated 1.8V are available from this block. Table 3 PART TSE TSE - TSE Core Card Power Consumption SUPPLY 1.8 VDDI 1.8 AVDL CURRENT 3835mA 965mA 4800mA QUANTITY 1 1 POWER 6903mW 1824mW 8727mW 1.8V WORST TOTAL TSE MC100LVEL14 MC100LVELT23 MC100LVELT22 49FCT3805 MB OSCILATOR 3.3 3.3 3.3 3.3 3.3 3.3 1298mA 40mA 33mA 33mA 30mA 90mA 1 2 1 1 2 1 4283mW 264mA 109mW 109mW 200mW 279mW PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 21 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 74ALVC125 XC9572XL 74HC244 SSF-LXH5174 PLX9054 3.3V WORST TOTAL 3.3 3.3 3.3 3.3 3.3 50mA 50mA 60mA 80mA 200mA 2109mA 1 1 1 2 165mW 165mW 198mW 528mW 660mW 6960mW 7.6.1 Voltage Regulators Two voltage regulators supply the 1.8V digital and 1.8V analog pins of the TSE device - 1.8V is not used anywhere else on the board. The supply labelled 1.8V is used for core digital (VDDI) power and uses the 5V for VIN of the regulator. The supply labelled VCC1 is used for AVDL (1.8V analog) pins and uses the 3.3V for VIN. Both regulators are capable of providing up to 5A of supply current at 1.8V. 7.6.2 Hot Swap Controller The Hot Swap Controller is used to allow a board to be safely inserted or removed from a live cPCI slot. External N-channel MOSFETS control the 3.3V and 5V supplies, while the +12V and -12V supplies are controlled with on-chip switches. The supply voltages are ramped up at a programmable rate. The hot swap controller is implemented using the Linear Technology LTC1643L. A typical cPCI Hot Swap circuit is shown below in Figure 2. Note that only the hot swap controller is implemented in the power block. Additional Hot Swap circuitry including the precharge circuitry for the cPCI bus is included in the CompactPCI block. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 22 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN Figure 12 - cPCI Hot Swap Circuit 0.007 Q1 IRF7413 +5V_PCI 0.005 +3.3V_PCI R1 Q1 IRF7413 R2 R4 5V 5A 3.3V 7.6A 10 100 R3 V(I/O) CompactPCI Connector R6 1.2k R7 2k 10 R5 3Vin 3Vsense GATE 3Vout 5Vin 5Vsense 5Vout 12Vin VEEin ON# V(I/O) FAULT# 12Vout VEEout 12V 500mA -12V 100mA +12V_PCI -12V_PCI BD_SELB LT1643L 12V HEALTHYB 0.1uF GND 0.1uF R8 2k PWRGD# GND TIMER 0.01uF The 3.3V, 5V, +12V, and -12V power supplies are generated from the medium length power pins on the PCI connector (+5V_PCI, +3.3V_PCI, etc). The long power pins which make the first connections are used to generate a 1V precharge voltage on the cPCI bus pins. In the circuit above, the 3.3V and 5V power supplies are controlled by the Nchannel pass transistors Q1 and Q2. Internal circuitry controls the +/-12V rails. R1 and R2 control overcurrent conditions. R5 and C1 provide current control loop compensation. R3 and R4 prevent high frequency oscillations in the pass transistors. Finally, the 12V Zener diode protects against power surges on the -12V rail. During an insertion and power-up sequence, the BD_SEL# pin is the final pin to connect to the board. This pin is connected to the ON# pin of the Hot Swap Controller. When the ON# pin is pulled low, the pass transistors are turned on by pulling the GATE pin high, and the current in each pass transistor rises at a rate of dv/dt = 50A/C1, until reaching the preset limit. If there is a high load capacitance, the rate of increase will be controlled by this value. Once the supply voltages stabilize the PWRGD# signal is pulled low. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 23 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN The current limit for the 5V and 3.3V supplies is set by the sense resistors R1 and R2 in Figure 12 above, and is governed by the following equation: I lim = 53mV / Rsense In the circuit shown above, the 3.3V current limit will be 10.6A, and the 5V limit will be 7.6A. Upon removal, the /ON pin will be pulled high, and the GATE pin on the pass transistors is pulled low to prevent load currents on the 3.3V and 5V rails from instantaneously going to zero and glitching the power supply. The /PWRGD pin is pulled high if any of the supply voltages moves below its threshold. Refer to the LT1643 datasheets for additional operation and applications information. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 24 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 8 8.1 IMPLEMENTATION DESCRIPTION Root Drawing The root drawing shows the interconnections between the CPCI_BLOCK, CPLD_BLOCK, TSE_BLOCK, CLOCK_DISTRIBUTION, POWER_BLOCK and SYSTEM_INTERFACE. 8.2 TSE Block Sheets 2,3,4 Signalling for the TSE device is simple and no additional components are used for termination for LVDS - all pairs are internally differentially terminated with 100. Care must be taken to ensure uninterrupted impedance while routing to the HS3 connector when routing the 128 LVDS paired lines to the connector. All 1.8V supplies for the TSE device require 5% tolerance, while 3.3V supplies have 10% tolerance. Decoupling capacitors of 0.1F are used for VDDO[1..36] pins at the four corners of the TSE device. Decoupling capacitors of 0.1F are distributed around the device for all other supply pins. All decoupling capacitors should be positioned as close to the pins as possible to reduce series inductance. Reference resistors of 3.16 k 1% are required for TSE analog stages on the RES and RESK pins. The JTAG port and the analog test buses are not accessed. TRSTB shares the device reset RSTB. 8.3 CPLD Block Buffers have been added for additional current drive for high edge rates of SYSCLK_TSE and FP. Buffers are also present on xCMP and RWSEL to provide for the multidropped loads. To drive the 20mA LEDs, a 74HC244 device is used. Programming of the XC9572XL device is provided for with the header connection to its JTAG port. VCCIO and VCCINT are both connected to 3.3V and have been decoupled according to the manufacturers recommendations with 0.01F and 0.1F. Decoupling capacitors should be positioned as close to the pins as possible to reduce trace inductance. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 25 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN A 49.9 series termination resistor is used on the FP output of the 74ALVC125 device to control the effects of fast rise/fall times. The small output resistance of the CMOS driver and the terminating resistor should match the 50 line and matching HS-3 connector. The extra connection after the terminating resistor adds to the load capacitance applied to the line beyond the backplane. xCMP and RWSEL are relatively slow moving signals and their traces do not act like transmission lines. A 56 series termination resistor is used on the SYSCLK_TSE line to match the 65 traces used for on-board signalling. 8.3.1 VHDL Programming Code The programming file for the Xilinx XC9572XL was designed using Xilinx WebPack tools in VHDL. Standard libraries provided with the software were used. 8.4 Clock Block SYSCLK (77.76 MHz) is distributed using differential PECL signaling to minimize jitter and to maximize noise immunity. As well, backplane noise contributions are reduced with less signal swing compared to a TTL signal. This is accomplished using a 1:5 differential PECL clock driver. Four pairs continue to the backplane and one pair is used as a possible clock source (SYSCLK_IN1) for the TSE device. The second 100LVEL14 device is optional and provides an additional five SYSCLK PECL pairs for a total of nine connecting to the backplane. The scan clock (SCLK) input of the device is left open and ignored with SEL set low. The FCT3807 device is used to distribute the additional SYSCLK_TTL to the CPLD and uses a 49.9 series termination resistor at the driver. Series termination resistors outputs are used at the PECL-to-TTL converter outputs also. Decoupling capacitors accompany the power pins of each device and should be positioned close to the pin to reduce trace inductance. Termination is required for each differential PECL signal on the destination board, and all PECL lines have been made 50 . 8.4.1 PECL Termination SYSCLK<9..1> differential PECL pairs require termination resistors. Since a 50 ohm backplane and the HS-3 connector is a controlled 50 a 100 ohm differential impedance results between the PECL pairs. A 100 ohm resistor PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 26 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN should be used at the clock receiver as close to the pins as allowed. Also, a bias resistor, Rpd, is required at the output for all PECL signals. Figure 13 - PECL Termination for Clock Distribution Differential PECL Transmitter Re Re Rt Differential PECL Receiver Re = 237 ohms Rt = 100 ohms 8.5 System Interface As maximum signal density within the HS3 is required, optimal noise pin assignments could not be used. TTL switching signals like FP have been isolated from the LVDS signals to reduce single mode coupling. The pin assignments have followed a similar pattern to the TSE device with groupings of four pairs together. Only LVDS signals are located in Rows G,H, J and K so a six row connector can be used optionally. Table 4 A J4 TN1 1 - Pinout of Backplane Connection (J4,J5,J6) B C D E F G H J K TP1 TN7 TP7 RN9 RP9 RN15 RP15 TN21 TP21 TN2 2 TP2 TN8 TP8 RN10 RP10 RN16 RP16 TN22 TP22 TN3 3 TP3 RN5 RP5 RN11 RP11 TN17 TP17 TN23 TP23 TN4 4 TP4 RN6 RP6 RN12 RP12 TN18 TP18 TN24 TP24 RN1 5 RP1 RN7 RP7 TN13 TP13 TN19 TP19 RN21 RP21 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 27 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN RN2 6 RP2 RN8 RP8 TN14 TP14 TN20 TP20 RN22 RP22 RN3 7 RP3 TN9 TP9 TN15 TP15 RN17 RP17 RN23 RP23 RN4 8 RP4 TN10 TP10 TN16 TP16 RN18 RP18 RN24 RP24 TN5 9 TP5 TN11 TP11 RN13 RP13 RN19 RP19 TN25 TP25 TN6 10 TP6 TN12 TP12 RN14 RP14 RN20 RP20 TN26 TP26 J5 A B C D E F G H J K TN27 1 TP27 TN33 TP33 RN33 RP33 RN39 RP39 TN47 TP47 TN28 2 TP28 TN34 TP34 RN34 RP34 RN40 RP40 TN48 TP48 TN29 3 TP29 RN29 RP29 RN35 RP35 TN43 TP43 TN49 TP49 TN30 4 TP30 RN30 RP30 RN36 RP36 TN44 TP44 TN50 TP50 RN25 5 RP25 RN31 RP31 TN39 TP39 TN45 TP45 RN45 RP45 RN26 6 RP26 RN32 RP32 TN40 TP40 TN46 TP46 RN46 RP46 RN27 7 RP27 TN35 TP35 TN41 TP41 RN41 RP41 RN47 RP47 RN28 8 RP28 TN36 TP36 TN42 TP42 RN42 RP42 RN48 RP48 TN31 9 TP31 TN37 TP37 RN37 RP37 RN43 RP43 RN49 RP49 TN32 10 TP32 TN38 TP38 RN38 RP38 RN44 RP44 RN50 RP50 J6 A B C D E F G H J K TN51 1 TP51 RN51 RP51 TN55 TP55 RN55 RP55 RN59 RP59 TN52 2 TP52 RN52 RP52 TN56 TP56 RN56 RP56 RN60 RP60 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 28 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN TN53 3 TP53 RN53 RP53 TN57 TP57 RN57 RP57 TN63 TP63 TN54 4 TP54 RN54 RP54 TN58 TP58 RN58 RP58 TN64 TP64 SYSCLK 5 N1 SYSCLK 6 N2 SYSCLK 7 N3 SYSCLK 8 N4 GND 9 SYSCLK P1 SYSCLK P2 SYSCLK P3 SYSCLK P4 RWSEL SYSCLK N5 SYSCLK N6 SYSCLK N7 GND SYSCLK P5 SYSCLK P6 SYSCLK P7 GND SYSCLK N8 SYSCLK N9 SYSCLK N_IN GND SYSCLK P8 SYSCLK P9 SYSCLK P_IN FP_IN TN59 TP59 RN61 RP61 TN60 TP60 RN62 RP62 TN61 TP61 RN63 RP63 TN62 TP62 RN64 RP64 xCMP FP1 FP2 FP3 GND GND GND GND GND 10 TJOFP SDEN SDENO UT ACTIVE FP4 GND GND GND GND 8.6 Compact PCI Block 8.6.1 Layout Considerations The Compact PCI specification outlines a number of layout requirements for the cPCI design. These include: * * * * * All 10 ohm stub termination resistors must be placed within 0.6" of the J1 pins. All PCI signal traces must be less than 1.5" except P_CLK. P_CLK trace must be 2.5" +/- 0.1" CPCI bus traces impedance is 65 . 39 ohm stub resistor on REQ# should be placed near its source on the PCI9054. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 29 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 8.7 Power Block All 3.3V power requirements for the board are sourced directly from the hot swap control circuitry. The 3.3V requirements are minimal for the TSE device, but all non-PMC devices use the 3.3V supply. A switching regulator module is used to provide the 1.8V supply at high efficiency for digital pins of the TSE device. A 182 resistor on its output draws a stabilizing 10 mA current in all conditions. An additional 1.8V supply using a linear regular has been created for the 1.8V analog pins of the TSE device. To minimize power consumption the regulator uses the 3.3V rail. The output voltage of the 1.8V linear regulator is set by the following formula: VOUT = VREF (1 + R2/R1) + IadjR2 . PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 30 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 9 SCHEMATICS PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 31 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 10 BILL OF MATERIALS Table 5 - Bill of Materials Part Number Ref Des D7 U14 NO. 1 2 Part Name Value Description Qty 1 1 1N4148 74ALVC125_SOIC14 IDT74ALVC125DC -BAS E-VCC=3.3V AMP_HS3_10X10_F 97-8159-07 EMALE _RA-BASE CAPACITOR-0.01UF, DIGIKEY 50V, X7R_603 PCC103BVCT-ND 3 J2, J4, J5 IC 3V3 CMOS QUAD BUS BUFFER GATE W/ 3STATE OUTPUTS Z-PACK 10 ROW RA HS3 BACKPLANE FEMALE CONNECTOR 3 4 5 6 7 8 9 10 11 12 13 14 C74, C81, C83, C85, C87, C89, C91, C93 CAPACITOR-0.1UF, PANASONIC -- ECJ- C26-C73, 16V, X7R_603 1VB1C104K C75-C80, C82, C84, C86, C88, C90, C92, C97-C101 CAPACITOR-100UF, DIGI-KEY -- P1211- C96 10V, ELECTRO ND CAPACITOR-10UF, DIGI-KEY -C95 16V, TANT TEH PCT3106CT-ND CAPS-0.01UF, 50V, ECU-V1H103KBV C7, C19 X7R_603 CAPS-0.047UF, 50V, ECU-V1H473KBW C8 X7R_1206 CAPS-0.1UF, 16V, ECJ-1VB1C104K C9, C12X7R_603 C17 CAPS-0.1UF, 50V, ECU-V1H104KBW C5, C6, X7R_1206 C10, C11, C18, C20 CAPS-10UF, 16V, ECS-H1CC106R C23, C25 TANCAPC CAPS-10UF, 25V, ECS-H1ED106R C21, C22, TANCAPD C24, C94 CAPS-2.2UF, 35V, ECS-H1VC225R C2, C3 TANCAPC 8 MULTILAYER CERAMIC CHIP CAPACITOR X7R 0603 0.1UF 16V 65 PANASONIC HFS RADIAL AL. PANASONIC TEH TANT. CAP. CAP CERAMIC X7R 0603 50V 0.01UF CAP CERAMIC X7R 1206 50V 0.047UF CAP CERAMIC X7R 0603 16V 0.1UF CAP CERAMIC X7R 1206 50V 0.1UF CAP TANCAPC 16V 20% 10UF CAP TANCAPD 25V 20% 10UF CAP TANCAPC 35V 20% 2.2UF 1 1 2 1 7 6 2 4 2 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 32 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 15 16 CAPS-220UF, 50V, ECE-A1HFS221 ELECTRO HFS CON_MICTOR_38PI 2-767004-2 N_2-7 67004-2-BAA C1, C4 J7, J8 17 18 CPCI_ESD_STRIP_B PART OF PCB OTTO M_EDGEBASE HEADER6_100MIL- PZC36SAAN BASE HEADER_3A_100 MIL-BASE HEADER_4X2_SMT_ 2MM-B ASE IRF7413 LED-CLEAR GREEN, LED_5MM VERT PA P1 J10 19 20 21 22 DIGI-KEY S1011-36- J9 ND 87267-0850 J3 CAP ELECTRO VA SMD 50V 20% 220UF 38 PIN SIGNAL CONNECTOR, MATCHED IMPEDANCE, 0.025, SMD COMPACT PCI ESD STRIP, CREATE ON PCB LAYOUT CONN HEADER STRAIGHT 36POS MALE .1" SINGLE ROW 100 MIL SPACING HEADER HEADER 2X4 SMT 2MM MALE 2 2 1 1 1 1 2 4 23 24 25 26 27 28 29 30 Q1, Q2 D2-D4, D6 T-1 3/4 LED CLEAR GREEN VERTICAL PCB MOUNT LED-YELLOW, PCB DIGI-KEY -- L20367- D8 .29" TALL RIGHT .29 RIGHT ANGLE ND ANGLE PCB MOUNT LT1084CM_SMT_RE LT1084CM U19 5.0A LOW DROPOUT G-BAS E POSITIVE ADJUSTABLE REGULATORS LT1117_SOT-ADJ LT1117CST U5 ADJUSTABLE REGULATOR LTC1643L_SSOPLTC1643LCGN U2 CPCI HOT SWAP BASE CONTROLLER MAX811T_SOT143- MAX811T U16 4 PIN UP VOLTAGE BASE MONITOR WITH MANUAL RESET INPUT 3.08V SOT143 MAX812R_SOT143- MAX812R U3 4 PIN UP VOLTAGE BASE MONITOR WITH MANUAL RESET INPUT 2.63V SOT143 MB3100H-77.76MHZ, MB3100H-77.76MHZ Y1 OSC HCMOS/TTL HALF 100PPM SIZE 8 PIN 77.76MHZ 100PPM MC100LVEL14_SOIC MC100LVEL14DW U10, U11 IC LOW SKEW 1:5 -BAS E CLOCK DISTRIBUTION CHIP SO20WB DIGIKEY -- LT1132ND 1 1 1 1 1 1 1 2 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 33 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 31 MC100LVELT22D_S MC100LVELT22D OIC8- BASE U9 32 MC100LVELT23D_S MC100LVELT23D OIC8- BASE U12 33 MC74HC244ADW_S MC74HC244ADW O20WB- BASEVCC=3A U18 34 35 MOUNTING_HOLE_ MOUNTING HOLE 150MIL -BASE NM93CS46_DIP8_S NM93CS46EN OCKET -BASE PBNO_VERT_6MMBASE PCI9054_PQFPBASE PI49FCT3805_QSOP 20-S PEED GRADEA RES-0, 5%, 603 RES-1.2K, 5%, 603 RES-10, 5%, 603 RES-100, 1%, 603 RES-100K, 5%, 603 RES-10M, 5%, 805 RES-130, 1%, 603 RES-182, 1%, 603 RES-2.0K, 5%, 603 RES-200, 5%, 603 M1 U1 36 37 38 DIGIKEY -- P8009S- SW1 ND PCI9054-AA50PI U4 PI49FCT3805CQ20 U8, U13 IC DUAL DIFFERENTIAL LVPECL TO TTL TRANSLATOR SOIC8 IC DUAL DIFFERENTIAL LVPECL TO TTL TRANSLATOR SOIC8 IC OCTAL 3-STATE NONINVERTING BUFFER/LINE DRIVER/LINE RECEIVER SO20WB MOUNTING HOLE .150" DIA 1K-BIT SER EEPROM W/ DATA PROTECT AND SEQ READ DIP8 VERT PCB MOUNT SPST PUSH BUTTOM PCI I/O ACCELERATOR IC 3.3V 2X1:5 CMOS CLOCK DRIVER QSOP20 RES 0603 1/16W 5% ZERO OHM RES 0603 1/16W 5% 1.2K OHM RES 0603 1/16W 5% 10 OHM RES 0603 1/16W 1% 100 OHM RES 0603 1/16W 5% 100K OHM RES 0805 1/10W 5% 10M OHM RES 0603 1/16W 1% 130 OHM RES 0603 1/16W 1% 182 OHM RES 0603 1/16W 5% 2.0K OHM RES 0603 1/16W 5% 200 OHM 1 1 1 1 1 1 1 2 39 40 41 42 43 44 45 46 47 48 ERJ-3GSY0R00V ERJ-3GSYJ122V ERJ-3GSYJ100V ERJ-3EKF1000V ERJ-3GSYJ104V ERJ=6GEYJ106V ERJ-3EKF1300V ERJ-3EKF1820V ERJ-3GSYJ202V ERJ-3GSYJ201V R31 R2 R6, R8 R9 R24 R26-R28 R22 R1 R3, R4 R10-R13 1 1 2 1 1 3 1 1 2 4 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 34 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 49 50 51 52 53 54 55 56 57 58 59 RES-24, 5%, 805 RES-270, 5%, 603 RES-39.2, 1%, 805 ERJ-6GEYJ240V ERJ-3GSYJ271V ERJ-6ENF39R2V R21 R25 R16 R14, R17R20 R7, R29, R48 R23 R15 R5 R44, R45, R56, R57 R50 R38-R41, R52-R55, R58-R73 R32-R35 R36 R42, R43 R30 R37, R46, R47, R51, R74-R76 R49 RN7-RN14, RN17RN21 RN22RN34 RN36 RES-4.75K, 1%, 603 ERJ-3EKF4751V RES-4.7K, 5%, 603 RES-47.5, 1%, 805 RESISTOR-.01, 1%, 1206 RESISTOR-0.005, 5%, 603 RESISTOR-100, 1%, 603 RESISTOR-100, 1%, 805 RESISTOR-237, 1%, 603 RESISTOR-3.16K, 1%, 805 RESISTOR-3.3, 1%, 805 RESISTOR-4.7K, 5%, 603 RESISTOR-44.2, 1%, 805 RESISTOR-49.9, 1%, 603 RESISTOR-56.2, 1%, 805 RES_ARRAY_4_SM D-10 ERJ-3GSYJ472V ERJ-6ENF47R5V IRC-TT LRCLR1206-01-R01 0-F RES 0805 1/10W OHM RES 0603 1/16W 270 OHM RES 0805 1/10W 39.2 OHM RES 0603 1/16W 4.75K OHM RES 0603 1/16W 4.7K OHM RES 0805 1/10W 47.5 OHM 5% 24 5% 1% 1% 5% 1% 1 1 1 5 3 1 1 1 4 1 24 DIGI-KEY -P 60 61 62 63 64 4 1 2 1 7 65 66 67 68 DIGI-KEY -P 1 13 13 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 35 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN 69 70 71 72 73 74 75 76 77 78 79 ND RES_ARRAY_4_SM DIGI-KEY -D-1K Y4 RN6, RN15 2 RN1-RN5, RN16, RN35 U17 D5 TP7, TP8 TP3-TP6, TP9-TP18 U6, U7 TP1, TP2 U15 D1 J1 7 NON-ISOLATED BUCK CONVERTER QUAD GREEN LED. TEST POINT THRUHOLE PAD50CIR32D TEST POINT THRUHOLE PAD60CIR36D 1 1 2 14 2 2 CPLD 3.3V 10NS 1 1 CONNECTOR ZPACK CPCI 2MM HM 110 POS. TYPE A WITH GND SHIELD 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 36 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN NOTES PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 37 PRELIMINARY REFERENCE DESIGN PMC-1991247 ISSUE 1 PM5372 TSE REFERENCE DESIGN CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com Document Information: Corporate Information: Application Information: Web Site: None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2000 PMC-Sierra, Inc. PMC-991247 (P1) ref PMC-990713 (P3) Issue date: March 2000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE |
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