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| PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN PM73121 AAL1GATOR II REFERENCE DESIGN ISSUE 3 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE i PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN CONTENTS 1 2 3 FEATURES ............................................................................................... 1 OVERVIEW............................................................................................... 2 DEVELOPMENT DESCRIPTION ............................................................. 4 3.1 3.2 4 COMET VERSION OF REFERENCE DESIGN ............................. 4 TQUAD/EQUAD VERSION OF REFERENCE DESIGN ................ 6 HIGH LEVEL DESIGN.............................................................................. 8 4.1 AAL1GATOR II PLUS COMET DESIGN ........................................ 8 4.1.1 MICROPROCESSOR AND MEMORY SYSTEM INTERFACE ...................................................................... 11 4.1.2 FIELD PROGRAMMABLE GATE ARRAY (FPGA) ............ 18 4.1.3 CLOCK AND POWER SUPPLY CIRCUITRY .................... 22 4.1.4 UTOPIA INTERFACE ........................................................ 22 4.1.5 ADDITIONAL CONNECTIONS ......................................... 24 4.1.6 LINE INTERFACE ............................................................. 26 4.1.7 ADDITIONAL COMET CONNECTIONS ........................... 26 4.1.8 COMET CONFIGURATION............................................... 29 4.1.9 AAL1GATOR II CONFIGURATION.................................... 29 4.1.10 THE JTAG PORT............................................................... 29 4.2 AAL1GATOR II PLUS TQUAD/EQUAD DESIGN ......................... 30 4.2.1 MICROPROCESSOR AND MEMORY SYSTEM INTERFACE ...................................................................... 30 4.2.2 LINE SIDE INTERFACE TO THE AAL1GATOR II.............. 30 4.2.3 LINE INTERFACE ............................................................. 30 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE ii PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 4.2.4 ADDITIONAL CONNECTIONS FOR THE TQUAD DEVICE .......................................................................................... 34 4.2.5 TQUAD/EQUAD CONFIGURATION.................................. 35 5 6 MEMORY MAP AND REGISTER DEFINITIONS ................................... 36 SOFTWARE CONFIGURATION............................................................. 39 6.1 6.2 6.3 6.4 7 AAL1GATOR II CONFIGURATION............................................... 39 COMET CONFIGURATION ......................................................... 43 TQUAD/EQUAD CONFIGURATION............................................. 45 FPGA CONFIGURATION............................................................. 45 IMPLEMENTATION DESCRIPTION ....................................................... 46 7.1 COMET VERSION SCHEMATICS ............................................... 46 7.1.1 ROOT DRAWING, SHEET 1 ............................................. 46 7.1.2 COMET BLOCK, SHEETS 2-9.......................................... 46 7.1.3 LINE INTERFACE, SHEETS 10-13................................... 46 7.1.4 FPGA BLOCK, SHEET 14 ................................................ 46 7.1.5 MEMORY SYSTEM BLOCK, SHEET 15 .......................... 46 7.1.6 AAL1GATOR II BLOCK, SHEET 16 .................................. 47 7.1.7 MICRO INTERFACE, SHEET 17....................................... 47 7.2 TQUAD VERSION SCHEMATICS................................................ 47 7.2.1 ROOT DRAWING, SHEET 1 ............................................. 47 7.2.2 TQUAD/EQUAD BLOCK, SHEETS 2,3............................. 47 7.2.3 AAL1GATOR II BLOCK, SHEET 4 .................................... 47 7.2.4 FPGA BLOCK, SHEET 5 .................................................. 47 7.2.5 MEMORY SYSTEM BLOCK, SHEET 6 ............................ 48 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE iii PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 7.2.6 MICRO INTERFACE BLOCK, SHEET 7 ........................... 48 7.2.7 LIU INTERFACE BLOCK, SHEET 8.................................. 48 8 9 10 11 12 13 14 15 16 MODULARIZATION ISSUES .................................................................. 49 REFERENCES ....................................................................................... 55 APPENDIX A: BILL OF MATERIALS (COMET VERSION) ..................... 56 APPENDIX B: BILL OF MATERIALS (TQUAD/EQUAD VERSION) ........ 60 APPENDIX C: AAL1GATOR II PLUS COMET SCHEMATIC DIAGRAM. 62 APPENDIX D: SCHEMATIC DIAGRAM (TQUAD/EQUAD VERSION) .... 63 APPENDIX E: SAMPLE VHDL CODE .................................................... 64 DISCLAIMER.......................................................................................... 85 NOTES ................................................................................................... 86 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE iv PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN LIST OF FIGURES FIGURE 1. SYSTEM CONFIGURATION OPTIONS WITH AAL1GATOR II. ....... 2 FIGURE 2. COMET/AAL1GATOR II BLOCK DIAGRAM. .................................... 4 FIGURE 3. THE COVERAGE OF THE COMET REFERENCE DESIGN. 5 FIGURE 4. TQUAD/EQUAD TO AAL1GATOR II BLOCK DIAGRAM................... 6 FIGURE 5. COVERAGE OF THE TQUAD/EQUAD REFERENCE DESIGN. ...... 7 FIGURE 6. AAL1GATOR II TO COMET HIGH LEVEL DESIGN. ........................ 9 FIGURE 7. GLUELESS AAL1GATOR II TO COMET INTERCONNECTION..... 10 FIGURE 8. BLOCK DIAGRAM OF MICROPROCESSOR INTERFACE. .......... 11 FIGURE 9. AAL1GATOR II CONNECTIONS TO MICROPROCESSOR. .......... 14 FIGURE 10.COMET INTERFACE TO MICROPROCESSOR............................ 16 FIGURE 11.TERMINATION OF TL_CLK SIGNAL............................................. 19 FIGURE 12.TL_CLK SWITCHING TERMINATION OPTION............................. 20 FIGURE 13.INTERNAL FPGA CIRCUITRY....................................................... 23 FIGURE 14. AAL1GATOR II PLUS TQUAD/EQUAD HIGH LEVEL DESIGN. ... 33 FIGURE 15.FLOWCHART FOR CONFIGURING THE AAL1GATOR II............. 40 FIGURE 16.AAL1GATOR II BOARD.................................................................. 50 FIGURE 17.COMET BOARD. ........................................................................... 51 FIGURE 18.TQUAD BOARD. ............................................................................ 52 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE v PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN LIST OF TABLES TABLE 1. TABLE 2. AAL1GATOR II TO COMET INTERCONNECTIONS. ....................... 8 MICROPROCESSOR INTERFACE PIN ASSIGNMENT. ................ 12 TABLE 3. ADDITIONAL AAL1GATOR II TO MICROPROCESSOR CONNECTIONS. ............................................................................................... 15 TABLE 4. TABLE 5. TABLE 6. TABLE 7. TABLE 8. TABLE 9. ADDRESS RANGES OF THE COMET DEVICES.......................... 17 TL_CLK OPTIONS. ........................................................................ 18 ADDITIONAL CONNECTIONS TO AAL1GATOR II. ....................... 24 ADDITIONAL CONNECTIONS TO THE COMET DEVICE. ............ 26 LINE INTERFACE UNIT CONNECTIONS...................................... 31 ADDITIONAL TQUAD DEVICE CONNECTIONS. .......................... 34 TABLE 10. AAL1GATOR II REFERENCE DESIGN MEMORY MAP ................ 36 . TABLE 11. SOURCE_SELECT REGISTER (400000H). .................................. 36 TABLE 12. N_CLK_SOURCE REGISTER (400001H). .................................... 37 TABLE 13. XCLK_SELECT REGISTER (400002H). ........................................ 37 TABLE 14. TL_CLK OPTIONS FOR THE AAL1GATOR II. ............................... 41 TABLE 15. SUMMARY OF MINIMUM AAL1GATOR II LINE CONFIGURATIONS.42 TABLE 16. SUMMARY OF THE MINIMUM COMET DEVICE CONFIGURATIONS. ......................................................................................... 44 TABLE 17. SUMMARY OF FPGA CONFIGURATIONS. ................................... 45 TABLE 18. AAL1GATOR II TO FRAMER INTERFACE. .................................... 53 TABLE 19. COMET VERSION BILL OF MATERIALS....................................... 56 TABLE 20. TQUAD/EQUAD VERSION BILL OF MATERIALS.......................... 60 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE vi PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 1 FEATURES * * * * * * * * * * * Implementation strategy for AAL1gator II in a Multi Service Access Concentrator environment using the PM4351 COMET. Implementation strategy for AAL1gator II in a Multi Service Access Concentrator environment using the PM4344 TQUAD or PM6344 EQUAD. Implementation strategy for AAL1gator II in a DS3 system. Complete implementation of 8 link Circuit Emulation Service. Supports structured and unstructured (both with and without CAS) CES for T1/E1 links. Supports independently clocked links. Microprocessor interface for configuration and monitoring. Allows 8 T1/E1 lines (1.544 Mbit/s/2.048 Mbit/s) to be serviced. Supports enabling/disabling of Synchronous Residual Time Stamp (SRTS) clocking. Modular design Includes a software driven clock multiplexer to allow customers to select one of several possible TL_CLK sources. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 2 OVERVIEW This document describes the hardware and software configuration required for the PM73121 AAL1gator II Reference Design. This will be a paper only reference design, intended to assist customers in their efforts to build a Circuit Emulation Service (CES) card. The purpose of a CES card is to emulate circuit oriented transmission technology characteristics in order to support Constant Bit Rate (CBR) traffic. One example of CBR traffic is time sensitive voice applications. The purpose of the AAL1gator II is to provide T1/E1, or DS3/E3/J2 line interfaces access to an AAL1 CBR ATM network. Figure 1 below indicates the ways in which an AAL1gator II can be used to connect to T1/E1 or DS3/E3/J2 line interfaces. Not shown is the interface to the UTOPIA bus, and associated routing tables, and switching elements. UTOPIA INTERFACE PM73121 AAL1gator Structured or Unstructured T1/E1 Unstructured DS3/E3/J2 TDM Switch DS3/E3/J2 FRAMER (S/UNI QJET) T1/E1 Framer (TQUAD/EQUAD) T1/E1 Framer (COMET) T1/E1 LIU (QDSX) DS3 LIU D3MX DS3/E3/J2 LIU LINE INTERFACE Figure 1. System Configuration options with AAL1gator II. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 2 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN The AAL1gator II is capable of supporting eight data streams, where a single data stream cannot exceed 15 Mbit/s and the aggregate total cannot exceed 20 Mbit/s , or one data stream which can support up to 45 Mbit/s. The reference design will consist of two separate AAL1gator II implementations: 1. AAL1gator II with 8 COMET'S 2. AAL1gator II with 2 TQUAD's or EQUAD's The first implementation will target the Multi Service Access Concentrator market, while the second will provide a building block for using the AAL1gator II in a DS3 application. The reference design will further support a modularized implementation, should the need arise in the future to build prototypes based on the design. A modular implementation was chosen to allow either a board consisting of 8 COMET devices or 2 TQUAD/EQUAD devices to be connected over a common interface to a main board consisting of a single AAL1gator II along with associated memory and microprocessor interface. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 3 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 3 3.1 DEVELOPMENT DESCRIPTION COMET Version of Reference Design Figure 2 illustrates the block diagram of the PM73121 Reference Design using 8 COMET devices. The hardware allows full access to the AAL1gator II device via the microprocessor interface. Each COMET device acts as a line interface unit with an integrated long haul LIU, and T1/E1 framer/deframer. In the receive path (from T1 or E1 line), the COMET converts the incoming line data (in the form of channels) to a serial bit stream. The AAL1gator II then receives this data (and clocking information) from the COMET, and builds ATM cells to be sent to the UTOPIA bus. In the transmit path (to T1 or E1 line), the AAL1gator II receives ATM cells from the UTOPIA bus. The AAL1gator II retrieves the data and signaling information, and places the data to be transmitted over the T1 (or E1) line (via the COMET) in the appropriate port and time slot. 8 T1 or E1 Lines COMET Clock and Data Lines MEMORY SYSTEM AND DECODE LOGIC MICROPROCESSOR INTERFACE Figure 2. COMET/AAL1gator II Block Diagram. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 4 UTOPIA BUS text text text text text text PM4351 text PM73121 AAL1gator II PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN UTOPIA INTERFACE PM73121 AAL1gator Structured or Unstructured T1/E1 Unstructured DS3/E3/J2 TDM Switch DS3/E3/J2 FRAMER (S/UNI QJET) T1/E1 Framer (TQUAD/EQUAD) T1/E1 Framer (COMET) T1/E1 LIU (QDSX) DS3 LIU D3MX DS3/E3/J2 LIU LINE INTERFACE Figure 3. The coverage of the COMET reference design. With reference to Figure 1, Figure 3 shows how a T1 or E1 line can be interfaced to an ATM network via the UTOPIA bus by using the COMET and AAL1gator II devices. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 5 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 3.2 TQUAD/EQUAD Version of Reference Design Figure 4 illustrates the AAL1gator II in an application involving the use of 2 TQUAD (or the pin compatible EQUAD) devices. This design could form a building block for the use of AAL1gator II in a DS3 system. The operation is similar to that of Figure 2. Line Interface Clock and Data Lines MEMORY SYSTEM AND DECODE LOGIC MICROPROCESSOR INTERFACE Figure 4. TQUAD/EQUAD to AAL1gator II Block Diagram. With reference to Figure 1, Figure 5 illustrates the coverage of the TQUAD/EQUAD design. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 6 UTOPIA BUS PM4314 QDSX or PM4314 PM8313 QDSX D3MX Clock and Data Lines PM4344 TQUAD or PM6344 EQUAD PM73121 AAL1gator II PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN UTOPIA INTERFACE PM73121 AAL1gator Structured or Unstructured T1/E1 Unstructured DS3/E3/J2 TDM Switch DS3/E3/J2 FRAMER (S/UNI QJET) T1/E1 Framer (TQUAD/EQUAD) T1/E1 Framer (COMET) T1/E1 LIU (QDSX) DS3 LIU D3MX DS3/E3/J2 LIU LINE INTERFACE Figure 5. Coverage of the TQUAD/EQUAD reference design. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 7 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 4 4.1 HIGH LEVEL DESIGN AAL1gator II plus COMET Design Figure 6 on the following page represents the high level design of the AAL1gator II plus COMET reference design. As can be seen, the design contains the following functional blocks: 1. AAL1gator II Integrated Circuit 2. 8 COMET Devices 3. Microprocessor and Memory System Interface 4. Field Programmable Gate Array 5. Clock Sources 6. UTOPIA Interface 7. Line Interface The AAL1gator II communicates with the COMET devices via the framer bus signals listed in Table 1. As noted in Figure 9, one bit of each signal group connects to its associated COMET device. For instance, TL_FSYNC(0) connects to COMET0, while TL_FSYNC(1) connects to COMET1. Table 1. SIGNAL TL_FSYNC(7..0) AAL1gator II to COMET Interconnections. DESCRIPTION The FPGA generates this signal for both the AAL1gator II and COMET. In T1 mode, this signal consists of a pulse once every 193 bit periods. This is a clock signal at the transmit line rate. Its source is determined by the configuration of the FPGA. Receive line clock at either 1.544 MHz or 2.048 MHz, derived from the recovered line rate timing. Carries receive frame synchronization from the COMET devices. Carries the CAS signaling information from the COMET devices. Carries the receive data from the COMET devices. Carries the CAS signaling outputs to the COMET devices. Carries the serial data to the COMET devices. TL_CLK(7..0) RL_CLK(7..0) RL_FSYNC(7..0) RL_SIG(7..0) RL_SER(7..0) TL_SIG(7..0) TL_SER(7..0) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 8 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN LINE INTERFACE COMET 0 COMET 1 COMET 2 COMET 3 COMET 4 COMET 5 COMET 6 COMET 7 FRAMER BUS MICROPROCESSOR BUS One bit of these signals go to their respective COMET device via the FRAMER BUS. For example, BTFP(0) connects to COMET0 BRPCM(7:0) BRCLK(7:0) BTCLK(7:0) BRSIG(7:0) BRFP(7:0) BTSIG(7:0) TL_SIG(7:0) BTFP(7:0) TIMING SOURCES CONTROL BUS ADDRESS BUS DATA BUS FPGA SRTS_DOUT(3:0) TL_FSYNC(7:0)/ TL_MSYNC(7:0) TL_CLK(7:0) RL_CLK(7:0) RL_FSYNC(7:0) RL_SER(7:0) RL_SIG(7:0) DATA BUS DATA BUS ADDRESS BUS CONTROL BUS ADDRESS BUS CONTROL BUS AAL1gator II MICROPROCESSOR INTERFACE UTOPIA INTERFACE UTOPIA BUS Figure 6. AAL1gator II to COMET High Level Design. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE SRTS_LINE(3:0) ADAP_STRB 9 TL_SER(7:0) N_CLK MICROPROCESSOR AND MEMORY SYSTEM BTPCM(7:0) PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN In Figure 6, the FPGA is shown with a dotted line. This is because it is possible to directly connect the AAL1gator II to the COMET device as illustrated in Figure 7. In this way, it is possible to align signaling bits to the multiframe boundary. COMET BTCLK BTSIG BTFP TL_FYSNC TL_MYSNC OPTIONAL EXTERNAL CLOCK SOURCE (ADAPTIVE CLOCK RECOVERY) TL_CLK AAL1gator II Figure 7. Glueless AAL1gator II to COMET interconnection. Using the approach of Figure 7, the FPGA depicted in Figure 6 is no longer necessary. The main purpose of the FPGA is to provide maximum clock distribution flexibility by allowing for independently clocked links. Using the FPGA , it is possible to use Adaptive Clock Recovery for the generation of TL_CLK (AAL1gator II) and BTCLK (COMET). In addition, the FPGA generates an appropriate signal for N_CLK (at 2.43 MHz), and also distributes XCLK signals to the 8 COMET devices from only two clock oscillators (1.544 MHz and 2.048 MHz). Therefore, without the FPGA, some other method will have to be found to generate a 2.42 MHz signal for N_CLK (if SRTS is in use) and to distribute XCLK signals to the COMET devices. Please see section 4.1.2 for further discussion of the FPGA. The other difference between the two drawings is that in Figure 7, both TL_FSYNC and TL_MSYNC of the AAL1gator II connects to the COMET BTFP pin (configured as an output), rather than just TL_FSYNC. As mentioned above, this allows for alignment of signaling bits on multiframe boundaries. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE TL_SIG 10 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 4.1.1 Microprocessor and Memory System Interface The interface between the system microprocessor can be divided into two sections. The first section interfaces the system microprocessor to the AAL1gator II, while the second section interfaces the system microprocessor to the COMET devices and the FPGA. The following figure (Figure 8) represents a high level view the microprocessor interface. AAL1gator II COMET DEVICES FPGA COMET/FPGA ADDRESS BUS COMET/FPGA CONTROL BUS COMET/FPGA CONTROL BUS SRAM DECODER DATA TRANSCEIVER ADDRESS BUFFER DATA TRANSCEIVER ADDRESS BUFFER AAL1gator II CONTROL BUS COMET/FPGA CONTROL BUS ADDRESS BUS DATA BUS MICROPROCESSOR INTERFACE Figure 8. Block Diagram of microprocessor interface. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 11 COMET/FPGA ADDRESS BUS AAL1gator II ADDRESS BUS SRAM CONTROL BUS AAL1gator II CONTROL BUS AAL1gator II DATA BUS COMET/FPGA DATA BUS COMET/FPGA DATA BUS PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN In order to provide maximum system implementation flexibility, a particular microprocessor has not been specified. However, in order to implement the microprocessor and memory system as shown in this document, the system microprocessor must have the following capabilities: 1. 2. 3. 4. Minimum 22 bit address bus Minimum 16 bit data bus Minimum 3 programmable chip selects Minimum 2 independent interrupt request lines An example of a device that meets these minimum requirements is the Motorola MC68330 microprocessor. Another scenario would see the design implemented in a PCI or compact PCI system. Table 2 lists the pin assignment of a potential microprocessor interface (96 pin DIN). Note that this interface includes all connections from the microprocessor to the AAL1gator II, COMET devices, and FPGA. Table 2. PIN NAME D(15) D(14) D(13) D(12) D(11) D(10) D(9) D(8) D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0) A(21) A(20) A(19) A(18) A(17) Microprocessor Interface Pin Assignment. PIN TYPE I/O PIN NUMBER A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 C11 C12 C13 C14 C15 FUNCTION 16 bit data bus Input (from uP) 22 bit address bus PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 12 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN PIN NAME A(16) A(15) A(14) A(13) A(12) A(11) A(10) A(9) A(8) A(7) A(6) A(5) A(4) A(3) A(2) A(1) A(0) RDB WRB PROC_ACK IRQ1B IRQ2B RESETB CS1B CS2B CS3B HOLDOFF GND PIN TYPE Input Input Input Output (to uP) Output Input Input Input Input Output n/a PIN NUMBER C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C7 C8 C1 C5 C7 A1 C2 C3 C4 A2 B1 - B26 FUNCTION Active Low read signal Active Low write signal. Active Low acknowledge signal to uP . Active low interrupt request to uP from . AAL1gator II Active low interrupt request to uP from Framer Active low global reset. Active low chip select. When asserted, the AAL1gator II is selected. Active low chip select. When asserted, the COMET or TQUAD/EQUAD is selected. Active low chip select. When asserted, the FPGA is selected. Prevents uP from gaining too many cycles. GND. Ground Reference Figure 9 on the following page represents the design of the interface from the AAL1gator II to its associated memory system and the system microprocessor. As can be noted, the interface consists of 2 128K x 8 static ram devices. In the transmit direction (from the line via RL_SER and RL_SIG, to the ATM network), the devices store queued data while cells for transmission are built. In the receive direction (from the ATM network via the UTOPIA bus to the line side interface) the SRAM holds data while frames are built for transmission on the T1 or E1 line. The selected SRAM must be 12 ns or faster, with a write setup time of 7 ns or faster. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 13 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN AAL1gator II MEM_WEB(0) 128k x 8 SRAM MEM_CSB MEM_OEB D(7:0) 128k x 8 SRAM MEM_WEB(1) A(16:0) D(15:8) D(15:0) A(16:0) SP_DATA_CLK SP_DATA_DIR SP_DATA_ENB SP_ADD_ENB A(16:0) ADDR17 16 BIT XCVRs (IDT74FCT162646) 20 BIT BUFFER (IDT74FCT162827) PROC_INT PROC_CSB PROC_WRB PROC_RDB PROC_ACKB HOLDOFF D(15:0) A(16:0) A 1 7 IRQ1B CS1B WRB RDB ACKB HOLDOFF MICROPROCESSOR INTERFACE Figure 9. AAL1gator II Connections to Microprocessor. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 14 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN Figure 9 also indicates the usage of external address buffers and data transceivers. In order for the system to operate at the maximum frequency of 40.00 MHz, the address buffers must have a worst case propagation delay of 8ns, while the data transceivers must have a worst case delay of 10ns. For these reasons the IDT74FCT162827CT was chosen as the address buffer. This 20 bit device has a maximum propagation delay of 4.4ns (50pF, 500 load). The IDT74FCT162646 was chosen as the data transceiver. This 16 bit device has a worst case propagation delay of 5.4ns under the same loading conditions. As can be seen, serial termination resistors are placed on the MEM_WEB(x) and MEM_CSB signals. The resistor value was chosen in accordance with the discussion in section 8.6 of the AAL1gator II data sheet. Please refer to that section for additional information. Table 3 below describes additional connections between the AAL1gator II, the microprocessor and the memory system. Table 3. SIGNAL NAME MEM_WEB(0) MEM_WEB(1) MEM_CSB MEM_OEB SP_DATA_CLK Additional AAL1gator II to Microprocessor Connections. DESCRIPTION Active low write enable for low order byte SRAM Active low write enable for high order byte SRAM Active low chip select for SRAM devices Active low output enable of SRAM devices Memory or register read data is written into the FCT162646 data transceiver on the rising edge of this signal. The microprocessor may then access the data. Signal is driven by the AAL1gator II. SP_DATA_DIR Controls the direction of data movement in the FCT162646. When high, data flows toward the microprocessor, when low, towards the AAL1gator II. Signal is driven by the AAL1gator II. SP_DATA_ENB AAL1gator II driven signal that enables the FCT162646 data transceiver. SP_ADD_ENB AAL1gator II driven signal that enables the FCT162827 address buffer. PROC_INT Active high interrupt from the AAL1gator II to the microprocessor. PROC_CSB Active low chip select from the microprocessor (via CS1B). ADDR17 When high, the CMD_REG of the AAL1gator II is selected. PROC_WRB Active low write signal for the AAL1gator II from the microprocessor. PROC_RDB Active low read signal for the AAL1gator II from the microprocessor. PROC_ACKB Active low acknowledge signal from the AAL1gator II. HOLDOFF When high, prevents the microprocessor from additional accesses until 20 SYS_CLK cycles from the last processor access. Figure 10 on the following page illustrates the connections between the microprocessor, and the 8 COMET devices plus the FPGA. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 15 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN FPGA D(7:0) D(7:0) /CS3 A(2:0) /RD / W R A(2:0) COMET INTERFACE D(7:0) A(8:0) D(7:0) A(8:0) /RDB /WRB Decoder S1 S2 S3 D1 /CS(7:0) D8 /RSTB 74HCT138 ENB EN /INTB B DIR Y(8:0) Y9 Y10 Y11 Y12 Y13 Y14 Y15 16 BIT XCVR (74FCT162646) /OE A 16 BIT BUFFER (74FCT162827) /OE A(8:0) A9 A10 A11 A12 A13 A14 A15 D(7:0) /CS3 A(8:0) /RD / W R A20 A19 A18 /CS2 A21 /RSTB /IRQ2 MICROPROCESSOR INTERFACE Figure 10. COMET Interface to Microprocessor. When the microprocessor wishes to communicate with a COMET device, it asserts an address as listed in the following table (Table 4). When an appropriate address is driven onto the bus, the microprocessor simultaneously asserts CS2B. Since A21 is high, the decoder is then active. Address bits A(20..18) determine which output of the decoder is PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 16 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN driven low. One decoder output connects to the CSB input of each COMET device. For example, if A(20..18) are 000, then decoder output Y0 is driven low, which also asserts CSB of COMET0. No other COMET device is selected at this time. Address bits A(8..0) determine which register of the COMET the microprocessor is communicating with. In order to meet the timing requirements of the COMET devices (see PM4351 COMET data sheet), the 3-8 decoder (74HCT138) must have a minimum propagation delay of 10ns. With a 15pF load, the device has a typical delay of 13ns. At 50pf (VCC = 4.5), the delay increases to 27ns, and therefore will meet the specifications. Table 4. Address Ranges of the COMET devices. BASE ADDRESS 200000h 240000h 280000h 2C0000h 300000h 340000h 380000h 3C0000h ADDRESS RANGE 200000 - 2001FFh 240000 - 2401FFh 280000 - 2801FFh 2C0000 - 2C01FFh 300000 - 3001FFh 340000 - 3401FFh 380000 - 3801FFh 3C0000 - 3C01FFh COMET COMET0 COMET1 COMET2 COMET3 COMET4 COMET5 COMET6 COMET7 Since the address and data buses are shared among many devices, a 20 bit buffer and transceiver is used. This insures that clean signals are present on the inputs of the devices, and that no data collisions occur. The buffer (FCT162827) is not only placed on the address lines, but the various control signals such as WRB and RDB as well. The 16 bit transceiver (FCT162646) is used in flow through mode to control data bus access. The transceivers output enable is controlled by the result of a logical AND of CS2 and CS3. In this way, whenever the microprocessor needs to communicate with either a COMET or the FPGA, either the CS2, or CS3 signal must be driven low, which drives the active low output enable signal of the transceiver low. The transceivers direction is controlled by the WRB signal. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 17 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 4.1.2 Field Programmable Gate Array (FPGA) The FPGA (see Figure 13 page 23) performs the following functions on a per line basis: 1. Allows fully software selectable TL_CLK source. 2. Allows a fully selectable COMET XCLK source (1.544 or 2.048 MHz). 3. Generates framing pulses at the 8 kHz rate for the TL_FSYNC (AAL1gator II) and BTFP (TQUAD or COMET) signals. 4. Produces a software selected N_CLK signal (gnd, or 2.43 MHz). In order to provide maximum system flexibility, the AAL1gator II provides several options for the TL_CLK signal. Table 5 lists the options that the user may select. As can be seen, the FPGA permits the use of all options on a per line basis. The options must also be set in the LIN_STR_MODE register (CLK_SOURCE bits) of the AALI1gator II. Table 5. TL_CLK options. FUNCTION External Clock Source Recovered: based on RL_CLK Nominal T1 or E1 Clock Synthesis SRTS TL_CLK I/O input output output output SUPPORTED YES YES YES YES CLK_SOURCE(5..4) 00 01 10 11 When the CLK_SOURCE(5..4) bits are set to 00, TL_CLK is configured as an input. In this mode, the FPGA will allow a 1.544 MHz, 2.048 MHz, or adaptive clock source to be supplied to the TL_CLK input (and also to the BTCLK input of the COMET or TQUAD device). In adaptive clock mode, an adaptive clock generator block provides a queue depth difference for control of an external clock. If the queue depth is low, the clock frequency is reduced, while if the queue depth is high, the clock frequency is increased. Adaptive clock data from the AAL1gator II appears on the SRTS port when the ADAP_STRB signal is asserted by the AAL1gator II. In recovered mode, (CLK_SOURCE set to 01), the clock signal output on TL_CLK is based on the received RL_CLK. When the CLK_SOURCE(5..4) bits are set to 10, the AAL1gator II is configured to generate a nominal T1 or E1 clock derived from a 38.88 MHz SYS_CLK. SYS_CLK must be network derived in order to lock the synthesized clock to the network clock. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 18 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN When CLK_SOURCE(5..4) are set to 11, the AAL1gator II is configured to use the Synchronous Residual Time Stamp (SRTS) option. In this mode, the AAL1gator II compares locally generated SRTS values with received SRTS values. A 4 bit difference code is then generated. If the code value is higher than that previously generated, the remote clock is running faster than the local clock. Alternatively, if the code is lower, the remote clock is running slower than the local clock. The AAL1gator II uses this information to synthesize TL_CLK. In this implementation, the interconnection between the AAL1gator II TL_CLK pin and the FPGA is bidirectional. There are many possible ways to alleviate the complexity of terminating a bidirectional signal. The first method, illustrated below in Figure 11, utilizes two separate FPGA ports for TL_CLK. The TL_CLKI port is an input port from the AAL1gator II, while the TL_CLKO port is an output port to the AAL1gator II. In additon two series terminating resistors (value between 33 and 50) and one jumper per line are required. When the AAL1gator II is sourcing TL_CLK (to the TL_CLKI input of the FPGA), the jumper is not installed, and the resistor nearest the AAL1gator II is installed. Likewise, when the TL_CLKO port of the FPGA is sourcing TL_CLK, the jumper is installed, and the resistor nearest he AAL1gator II is not installed. This, in essence, creates a unidirectional transmission path for each direction. TL_CLKO AAL1gator II Install Jumper only if TL_CLKO sources TL_CLK FPGA TL_CLKI TL_CLK Install resistor only if AAL1gator II sources TL_CLK Figure 11. Termination of TL_CLK signal. However, there is a disadvantage to the above method. It is no longer possible to interactively switch between having the AAL1gator II source TL_CLK, or have an external source provide TL_CLK to the AAL1gator II. Therefore, an alternative approach would be to combine the TL_CLKI and TL_CLKO ports of the FPGA into one bidirectional port (for each line). The signal path distance between the AAL1gator II and the FPGA must then be kept as short as possible. If this is not possible, both ends of the signal path may be serially terminated with an appropriate value resistor. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 19 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN One last alternative is a hybrid between the previous two approaches. As illustrated in Figure 12 for one of the eight TL_CLK lines, this method utilizes a switching arrangement to change between having the AAL1gator II source TL_CLK, to having the FPGA source TL_CLK to the AAL1gator II. AAL1gator II FPGA TL_CLK Figure 12. TL_CLK switching termination option. The switches could take the form of dip switches, requiring manual interchange, or could be digitally controlled analog swiches. In addition, the switches could be replaced by jumpers. PMC-Sierra Inc. has secured an agreement with Bellcore (patent holders for SRTS clock recovery technique). Please refer to the AAL1gator II data sheet for important information regarding this agreement. In a typical application employing SRTS, N_CLK must be a 2.43 MHz signal derived from the ATM network (for example, from the 155.52 MHz SONET clock). To disable SRTS, N_CLK is connected to GND, whereas to enable SRTS, N_CLK must be connected to a 2.43 MHz signal. This is accomplished via a divide by 16 block in the FPGA whose input is the 38.88 MHz network clock signal. Another function of the FPGA is to generate the 8 kHz framing pulse from the transmit line clock output (BTCLK) to the framer. This 8 kHz signal connects to the AAL1gator II TL_FSYNC input, and the framer's BTFP input. In T1 mode, a pulse one BTCLK period wide is generated every 193 bits, while in E1 mode, the pulse is generated every 256 bits. In an implementation involving the AAL1gator II and TQUAD or EQUAD device, each BTCLK output from the FPGA must be inverted. Whereas if the design involves AAL1gator II to COMET devices, the BTCLK output must not be inverted with respect to TL_CLK. The reason for this is the timing requirements of the line side interface of the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 20 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN AAL1gator II. In the receive direction (from the ATM network to the line) , the AAL1gator II updates signals (TL_SIG, TL_SER) on the rising edge of TL_CLK. In addition, the TQUAD samples the corresponding signals on the rising edge of its BTCLK (analogous to TL_CLK) signal. If the output of the FPGA is not inverted, this would cause the TQUAD or EQUAD device to sample the TL_SIG and TL_SER (BTSIG and BTPCM) signals at the same time that they are in transition. Inverters shift the sample point to a time in which all signals are stable. The COMET version does not require inverters because it allows users to select the active edge (on which it samples BTSIG and BTPCM) of its BTCLK signal. Please see sections 5 and 6 for FPGA register and programming information. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 21 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 4.1.3 Clock and Power Supply Circuitry This is a relatively simple block. It consists of two crystal oscillators: One at 2.048 MHz (50 ppm), and one at 1.544 MHz (50 ppm). These crystals provide the XCLK signal via the FPGA to the individual COMET devices on a per line basis. For instance, if COMET 0 is configured to interface to a T1 line, a 1.544 MHz clock is applied to its XCLK input. Alternatively, if it is to interface to an E1 line, a 2.048 MHz clock signal is applied to its XCLK input. The AAL1gator II requires a 38.88 MHz clock signal on its SYS_CLK input. Ideally, this is a network derived signal (for example, the 155.52 MHz SONET clock divided by four) with a duty cycle variance of 2.5 %. In applications employing SRTS, SYS_CLK need not be network derived, provided N_CLK is network derived. In applications that do not employ SRTS (for example, synthesizing a nominal T1 or E1 clock), the accuracy of the synthesized clock is dependent on the accuracy of SYS_CLK. For example, to generate a T1 clock with 50 ppm accuracy, SYS_CLK must have 50 ppm accuracy. To lock this synthesized clock to a network clock, SYS_CLK must be derived from the network clock. To accomplish these requirements in this reference design, the network clock signal (ideally, the 155.52 MHz SONET clock) is input to the FPGA via an SMA connector. The FPGA then provides a 38.88 MHz SYS_CLK signal for the AAL1gator II. As mentioned previously, the FPGA also generates the 2.43 MHz N_CLK signal from this same source. In addition to the clock circuitry, this block also generates the required +5V/+3.3V supply for the board. 4.1.4 UTOPIA Interface The AAL1gator II communicates with various ATM devices, such as the ATLAS or the QRT/QSE via the UTOPIA interface. Please refer to section 4.3 of the AAL1gator II data sheet for a discussion of the individual signals. There are two possible UTOPIA modes of operation for the AAL1gator II: ATM mode and PHY mode. In ATM mode, the AAL1gator II is configured with an ATM layer UTOPIA interface. In PHY mode, it is configured with a PHY layer UTOPIA interface. When PHY_ENABLE is high, PHY mode is enabled, while if low, the device is in ATM mode. To allow for application specific implementations, an optional jumper will be specified in the schematic diagram. If a PHY mode application is required, the jumper PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 22 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN may be installed, otherwise it may be left unconnected, due to the internal pulldown resistor within the device (device defaults to ATM mode). NOTE: IN TQUAD/EQUAD IMPLEMENTATIONS, BTCLK MUST BE INVERTED AT THE OUTPUT OF THE MULTIPLEXOR TO FRAMER BTCLK (7:0) 38.88MHz NETWORK CLOCK SOURCE SOURCE_SELECT (400000h) 1 0 /16 SRTS_DOUT (3:0) SRTS_DOUT (3:0) ADAP_STRB ADAPTIVE CLOCK GENERATOR 1 0 N_CLK_SOURCE (400001h) XCLK_SELECT (400002h) N_CLK TL_FSYNC (7..0) or BTFP (7..0) 1.544 MHz SOURCE 2.048 MHz SOURCE 1 XCLK(7..0) 0 0 1 SOURCE_SELECT (400000h) N_CLK_SOURCE (400001h) XCLK_SELECT (400002h) FRAME PULSE GENERATOR 1.544 MHz FRAME PULSE GENERATOR 2.048 MHz SOURCE_SELECT (400000h) CS3B WRB RDB MICROPROCESSOR PORT BTCLK (7..0) See Note Above A(2..0) D(7..0) TL_CLKO (7..0) TL_CLKI (7..0) Figure 13. Internal FPGA Circuitry. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 23 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 4.1.5 Additional Connections The following table (Table 6) lists the remaining connections to the AAL1gator II not already discussed. Table 6. PIN NAME PHY_ENABLE Additional Connections to AAL1gator II. AAL1GATOR II PIN NUMBER 56 DESCRIPTION Determines which UTOPIA mode the UTOPIA interface is configured for. Connect optional resistor to VCC for PHY mode, otherwise leave unconnected for ATM mode operation. Transmit Line Multiframe Synchronization (TL_MSYNC). An edge an these signals indicate the start of a multiframe. Connect to GND if unused. Receive Line Multiframe Synchronization (RL_MSYNC). RL_MSYNC carries the signaling information from the framer. Indicates the start of a multiframe. Connect to GND if unused.. Output Enable (/OE). Active low signal to enable outputs of the device. Connect to GND. Scan Test Reset (/SCAN_TRST). Reset signal for boundary scan logic. Connect to GND (if JTAG port unused) or header. Scan Test Mode Select (SCAN_TMS). Mode select signal for boundary scan logic. Connect to header. Scan Test Data Input (SCAN_TDI). Serial data input for boundary scan. TL_MSYNC(x) 154, 141, 129, 113, 101, 82, 70, 51 RL_MSYNC(x) 160, 147, 135, 123, 107, 95, 76, 64 /OE 184 /SCAN_TRST 167 SCAN_TMS 166 SCAN_TDI 165 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 24 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN PIN NAME SCAN_TDO AAL1GATOR II PIN NUMBER 168 DESCRIPTION Connect to header. Scan Test Data Output (SCAN_TDO). Serial data output from boundary scan. Connect to header Scan Test Clock (SCAN_TCLK). Clock for boundary scan logic. Connect to 330 resistor to GND (if JTAG port unused) or to header. Process Test (P_TEST). Used to measure process test parameters. N.C. Pullup Disable. Used to disable pullup resistors during manufacturing tests. Connect to GND +5V supply Ground Reference SCAN_TCLK 169 P_TEST 170 PULLUP_DISABLE 238 VDD GND N.C. = No Connection multiple multiple Note: The JTAG port signals (eg. SCAN_TDO) will connect to a header to allow for connection to other devices that have a JTAG port to allow for comprehensive boundary scan testing. On the schematic diagram, the SCAN_TRST pin is connected to a header and pulled up via a 4.7K resistor to VCC, to allow for external connection to a JTAG controller. If the JTAG port is not being used, the SCAN_TRST pin should be connected to ground via a 330 resistor. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 25 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 4.1.6 Line Interface Although the COMET device has an integral Line Interface Unit, additional circuitry is required before connecting to the T1 or E1 line. Transformers must be placed between the tip and ring lines. In addition, transient voltage suppressors must be placed in series with each line. Each set of tip and ring lines connect to the T1 or E1 line via a bantam connector. 4.1.7 Additional COMET Connections The following table (Table 7) lists additional connections to the COMET device not previously discussed. Table 7. PIN NAME TDAT Additional Connections to the COMET Device. DESCRIPTION Transmit Digital PCM Data (TDAT). Provides the line side NRZ PCM data (when transmit digital interface is enabled). N.C. Transmit Digital Frame Pulse (TFP). When enabled, indicates the frame alignment of the line side transmitted PCM stream. Receive Digital Line Data (RDAT). When enabled, samples the line side recovered NRZ PCM data. N.C. Receive Digital Line Clock (RCLK). When the transmit digital interface is enable, the externally recovered line rate clock is provided on this pin. Connect to GND. Recovered Clock Synchronization Signal (RSYNC). Provides a 8 kHz timing reference signal for T1 and E1 applications. N.C. Transmit Clock Reference (TCLKI). May be used a reference for transmit line rate generation. May be any multiple of 8 kHz. Connect to GND. Crystal Clock Input (XCLK). Jitter free, 50% duty cycle clock at 1.544 TFP RDAT RCLKI RSYNC TCLKI XCLK PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 26 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN PIN NAME ATB DESCRIPTION MHz (if T1) or 2.048 MHz if E1. 50 ppm. Analog Test Bus (ATB). Reserved for production test. Connect to GND. Trim Fuse. Reserved for production purposes. TRIMF TCK Connect to GND Test Clock (TCK) Boundary scan clock. Connect via 330 resistor to GND (if JTAG port unused) or header. Test Mode Select (TMS). Boundary scan test select signal. Connect to header. Test Data Input (TDI). Boundary scan input serial data. Connect to header. Test Data Output (TDO). Boundary scan serial test data output. Connect to header. Test Reset (TRSTB). Boundary scan test reset. Connect to header and VCC via 4.7K resistor, or to RSTB (if JTAG port unused). Output Power Pins Connect to well decoupled +3.3V supply (in common with VDDI. Output Ground Pins. Connect to GND in common with VSSI. Internal Power Pins Connect to well decoupled +3.3V supply in common with VDDOx Internal Ground Pins Connect to GND in common with VSSOx +5 V Bias. Facilitates 5 V tolerance on inputs. Connect to well decoupled +5 V rail. Transmit Analog Power. Power for transmit LIU reference circuitry. TMS TDI TDO /TRSTB VDDOx VSSOx VDDIx VSSIx BIAS TAVD1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 27 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN PIN NAME DESCRIPTION Connect to analog +3.3V Transmit Analog Power. Transmit power for transmit LIU output drivers. Connect to analog +3.3V. Transmit Analog Power. Supplies power for transmit clock synthesis. Connect to analog +3.3 V. Transmit Analog Ground TAVD2, TAVD3 TAVD4 TAVS1 Connect to analog GND. TAVS2, TAVS3 Transmit Analog Ground. Connect to analog GND. Transmit Analog Ground. Connect to analog GND. Receive Analog Power. Supplies power for receive LIU input equalizer. Connect to analog +3.3V. Receive Analog Power. Supplies power for analog peak detect and slicer. Connect to analog +3.3 V. Receive Analog Ground. Connect to analog GND. Quiet Analog Power. Supplies power for core analog circuitry. Connect to analog +3.3 V Quiet Analog Ground. Connect to analog GND. N.C. = No Connection Note: The JTAG port signals (eg. TCK) will connect to a header to allow for connection to other devices that have a JTAG port to allow for comprehensive boundary scan testing. TAVS4 RAVD1 RAVD2 RAVS1, RAVS2 QAVD QAVS PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 28 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 4.1.8 COMET Configuration Soon after power up, a hardware reset should be performed. The following minimum additional COMET software configurations are required: 1. Set active edge of BTCLK to falling edge. 2. Set active edge of BRCLK to rising edge. 3. Set BRCLK as output. 4. Set BRFP as output. For additional information, including COMET configuration data, please refer to Section 6 and the COMET data sheet (PMC-970624). 4.1.9 AAL1gator II Configuration Please refer to Section 6 and the AAL1gator II data sheet (PMC-980620) for additional information regarding configuration of the AAL1gator II. 4.1.10 The JTAG Port The JTAG port is connected among all devices to allow for boundary scan testing. The signals are connected in the following way: 1. TMS The Test Mode Select signal is connected in parallel among all COMET devices and the AAL1gator II. 2. TCK The Test Clock signal is connected in parallel among all COMET devices and the AAL1gator II. 3. TRSTB The Test Reset Select signal is connected in parallel among all COMET devices and the AAL1gator II. The source of this signal may either be the JTAG controller, or from a pushbutton activation 4. TDI/TDO The Test Data Input/Test Data Output signal is connected serially among all COMET devices and the AAL1gator II, beginning with the AAL1gator II, and ending with the last COMET device. The JTAG port signals connect to an externally accessible header. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 29 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 4.2 AAL1gator II Plus TQUAD/EQUAD Design The high level design of the AAL1gator II plus TQUAD/EQUAD is illustrated in Figure 14 on page 33. As can be seen, the COMET design and the TQUAD/EQUAD design are nearly identical. However, they do have the following differences: 1. Only 2 TQUAD/EQUAD are devices used in the TQUAD/EQUAD design. 2. The address bus connecting to each individual TQUAD/EQUAD is 10, rather than 9 bits wide. 3. The TQUAD/EQUAD device does not contain an integral Line Interface Unit, therefore a separate LIU such as the QDSX or D3MX must be used. 4. The TQUAD or EQUAD does not require a 1.544 or 2.048 MHz oscillator. Instead, a 37.56 MHz 32/50 ppm (49.152 MHz 32/50 ppm) if EQUAD) oscillator is used. 4.2.1 Microprocessor and Memory System Interface The same microprocessor and memory system interface as that used in the AAL1gator II plus COMET reference design is used in the AAL1gator II plus TQUAD reference design. 4.2.2 Line Side Interface to the AAL1gator II As discussed in section 4.1.2, the AAL1gator II plus TQUAD requires additional inverters on the line side interface. This is because the AAL1gator II samples RL_SER and RL_SIG on the falling edge of RL_CLK while the TQUAD asserts the corresponding signals on the falling edge of RCLKO. Therefore, inverters are placed on the RCLKO output to the AAL1gator II device. 4.2.3 Line Interface Also mentioned previously, the TQUAD does not contain an integral Line Interface Unit. Therefore, an LIU such as the QDSX or D3MX (if used in a channelized DS3 application) must be used. Table 8 lists the pin information for the connections to the line interface unit. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 30 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN Table 8. SIGNAL NAME XCLK TDP(7) TDP(6) TDP(5) TDP(4) TDP(3) TDP(2) TDP(1) TDP(0) TDN(7) TDN(6) TDN(5) TDN(4) TDN(3) TDN(2) TDN(1) TDN(0) TCLKO(7) TCLKO(6) TCLKO(5) TCLKO(4) TCLKO(3) TCLKO(2) TCLKO(1) TCLKO(0) RDP(7) RDP(6) RDP(5) RDP(4) RDP(3) RDP(2) RDP(1) RDP(0) RDN(7) RDN(6) RDN(5) RDN(4) RDN(3) Line Interface Unit Connections. FUNCTION XCLK. Crystal Clock signal. Nominally 37.056 MHz if T1, 49.152 MHz if E1. Transmit Digital Positive Line Pulse (TDP). Available when the TQUAD/EQUAD is configured to transmit dual rail data. Transmit Digital Negative Line Pulse (TDN). Available when the TQUAD/EQUAD is configured to transmit dual rail data. Transmit Clock Output (TCLKO) Signals TDN and TDP are updated on the active edge of this signal. Receive Digital Positive Line Pulse (RDP). Available when the TQUAD/EQUAD is configured to receive dual rail data. Receive Digital Negative Line Pulse (RDN). Available when the TQUAD/EQUAD is configured to receive dual rail data. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 31 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN SIGNAL NAME RDN(2) RDN(1) RDN(0) RCLKI(7) RCLKI(6) RCLKI(5) RCLKI(4) RCLKI(3) RCLKI(2) RCLKI(1) RCLKI(0) GND FUNCTION Receive Line Clock Input (RCLKI). Each input is an externally recovered 1.544 MHz (or 2.048 MHz) line clock that may be enabled to sample the RDN and RDP inputs, when the device is configured to receive dual rail data. GND. Ground Reference. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 32 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN LINE INTERFACE (QDSX, D3MX) RDN(3:0) TCLKO(3:0) TCLKO(7:4) RCLKI(3:0) RDN(7:4) RDP(3:0) RDP(7:4) TDN(3:0) TDN(7:4) TDP(3:0) TDP(7:4) TQUAD 0 EQUAD 1 FRAMER BUS MICROPROCESSOR BUS Four bits of each signal go to each TQUAD/EQUAD via the FRAMER BUS. For example, bits (3:0) go to TQUAD0 while (7:4) go to TQUAD1. BRPCM(7:0) RCLKO(7:0) BTCLK(7:0) BRSIG(7:0) BRFP(7:0) BTSIG(7:0) TL_SIG(7:0) BTFP(7:0) RCLKI(7:4) TIMING SOURCES CONTROL BUS ADDRESS BUS DATA BUS FPGA TLCLK_OUTPUT_EN SRTS_DOUT(3:0) TL_FSYNC(7:0) RL_CLK(7:0) TL_CLK(7:0) RL_FSYNC(7:0) RL_SER(7:0) RL_SIG(7:0) DATA BUS DATA BUS ADDRESS BUS CONTROL BUS ADDRESS BUS CONTROL BUS AAL1gator II MICROPROCESSOR INTERFACE UTOPIA INTERFACE UTOPIA BUS Figure 14. AAL1gator II plus TQUAD/EQUAD High Level Design. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE SRTS_LINE(3:0) ADAP_STRB 33 TL_SER(7:0) N_CLK MICROPROCESSOR AND MEMORY SYSTEM BTPCM(7:0) PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 4.2.4 Additional Connections for the TQUAD Device The following table (Table 9) lists the additional connections for the TQUAD/EQUAD device not previously discussed. Table 9. PIN NAME BRCLKx Additional TQUAD Device Connections. TQUAD PIN NUMBER 94 DESCRIPTION Backplane Receive Clock. Either a 1.544 or 2.048 MHz clock signal. This signal is common to all framers within the TQUAD/EQUAD device. Connect to GND.. Multiplex Enable. When asserted low, the four sets of data per TQUAD are combined into a single bit interleaved 12.352 MHz stream. Connect to VCC via 4.7K resistor Receive Data Link Signal. Signals are available when the HDLC receiver is enabled. Connect to header. Receive Data Line Clock. Clock signals are available on these pins when the HDLC receiver is enabled. Connect to header. Multiplexed Receive Data (MRD). When MENB is low, four sets of data and signaling information is bit interleaved into a single 12.352 MHz data stream. Connect to header. Transmit Data Link Signal. When the associated HDLC transmitter is enabled, signaling data is available on these pins. Connect to header. Transmit Data Link Clock. When HDLC is enabled, used to sample the TDLSIG signal. Connect to header. XCLK. Crystal Clock Input. MENB 45 RDLSIGx 125, 126, 127, 128 RDLCLKx 119, 120, 123, 124 MRD 59 TDLSIGx 113, 114, 117, 118 TDLCLKx 109, 110, 111, 112 XCLK 60 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 34 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN PIN NAME TQUAD PIN NUMBER DESCRIPTION If TQUAD, connect to 37.056 MHz crystal. If EQUAD, connect to 49.152 MHz crystal. 32/50 ppm Address Latch Enable. Allows TQUAD to be connected to a multiplexed address data bus. Connect to VCC via 4.7K resistor. AC Power Pins. Connect to well decoupled +5 V supply together with PHD. DC Power Pins. Connect to well decoupled +5 V supply together with PHA. AC Ground Pins Connect to common ground with PLD DC Ground Pins Connect to common ground with PLA. N.C. = No Connection ALE 41 PHAx 18, 52, 89, 105, 121 PHDx 20, 50, 85, 115 PLAx 19, 53, 90, 106, 122, 1 21, 51, 86, 116 PLDx 4.2.5 TQUAD/EQUAD Configuration A software reset should occur soon after power up to restore the TQUAD or EQUAD to its default configuration state. Please refer to Section 6 and the TQUAD or EQUAD data sheet (PMC-940910, PMC-951013) for additional configuration information. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 35 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 5 MEMORY MAP AND REGISTER DEFINITIONS The memory map for the AAL1gator II reference design is as indicated in Table 10. Table 10. AAL1gator II Reference Design Memory Map. BASE ADDRESS 000000h 020000h 200000h 200000h 240000h 240000h 280000h 2C0000h 300000h 340000h 380000h 3C0000h 400000h 400001h 400002h RANGE 000000h - 01FFFFh 020000h - 03FFFFh 200000h - 2001FFh 200000h - 2003FFh 240000h - 2401FFh 240000h - 2403FFh 280000h - 2801FFh 2C0000h - 2C01FFh 300000h - 3001FFh 340000h - 3401FFh 380000h - 3801FFh 3C0000h - 3C01FFh 400000h 400001h 400002h DEVICE AAL1gator II AAL1gator II CMD_REG COMET0 TQUAD0 COMET1 TQUAD1 COMET2 COMET3 COMET4 COMET5 COMET6 COMET7 FPGA SOURCE_SELECT Register FPGA N_CLK_SOURCE Register FPGA XCLK_SELECT Register To communicate with the FPGA and its internal registers, a programmable chip select on the system microprocessor should be configured to be asserted when an address in the range 400000h - 400002h is driven onto the address bus. The VHDL code within the FPGA will then examine the WRB and RDB to determine if a register read or write is being performed. The FPGA then either drives the data bus with the selected registers contents, or updates one of the following registers with the data driven on the data bus by the system microprocessor. As mentioned previously, the FPGA allows the support of several configurable options. This is accomplished through the use of the following registers within the FPGA: Table 11. bit 7 ss7 6 ss6 SOURCE_SELECT Register (400000h). 5 ss5 4 ss4 3 ss3 2 ss2 1 ss1 0 ss0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 36 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN The SOURCE_SELECT determines whether the signal transmitted to the COMET or TQUAD device via the BTCLK pin is from the AAL1gator II TL_CLK pin or from an external source. If an external source is selected, adaptive clock mode is enabled, and the FPGA synthesizes an external clock at the line rate. The synthesized clock appears at the TL_CLKIO<7..0> and BTCLK<7..0> pins ssX: 0 = AAL1gator II internal clock (nominal, recovered, or SRTS) sources clock signal via the FPGA to the COMET or TQUAD BTCLK Table 12 presents the structure of the N_CLK_SOURCE Register. If the srts_enable bit is set to 0, N_CLK is connected to GND. Otherwise, if the bit is set to 1, a 2.43MHz (38.88 MHz divided by 16) signal is presented on N_CLK. The affect of this register is to allow for disabling of Synchronous Residual Time Stamp (SRTS) on the AAL1gator II. If the N_CLK signal is connected to GND, SRTS is disabled. Bits 6 through 0 are unused. srts_enable: 1 = 2.43MHz signal presented on N_CLK. SRTS is enabled. 0 = N_CLK is set to a logic 0. SRTS is disabled. Table 13. Bit 7 xclk7 6 xclk6 XCLK_SELECT Register (400002h). 5 xclk5 4 xclk4 3 xclk3 2 xclk2 1 xclk1 0 xclk0 Table 13 lists the details of the XCLK_SELECT register. The purpose of this register to allow support of both T1 and E1 lines. If a T1 line is used, that lines bit (for example xclk7) must be set to 1. Otherwise, if an E1 line is in use, the associated lines bit must be set to 0. This feature is available on a per line basis. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 37 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN The effect of this register is seen in two places on a per line basis: 1. The register determines which clock signal (1.544 MHz or 2.048 MHz) is output from the FPGA to each individual COMETs XCLK pin. 2. The register determines which framing pulse format (T1 or E1) is used. The effect is seen on the outputs the AAL1gator II's TL_FSYNC<7..0> pins and the COMET or TQUAD/EQUAD's BTFP pins. xclk: 1 = Line is T1. If using a COMET device, the COMET receives a 1.544MHz clock signal on its XCLK pin. In addition, a pulse one BTCLK period wide is generated every 193 bits, and output to the AAL1gator II and COMET or TQUAD device. 0 = Line is E1. If using a COMET device, the COMET receives a 2.048MHz clock signal on its XCLK pin. In addition, a pulse one BTCLK period wide is generated every 256 bits, and output to the AAL1gator II and COMET or EQUAD device. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 38 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 6 SOFTWARE CONFIGURATION This section describes how to configure the AAL1gator II to work with T1 and E1 lines. A hypothetical scenario consisting of the AAL1gator II interfacing to 4 T1 and 4 E1 lines will be explored. Lines 0 through 3 will be T1, while lines 4 through 7 will be E1. 6.1 AAL1gator II Configuration The basic configuration steps for the AAL1gator II are as outlined in Figure 15 (next page). As can be seen, the first step is to enter a SW_RESET state. There are two possible ways to enter the SW_RESET state: 1. By performing a hardware reset. Once the hardware reset is removed, the AAL1gator II enters the SW_RESET state. 2. By asserting bit 5 (SW_RESET) of the CMD_REG (base address 20000h). Once in the SW_RESET state, various configurable options are set by writing to the data structures in memory. Among many others, these options include: 1. Type of line (T1 or E1). 2. Source of the TL_CLK signal. 3. The value of empty bytes in partially filled cells. 4. OAM cell format. When the AAL1gator II has been set up in the desired format, the CMD_REG_ATTN bit (bit 3 in the CMD_REG) should be set to 1. Finally, to complete the configuration, the SW_RESET bit in the CMD_REG should be deasserted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 39 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN Hardware Reset Set SW_RESET bit Perform Line Configuration Set CMD_REG_ATTN Bit Setup R_CHAN_TO_Q_TBL Exit SW_RESET State Configure Queue Set Bit in ADD_QUEUE Table Yes Set CSD_ATTN Bit Enable appropriate channels in R_CHAN_TO_Q_TBL Repeat? No Resume Normal Operation Figure 15. Flowchart for configuring the AAL1gator II. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 40 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN To configure the AAL1gator II to operate with the conditions given above, the following operations should be performed: 1. Enter the SW_RESET state 2. Write a 1 to bit 6 (MIXED_MODE_EN) of the COMP_LIN_REG (base address 1h). This permits the device to operate with a mix of T1 and E1 lines. 3. Write to the remaining bits of the COMP_LIN_REG as necessary for each individual implementation. 4. Write to the LINE_STR_MODE_X registers. These eight registers store the per line configuration. In these registers, users may set each line in T1 or E1, and determine the source of TL_CLK. To set lines 0 through 3 for T1 mode, write a 1 to bit 13 (T1_MODE) of LINE_STR_MODE_0 through LINE_STR_MODE_3 (addresses 10h through 13h). To set lines 4 through 7 for E1 mode, write a 0 to bit 13 of LINE_STR_MODE_4 through LINE_STR_MODE_7. The TL_CLK source for each line may be set at the same time that the line mode is set. The remaining bits may be set as required, and as indicated in the AAL1gator II data sheet. Table 14. CLK_SOURCE(5:4) 00 01 10 11 TL_CLK options for the AAL1gator II. DESCRIPTION Use external clock (TL_CLK is an input) Looped: Loop the recovered RL_CLK as the source. Nominal: Generate a clock of the nominal T1 or E1 frequency based on SYS_CLK SRTS: Generate a clock based on the received SRTS values. 5. Set CMD_REG_ATTN (bit 3) in the CMD_REG (20000h) 6. Configure the R_CHAN_TO_Q_TBL data structure (base address 08200h) as required. See the AAL1gator II data sheet, section 7.8.6 for further details. 7. Exit the SW_RESET state. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 41 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 8. Configure a queue via the T_QUEUE_TBL (base address 2000h) as required. See the AAL1gator II data sheet, section 7.6.8 for further details. 9. Set corresponding bit for the queue just added in the ADD_QUEUE table (base address 30h). See the AAL1gator II data sheet, section 7.6.8 for further details. 10. Set CSD_ATTN (bit 4) in the CMD_REG (base address 20000h). 11. Perform steps 8 through 10 as necessary, adding only queue at a time (helps minimize CDV due to clumping). Table 15. REGISTER COMP_LIN_REG Summary of minimum AAL1gator II line configurations. BASE ADDRESS 1h 10h VALUE 0040h 2000h FUNCTIONAL DESCRIPTION AAL1gator II is set to operate with mixed lines. Line 0 is in T1 mode, using adaptive clock recovery (external TL_CLK source). Line 1 is in T1 mode. TL_CLK outputs a looped RL_CLK. Line 2 is in T1 mode. AAL1gator II generates a nominal T1 clock, and outputs it on TL_CLK. Line 3 is in T1 mode. AAL1gator II is using SRTS clock recovery on this line. Line 0 is in E1 mode, using adaptive clock recovery (external TL_CLK source). Line 1 is in E1 mode. TL_CLK outputs a looped RL_CLK. Line 2 is in E1 mode. AAL1gator II generates a nominal T1 clock, and outputs it on TL_CLK. Line 3 is in E1 mode. AAL1gator II is using SRTS clock recovery on this line. LINE_STR_MODE_0 LINE_STR_MODE_1 LINE_STR_MODE_2 11h 12h 2010h 2020h LINE_STR_MODE_3 13h 2030h LINE_STR_MODE_4 14h 0000h LINE_STR_MODE_5 LINE_STR_MODE_6 15h 16h 0010h 0020h LINE_STR_MODE_7 17h 0030h PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 42 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN The minimum line configuration for the AAL1gator II has now been performed to enable it to work with 4 T1 and 4 E1 lines. For additional configuration options, please refer to the AAL1gator II data sheet. 6.2 COMET Configuration The next step is to perform the necessary configurations on the COMET or TQUAD/EQUAD devices. First, let us assume that 8 COMET devices are being used. Let us further assume that COMET devices 0 though 3 will operate in T1 mode, while COMET devices 4 through 7 operate in E1 mode. The following steps are required to configure the COMET devices: 1. Write a 0 to bit 0 (E1/T1B) of the Global Configuration register (000h) of COMETs 0 through 3. 2. Write a 1 to bit 0 (E1/T1B) of the Global Configuration register (000h) of COMETs 4 through 7. 3. For COMETs 0 through 3, write 18h to the BRIF Configuration register (030h). This configures the COMET in the following way: * * * * * Full frame mode BRCLK is an output BRPCM and BRSIG are updated on the rising edge of BRCLK. BRFP is updated on the rising edge of BRCLK. BRCLK is at the backplane rate (1.544 MHz). 4. For COMETs 4 through 7 write 19h to the BRIF Configuration register. This action configures the COMET in the same way as step 3, with the exception that BRCLK is at the E1 rate of 2.048 MHz. 5. For all COMET devices, write 00h to the BRIF Frame Pulse Configuration register (031h). This action sets the BRFP pin as an output, and causes BRFP to pulse high for one BRCLK period every 193 (T1) or 256 (E1) bits. 6. For COMETs 0 through 3, write 20h to the BTIF Configuration register (040h). This action configures the COMETs in the following way: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 43 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN * * * * * Full Frame mode. BTCLK is an input. BTSIG and BTPCM are sampled on the falling edge of BTCLK. BTFP is sampled on the falling edge of BTCLK. BTCLK is at the backplane rate (1.544 MHz). 7. For COMETs 4 through 7, write 21h to the BTIF Configuration register (040h). This action configures the COMET in the same way as step 6, with the exception that BTCLK is at the E1 rate of 2.048 MHz. Table 16. Summary of the minimum COMET device configurations. BASE ADDRESS 000h 000h 030h VALUE 10h 00h 18h FUNCTIONAL DESCRIPTION Sets the COMET devices to operate in T1 mode. Sets the COMET devices to operate in E1 mode. COMET configured for: * Full Frame Mode * BRCLK is an output * BRPCM, BRSIG, BRFP updated on rising edge of BRCLK. * BRCLK is at the backplane rate (1.544 MHz). COMET configured for: * Full Frame Mode * BRCLK is an output * BRPCM, BRSIG, BRFP updated on rising edge of BRCLK. * BRCLK is at 2.048 MHz. BRFP is an output COMET REGISTER 0-3 4-7 0-3 Global Configuration Global Configuration BRIF Configuration 4-7 BRIF Configuration 030h 19h 0-7 BRIF Frame Pulse Configuration 031h 00h PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 44 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN COMET REGISTER 0-3 BTIF Configuration BASE ADDRESS 040h VALUE 20h FUNCTIONAL DESCRIPTION COMET configured for: * Full Frame Mode * BTCLK is an input * BTPCM, BTSIG, BTFP sampled on rising edge of BTCLK. BTCLK is at the backplane rate (1.544 MHz). COMET configured for: * Full Frame Mode * BTCLK is an input * BTPCM, BTSIG, BTFP sampled on rising edge of BTCLK. BTCLK is at the backplane rate (2.048 MHz). 4-7 BTIF Configuration 040h 21h 6.3 TQUAD/EQUAD Configuration An alternative to using COMET devices as the line interface is to use a PM4344 TQUAD for lines 0 through 3 and a PM6344 EQUAD for lines 4 through 7. The device should be placed in a default state (either by asserting RSTB, or asserting the RESET register bit. Once this is completed, the RCLKOSEL bit (bit 7) of the Receive Backplane Options register (001h, 081h, 101h, 181h) should be set to a logic 1. This causes BRPCMx and BRSIGx to be updated on the falling edge of RCLKOx. Once this is completed, user and application specific configurations may then be performed. Please refer to the TQUAD or EQUAD data sheet for further information. 6.4 FPGA Configuration Table 17. Summary of FPGA Configurations. ADDRESS 400000h 400001h 400002 VALUE 11h 80h 0Fh FUNCTIONAL DESCRIPTION Lines 0, 4 external clock source. SRTS enabled. Lines 0-3 are T1, 4-7 are E1. REGISTER SOURCE_SELECT N_CLK_SOURCE XCLK_SELECT PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 45 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 7 IMPLEMENTATION DESCRIPTION Both reference design schematics were captured using Cadence software Concept Schematics Capture tool. 7.1 COMET Version Schematics 7.1.1 ROOT DRAWING, Sheet 1 This sheet provides an overview of the major functional blocks of the AAL1gator II plus COMET reference design. In addition it shows the interconnection between the various blocks. 7.1.2 COMET BLOCK, Sheets 2-9 These sheets show the COMET device and its power circuitry. The power circuitry includes a schottky diode for protection while powering up the COMET device and separate filtering circuitry for the analog and digital power pins. In addition, the JTAG port is connected among the 8 COMET devices, and the AAL1gator II. 7.1.3 LINE INTERFACE, Sheets 10-13 These schematics show the termination, magnetics and protection circuitry for the line interface. A 1:2.42 transformer is used to couple the COMET transmit and receive line to the connectors. The LC01-6 transient voltage suppressor (TVS) and the Raychem PTC provide over voltage protection. A single footprint is provided for both the bantam and RJ48C connectors. 7.1.4 FPGA BLOCK, Sheet 14 This sheet shows the interconnection of the FPGA between the AAL1gator II and the COMET devices. Two oscillators are present to supply the XCLK signal to the COMET devices. 0.1uF bulk capacitors are specified, and should be placed at the corners of the FPGA. 7.1.5 MEMORY SYSTEM BLOCK, Sheet 15 This sheet indicates the connections between the system microprocessor, and the AAL1gator II, COMET devices, and FPGA. 20 bit buffers and 16 bit data transceivers are used to minimize part count. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 46 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 7.1.6 AAL1gator II BLOCK, Sheet 16 This sheet shows how the AAL1gator II is connected into the system. A connector is provided to provide access to the UTOPIA bus externally. 7.1.7 MICRO INTERFACE, Sheet 17 This page shows the connections between the system microprocessor, and the board. The LT1528 low drop out voltage regulator provides up to 3A at 3.3V to the 8 COMET devices. The LT1528 should be in the DD package, so that no additional heat sink is required.. Included is a pushbutton to provide a hardware reset. 7.2 TQUAD Version Schematics 7.2.1 ROOT DRAWING, Sheet 1 This sheet provides an overview of the major functional blocks of the AAL1gator II plus TQUAD/EQUAD reference design. In addition it shows the interconnection between the various blocks. 7.2.2 TQUAD/EQUAD BLOCK, Sheets 2,3 These sheets show how to connect a TQUAD or EQUAD into the system. If a T1 line is in use, the PM4344 TQUAD should be used (sheet 2). If an E1 line is in use, the PM6344 EQUAD should be used. Included in the schematics are 0.1 F bulk capacitors, and 0.01F decoupling capacitors. These should be placed at the corners of each device. Also included is 37.056MHz or 49.152MHz oscillator. 7.2.3 AAL1gator II BLOCK, Sheet 4 This schematic diagram is the same as that for the COMET version. 7.2.4 FPGA BLOCK, Sheet 5 This sheet is similar to the COMET version with the following exceptions. First, the 1.544MHz and 2.048MHz oscillator are not present since the TQUAD and EQUAD operate with 37.056MHz and 49.152MHz oscillators. Second, in the COMET version there is an XCLK bus which supplies the individual COMET devices with a 1.544MHz or 2.048MHz clock signal. This signal is not required by the TQUAD or EQUAD and is not supplied. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 47 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 7.2.5 MEMORY SYSTEM BLOCK, Sheet 6 This sheet is identical (with the exception of signal names) to the COMET version. 7.2.6 MICRO INTERFACE BLOCK, Sheet 7 This sheet shows the interconnection between the system microprocessor and the board. Included is a pushbutton to provide a hardware reset. 7.2.7 LIU INTERFACE BLOCK, Sheet 8 This sheet shows how the TQUAD or EQUAD could interface with a Line Interface Unit such as the PM4314 QDSX. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 48 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 8 MODULARIZATION ISSUES Some implementations may require a modular deployment of this reference design. This section describes one possible strategy for creating a modular system based on either the AAL1gator II plus COMET or AAL1gator II plus TQUAD/EQUAD reference design. The strategy developed involves separating the AAL1gator II from the desired framer device (COMET or TQUAD/EQUAD). In this way, one card would contain the AAL1gator II, the FPGA, and microprocessor and memory system as indicated in Figure 16 on the next page. As can be seen, this modularization requires breaking the connections between the AAL1gator II and COMET or TQUAD/EQUAD and inserting a 96 pin DIN connector. Figure 17 on page 51 indicates the suggested layout for the COMET board, while Figure 18 on page 52 shows the suggested layout for the TQUAD/EQUAD board. The interface between the AAL1gator II board and the board containing either the COMET or TQUAD/EQUAD was standardized as listed in Table 18 on page 53. This table lists the interface connections from the AAL1gator II point of view. The associated signals on the COMET or TQUAD/EQUAD board can be determined using either Figure 17 or Figure 18. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 49 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN FRAMER INTERFACE 96 PIN DIN TCLKO BTCLK BTFP RL_FSYNC(7:0) RL_SER(7:0) RL_CLK(7:0) POWER SUPPLY CLOCK CIRCUITRY FPGA N_CLK DATA (7:0) A(22, 2:0) TL_CLK_EN ADAP_STRB SRTS_DOUT(3:0) SRTS_LINE(3:0) TL_FSYNC(7:0) TL_CLK(7:0) ADAP_STRB TLCLK_OUTPUT_EN N_CLK DATA BUS (15:0) AAL1gator II /OE MEMORY SYSTEM (BUFFERS, XCVRS, SRAM, DECODE LOGIC) ADDRESS BUS (16:0) CONTROL BUS (6:0) TL_SER(7:0) RL_SIG(7:0) TL_SIG(7:0) GND RATM_DATA (7:0) MICROPROCESSOR INTERFACE CONTROL BUS (5:0) ADDRESS BUS (22:0) DATA BUS (15:0) UTOPIA INTERFACE Figure 16. AAL1gator II board. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 50 TATM_DATA (7:0) RATM_EMPTY /RPHY_ADDR /TPHY_ADDR TATM_FULL RATM_SOC TATM_SOC RATM_CLK TATM_CLK RATM_EN TATM_EN PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN LINE INTERFACE PHYSICAL LINE INTERFACE CIRCUITRY PROTECTION, TRANSFORMERS TIP/RING TIP/RING TIP/RING TIP/RING TIP/RING TIP/RING TIP/RING COMET0 COMET1 TIP/RING COMET2 COMET3 COMET4 COMET5 COMET6 COMET7 ADDRESS (9:0) CONTROL BUS (12:0) DATA BUS (7:0) One bit of these signals each go to their respective COMET device. For example, BTFP(0) connects to COMET0. BUFFERS/XCVRs DECODE LOGIC BRPCM (7:0) BTPCM (7:0) TCLKO (7:0) BRCLK (7:0) BTCLK (7:0) BRSIG (7:0) BTSIG (7:0) BRFP (7:0) BTFP (7:0) MICROPROCESSOR INTERFACE CONTROL BUS (5:0) ADDRESS BUS (22:0) DATA BUS (15:0) FRAMER INTERFACE 96 PIN DIN Figure 17. COMET board. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 51 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN LINE INTERFACE (QDSX, D3MX) RDN(3:0) RCLKO(3:0) RDN(7:4) RDP(3:0) RDP(7:4) TQUAD0 TQUAD1 ADDRESS (9:0) CONTROL BUS (12:0) DATA BUS (7:0) For bits of each signal go to each TQUAD. For example, bits (0:3) go to TQUAD0 while (4:7) go to TQUAD1 BUFFERS/XCVRs DECODE LOGIC BRPCM (7:0) BTPCM (7:0) BRCLK (7:0) TCLKO (7:0) BTCLK (7:0) BRSIG (7:0) BTSIG (7:0) BRFP (7:0) BTFP (7:0) MICROPROCESSOR INTERFACE CONTROL BUS (5:0) ADDRESS BUS (22:0) DATA BUS (15:0) FRAMER INTERFACE 96 PIN DIN Figure 18. TQUAD board. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 52 RCLKO(7:4) TDN(3:0) TCLKO(3:0) TDN(7:4) TCLKO(7:4) TDP(3:0) TDP(7:4) PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN Table 18. PIN NAME TCLK0(7) TCLK0(6) TCLK0(5) TCLK0(4) TCLK0(3) TCLK0(2) TCLK0(1) TCLK0(0) BTFP(7) BTFP(6) BTFP(5) BTFP(4) BTFP(3) BTFP(2) BTFP(1) BTFP(0) BTCLK(7) BTCLK(6) BTCLK(5) BTCLK(4) BTCLK(3) BTCLK(2) BTCLK(1) BTCLK(0) RL_CLK(7) RL_CLK(6) RL_CLK(5) RL_CLK(4) RL_CLK(3) RL_CLK(2) RL_CLK(1) RL_CLK(0) GND AAL1gator II to Framer Interface. PIN TYPE Input (from Framer) PIN NUMBER B(31) B(27) B(23) B(19) B(15) B(11) B(7) B(3) A(7) A(6) A(5) A(4) A(3) A(2) A(1) A(0) A(15) A(14) A(13) A(12) A(11) A(10) A(9) A(8) C(7) C(6) C(5) C(4) C(3) C(2) C(1) C(0) B(30) - B(28), B(26) - B(24), B(22) - B(20), B(18) - B(16), B(14) - B(12), B(10) - B(8), B(6) - B(4), FUNCTION Transmit Clock Output. TCLKO is a clock at the transmit line rate. The FPGA uses this signal to generate the BTFP signal. Output (to Framer) Output Backplane Transmit Frame Pulse (BTFP). In T1 mode, a pulse at least one BTCLK period wide must occur every 193 bits. In E1 mode, it must occur every 256 bits. This signal is generated by the FPGA after passing through either the T1 or E1 pulse generator. Backplane Transmit Clock (BTCLK). The signal may be 1.544 MHz, or a multiple of 2.048 MHz. The source of the signal is determined by register settings of the FPGA. Input Receive Line Clock. A 1.544 or 2.048 MHz clock signal derived from the recovered line rate timing. n/a GND. Ground Reference. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 53 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN PIN NAME RL_FSYNC(7) RL_FSYNC(6) RL_FSYNC(5) RL_FSYNC(4) RL_FSYNC(3) RL_FSYNC(2) RL_FSYNC(1) RL_FSYNC(0) RL_SIG(7) RL_SIG(6) RL_SIG(5) RL_SIG(4) RL_SIG(3) RL_SIG(2) RL_SIG(1) RL_SIG(0) RL_SER(7) RL_SER(6) RL_SER(5) RL_SER(4) RL_SER(3) RL_SER(2) RL_SER(1) RL_SER(0) TL_SIG(7) TL_SIG(6) TL_SIG(5) TL_SIG(4) TL_SIG(3) TL_SIG(2) TL_SIG(1) TL_SIG(0) TL_SER(7) TL_SER(6) TL_SER(5) TL_SER(4) TL_SER(3) TL_SER(2) TL_SER(1) TL_SER(0) PIN TYPE Input Input Input Output Output PIN NUMBER B(2) - B(0) C(15) C(14) C(13) C(12) C(11) C(10) C(9) C(8) C(23) C(22) C(21) C(20) C(19) C(18) C(17) C(16) C(31) C(30) C(29) C(28) C(27) C(26) C(25) C(24) A(23) A(22) A(21) A(20) A(19) A(18) A(17) A(16) A(31) A(30) A(29) A(28) A(27) A(26) A(25) A(24) FUNCTION Receive Line Frame Synchronization (RL_FSYNC) carry receive frame information from the framer. Receive Line Signaling (RL_SIG) bits. RL_SIG carries the CAS signaling information from the framers. Receive Line Serial Data (RL_SER) bits. RL_SIG carries the receive data from the framers. Transmit Line Signaling (TL_SIG) bits. TL_SIG carries the CAS signaling outputs to the framer devices. Transmit Line Serial Data (TL_SER). TL_SER carries the serial data to the framer devices. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 54 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 9 REFERENCES 1. PMC-Sierra, PMC-970624, "PM4351 COMET Combined E1/T1 Transceiver/Framer", November 1998, Issue 5. 2. PMC-Sierra, PMC-940910, "PM4344 TQUAD Quadruple T1 Framer", June 1998, Issue 7. 3. PMC-Sierra, PMC-980620, "PM73121 AAL1gator II AAL1 Segmentation and Reassembly Processor Data Sheet", December 1998, Issue 2. 4. PMC-Sierra, PMC-951013, "PM6344 EQUAD Quadruple E1 Framer", June 1998, Issue 5. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 55 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 10 APPENDIX A: BILL OF MATERIALS (COMET VERSION) Table 19. COMET version Bill of Materials. PART NUMBER ECU-V1H102KBN MANUFACTURER REF DES QTY PANASONIC C2, C3, C5, C6, C9-C11, 104 C13, C16-C18, C20,C21, C23, C24, C27-C29,C31, C34-C36, C38, C39,C41, C42, C45-C47, C49, C52-C54, C56, C57,C59, C60, C63-C65, C67, C69-C71, C74, C75,C77, C78, C81-C83, C85, C88-C90, C92, C93,C95, C96, C99-C101, C103, C106-C108, C110,C111, C113, C114, C117-C119, C121, C124-C126, C128, C129, C131, C132, C135-C137, C139, C142- C144, C155C162, C171-C173, C190-C194 44 PANASONIC C8, C14, C15, C26, C32, C33, C44, C50, C51, C62, C68, C72, C80, C86, C87, C98, C104, C105, C116, C122, C123, C134, C140, C141, C163-C170, C174-C180, C185-C189 PANASONIC C1, C19, C37, C55, C73, 9 C91, C109, C127, C183 PANASONIC PANASONIC PANASONIC C182 C153, C154 C4, C12, C22, C30, C40, C48, C58, C66, C76, C84, C94, C102, C112, C120, C130, C138 C145-C152 1 2 16 DESCRIPTION CAPACITOR, 0.01UF, 50V, X7R_805 CAPACITOR, 0.1UF, ECJ-2VB1E104K 50V, X7R_805 CAPACITOR, 0.47UF, 25V, TANT TEH CAPACITOR, 1.0UF, 16V, Y5V_805 CAPACITOR, 22PF, 50V, NPO_805 CAPACITOR, 22UF, 6.3V, TANT TEH ECS-H1EY474R ECJ-2VF1C105Z ECU-V1H220JCN EEV-FC0J221P CAPACITOR, 4.7UF, ECS-H1AX475R 10V, PANASONIC 8 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 56 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN DESCRIPTION TANT TEH CAPACITOR, 47UF, 10V, TANT TEH CAPACITOR, 68UF, 6.3V, TANT TEH DIODE, 1N5817, MELF LED SUPERGREEN, SURFACE MOUNT FUSE, 1.500A RJ-48 SMA-BASE BANTAM-BASE, BLACK HEADER2 100 MIL BASE HEADER5 100 MIL BASE HEADER6 100 MIL BASE HEADER10 100 MIL BASE DIN96 MALE-BASE 2x20 MALE, BASE RESISTOR, 1.0, 1%, 805 PART NUMBER ECS-H1AD476R MANUFACTURER PANASONIC REF DES C181, 184, C195-C197 QTY 5 ECS-H0JD686R- PANASONIC C7, C25, C43, C61, C79, C97, C115, C133 D1-D8 D9, D10 F1 J2, J5, J8, J11, J14, J17, J20, J23 J26 J1, J3, J4, J6, J7, J9, J10, J12, J13, J15, J16, J18, J19, J21, J22, J24 JP1, JP2 J25, J29 J30 J27, J28 P1 P2 R13-R15, R19-R21, R25R27, R31-R33, R37-R39, R43-R45, R49-R51, R55R57 R67-R70, R77-R80, R88R91, R100-R103 R17, R23, R29, R35, R41, R47, R53, R59, R66 R8 R60, R61, R63, R64, R71-R74, R82, R84, R85, R92-R94, R96, R97 R62, R65, R75, R81, 8 1N5817MCT 7002X5 F1T66CT-ND 95001-9841 901-144 PC834 DIODES INC INDUSTRIAL DEVICES LITTLEFUSE MOLEX AMPHENOL ADC 8 2 1 8 1 16 640452-2 640452-5 640452-6 1-640452-0 650473-5 87331-4020 ERJ-6RQF1.0V AMP AMP AMP AMP AMP MOLEX PANASONIC 1 2 1 2 1 1 24 RESISTOR, 100, 5%, 603 RESISTOR, 100K, 5%, 805 RESISTOR, 10K, 5%, 805 RESISTOR, 12.7, 1%, 603 RESISTOR, ERJ-3GSY100 ERJ-6GEY100K PANASONIC PANASONIC 16 9 ERJ-6GEY10K ERJ-3EK712.7V PANASONIC PANASONIC 1 16 ERJ-3EK718.2V PANASONIC 8 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 57 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN DESCRIPTION 18.2, 1%, 603 RESISTOR, 1K0, 5%, 805 RESISTOR, 270, 5%, 805 RESISTOR, 330, 5%, 805 PART NUMBER ERJ-6GEY1K0 ERJ-6GEY270 ERJ-6GEY330 MANUFACTURER PANASONIC PANASONIC PANASONIC REF DES R83, R86, R95, R98 R3 R1, R2 R5, R7, R104-R108, R115, R116, R119, R122, R125, R128, R131, R134, R148 R12, R18, R24, R30, R36, R42, R48, R54 R4, R6, R16, R22, R28, R34, R40, R46, R52, R58, R117, R118, R120, R138-143, R149 R145-R147 RN6 RN3-RN5 RN1, RN2 SW1 T1-T4, T7-T10, T13-T16, T19-T22 T5, T6, T11, T12, T17, T18, T23, T24 TR1-TR32 TP1-TP4 U1 U2-U9 U10 U11 U12 U13 U14 QTY 1 2 17 RESISTOR, 4.7, 5%, 805 RESISTOR, 4.7K, 5%, 805 ERJ-6GEY4.7 ERJ-6GEY4K7 PANASONIC PANASONIC 8 20 RESISTOR, 49.9, 1%, 805 RESISTOR ARRAY 4K7, SMD RESISTOR ARRAY, 10K, SMD RESISTOR ARRAY, 68, SMD SWITCH, NO PB, 6MM, VERT TRANSFORMER, 1:2.42 TRANSFORMER ERJ-6ENF49.9V 766161472G 742163103J 742163680J EVQ-PAG04K MI50436 PE68624 PANASONIC CTS CTS CTS PANASONIC MIDCOM PULSE ENGINEERING RAYCHEM SULLINS ELECTRONICS PMC-SIERRA PMC-SIERRA TEXAS INSTRUMENTS MOTOROLA ACTEL TEXAS INSTRUMENTS MAXIM 3 1 3 2 1 16 8 32 4 1 8 1 1 1 1 1 THERMISTOR, PTC TR250-180U TEST_POINT PZC36SAAN IC, AAL1GATOR II QFP IC, COMET, CABGA IC, CMOS QUAD NAND GATE, SOIC IC, CMOS 3 to 8 DECODER, SOIC IC, FPGA, PQFP IC, CMOS HEX INVERTER, SOIC IC, POWER SUPPLY MONITOR, PM73121-RI-P PM4351-NI SN74HCT08 MC74HC T138AD A1425A-PQ-160C SN74HCT 04D MAX701ESA PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 58 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN DESCRIPTION SOIC8 IC, TVS DIODE ARRAY, SOIC8 IC, TVS, SO-16W IC, 3.3V PRECISON VOLTAGE REGULATOR, DD PACKAGE IC, FAST 20 BIT BUFFER, SOP IC FAST 16 BIT TRANSCEIVER, SOP IC 1MB SRAM, 10NS, TSOP TTL OSC, 1.544MHZ, 32PPM TTL OSC, 2.048MHz, 50PPM PART NUMBER SRDA3.3_4 LC01-6 LT1528 MANUFACTURER SEMTECH SEMTECH LINEAR TECHNOLOGIES REF DES U18, U19, U24, U25, U30, U31, U36, U37 U20-U23, U26-U29, U32U35, U38-U41 U42 QTY 8 16 1 IDT74FCT162827CT IDT IDT74FCT162646CT IDT U44, U46 U45, U49 2 2 KM681002B-10 K1125BA K1150BA SAMSUNG CHAMPION CHAMPION U47, U48 Y2 Y5 2 1 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 59 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 11 APPENDIX B: BILL OF MATERIALS (TQUAD/EQUAD VERSION) Table 20. TQUAD/EQUAD version Bill of Materials. PART NUMBER ECU-V1H102KBN MANUFACTURER REF DES PANASONIC C1, C6-C10, C15C22, C31-C33, C37C40, C54-C58 PANASONIC C2-C5, C11-C14, C23-C30, C34, C43C53 PANASONIC C42 QTY 26 DESCRIPTION CAPACITOR, 0.01UF, 50V, X7R_805 CAPACITOR, 0.1UF, 50V, X7R_805 CAPACITOR, 1.0UF, 16V, Y5V_805 CAPACITOR, 47UF, 10V, TANT TEH LED SUPERGREEN, SURFACE MOUNT SMA-BASE HEADER2 100 MIL-BASE HEADER5 100 MIL-BASE HEADER6 100 MIL-BASE HEADER10, 100 MIL BASE DIN96 MALE-BASE 2x20 MALE, BASE RESISTOR, 1K, 5%, 805 RESISTOR, 270, 5%, 805 RESISTOR, 10K, 5%, 805 RESISTOR, 330, 5%, 805 RESISTOR, 4.7K, 5%, 805 RESISTOR, ECJ-2VB1E104K 28 ECJ-2VF1C105Z 1 ECS-H1AD476R PANASONIC C41 1 7002X5 INDUSTRIAL DEVICES AMPHENOL AMP AMP AMP AMP AMP MOLEX PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC D1 1 901-144 640452-2 640452-5 640452-6 1-640452-0 650473-5 87331-4020 ERJ-3GSY1K0 ERJ-3GSY270 ERJ-6GEY10K ERJ-6GEY330 ERJ-6GEY4K7 J1 JP1, JP2 J2 J3, J7 J4-J6 P2, P3 P1, P4, P5 R1 R18 R3 R4, R6, R11-R15 R2, R5, R8-R10, R16, R17, R19-R21, R25R29 R22-R24 1 2 1 2 3 2 3 1 1 1 7 15 ERJ-6ENF49.9V PANASONIC 3 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 60 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN DESCRIPTION 49.9, 1%, 805 RESISTOR ARRAY, 10K, SMD RESISTOR ARRAY, 4K7, SMD RESISTOR ARRAY, 68, SMD SWITCH, NO PB, 6MM, VERT IC, AAL1GATOR II QFP IC, TQUAD IC, EQUAD IC, CMOS QUAD NAND GATE, SOIC IC, CMOS 3 to 8 DECODER, SOIC IC, FPGA, PQFP IC, CMOS HEX INVERTER, SOIC IC, FAST 20 BIT BUFFER, SOP IC FAST 16 BIT TRANSCEIVER, SOP IC, POWER SUPPLY MONITOR IC 1MB SRAM, 10NS, TSOP TTL OSC, 37.056 MHz, 32/50 TTL 0SC 49.152 MHz, 32/50 PART NUMBER 742163103J 766161472G 742163680J EVQ-PAG04K PM73121-RI-P PM4344 -R1 PM6344 -R1 SN74HCT08 MC74HC T138AD A1425A-PQ-160C SN74HCT 04D MANUFACTURER CTS CTS CTS PANASONIC PMC-SIERRA PMC-SIERRA PMC-SIERRA TEXAS INSTRUMENTS MOTOROLA REF DES RN2-RN4 RN5 RN1 SW1 U1 U2 U3 U5 U13 U12 U4, U14, U15 U7, U10 U6, U11 QTY 3 1 1 1 1 1 1 1 1 1 3 2 2 ACTEL TEXAS INSTRUMENTS IDT74FCT162827CT IDT IDT74FCT162646CT IDT MAX701ESA MAXIM U16 1 KM681002B-10 K1125BA K1125BA SAMSUNG CHAMPION CHAMPION U8, U9 Y1 Y2 2 1 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 61 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 12 APPENDIX C: AAL1GATOR II PLUS COMET SCHEMATIC DIAGRAM PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 62 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 13 APPENDIX D: SCHEMATIC DIAGRAM (TQUAD/EQUAD VERSION) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 63 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 14 APPENDIX E: SAMPLE VHDL CODE Note: The module adapt_clk is not provided in this document. The module is available from PMC-Sierra, Inc. on a special zero fee license. Please contact PMC-Sierra for additional information. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 64 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN -- -------------------------------------------------------------------- -------------------------------------------------------------------- PMC-Sierra, Inc. -- PROPRIETARY AND CONFIDENTIAL --- Copyright 1999 PMC-Sierra, Inc. --- All rights reserved. No part of this documentation or computer -- program may be used, modified, reproduced, or distributed in any -- form by any means without the prior written permission of -- PMC-Sierra, Inc. --- This documentation and computer program contains trade secrets, -- confidential business information and commercial or financial -- information (collectively, the "Information") of PMC-Sierra, Inc., -- or unlawful disclosure of any or all of the Information may cause -- irreparable harm and result in significant commercial and -- competitive loss to PMC-Sierra, Inc. -- -------------------------------------------------------------------- -------------------------------------------------------------------- PMC-Sierra, Inc. -- 105 - 8555 Baxter Place -- Burnaby, B.C. -- Canada V5A 4V7 -- Tel: 604-415-6000 -- Fax: 604-415-6206 -- email: apps@pmc-sierra.com -- -------------------------------------------------------------------- Project : PMC-990206 -- File Name : aal1gator_top.vhd -- Path : -- Designer : SW --- Revision History -- Issue Date Initials Description -- 1 03/23/99 SW Initial Release --- Function -- This is the top level of the VHDL code required for the AAL1gator II -- reference design. The code instantiates several modules, and -- creates various multiplexers. ---------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 65 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN library aal1_lib; use aal1_lib.all; entity aal1gator_top is port ( tl_fsync_btfp : out std_logic_vector (7 downto 0) := "ZZZZZZZZ"; tl_clkio : inout std_logic_vector (7 downto 0) := "ZZZZZZZZ"; btclk : out std_logic_vector (7 downto 0) := "ZZZZZZZZ"; xclk : out std_logic_vector (7 downto 0); srts_dout : in std_logic_vector (3 downto 0) := "0000"; srts_line : in std_logic_vector (3 downto 0) := "0000"; adap_strb : in std_logic := '0'; cs3b : in std_logic := '1'; rdb : in std_logic := '1'; resetb : in std_logic := '1'; wrb : in std_logic := '1'; network_clk : in std_logic := '0'; Eclk : in std_logic := '0'; --2.048 MHz source Tclk : in std_logic := '0'; --1.544 MHz source n_clk : out std_logic := '0'; aal1_sysclk : out std_logic := '0'; fpga_data : inout std_logic_vector (7 downto 0) := "ZZZZZZZZ"; fpga_add : in std_logic_vector (2 downto 0) := "ZZZ" ); end aal1gator_top; architecture aal1gator_top_arch of aal1gator_top is component div16 port ( clk_in : in std_logic; resetb : in std_logic; clk_out : out std_logic ); end component; component frame_genE port ( clk_in : in std_logic; resetb : in std_logic; frame_out : out std_logic; pre_frame_out : out std_logic ); end component; component frame_genT port ( PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 66 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN clk_in : in std_logic; resetb : in std_logic; frame_out : out std_logic; pre_frame_out : out std_logic ); end component; component microport port ( CS3B : in std_logic; WRB : in std_logic; RDB : in std_logic; RESETB : in std_logic; IO: inout std_logic_vector (7 downto 0) := "ZZZZZZZZ"; address: in std_logic_vector (2 downto 0) := "ZZZ"; source_select :out std_logic_vector (7 downto 0); n_clk : out std_logic_vector (7 downto 0); xclk : out std_logic_vector (7 downto 0); clk : in std_logic ); end component; -- Note 1. The following block is not provided with this code. It is -- available from PMC-Sierra with a special zero fee license. -- Please contact PMC-Sierra for further information. -- Note 2. The module (as tested in this application) has been -- modified such that the top level entity is as shown in the following -- component declaration. This was done to remove the SRTS code -- which is not required in this example. component adapt_clk port ( clk3888: in std_logic; srts_dout: in std_logic_vector(3 downto 0); srts_line: in std_logic_vector(3 downto 0); adap_strobe: in std_logic; -- if 1, use T1 mode, else E1 t1_mode: in std_logic_vector(7 downto 0); reset: in std_logic; -- when 1 reset tclk: out std_logic_vector(7 downto 0) ); end component; signal tl_clki : std_logic_vector (7 downto 0); PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 67 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN signal tl_clko : std_logic_vector (7 downto 0); --Source Mux out connects to BTCLK signal source_mux_out : std_logic_vector (7 downto 0); signal reset : std_logic := '0'; --Pulse generator outputs signal Tpulse_out : std_logic_vector (7 downto 0); signal Epulse_out : std_logic_vector (7 downto 0); signal pre_Tpulse_out : std_logic_vector (7 downto 0); signal pre_Epulse_out : std_logic_vector (7 downto 0); --Source select determines signal source_select : std_logic_vector(7 downto 0); signal adapt_clk_out : std_logic_vector(7 downto 0); -- connects output of pulse gens to output pins signal tl_fsync_btfp_sig : std_logic_vector (7 downto 0); -- control register that sets the XCLK source -- only required in AAL1gator II plus COMET implementations signal xclk_reg : std_logic_vector (7 downto 0); -- controls the n_clk multiplexer signal nclk_reg : std_logic_vector (7 downto 0); -- Input signal to n_clk mux signal n_clk_mux_in : std_logic; signal btclk_sig : std_logic_vector (7 downto 0); begin -- divides the network_clk by 16 (out = 2.43MHz) divider : div16 port map ( clk_in => network_clk, resetb => resetb, clk_out => n_clk_mux_in ); adaptive : adapt_clk port map ( clk3888 => network_clk, srts_dout => srts_dout, PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 68 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN srts_line => srts_line, adap_strobe => adap_strb, t1_mode => xclk_reg, reset => reset, tclk => adapt_clk_out ); Micro : microport port map ( CS3B => cs3b, WRB => wrb, RDB => rdb, RESETB => resetb, IO => fpga_data, address => fpga_add, source_select => source_select, n_clk => nclk_reg, xclk => xclk_reg, clk => network_clk ); --The following 16 blocks produce a pulse every 193 bits -- (if T1) or 256 bits if E1. Eblock0 : frame_genE port map ( clk_in => btclk_sig(0), resetb => resetb, frame_out => Epulse_out(0), pre_frame_out => pre_Epulse_out(0) ); Eblock1 : frame_genE port map ( clk_in => btclk_sig(1), resetb => resetb, frame_out => Epulse_out(1), pre_frame_out => pre_Epulse_out(1) ); Eblock2 : frame_genE port map ( clk_in => btclk_sig(2), resetb => resetb, frame_out => Epulse_out(2), pre_frame_out => pre_Epulse_out(2) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 69 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN ); Eblock3 : frame_genE port map ( clk_in => btclk_sig(3), resetb => resetb, frame_out => Epulse_out(3), pre_frame_out => pre_Epulse_out(3) ); Eblock4 : frame_genE port map ( clk_in => btclk_sig(4), resetb => resetb, frame_out => Epulse_out(4), pre_frame_out => pre_Epulse_out(4) ); Eblock5 : frame_genE port map ( clk_in => btclk_sig(5), resetb => resetb, frame_out => Epulse_out(5), pre_frame_out => pre_Epulse_out(5) ); Eblock6 : frame_genE port map ( clk_in => btclk_sig(6), resetb => resetb, frame_out => Epulse_out(6), pre_frame_out => pre_Epulse_out(6) ); Eblock7 : frame_genE port map ( clk_in => btclk_sig(7), resetb => resetb, frame_out => Epulse_out(7), pre_frame_out => pre_Epulse_out(7) ); Tblock0 : frame_genT port map ( clk_in => btclk_sig(0), resetb => resetb, frame_out => Tpulse_out(0), PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 70 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN pre_frame_out => pre_Tpulse_out(0) ); Tblock1 : frame_genT port map ( clk_in => btclk_sig(1), resetb => resetb, frame_out => Tpulse_out(1), pre_frame_out => pre_Tpulse_out(1) ); Tblock2 : frame_genT port map ( clk_in => btclk_sig(2), resetb => resetb, frame_out => Tpulse_out(2), pre_frame_out => pre_Tpulse_out(2) ); Tblock3 : frame_genT port map ( clk_in => btclk_sig(3), resetb => resetb, frame_out => Tpulse_out(3), pre_frame_out => pre_Tpulse_out(3) ); Tblock4 : frame_genT port map ( clk_in => btclk_sig(4), resetb => resetb, frame_out => Tpulse_out(4), pre_frame_out => pre_Tpulse_out(4) ); Tblock5 : frame_genT port map ( clk_in => btclk_sig(5), resetb => resetb, frame_out => Tpulse_out(5), pre_frame_out => pre_Tpulse_out(5) ); Tblock6 : frame_genT port map ( clk_in => btclk_sig(6), resetb => resetb, PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 71 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN frame_out => Tpulse_out(6), pre_frame_out => pre_Tpulse_out(6) ); Tblock7 : frame_genT port map ( clk_in => btclk_sig(7), resetb => resetb, frame_out => Tpulse_out(7), pre_frame_out => pre_Tpulse_out(7) ); btclk_sig <= not source_mux_out; -- If the application involves the TQUAD/EQUAD device, the following line -- should be uncommented. -- btclk <= not source_mux_out; -- If the application involves the COMET device the following line -- should be commented out btclk <= source_mux_out; -- if the application uses a mix of TQUAD/EQUAD and COMETS, invert the -- source_mux_out bit lines that connect to TQUAD or EQUAD devices. Leave -- lines connecting to COMET lines uninverted. tl_fsync_btfp <= tl_fsync_btfp_sig; -- The following mux set the output signal that eventually connects -- to the framer BTCLK signal. The option is a signal from the -- AAL1gator II (TL_CLKI) or an external source. source_mux_out(7) <= adapt_clk_out(7) when source_select(7) = '1' else tl_clkio(7); source_mux_out(6) <= adapt_clk_out(6) when source_select(6) = '1' else tl_clkio(6); source_mux_out(5) <= adapt_clk_out(5) when source_select(5) = '1' else tl_clkio(5); source_mux_out(4) <= adapt_clk_out(4) when source_select(4) = '1' else tl_clkio(4); source_mux_out(3) <= adapt_clk_out(3) when source_select(3) = '1' PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 72 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN else tl_clkio(3); source_mux_out(2) <= adapt_clk_out(2) when source_select(2) = '1' else tl_clkio(2); source_mux_out(1) <= adapt_clk_out(1) when source_select(1) = '1' else tl_clkio(1); source_mux_out(0) <= adapt_clk_out(0) when source_select(0) = '1' else tl_clkio(0); --The following signals set the output value of the bidir pin TL_CLKIO. --When high Z, any signal driven onto the tl_clkio pin externally will --be passed through by virue of the vhdl resolution function. --IMPORTANT NOTE 1: When switching between having the AAL1gator II source, to --having the FPGA source, the following steps must be taken: -1) Configure AAL1gator II to receive external clock (via clk_source(5:4)) -2) Configure FPGA to source external clk via tl_clkio ---IMPORTANT NOTE 2: When switching between having the FPGA source, to --having the AAL1gator II source, the following steps must be taken: -1) Configure FPGA to receive external clock tl_clkio -2) Configure AAL1gator II to source via clk_source(5:4) tl_clkio(7) <= adapt_clk_out(7) when source_select(7) = '1' else 'Z'; tl_clkio(6) <= adapt_clk_out(6) when source_select(6) = '1' else 'Z'; tl_clkio(5) <= adapt_clk_out(5) when source_select(5) = '1' else 'Z'; tl_clkio(4) <= adapt_clk_out(4) when source_select(4) = '1' else 'Z'; tl_clkio(3) <= adapt_clk_out(3) when source_select(3) = '1' else 'Z'; tl_clkio(2) <= adapt_clk_out(2) when source_select(2) = '1' else 'Z'; tl_clkio(1) <= adapt_clk_out(1) when source_select(1) = '1' else 'Z'; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 73 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN tl_clkio(0) <= adapt_clk_out(0) when source_select(0) = '1' else 'Z'; -- The following mux determines which pulse generator source should be used -- on a per line basis. tl_fsync_btfp_sig(7) <= Epulse_out(7) when xclk_reg(7) = '0' else Tpulse_out(7); tl_fsync_btfp_sig(6) <= Epulse_out(6) when xclk_reg(6) = '0' else Tpulse_out(6); tl_fsync_btfp_sig(5) <= Epulse_out(5) when xclk_reg(5) = '0' else Tpulse_out(5); tl_fsync_btfp_sig(4) <= Epulse_out(4) when xclk_reg(4) = '0' else Tpulse_out(4); tl_fsync_btfp_sig(3) <= Epulse_out(3) when xclk_reg(3) = '0' else Tpulse_out(3); tl_fsync_btfp_sig(2) <= Epulse_out(2) when xclk_reg(2) = '0' else Tpulse_out(2); tl_fsync_btfp_sig(1) <= Epulse_out(1) when xclk_reg(1) = '0' else Tpulse_out(1); tl_fsync_btfp_sig(0) <= Epulse_out(0) when xclk_reg(0) = '0' else Tpulse_out(0); -- The following mux is only required in applications involving the COMET -- device. It sets the XCLK source signal to each COMET. xclk(7) <= Tclk when xclk_reg(7) = '1' else Eclk; xclk(6) <= Tclk when xclk_reg(6) = '1' else Eclk; xclk(5) <= Tclk when xclk_reg(5) = '1' else Eclk; xclk(4) <= Tclk when xclk_reg(4) = '1' PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 74 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN else Eclk; xclk(3) <= Tclk when xclk_reg(3) = '1' else Eclk; xclk(2) <= Tclk when xclk_reg(2) = '1' else Eclk; xclk(1) <= Tclk when xclk_reg(1) = '1' else Eclk; xclk(0) <= Tclk when xclk_reg(0) = '1' else Eclk; -- Sets n_clk to be either 2.43 MHz (SRTS enabled) or GND -- (SRTS disabled). n_clk <= n_clk_mux_in when nclk_reg(7) = '1' else '0'; end aal1gator_top_arch; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 75 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN -- -------------------------------------------------------------------- -------------------------------------------------------------------- PMC-Sierra, Inc. -- PROPRIETARY AND CONFIDENTIAL --- Copyright 1999 PMC-Sierra, Inc. --- All rights reserved. No part of this documentation or computer -- program may be used, modified, reproduced, or distributed in any -- form by any means without the prior written permission of -- PMC-Sierra, Inc. --- This documentation and computer program contains trade secrets, -- confidential business information and commercial or financial -- information (collectively, the "Information") of PMC-Sierra, Inc., -- or unlawful disclosure of any or all of the Information may cause -- irreparable harm and result in significant commercial and -- competitive loss to PMC-Sierra, Inc. -- -------------------------------------------------------------------- -------------------------------------------------------------------- PMC-Sierra, Inc. -- 105 - 8555 Baxter Place -- Burnaby, B.C. -- Canada V5A 4V7 -- Tel: 604-415-6000 -- Fax: 604-415-6206 -- email: apps@pmc-sierra.com -- -------------------------------------------------------------------- Project : PMC-990206 -- File Name : frame_genE.vhd -- Path : -- Designer : SW --- Revision History -- Issue Date Initials Description -- 1 03/23/99 SW Initial Release --- Function -- This module generates an output pulse 1 clk period wide every 256 bits ---------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity frame_genE is port( clk_in : in std_logic; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 76 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN resetb : in std_logic; frame_out : out std_logic; pre_frame_out : out std_logic ); end frame_genE; architecture frame_genE_arch of frame_genE is --every 256 bits output a frame pulse 1 clk_out cycle wide constant frame_count_max : integer := 256; begin --a frame pulse, 1 cycle clk_out wide is generated every 256 bits gen_framepulse : process(clk_in, resetb) variable count_frame: integer := 1; begin if resetb = '0' then count_frame := 1; frame_out <= '0'; pre_frame_out <= '0'; elsif (clk_in'event and clk_in = '0') then --falling edge if count_frame = (frame_count_max - 1) then pre_frame_out <= '1'; frame_out <= '0'; count_frame := count_frame + 1; elsif count_frame = frame_count_max then pre_frame_out <= '0'; frame_out <= '1'; count_frame := 1; else count_frame := count_frame + 1; frame_out <= '0'; pre_frame_out <= '0'; end if; end if; end process; end frame_genE_arch; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 77 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN -- -------------------------------------------------------------------- -------------------------------------------------------------------- PMC-Sierra, Inc. -- PROPRIETARY AND CONFIDENTIAL --- Copyright 1999 PMC-Sierra, Inc. --- All rights reserved. No part of this documentation or computer -- program may be used, modified, reproduced, or distributed in any -- form by any means without the prior written permission of -- PMC-Sierra, Inc. --- This documentation and computer program contains trade secrets, -- confidential business information and commercial or financial -- information (collectively, the "Information") of PMC-Sierra, Inc., -- or unlawful disclosure of any or all of the Information may cause -- irreparable harm and result in significant commercial and -- competitive loss to PMC-Sierra, Inc. -- -------------------------------------------------------------------- -------------------------------------------------------------------- PMC-Sierra, Inc. -- 105 - 8555 Baxter Place -- Burnaby, B.C. -- Canada V5A 4V7 -- Tel: 604-415-6000 -- Fax: 604-415-6206 -- email: apps@pmc-sierra.com -- -------------------------------------------------------------------- Project : PMC-990206 -- File Name : frame_genT.vhd -- Path : -- Designer : SW --- Revision History -- Issue Date Initials Description -- 1 03/23/99 SW Initial Release --- Function -- This module generates an output pulse 1 clk period wide every 193 bits ---------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity frame_genT is port( clk_in : in std_logic; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 78 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN resetb : in std_logic; frame_out : out std_logic; pre_frame_out : out std_logic ); end frame_genT; architecture frame_genT_arch of frame_genT is --every 193 bits output a frame pulse 1 clk_out cycle wide constant frame_count_max : integer := 193; begin --a frame pulse, 1 cycle clk_out wide is generated every 193 bits gen_framepulse : process(clk_in, resetb) variable count_frame: integer := 1; begin if resetb = '0' then count_frame := 1; frame_out <= '0'; pre_frame_out <= '0'; elsif (clk_in'event and clk_in = '0') then --falling edge if count_frame = (frame_count_max - 1) then pre_frame_out <= '1'; frame_out <= '0'; count_frame := count_frame + 1; elsif count_frame = frame_count_max then pre_frame_out <= '0'; frame_out <= '1'; count_frame := 1; else count_frame := count_frame + 1; frame_out <= '0'; pre_frame_out <= '0'; end if; end if; end process; end frame_genT_arch; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 79 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN -- -------------------------------------------------------------------- -------------------------------------------------------------------- PMC-Sierra, Inc. -- PROPRIETARY AND CONFIDENTIAL --- Copyright 1999 PMC-Sierra, Inc. --- All rights reserved. No part of this documentation or computer -- program may be used, modified, reproduced, or distributed in any -- form by any means without the prior written permission of -- PMC-Sierra, Inc. --- This documentation and computer program contains trade secrets, -- confidential business information and commercial or financial -- information (collectively, the "Information") of PMC-Sierra, Inc., -- or unlawful disclosure of any or all of the Information may cause -- irreparable harm and result in significant commercial and -- competitive loss to PMC-Sierra, Inc. -- -------------------------------------------------------------------- -------------------------------------------------------------------- PMC-Sierra, Inc. -- 105 - 8555 Baxter Place -- Burnaby, B.C. -- Canada V5A 4V7 -- Tel: 604-415-6000 -- Fax: 604-415-6206 -- email: apps@pmc-sierra.com -- -------------------------------------------------------------------- Project : PMC-990206 -- File Name : micrport.vhd -- Path : -- Designer : SW --- Revision History -- Issue Date Initials Description -- 1 03/23/99 SW Initial Release --- Function -- This module creates a port for which the microprocessor communicates -- with in order to set the function of the FPGA. --------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity MICROPORT is PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 80 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN port ( CS3B : in std_logic; WRB : in std_logic; RDB : in std_logic; RESETB : in std_logic; IO: inout std_logic_vector (7 downto 0) := "ZZZZZZZZ"; address: in std_logic_vector (2 downto 0) := "ZZZ"; source_select :out std_logic_vector (7 downto 0); n_clk : out std_logic_vector (7 downto 0); xclk : out std_logic_vector (7 downto 0); clk : in std_logic ); end MICROPORT; architecture MICROPORT_ARCH of MICROPORT is -- setup the control registers: type regtype is array (0 to 2) of std_logic_vector(7 downto 0); signal fpga: regtype := (("11111111"), ("11111111"), ("11111111")); -- utility function to convert std_logic_vectors to intergers function vec2int(vec1: std_logic_vector) return integer is variable retval: integer:= 0; alias vec : std_logic_vector(vec1'length -1 downto 0) is vec1; begin for i in vec'high downto 1 loop if (vec(i) = '1') then retval:= (retval+1)*2; else retval := retval*2; end if; end loop; if vec(0) = '1' then retval := retval + 1; end if; return retval; end vec2int; begin process (CS3B) begin if CS3B = '1' then IO <= "ZZZZZZZZ"; else if WRB = '0' then PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 81 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN fpga (vec2int(address)) <= IO; elsif RDB = '0' then IO <= fpga(vec2int(address)); end if; end if; end process; source_select <= fpga(0) after 1 ns; n_clk <= fpga(1) after 1 ns; xclk <= fpga(2) after 1 ns; end MICROPORT_ARCH; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 82 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN -- -------------------------------------------------------------------- -------------------------------------------------------------------- PMC-Sierra, Inc. -- PROPRIETARY AND CONFIDENTIAL --- Copyright 1999 PMC-Sierra, Inc. --- All rights reserved. No part of this documentation or computer -- program may be used, modified, reproduced, or distributed in any -- form by any means without the prior written permission of -- PMC-Sierra, Inc. --- This documentation and computer program contains trade secrets, -- confidential business information and commercial or financial -- information (collectively, the "Information") of PMC-Sierra, Inc., -- or unlawful disclosure of any or all of the Information may cause -- irreparable harm and result in significant commercial and -- competitive loss to PMC-Sierra, Inc. -- -------------------------------------------------------------------- -------------------------------------------------------------------- PMC-Sierra, Inc. -- 105 - 8555 Baxter Place -- Burnaby, B.C. -- Canada V5A 4V7 -- Tel: 604-415-6000 -- Fax: 604-415-6206 -- email: apps@pmc-sierra.com -- -------------------------------------------------------------------- Project : PMC-990206 -- File Name : div16.vhd -- Path : -- Designer : SW --- Revision History -- Issue Date Initials Description -- 1 03/23/99 SW Initial Release --- Function -- This module divides a clock signal by 16 ---------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity div16 is port( clk_in : in std_logic; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 83 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN resetb : in std_logic; clk_out : out std_logic ); end div16; architecture div16_arch of div16 is constant clk_count_max : integer := 8; signal div_clk : std_logic := '0'; begin gen_clock : process(clk_in, resetb) variable clk_count: integer := 0; begin if (resetb = '0') then clk_count := 0; div_clk <= '0'; elsif (clk_in'event and clk_in = '1') then --rising edge clk_count := clk_count + 1; if (clk_count = clk_count_max) then div_clk <= not div_clk; clk_count := 0; end if; end if; end process; clk_out <= div_clk; end div16_arch; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 84 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 15 DISCLAIMER This reference design has not been built or tested. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 85 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN 16 NOTES PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 86 PM73121 AAL1GATOR II REFERENCE DESIGN PMC-990206 ISSUE 3 AAL1GATOR II REFERENCE DESIGN CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com Document Information: Corporate Information: Application Information: Web Site: None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1999 PMC-Sierra, Inc. PMC-990206 Issue date: May 1999 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE |
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