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PMC-Sierra,Inc.
Preliminary
* Supports a glueless interface to the PM4344 TQUAD, PM6344 EQUAD, and PM4351 COMET T1/E1 interface devices. * Supports counters as required by ATM Forum CES 2.0 MIB. * Pin-compatible with the WAC-021-X. * Built-in T1/E1 transmit line clock generation based on received Synchronous Residual Time Stamp (SRTS) values, the received line clock, or a nominal frequency.
PM73121 AAL1gator II
RECEIVE CELL INTERFACE * Provides an ATM-layer or PHY-layer 33 MHz UTOPIA Level 2 interface. Both SPHY and MPHY modes are supported. * Provides per-VC queues with individual CDV tolerance settings and partially filled cell length settings. * Provides per-VC partially filled cell length settings. * Provides a multiplexed interface to external receive Phase-Locked Loops (PLLs) for SRTS clock recovery for unstructured modes or adaptive clock recovery. * Provides a supervisory receive queue and processor interrupts for OAM cell receptions. * Provides sequence number processing in accordance with the "Fast SN Algorithm" as specified in the ITU-T Recommendation I.363.1.
Eight Link Circuit Emulation Service on a Chip
FEATURES
* Performs AAL1 Segmentation And Reassembly (SAR) function on either eight T1/E1 links or a single DS3/E3 link. * Supports 256 Virtual Channels (VCs). * Adheres to the ATM Forum's Circuit Emulation Service (CES) 2.0 (af-vtoa0078.000) specification and ITU-T Recommendation I363.1 for AAL1. * Supports both structured and unstructured data formats selectable on a per-link basis. * Supports both T1 and E1 lines selectable on a per-link basis. * Supports n x 64 structured data format with Common Channel Signaling (CCS) and Channel Associated Signaling (CAS) configuration options. * Supports arbitrary timeslot-to-VC mappings, including alternating timeslots. * Provides per-VC data and signalling conditioning in both the transmit and the receive directions. * Arbitrates a 16-bit microprocessor interface to two 128K x 8 (12 ns) SRAMs. * Supports multicast connections, ATM Monitoring (AMON), Remote Monitoring (RMON), and ATM Circuit Steering (ACS).
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TRANSMIT CELL INTERFACE FEATURES Provides an ATM-layer or PHY-layer 33 MHz UTOPIA Level 2 interface. Both Single PHY (SPHY) and MultiPHY (MPHY) modes are supported. Provides per-VC transmit queueing with individual partially filled cell length settings. Supports a calendar queue service algorithm that produces minimal Cell Delay Variation (CDV). Generates and transmits SRTS values for unstructured modes. Provides a supervisory transmit buffer for Operations, Administration, and Maintenance (OAM) cells, and for ATM signalling.
APPLICATIONS
* ATM Multiservice Switches * ATM Access Concentrators or Multiplexers * Digital Access Cross-Connects * Multiservice Access Devices
BLOCK DIAGRAM
/SCAN_TRST /SCAN_TMS /SCAN_TDI /SCAN_TDO /SCAN_TCLK /SYS_CLK /RESET P_TEST /OE
RL_CLK[7:0] RL_SIG[7:0] RL_SER[7:0] RL_MSYNC[7:0] RL_FSYNC[7:0] N_CLK TL_CLK[7:0] TL_SIG[7:0] TL_SER[7:0] TL_MSYNC[7:0] TL_FSYNC[7:0] TLCLK_OUTPUT_EN
Transmit Frame Transfer Controller (TFTC)
Cell Service Decision (CSD)
JTAG Transmit Adaptation Layer Processor (TALP)
Transmit UTOPIA Interface Block (TUTOPIA)
TATM_CLK TATM_SOC TATM_DATA[7:0] /TATM_EN /TATM_FULL PHY_ENABLE
Receive Frame Transfer Controller (RFTC)
Memory Interface and Arbitration Controller (MIAC)
Receive Adaptation Layer Processor (RALP)
Receive UTOPIA Interface Block (RUTOPIA)
RATM_CLK RATM_SOC RATM_DATA[7:0] /RATM_EN /RATM_EMPTY
SRTS_LINE[3:0]
SRTS_STRB
ADDR17 HOLDOFF /PROC_RD /PROC_WR /PROC_CS /PROC_ACK PROC_INT SP_DATA_CLK SP_DATA_DIR /SP_ADD_EN /SP_DATA_EN MEM_DATA[15:0] MEM_ADDR[16:0]
SRTS_DOUT[3:0]
/MEM_OE /MEM_WE[1:0] /MEM_OE MEM_CS
ADAP_STRB
Configured in ATM Mode Note: The AAL1gator II device contains SRTS logic for which Bellcore holds the patent.
PMC-980621 (P2)
(c)A1998 PMC-Sierra, Inc. September, 1998
Preliminary PM73121 AAL1gator II
Eight Link Circuit Emulation Service on a Chip
TYPICAL APPLICATIONS
EIGHT LINK T1/E1 CIRCUIT EMULATION APPLICATION
AAL5 SAR Processor PM4351 8PH@U Combined T1/E1 Framer/Transceiver PM4351 8PH@U Combined T1/E1 Framer/Transceiver PM4351 8PH@U Combined T1/E1 Framer/Transceiver PM4351 8PH@U Combined T1/E1 Framer/Transceiver PM4351 8PH@U Combined T1/E1 Framer/Transceiver PM4351 8PH@U Combined T1/E1 Framer/Transceiver PM4351 8PH@U Combined T1/E1 Framer/Transceiver PM4351 8PH@U Combined T1/E1 Framer/Transceiver PM73121
66G thADDA
T1/E1
T1/E1
T1/E1
T1/E1
TM
PM5347 Cell Multiplexer
TVID $$QGVTA
T1/E1
AAL1 SAR Processor
TM
SATURN User Network Interface 155-PLUS
OC-3
T1/E1
T1/E1
T1/E1
UTOPIA Bus
CHANNELIZED DS3 PORT CARD FOR MULTISERVICE ATM SWITCH
PM4344
URV69
Quad T1 Framer PM4344
URV69
PM73121
66G thADDA
TM
AAL1 SAR Processor
Quad T1 Framer PM4344
URV69
Quad T1 Framer PM8313 DS3
9"HY
PM73121
66G thADDA
TM
PM4344
URV69
M13 Multiplexer/ Demultiplexer
AAL1 SAR Processor
PM73487
RSUA
TM
PM73488
RT@A
TM
Quad T1 Framer PM4344
URV69
622 Mbit/s ATM Traffic Management Device PM73121
66G thADDA
5 Gbit/s ATM Switch Fabric Element
Quad T1 Framer PM4344
URV69
TM
AAL1 SAR Processor
Quad T1 Framer PM4344
URV69
PM73121
66G thADDA
Quad T1 Framer
TM
AAL1 SAR Processor UTOPIA Bus
Head Office: PMC-Sierra, Inc. #105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200
To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator
All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com
PMC-980621 (P2) (c) 1998 PMC-Sierra, Inc. September, 1998 AAL1gator II, QRT, QSE, and S/UNI-155-PLUS are trademarks of PMC-Sierra, Inc.

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