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PRELIMINARY INFORMATION TECHNICAL OVERVIEW PMC-971016 ISSUE 1
PM7346 S/UNI-QJET
S/UNI-QJET TECHNICAL OVERVIEW
PM7346
Q JE T
S/UNITM-QJET
SATURN QUAD USER NETWORK INTERFACE FOR J2/E3/T3
TECHNICAL OVERVIEW
PRELIMINARY ISSUE 1: OCTOBER 1997
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PRELIMINARY INFORMATION TECHNICAL OVERVIEW PMC-971016 ISSUE 1
PM7346 S/UNI-QJET
S/UNI-QJET TECHNICAL OVERVIEW
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PRELIMINARY INFORMATION TECHNICAL OVERVIEW PMC-971016 ISSUE 1
PM7346 S/UNI-QJET
S/UNI-QJET TECHNICAL OVERVIEW
CONTENTS 1 2 3 INTRODUCTION...................................................................................... 1 APPLICATION EXAMPLES ..................................................................... 3 FUNCTIONAL OVERVIEW ...................................................................... 5 3.1 3.2 3.3 4 RECEIVE OPERATION ................................................................ 6 TRANSMIT OPERATION .............................................................. 7 AUXILIARY BLOCKS .................................................................... 8
J2/E3/T3 FRAMER OVERVIEW............................................................. 10 4.1 4.2 4.3 T3 FRAMER OPERATION .......................................................... 10 E3 FRAMER OPERATION .......................................................... 12 J2 FRAMER OPERATION........................................................... 16
5 6
ATM CELL DELINEATION...................................................................... 18 PLCP FRAME PROCESSING ............................................................... 20 6.1 6.2 6.3 6.4 6.5 T3 PLCP FRAME FORMAT......................................................... 20 DS1 PLCP FRAME FORMAT...................................................... 21 G.751 E3 PLCP FRAME FORMAT.............................................. 21 E1 PLCP FRAME FORMAT ........................................................ 22 PLCP OVERHEAD PROCESSING ............................................. 23
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PRELIMINARY INFORMATION TECHNICAL OVERVIEW PMC-971016 ISSUE 1
PM7346 S/UNI-QJET
S/UNI-QJET TECHNICAL OVERVIEW
1
INTRODUCTION This document provides an overview of PM7346 S/UNI-QJET. Please refer to PMC-960835 S/UNI-QJET Data Sheet for a detailed description of this device. The S/UNI-QJET is a versatile four-channel device that can be used in cell-based and packet-based applications. Each channel has integrated J2, E3, T3 framers and direct cell-mapped or Physical Layer Convergence Protocol (PLCP) framed ATM cell processors as shown in Figure 1:
L ine S id e S ys tem S id e
4 4.7 36 M 3 4.3 68 M 6 .31 2 M u p to 5 2 M 1 .54 4 M 2 .00 0 M T 1 F ra m e r E 1 F ra m e r
T 3 F ra m e r D ire ct Ce ll M o de E 3 F ra m e r P LC P Fra m e M od e J2 F ram er B yp ass B yp ass
C ha nn el 1 of 4 o f S /U N I-Q JE T
U top ia Le ve l 2 In te rfa ce B it S erial In terfa ce
E xte rn al T1 /E1 fra m ers such a s T1 XC , E 1X C, E Q U A D, EQ UA D an d T O CT L
S ele ct on e fram er or b ypa ss mo de on ly
S ele ct Direct C e ll M ap , P LC P or B yp ass M o de
Figure 1: S/UNI-QJET Functional Overview. The flexibility offered by S/UNI-QJET allows each channel to be independently configured as an ATM physical layer device, as a framer, or as a cell delineation device. As an ATM physical layer device, S/UNI-QJET supports T3, E3 and J2 rates using an internal framer in conjunction with either PLCP-framed or direct cell-mapped ATM cell processor. Other rates, such as T1 and E1, can be supported using external framers such as T1XC, TQUAD, TOCTL, E1XC or EQUAD. In the receive direction, the ATM cell processor performs cell descrambling, HCS error detection, idle cell filtering, header descrambling and accumulates the number of idle and assigned cells in one second saturating counters. In the transmit direction, the cell processor performs optional ATM cell scrambling, header scrambling, HCS generation and programmable idle cell insertion. The S/UNI-QJET supports a 50 MHz 8 or 16-bit wide UTOPIA Level 2 compliant interface with parity support and multi-PHY control signals. For each channel, rate decoupling between the line and ATM layer device is provided by a four cell FIFO in transmit and receive directions.
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PRELIMINARY INFORMATION TECHNICAL OVERVIEW PMC-971016 ISSUE 1
PM7346 S/UNI-QJET
S/UNI-QJET TECHNICAL OVERVIEW
As a quad J2/E3/T3 framer, the S/UNI-QJET can generate gapped transmit and receive clocks to allow for a glueless interface to a data link layer device, such as PM7366 FREEDM-8, that access payload data bits only. The S/UNI-QJET provides integral transmit and receive HDLC controllers, with a deep 128 byte FIFO, to process data link messages carry in the T3 C-bit parity, E3 G.832 or J2 G.704 framing format. The S/UNI-QJET can be used as a quad ATM cell delineation device when the internal J2/E3/T3 framers are bypassed and only the cell processing blocks are activated. In this mode, each channel of the S/UNI-QJET can individually support cell rates up to 52 Mbit/s. The available modes are summarized in Table 1: Table 1: Valid S/UNI-QJET Operational Modes. Rate
T3 (44.736 Mbit/s) E3 (34.368 Mbit/s) J2 (6.312 Mbit/s) E1 (2 Mbit/s) T1 (1.544 Mbit/s) Arbitrary Cell Rate (up to 52 Mbit/s)
Format
C-bit Parity M23 G.751 G.832 G.704 & NTT CRC-4 PCM30 ESF SF
Framer Only external external external external bypass
SMDS PLCP Mapping n/a n/a n/a
ATM Direct Mapping
The S/UNI-QJET provides an 8-bit microprocessor interface for configuration, control, and status monitoring. It supports a standard five signal P1149.1 JTAG test port for boundary scan board test purposes. The SUNI-QJET is implemented using low power 3.3V CMOS technology with 5V tolerant inputs. It is available in a high-density 256 pin Super Ball Grid Array (SBGA) package with a physical dimension of 27mm by 27mm.
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PRELIMINARY INFORMATION TECHNICAL OVERVIEW PMC-971016 ISSUE 1
PM7346 S/UNI-QJET
S/UNI-QJET TECHNICAL OVERVIEW
2
APPLICATION EXAMPLES The S/UNI-QJET can be configured as an ATM physical layer device. On the line side, it connects to one or more J2/E3/T3 line interface units and on the system side, the S/UNI-QJET interfaces to the ATM layer device, such as PM7322 RCMP-800, over an 8 or 16 bit wide UTOPIA Level 2 interface (as shown in Figure 2).
T 1 /E 1 L in e C a rd O C -1 2 L in e C a rd
UT O P IA B us
PM 5355 S /U N I-6 2 2 PMD
PM 4314 QDSX
PM 7344 S /U N I-M P H
A T M S w itc h C o re J 2 /E 3 /T 3 L in e C a rd
J 2 /E3 /T 3 L IU S w itc h F a b ric
O C -3 L in e C a rd s
PM 5346 PM 5355 SS /U N I-6 2E /U N I-L IT 2
UT O P IA B us
J 2 /E3 /T 3 L IU J 2 /E3 /T 3 L IU J 2 /E3 /T 3 L IU
PM 7346 PM 5355 PM 7346 S /U N I-Q J E T /U N I-Q J E S S /U N I-6 2 2T
PM 7322 R C M P -8 0 0
E g re s s D e vic e
PM 7348 PM 7348 S /U N I-D U A L S /U N I-D U A L PM 5347 PM 5355 S /U N N I-6 2 2 S /U I-P L U S
Figure 2: S/UNI-QJET, as an ATM PHY, in an ATM Switch. S/UNI-QJET can be configured as a quad J2/E3/T3 framer for use in router, frame relay switch and multiplexer applications (as shown in Figure 3). In an unchannelized J2/E3/T3 line card, S/UNI-QJET interfaces directly to one or more PM7366 FREEDM-8 HDLC controllers. Each FREEDM-8 can process two highspeed links, such as T3 and E3, or it can process up to eight lower speed links such as J2. The S/UNI-QJET can gap all the overhead bits such that only the payload data is passed to and from FREEDM-8. On the line side, S/UNI-QJET is connected to one or more J2/E3/T3 line interface units. On the system side, S/UNI-QJET interfaces with a data link device over a serial bit interface. In a PPP-Over-SONET application, the S/UNI-QJET interfaces to PM5342 SPECTRA-155 to map three T3 data streams onto three corresponding STS-1 services that are collectively carried over an OC-3 link.
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PRELIMINARY INFORMATION TECHNICAL OVERVIEW PMC-971016 ISSUE 1
PM7346 S/UNI-QJET
S/UNI-QJET TECHNICAL OVERVIEW
A C C E S S S ID E
U P L IN K S ID E
U n ch a n n e lize d J 2 /E 3 /T 3 C a rd J 2 /E3 /T 3 L IU P M 73 4 6 P M 73 4 6 P M 53 5 5 S /U N I-Q J E T SS /U N I-6 2 2T /U N I-Q J E J 2 /E3 /T 3 L IU J 2 /E3 /T 3 L IU J 2 /E3 /T 3 L IU P a c k e t O ve r S O N E T C a rd (3 D S -3 s O ve r O C -3 )
8 P o rt C h a n ne lize d T 1 C a rd PM43 4 43 PPM431144 PMM43114 QDSSX QQDSXX QDDSX
PCI Bus
P M 43 8 8 P M 43 8 8 TO CTL TO CTL
PM 73 6 6 PPM736665 M 73 PM 73 646 FREEEDM D-8 FSREEEI-PM-8 F /U E DM-8H FRRENDDM -8
IP S w itch /R o u te r C o re
4 P o rt C h a n n e lize d E1 C a rd P M 43 1 4 P M 43 1 4 QDSX QDSX P M 63 4 4 P M 43 8 8 EQ UAD TO CTL P M 73 6 6 P M 73 4 5 F R EN I-P D H S /U E D M -8 S w itc h F ab ric
P M 73 6 6 P M 73 6 6 F R E E D M -8 F R E E D M -8
2 8 P o rt U n c h a n ne lize d T 1 C a rd (M 13 ) P M43 8 43 PPM43 88 8 PPM43 8888 PM M43888 M 43 8 TOC L TTOCTTL TTOCT TL TO OCTLL O CC L T D S -3 L IU P M 83 1 3 P M 83 1 3 D3MX D3MX P M 73 6 4 P M 73 4 5 FS /UE D M D H R E N I-P -3 2
Figure 3: S/UNI-QJET, as a Quad Framer Device, in a Frame Relay Equipment. The S/UNI-QJET can be configured as a cell processor to provide cell mapping functions for xDSL modems in an ATM based Digital Subscriber Loop Access Multiplexer (DSLAM) equipment. As shown in Figure 4, each S/UNI-QJET provides four cell processors. Two S/UNI-QJETs are required in an 8 port xDSL line card.
A C C E S S S ID E 8 P o rt x D S L C a rd
xD S L M o d e m
PCI Bus
P ro ce s s o r
Packet M e m o ry
P M 73 6 6 F R E E D M -8 P M 73 6 6 F R E E D M -8
P M 73 4 6 S /U N I-Q J E T
P M 5 34 2 S P E C T R A -15 5
O p tic s
U P L IN K S ID E
xD S L M o d e m
xD S L M o d e m
PM 7346 PM 7346 PM 5355 S /U N I-Q J E T SS /U N I-6 2 2T /U N I-Q J E
A T M S w itc h C o re
S w itc h F a b ric
O C -3 L in e C a rd s
PM 5346 PM 5355 SS /U N I-6 2E /U N I-L IT 2 PM 7348 PM 7348 S /U N I-D U A L S /U N I-D U A L
xD S L M o d e m
xD S L M o d e m
xD S L M o d e m
xD S L M o d e m
PM 7346 PM 7346 PM 5355 S /U N I-Q J E T SS /U N I-6 2 2T /U N I-Q J E
PM 7322 R C M P -8 0 0
E g re s s D e v ic e
PM 5347 PM 5347 S /U N I-P L U S S /U N I-P L U S
U TO P IA B us
U TO P IA B us
xD S L M o d e m
Figure 4: S/UNI-QJET, as a Cell Processor, in a DSLAM Equipment.
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PRELIMINARY INFORMATION TECHNICAL OVERVIEW PMC-971016 ISSUE 1
PM7346 S/UNI-QJET
S/UNI-QJET TECHNICAL OVERVIEW
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FUNCTIONAL OVERVIEW This section describes the major functional blocks of S/UNI-QJET. A simplified block diagram of S/UNI-QJET is show in Figure 5.
L in e S id e P M 7 3 4 6 S /U N I-Q J E T S ys te m S id e
1 o f 4 C h a n n e ls
O ve rh e a d O ve rh e a d O ve rh e a d In s e rt In s e rt In s e rt
C e ll Proce ssor B ypass
D S 3 /E 3 /J 2 D S 3 /E 3 /J 2 T RAN T x F ra m e T x F ra m e rr
T S P LT P x P LC F ra m e r
T x C ell TXCP_50 P ro c e s s o r
T x C ell T X FF F IF O 8 /1 6 B it 8 /1 6 B it U T O P IA U T O P IA L e v e ll 2 Leve 2 In te rfa c e In te rfa c e R x C e ll RXFF F IF O
Fram e r B yp ass
ATM F ATM F SPLR SPLR
P a tteD P R G rn G e n /D e te c t
D S 3 /E 3 /J 2 FRMR R x F ra m e r
R x C e ll RXCP_50 P ro c e s s o r
O ve rh e a d O ve rh e a d E x tra c tt E x tra c
P e rfo rm a n c e CPPM M o n ito rin g
C e ll Proce ssor B ypass
M ic ro p ro c e s s o rr M ic ro p ro c e s s o In te rfa c e In te rfa c e
M ic ro p ro c e s s o r JTAG In te rfa c e
Figure 5: S/UNI-QJET Block Diagram.
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PRELIMINARY INFORMATION TECHNICAL OVERVIEW PMC-971016 ISSUE 1
PM7346 S/UNI-QJET
S/UNI-QJET TECHNICAL OVERVIEW
3.1
Receive Operation The steps in the receive operation are summarized below: Block Name FRMR: Receive Framer: Functional Overview The receive framer consists of three independent framers: * T3-FRMR to decode a T3 frame in either M23 or C-bit parity formats. * E3-FRMR to decode an E3 frame in either G.751 or G.832 formats. * J2-FRMR to decode a J2 frame in either G.704 or NTT formats. The operations of the FRMR are further described in Section 4: J2/E3/T3 framer overview. The Overhead Extract block consists of several subblocks that complement the FRMR in performing framer decoding functions: * RBOC: The Bit-Oriented Code Detector is only used in T3 C-bit parity. RBOC detects the presence of 63 of the 64 possible bit-oriented codes contained in the T3 C-bit parity far end th alarm and control (FEAC) channel. The 64 code (111111b) is similar to the HDLC flag sequence and is ignored. * RDLC: This block receives LAPD/HDLC frames on any serial HDLC bit stream such as the T3 Cbit parity Path Maintenance Data Link, the E3 G.832 Network Requirement byte or the General Purpose data link, the E3 G.751 Network Use bit, or the J2 m-bit data link. A 128 byte FIFO is provided to buffer the received HDLC messages in between microprocessor accesses. * PMON: The Performance Monitor Accumulator interfaces with FRMR to count framing errors. * Rx O/H Access: Extracts the receive J2/E3/T3 overhead bits on the ROH[x], ROHFP[x], and ROHCLK[x] pins. The ATMF block provides HCS-based cell delineation for non-PLCP based transmission formats. This block is described in Section 5: ATM Cell Delineation. The SPLR block supports DS1, T3, E1 and G.751 E3
Overhead Extract
ATMF: ATM Cell Delineator SPLR:
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PRELIMINARY INFORMATION TECHNICAL OVERVIEW PMC-971016 ISSUE 1
PM7346 S/UNI-QJET
S/UNI-QJET TECHNICAL OVERVIEW
Block Name PLCP Layer Receiver CPPM: Cell and PLCP Performance Monitor
RCXP_50: Receive Cell Processor
RXFF: Receive FIFO
Functional Overview PLCP frame processing. This block is described in Section 6: PLCP Frame Processing. The CPPM block interfaces directly to the SPLR to accumulate PLCP error events: * bit interleaved parity error events, * framing octet error events, * far end block error events. The RXCP_50 block supports optional cell payload unscrambling, optional cell header unscrambling, header check sequence (HCS) verification, idle cell filtering and performance monitoring. For PLCP based systems, cell delineation is performed by the SPLR block. For non-PLCP based systems, cell delineation is performed by the ATMF block. The RXFF provides FIFO management and the receive cell interface. The receive FIFO contains four cells and provides the cell rate decoupling function between the transmission system physical layer and the ATM layer. The FIFO interface is UTOPIA Level 2 compliant.
3.2
Transmit Operation The steps in the transmit operation are summarized below: Block Name TXFF: Transmit FIFO Functional Overview The TXFF block provides FIFO management and the transmit cell interface. The transmit FIFO contains four cells and provides the cell rate decoupling function between the transmission system physical layer and the ATM layer. The FIFO interface is UTOPIA Level 2 compliant. The TXCP_50 block supports ATM cell payload scrambling, header check sequence (HCS) generation and idle/unassigned cell generation. The SPLT block supports DS1, T3, E1 and G.751 E3 based PLCP frame insertion. This block is described in Section 6: PLCP Frame Processing. The Overhead Insert block consists of several subblocks that complement the TRAN in performing frame encode functions: * XBOC: The Bit Oriented Code Generator
TXCP_50: Transmit Cell Processor SPLT: SMDS PLCP Layer Transmitter Overhead Insert
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PRELIMINARY INFORMATION TECHNICAL OVERVIEW PMC-971016 ISSUE 1
PM7346 S/UNI-QJET
S/UNI-QJET TECHNICAL OVERVIEW
Block Name
TRAN: Transmit Framer
Functional Overview transmit 63 of the possible 64 bit oriented codes (BOC) in the C-bit parity Far End Alarm and Control (FEAC) channel. It can be used to automatically transmit J2 RAI. * TDPR: The Facility Data Link Transmitter provides a serial data link for the C-bit parity path maintenance data link in T3, the serial Network Operator byte or the General Purpose datalink in G.832 E3, the National Use bit datalink in G.751 E3 or the m-bit datalink in J2. * Tx O/H Access: Can be programmed to insert the transmit J2/E3/T3 overhead bits from the TOH[x], TOHFP[x], and TOHCLK[x] pins. The transmit framer consists of three independent framers: * T3-TRAN to transmit a T3 frame in either M23 or C-bit parity formats. * E3-TRAN to transmit an E3 frame in either G.751 or G.832 formats. * J2-TRAN to transmit a J2 frame in G.704 and NTT formats. The operations of the TRAN are described in Section 4: J2/E3/T3 framer overview.
3.3
Auxiliary Blocks
Block Name PRGD: Pseudo-Random Sequence Generator/Detector
JTAG Test Access Port
Functional Overview The PRGD block is a software programmable test pattern generator, receive and analyzer that may be used to send and receive pseudo-random binary sequence (PRBS) patterns to and from the transmission line. The PRGD block can be programmed to generate any PRBS with length up to 32 bits or any user programmable bit pattern from 1 to 32 bits in length. In addition, the PRGD can insert -1 -7 single bit errors or a bit error rate between 10 to 10 . The JTAG Test Access Port provides JTAG support for boundary scan purposes. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The S/UNI-QJET
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PRELIMINARY INFORMATION TECHNICAL OVERVIEW PMC-971016 ISSUE 1
PM7346 S/UNI-QJET
S/UNI-QJET TECHNICAL OVERVIEW
Block Name Microprocessor Interface
Functional Overview identification code is 073460CD hexadecimal. The microprocessor interface block provides normal and test mode registers and the logic required to connect to a microprocessor. The normal mode registers are required for normal operation and test mode registers are used to enhance the testability of the device.
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PRELIMINARY INFORMATION TECHNICAL OVERVIEW PMC-971016 ISSUE 1
PM7346 S/UNI-QJET
S/UNI-QJET TECHNICAL OVERVIEW
4 4.1
J2/E3/T3 FRAMER OVERVIEW T3 Framer Operation The S/UNI-QJET supports both M23 and C-bit parity T3 framing formats. This format can be extended to support direct byte mapping or PLCP mapping of ATM cells. An overview of the T3 frame format is shown in Figure 6.
6 80 bits (8 blo ck s o f 8 4+1 bits)
M -s ub fra m e 1 2 3 4 5 6 7
X 1 P ayloa d X 2 P ayloa d P 1 P ayloa d P 2 P ayloa d M 1 P ayloa d M 2 P ayloa d M 3 P ayloa d 8 4 b its
F1 F1 F1 F1 F1 F1 F1
P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d
C 1 P ayloa d C 1 P ayloa d C 1 P ayloa d C 1 P ayloa d C 1 P ayloa d C 1 P ayloa d C 1 P ayloa d
F2 F2 F2 F2 F2 F2 F2
P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d
C 2 P ayloa d C 2 P ayloa d C 2 P ayloa d C 2 P ayloa d C 2 P ayloa d C 2 P ayloa d C 2 P ayloa d
F3 F3 F3 F3 F3 F3 F3
P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d
C 3 P ayloa d C 3 P ayloa d C 3 P ayloa d C 3 P ayloa d C 3 P ayloa d C 3 P ayloa d C 3 P ayloa d
F4 F4 F4 F4 F4 F4 F4
P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d
Figure 6: T3 Frame Format. The T3 receiver decodes a B3ZS-encoded signal and provides indications of line code violations (LCVs). The B3ZS decoding algorithm and the LCV definition are software selectable. While in-frame, the T3 receiver continuously checks for line code violations, M-bit or F-bit framing bit errors, and P-bit parity errors. When C-bit parity mode is selected, both C-bit parity errors and far end block errors are accumulated. When the C-bit parity framing format is detected, both the far end alarm and control (FEAC) channel and the path maintenance data link are extracted. HDLC messages in the Path Maintenance Data Link are received by an internal data link receiver. The T3 transmitter allows for the insertion of the overhead bits into a T3 bit stream and produces a B3ZS-encoded signal. Status signals such as far end receive failure (FERF), the alarm indication signal (AIS) and the idle signal can be inserted when the transmission of these signals is enabled
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PRELIMINARY INFORMATION TECHNICAL OVERVIEW PMC-971016 ISSUE 1
PM7346 S/UNI-QJET
S/UNI-QJET TECHNICAL OVERVIEW
The processing of the overhead bits in the T3 frame is described in the following table. In the transmit direction, the overhead bits can be inserted on a bit-by-bit basis from a user supplied data stream.
Control Bit Xx: X-Bit Channel Px: P-Bit Channel
Transmit Operation Inserts the FERF signal on the X-bits. Calculates the parity for the payload data over the previous M-frame and inserts it into the P1 and P2 bit positions. Generates the M-frame alignment signal (M1=0, M2=1, M3=0).
Receive Operation Monitors and detects changes in the state of the FERF signal on the X-bits. Calculates the parity for the received payload. Errors are accumulated in internal registers.
Mx: M-Frame Alignment Signal
Fx: M-subframe Alignment Signal
Generates the M-subframe signal (F1=1, F2=0, F3=0, F4=1).
Cx: C-Bit Channels
M23 Operation: The C bits are passed through transparently in M23 framer only mode except for the C-bit Parity ID bit which toggles every M-frame. C-bit Parity Operation: The C-bit Parity ID bit is forced to logic 1. The second C-bit in M-subframe 1 is set to logic 1. The third C-bit in M-subframe 1 provides a farend alarm and control (FEAC) signal. The FEAC
Finds the M-frame alignment by searching for the F-bits and the Mbits. Out-of-frame is removed if the M-bits are correct for three consecutive M-frames while no discrepancies have occurred in the F-bits. Finds M-frame alignment by searching for the F-bits and the Mbits. Out-of-frame is removed if the M-bits are correct for three consecutive M-frames while no discrepancies have occurred in the F-bits. The state of the C-bit parity ID bit is stored in a register. This bit indicates whether an M23 or C-bit parity format is received. C-bit Parity Operation: The FEAC channel on the third Cbit in M-subframe 1 is detected by the RBOC block. Path parity errors and FEBEs on the C-bits in Msubframes 3 and 4 are accumulated in counters. The path maintenance datalink signal is extracted by the receive HDLC controller.
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PRELIMINARY INFORMATION TECHNICAL OVERVIEW PMC-971016 ISSUE 1
PM7346 S/UNI-QJET
S/UNI-QJET TECHNICAL OVERVIEW
Control Bit
Transmit Operation channel is sourced by the XBOC block. The 3 C-bits in M-subframe 3 carry path parity information. The value of these 3 C-bits is the same as that of the P-bits. The 3 Cbits in M-subframe 4 are the FEBE bits. The 3 C-bits in Msubframe 5 contain the 28.2 Kbit/s path maintenance datalink. The remaining Cbits are unused and set to logic 1.
Receive Operation
4.2
E3 Framer Operation The E3 framer decodes an HDB3-encoded signal and frames to the E3 bit stream. The E3 framer supports both G.751 and G.832 frame formats. The E3 Framer searches for frame alignment in the incoming serial stream based on G.751 or G.832 format. For the G.751 format, the E3 framer expects to see the correct framing pattern error-free for three consecutive frames before declaring an in-frame condition. For the G.832 format, the E3 framer expects to see the correct framing pattern error free for two consecutive frames before declaring an in-frame condition. Once the frame alignment is established, the incoming data is continuously monitored for framing bit errors and byte interleaved parity errors (in G.832 format). The E3 transmitter generates the frame alignment signal and inserts it into the incoming serial stream based on G.751 or G.832 format. All overhead and status bits in each frame format can be individually controlled by register bits or by transmit overhead insertion pins.
4.2.1 G.751 E3 Framer Operation The S/UNI-QJET provides support for the G.751 E3 frame format. This format can be extended to allow for direct byte mapping or PLCP mapping of ATM cells. The G.751 E3 frame format is shown in Figure 7.
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PRELIMINARY INFORMATION TECHNICAL OVERVIEW PMC-971016 ISSUE 1
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S/UNI-QJET TECHNICAL OVERVIEW
1
1
1
1
0
1
0
0
0
0
RAI
Na
372 P ayload bits 380 P ayload bits 380 P ayload bits
C 11 C 21 C 31 C 41 C 12 C 22 C 32 C 42 C 13 C 23 C 33 C 43 J1 J2 J3 J4
376 P ayload bits
Figure 7: G.751 E3 Frame Fromat The processing of the overhead bits in the G.751 E3 frame is described in the following table. In the transmit direction, the overhead bits can be inserted on a bit-by-bit basis from a user supplied data stream.
Control Bit Frame Alignment Signal
Transmit Operation Inserts the frame alignment signal 1111010000b.
RAI: Remote Alarm Indication Na: National Use Bit
Cjk: Justification Service Bits
Jk: Tributary
Receive Operation Finds frame alignment by searching for the frame alignment signal. When the pattern has been detected for three consecutive frames, an in-frame condition is declared. When errors are detected in four consecutive frames, an out-of-frame condition is declared. Optionally asserts the RAI Extracts the RAI signal and signal under a register control outputs it on the ROH output pin. or when LOS, OOF, AIS and The state of the RAI signal is also LCD conditions are detected. written to a register bit. Asserts the National Use bit Extracts the National Use bit and under a register control or stores the value in a register bit. from the internal HDLC controller. When the device is Extracts the Justification Service configured as an E3 G.751 Bits on the ROH output pin when framer device, the the Cjk bits are configured as Justification Service Bits can overhead. be inserted on the TDATI[x] input pin the same way as normal payload data. When the device is configured for ATM application, the Justification Service Bits are used as payload bits. When the device is Extracts the Tributary Justification
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Control Bit Justification Bits
Transmit Operation configured as a E3 G.751 framer, the Tributary Justification Bits can be inserted on the TDATI[x] input pin the same way as normal payload data. When the device is configured for ATM application, the Tributary Justification Bits are used a payload bits.
Receive Operation Bits on the ROH output pin when the Pk bits are configured as overhead.
4.2.2 G.832 E3 Framer Operation The S/UNI-QJET provides support for the G.832 E3 frame format. This format can be extended to allow for direct byte mapping or PLCP mapping of ATM cells. The G.832 E3 frame format is shown in Figure 8.
59 colum ns
FA 1 FA 2 EM TR
9 Rows
MA NR GC 530 octet payload
Figure 8: G.832 E3 Overhead Processing The processing of the overhead bits in the G.832 E3 frame is described in the following table. In the transmit direction, the overhead bits can be inserted on a bit-by-bit basis from a user supplied data stream.
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Control FA1, FA2: Frame Alignment Pattern
EM: Error Monitor, BIP-8
TR: Trail Trace
MA: Maintenance and Adaptation Byte
NR: Network Operator Byte
GC:
Receive Operation Searches the receive stream for the G.832 E3 frame alignment pattern. When the pattern is detected for two consecutive frames, an in-frame condition is declared. Note that there is no ATM cell alignment with the G.832 E3 frame. Therefore cell delineation must be performed to locate the ATM cell boundaries. Inserts the calculated BIP-8 Computes the incoming BIP-8 by computing even parity over value over one 125 s frame. The all transmit bits, including the result is held and compared overhead bits of the previous against the value in the EM byte of 125 s frame. the subsequent frame. Inserts the 16 byte trail Extracts the repetitive trail access access point identifier point identifier and verifies that the specified in internal registers. same pattern is received. Compares the received pattern to the expected pattern programmed in a register. Inserts the FERF, FEBE, Extracts and reports the FERF bit Payload Type bits, Tributary value when it has been the same Unit Multiframe Indicator bits for 3 or 5 consecutive frames. and the Timing Marker bit as S/UNI-QJET also extracts and programmed in a register or accumulates FEBE occurrences as indicated by detection of and extracts the Payload Type, receive OOF or BIP-8 errors. Tributary Unit Multiframe, and Timing Market indicator bits and reports them through microprocessor accessible registers. Inserts the Network Operator Extracts the Network Operator byte byte from the TOH overhead and outputs it on ROH or optionally stream or optionally from the terminates it in the RDLC. When TDPR. When not configured not configured for Tandem for Tandem Connection Connection Maintenance, all 8 bits Maintenance, all 8 bits of the of the Network Operator byte are Network Operator byte are extracted and presented on ROH inserted from TOH or from or to the RDLC. the TDPR. Inserts the GC byte from the Extracts the GC byte and outputs it
Transmit Operation Inserts the G.832 E3 frame alignment pattern (F628H).
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Control General Purpose Communication Channel 4.3
Transmit Operation TOH overhead stream or optionally from the TDPR block.
Receive Operation on ROH or optionally terminates it in the RDLC block.
J2 Framer Operation The S/UNI-QJET supports the G.704 and NTT J2 frame format. This format can be extended to allow for direct byte mapping of ATM cells as specified in G.804. The J2 format consists of 789 bit frames each 125 s long, consisting of 96 bytes of payload, 2 reserved bytes and 5 F-bits. The frames are grouped into 4 frame multiframes as shown in Figure 9.
125 uS
Bit # Fram e 1
1-8
9-1 6
17-24
25-32
75 2 760
76 17 68
76 97 76
777 78 4
7 85
78 6
7 87
788
7 89
TS1
TS2 TS2 TS2 TS2
TS3 TS3 TS3 TS3
TS4 TS4 TS4 TS4
T S 95 T S 96 T S 97 T S 98 T S 95 T S 96 T S 97 T S 98 T S 95 T S 96 T S 97 T S 98 T S 95 T S 96 T S 97 T S 98
1 1 x1 e1
1 0 x2 e2
0 1 x3 e3
0 0 a e4
m 0 m e5
Fram e 2 T S 1 Fram e 3 T S 1 Fram e 4 T S 1
96 O c tets of byte interleaved pa yloa d
Figure 9: G.704 J2 Frame Format The J2 framer decodes a unipolar or B8ZS encoded signal and frames to the resulting 6,312 Kbit/s J2 bit stream. Once in frame, the J2 framer provides indications of frame and multiframe boundaries and marks overhead bits, x-bits, m-bits and reserved channels (TS97 and TS98). Indications of loss of signal, bipolar violations, excessive zeroes, change of frame alignment, framing errors, and CRC errors are provided and accumulated in internal counters. The J2 transmitter inserts the overhead bits into a J2 bit stream and produces a B8ZS-encoded signal. The J2 transmitter adheres to the framing format specified in G.704 and NTT Technical Reference for High Speed Digital Leased Circuit Services.
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The processing of the overhead bits in the J2 frame is described in the following table. In the transmit direction, the overhead bits can be inserted on a bit-by-bit basis from a user supplied data stream.
Control TS1-TS96: Byte Interleaved Payload TS97-TS98: Signaling channels
Transmit Operation Receive Operation Inserts the ATM cells into TS1 Extracts the ATM cell octet payload to TS96 octets. and performs cell delineation. Inserts the signaling bytes from either register bits or from the TOH and TOHINS inputs. These bits can be optionally inserted via TDATI input when in framer only mode. Inserts the frame alignment signal automatically. Inserts the 4 KHz data link signal from the internal HDLC controller or from the bit oriented code generator. Inserts the spare bits via register bits or via TOH and TOHINS input pins. Extracts signaling bytes on the ROH output.
Frame Alignment Signal M-bits: 4kHz Data Link
Finds J2 frame alignment by searching for the frame alignment signal. Extracts the 4 KHz data link signal for the internal HDLC controller.
X-bits: Spare Bits
A-bit: Remote Loss of Frame Indication
Inserts the A-bit via register bit. The A-bit can be optionally be asserted when the J2 framer is in loss of frame condition. Automatically calculates and inserts the CRC-5 check sequence.
E1-E5: CRC-5 Check Sequence
Extracts and presents the x-bits on register bits. The X-bit states can be debounced and presented on the ROH output pin. An interrupt change can be generated to signal a change in the X-bit state. Extracts and presents the A-bit on a register bit. The A-bit state can be debounced and presented on the ROH output pin. An interrupt can be generated to signal a change in the A-bit state. Calculates the CRC-5 check sequence for the received data stream. Discrepancies with the received CRC-5 code can be configured to generate an interrupt. CRC-5 errors are accumulated in an internal counter.
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5
ATM CELL DELINEATION The S/UNI-QJET's ATM Cell Delinator (ATMF) block performs header check sequence (HCS) based cell delineation for non-PLCP based transmission formats. The ATMF block accepts a bit serial cell stream and performs cell delineation to locate cell boundaries. Cell delineation is the process of framing to ATM cell boundaries using the HCS field in the ATM cell header as shown in Figure 10. The HCS is a CRC-8 calculation over the first 4 octets of the ATM cell header. When performing delineation correct HCS calculations are assumed to indicate cell boundaries.
C o rrec t H C S (b it b y b it)
HU NT In c o rr ec t H C S (c ell b y ce ll)
PRESYNC
A L P H A c o n s ec u tive in c o rrec t H C S 's (c ell b y ce ll) SYNC
D E L T A c o n se c u tiv e co r rec t H C S 's (c ell b y ce ll)
Figure 10: Cell delineation State Diagram.. The ATMF performs a sequential bit-by-bit, nibble-by-nibble (for T3 direct mapped) or a byte-by-byte (J2 and E3 direct mapped) hunt for a correct HCS sequence. This state is referred to as the HUNT state. When receiving a bit serial cell stream from an upstream transmission system, the bit, nibble or byte boundaries are determined from the location of the overhead. When a correct HCS is found, the ATMF locks on the particular cell boundary and assumes the PRESYNC state. This state verifies that the previously detected HCS pattern was not a false indication. If the HCS pattern was a false indication then an incorrect HCS should be received within the next DELTA cells. At that point a transition back to the HUNT state is executed. If an incorrect HCS is not found in this PRESYNC period then a transition to the SYNC state is
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made. In this state synchronization is not relinquished until ALPHA consecutive incorrect HCS patterns are found. In such an event a transition is made back to the HUNT state The values of ALPHA and DELTA determine the robustness of the delineation method. ALPHA determines the robustness against false misalignments due to bit errors. DELTA determines the robustness against false delineation in the synchronization process. ALPHA is chosen to be 7 and DELTA is chosen to be 6 as recommended in ITU-T Recommendation I.432. These values result in a maximum average time to frame of 127 s for a T3 stream carrying ATM cells directly mapped into the T3 information payload. Loss of cell delineation (LCD) is detected by counting the number of incorrect cells while in the HUNT state. The count value which determines when LCD is declared can be set in an internal register.
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6
PLCP FRAME PROCESSING The S/UNI-QJET provides support for four different PLCP frame formats: * T3 PLCP frame format, * DS1 PLCP frame format, * G.751 E3 PLCP frame format, * E1 PLCP frame format.
6.1
T3 PLCP Frame Format The T3 PLCP frame (as shown in Figure 11) provides the transmission of 12 ATM cells every 125 s. The PLCP frame is nibble aligned to the overhead bits in the T3 frame. There is no relationship between the start of the PLCP frame and the start of the T3 M-frame. A trailer is inserted at the end of each PLCP frame. The number of nibbles inserted (13 or 14) varies continuously such that the resulting PLCP frame rate can be locked on to an 8 kHz reference clock.
A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 P 11 P 10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 Z6 Z5 Z4 Z3 Z2 Z1 F1 B1 G1 M2 M1 C1 AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell T railer
Fra m ing (3 octets)
53 octets PO H
13 or 14 nibble s
Figure 11: T3 PLCP Frame Format (with a Frame Rate of 125 s).
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6.2
DS1 PLCP Frame Format The DS1 PLCP frame provides the transmission of 10 ATM cells every 3 ms. The PLCP frame (as shown in Figure 12) is octet aligned to the framing bit in the DS1 frame. There is no relationship between the start of the PLCP frame and the start of the DS1 frame. A trailer is inserted at the end of each PLCP frame. The number of octets inserted is fixed at six.
A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 Z4 Z3 Z2 Z1 F1 B1 G1 M2 M1 C1 AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell T railer
Fra m ing (3 octets)
53 octets PO H
6 octets
Figure 12: DS1 PLCP Frame Format (with a Frame Rate of 3 ms). 6.3 G.751 E3 PLCP Frame Format The G.751 E3 PLCP frame provides the transmission of 9 ATM cells every 125 s. The PLCP frame (as shown in Figure 13) is octet aligned to the 16 overhead bits in the G.751 E3 frame. There is no relationship between the start of the PLCP frame and the start of the E3 frame. A trailer is inserted at the end of each PLCP frame. The number of octets inserted is nominally 18, 19, or 20 and is based on the number of E3 overhead octets (4, 5 or 6) that have been inserted during the PLCP frame period. The nominal octet stuffing can be varied by 1 octet to allow the E3 PLCP frame to be locked to an external 8 KHz reference clock. Thus the trailer can be 17, 18, 19, 20 or 21 octets in length.
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A1 A1 A1 A1 A1 A1 A1 A1 A1
A2 A2 A2 A2 A2 A2 A2 A2 A2
P8 P7 P6 P5 P4 P3 P2 P1 P0
Z3 Z2 Z1 F1 B1 G1 M2 M1 C1
AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell T railer
Fra m ing (3 octets)
53 octets PO H 17, 18, 1 9, 20 o r 21 octets
Figure 13: G.751 E3 PLCP Frame Format (with a Frame Rate of 125 s). 6.4 E1 PLCP Frame Format The E1 PLCP frame provides the transmission of 10 ATM cells every 2.375 ms. Thirty of the thirty-two available E1 channels are used for transporting the PLCP frame (as shown in Figure 14). The remaining two channels are reserved for E1 framing and signaling functions. The PLCP frame is octet aligned to the channel boundaries in the E1 frame. The PLCP frame is aligned to the 125 s E1 frame (the A1 octet of the first row of the PLCP frame is inserted in timeslot 1 of the E1 frame).
A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 Z4 Z3 Z2 Z1 F1 B1 G1 M2 M1 C1 AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell AT M C ell
Fram ing (3 octets)
53 octets PO H
Figure 14: E1 PLCP Frame Format (with a frame rate of 2.375 ms).
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6.5
PLCP Overhead Processing Table 2: PLCP Overhead Processing
Overhead Field A1, A2: Frame Alignment Pattern PO-P11: Path Overhead Identifier Z1-Z6: Growth:
Transmit Operation Inserts the PLCP frame alignment pattern (F628H)
Receive Operation Searches the receive stream for the PLCP frame alignment pattern.
F1: User Channel
B1: Bit Interleaved Parity
G1: Path Status
Inserts the path overhead identifier codes in accordance with the PLCP frame alignment. These octets are unused and are nominally programmed with all zeros. Access to these octets is provided by the PLCP transmit overhead access port. This octet is unused and the value inserted in this octet is controlled by an internal register or by TPOH pin. This octet contains an 8-bit interleaved parity (BIP) calculated across the entire PLCP frame (excluding the A1, A, Pn octets and the trailer). The B1 value is calculated based on even parity and the value inserted in the current frame is the BIP result calculated for the previous frame. The first four bit positions provide a PLCP far end block error function and indicates the number of B1 errors detected at the near end. The FEBE field has nine legal values (0000b-1000b) indicating between zero and eight B1 errors.
Identifies the PLCP path overhead bytes by monitoring the sequence of the POI bytes. These octets are ignored and are extracted on the RPOH pin.
This octet is ignored and is extracted on the RPOH pin.
The bit interleaved parity is calculated for the current frame and stored. The B1 octet contained in the subsequent frame is extracted and compared against the calculated value. Differences between the two values provide an indication of the end-to-end bit error rate. These differences are accumulated in an internal counter. The G1 byte provides the PLCP FEBE function and is accumulated in an internal counter. PLCP yellow alarm is detected or removed when the yellow bit is set to logic one or zero for ten consecutive frames. The yellow alarm state and the link status signal state are contained in an
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Overhead Field
M1, M2: Control Information
C1: Cycle/Stuff Counter
Transmit Operation The fifth bit position is used to transmit PLCP yellow alarm. The last three bit positions provide the link status signal used in IEEE802.6 DQDB implementations. Yellow alarm and link status signal insertion is controlled by the internal registers or by TPOH pin. These octets carry the DQDB layer management information. Internal register controls the nominal value inserted in these octets. These octets are unused in ATM Forum T3 UNI specification and should be programmed with all zeros. The coding of this octet depends on the PLCP frame format. For DS1 and E3 PLCP formats, this octet is programmed with all zeros. For the T3 PLCP format, this octet indicates the number of stuff nibbles (13 or 14) at the end of each PLCP frame. The C1 value is varied in a three frame cycle where the first frame always contains 13 stuff nibbles, the second frame always contains 14 nibbles, and the third frame contains 13 or 14 nibbles. For the G.751 E3 PLCP format, this octet indicates the number of stuff octets (17 to 21) at the end of the PLCP frame. Depending on the alignment of the G.751 E3
Receive Operation internal register.
These octets are ignored and are extracted on the RPOH pin.
Interprets the trailer length according to the selected PLCP frame format and the received C1 code.
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Overhead Field
Transmit Operation frame to the E3 PLCP frame, 18, 19 or 20 octets are nominally stuffed. The stuffing may be varied by 1 octet so that the PLCP frame rate can be locked to an external 8 KHz timing reference.
Receive Operation
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NOTES
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CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1997 PMC-Sierra, Inc. PM-971016 (R1) ref PMC-960835 (R3) Issue date: October 1997
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

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