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PM5346 S/UNI-155-LITE
APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
PM5346 S/UNITM
155-LITE
INTERFACING AND PC BOARD LAYOUT SUGGESTIONS FOR THE S/UNI-LITE
APPLICATION NOTE
ISSUE 8: SEPTEMBER 1997
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PM5346 S/UNI-155-LITE
APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PM5346 S/UNI-155-LITE
APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
CONTENTS 1 SUGGESTIONS FOR S/UNI-LITE BOARD LAYOUT............................... 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 DECOUPLING CAPACITORS ON ANALOG POWER .................. 1 POWER AND GROUND CONNECTIONS .................................... 1 FERRITE BEADS ON DIGITAL POWER SUPPLY ........................ 6 FERRITE BEADS ON ANALOG POWER SUPPLY....................... 7 REGULATING THE ANALOG POWER SUPPLY (OPTIONAL) ..... 7 ANALOG TEST PINS .................................................................... 7 LOOP FILTER COMPONENTS..................................................... 7 UNUSED INPUT PINS .................................................................. 7 DEALING WITH HIGH-SPEED RETURN CURRENTS................. 7
SUGGESTIONS FOR S/UNI-LITE PECL TERMINATIONS ..................... 9 2.1 2.2 2.3 2.4 S/UNI-LITE TXD TO PMD ........................................................... 10 DC COUPLED TXD+ VIA CMOS TO PECL CONVERTER ......... 10 DIFFERENTIAL REFERENCE OSCILLATOR TERMINATIONS . 12 SINGLE TTL/CMOS REFERENCE OSCILLATOR DRIVING BOTH RRCLK AND TRCLK ................................................................... 12
3
S/UNI-LITE CLOCK RECOVERY LOOP FILTER COMPONENTS ........ 14 3.1 POLARIZED TANTALUM CAPACITORS CONNECTED IN SERIES .................................................................................................... 15
4
REFERENCES....................................................................................... 17
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APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
LIST OF FIGURES FIGURE 1 - RECOMMENDED LAYOUT FOR VDD DECOUPLING CONNECTION TO ANALOG POWER PINS............................................ 1 FIGURE 2 -........................................................................................................ 2 FIGURE 3 - S/UNI-LITE TO PMD AND REFERENCE OSCILLATOR TERMINATIONS ...................................................................................... 9 FIGURE 4 -...................................................................................................... 10 FIGURE 5 - CMOS TO PECL CONVERTER................................................... 11 FIGURE 6 - REFERENCE OSCILLATOR TERMINATIONS ............................ 12 FIGURE 7 -...................................................................................................... 13 FIGURE 8 - LOOP FILTER USING CERAMIC NON-POLARIZED CAPACITORS15 FIGURE 9 - LOOP FILTER USING TANTALUM POLARIZED CAPACITORS.. 16
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PM5346 S/UNI-155-LITE
APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 - S/UNI-LITE POWER/GROUND PINS ............................................ 3 - RECOMMENDED COMPONENT VALUES ................................. 14 -...................................................................................................... 15
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PM5346 S/UNI-155-LITE
APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
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APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
1 1.1
SUGGESTIONS FOR S/UNI-LITE BOARD LAYOUT Decoupling Capacitors on Analog Power Decoupling capacitors (0.1 F Ceramic X7R) are recommended for each analog power pin (TAVD1, TAVD2, TAVD3, TXVDD, RAVD1, RAVD2, RAVD3, RAVD4) placed as close to the package pin as possible according to the layout recommendation in figure 1 below. In particular, separate decoupling capacitors are strongly recommended for the TAVD1, TAVD2, RAVD1 and RAVD2 pins. Separate decoupling is recommended to prevent transmit from coupling transient noise into the receiver. TAVD1 and RAVD1 are power supplies for voltage reference circuitry for the transmit and receive PLLs respectively. There must be separate decoupling of TAVD2 from TAVD1; RAVD2 must be separately decoupled from RAVD1. This prohibits transients from coupling into the references (i.e., RAVD1 and TAVD1). Figure 1 - Recommended Layout for VDD Decoupling Connection to Analog Power Pins
Via to VDD
Solder Pad for Decoupling Capacitor
Solder Pad for Power Pin
1.2
Power and Ground Connections It is advisable to separate the S/UNI-LITE transmit power/ground pins from the receive power/ground pins by splitting the power and ground planes in the area surrounding these pins as shown in figure 2.
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PM5346 S/UNI-155-LITE
APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
Figure 2
-
Pow er supplied from connector
VSS ALE A [7 ] A [6 ] A [5 ] A [4 ] A [3 ] A [2 ] A [1 ] A [0 ] D [7 ] D [6 ] D [5 ] D [4 ] VDDO5 VSSO5 D [3 ] D [1 ] D [2 ] D [0 ] INTB VD DI3 VSS I3 RDB WRB VSS
PIN 1 03
PIN 1 28
T R ANS M IT P O W E R /G R O U ND P LANE S
O ptica l Interface
TG N D TXD P TXD N TXV CC RXV CC SD RXDN R XD P RGND
P IN 1 T BV S S YP ATP2 TAVD 1 TAVS1 TAVD 2 TAVS2 TAVD 3 TRC L KTR CLK+ TAVS3 TXVDD TXC+ TXCTXD + TXDTXVSS VDDO1 VSS I1 VD DI1 VSSO1 RXD O+ RXDORAVD3 RXDRX D+ ALOSALOS+ RAVS3 RAVD1 RAV S1 RAVD4 RRC LKRRCLK+ RAVS4 RAVD2 RAV S2 VSS P IN 3 8
P IN 1 0 2
In d ex P in
PM 5 3 46 S/U N I-LIT E T op V ie w
N OT TO S CAL E
VSS RSTB CS B VCLK RAT E[0] RAT E[1] TS OC TXPRTY TDA T[7 ] TDA T[6 ] TDA T[5 ] TDA T[4 ] TDA T[3 ] TDA T[2 ] TDA T[1 ] TDA T[0 ] TC A TW RE NB TFC LK RS O C RXPRT VDDO4 Y VSSO4 R D A T [7 ] R D A T [6 ] R D A T [5 ] R D A T [4 ] R D A T [3 ] R D A T [2 ] VDDO3 VSSO3 R D A T [1 ] R D A T [0 ] RCA RRD ENB RFC LK TS E N VSS PIN 65
R E C E IV E P O W E R /G R O U ND P LANE S
VSS ATP1 RB YP LFP LFN LFO VSS9 VS S 10 VS S 11 VS S 12 VS S 13 XOFF TCP TGFC TFP O TCLK VDDO2 VSSO2 RCLK RFP RG FC RCP VD DI2 VSS I2 RALM VSS
PIN 39
P IN 64
D IG IT AL P O W E R /G R O UND P LANE S
Power and Ground requirements are a function of the noise environment on a board and the performance target of the board. Ground and power supply noise will degrade the bit error performance of the S/UNI-LITE and introduce intrinsic jitter on the transmitted data. Table 1 is a summary of all power and ground connections for the S/UNI-LITE. The "Supply Noise Sensitivity" column highlights pins that are sensitive to perturbations on the supply rails. The "Current" column identifies the current consumption for a particular pin as either dynamic (fluctuating over time) or static (constant over time). The "Layout Consideration" column provides further detail regarding the layout requirements for each pin.
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APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
Table 1
Pin Name
- S/UNI-LITE Power/Ground Pins
Type Supply Noise Sensitivity Current Pin No. Layout Consideration Static 31 The ground (RAVS1) pin for analog voltage reference circuitry
RAVS1
Ground
High
RAVS2
Ground
High
Dynamic
37
The ground (RAVS2) pin for receive loop filter and VCO.
RAVS3
Ground
High
Dynamic
29
The ground (RAVS3) pin for the RXD+/- & ALOS+/- PECL inputs.
RAVS4
Ground
High
Dynamic
35
The ground (RAVS4) pin for the RRCLK+/PECL inputs.
TAVS1
Ground
High
Static
5
The ground (TAVS1) pin for analog voltage reference circuitry
TAVS2
Ground
High
Dynamic
7
The ground (TAVS2) pin for the transmit clock synthesizer VCO.
TAVS3
Ground
High
Dynamic
11
The ground (TAVS3) pin for the transmit PECL inputs.
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APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
Pin Name
Type
Supply Noise Sensitivity
Current
Pin No.
Layout Consideration
TXVSS
Ground
High
Dynamic
17
The transmit pad ground (TXVSS) is the return path for the TXC+/and TXD+/outputs. TXVSS is physically isolated from the other device ground pins and should be noise free for good performance.
VSSI1H VSSI2 VSSI3
Ground
Low
Dynamic
19 62 106
The core ground (VSSI1 - VSSI3) pins should be connected to GND in common with VSSO.
VSSO1 VSSO2 VSSO3 VSSO4 VSSO5 VSS1, VSS2, VSS3, VSS4, VSS5, VSS6, VSS7, VSS8, VSS9, VSS10, VSS11, VSS12, VSS13
Ground
Low
Dynamic
21 56 72 80 113
The pad ring ground (VSSO1 VSSO5) pins should be connected to GND in common with VSSI.
Thermal Ground
Low
Dynamic
1 38 39 64 65 102 103 128, 45, 46, 47, 48, 49
The thermal grounds (VSS1 VSS13) provide a low thermal resistance for the dissipated heat. These pins must be connected to DIGITAL GND only for correct operation. Note: these pins are electrically connected together internally
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APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
Pin Name
Type
Supply Noise Sensitivity
Current
Pin No.
Layout Consideration
RAVD1
Power
High
Static
30
The power (RAVD1) pin for analog voltage reference circuitry.
RAVD2
Power
High
Dynamic
36
The power (RAVD2) pin for receive loop filter and VCO.
RAVD3
Power
High
Dynamic
24
The power (RAVD3) pin for the RXD+/- and ALOS+/- PECL inputs.
RAVD4
Power
High
Dynamic
32
The power (RAVD4) pin for the RRCLK+/PECL inputs.
TAVD1
Power
High
Static
4
The power (TAVD1) pin for analog voltage reference circuitry.
TAVD2
Power
High
Dynamic
6
The power (TAVD2) pin for the transmit clock synthesizer VCO.
TAVD3
Power
High
Dynamic
8
The power (TAVD3) pin for the transmit PECL inputs.
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APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
Pin Name
Type
Supply Noise Sensitivity
Current
Pin No.
Layout Consideration
TXVDD
Power
High
Dynamic
12
The transmit pad power (TXVDD) supplies the TXC+/- and TXD+/- outputs. TXVDD is physically isolated from the other device power pins and should be a well regulated +5 V DC and noise free for good performance.
VDDI1 VDDI2 VDDI3
Power
Low
Dynamic
20 61 107
The core power (VDDI1 - VDDI3) pins should be connected to a well decoupled +5 V DC in common with VDDO.
VDDO1 VDDO2 VDDO3 VDDO4 VDDO5
Power
Low
Dynamic
18 55 73 81 114
The pad ring power (VDDO1 VDDO5) pins should be connected to a well decoupled +5 V DC in common with VDDI.
1.3
Ferrite Beads on Digital Power Supply Power supply isolation using Ferrite beads is not advisable in digital switching circuits as di/dt noise is introduced into the power rail. Sufficient capacitive decoupling on all digital power pins is recommended.
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APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
1.4
Ferrite Beads on Analog Power Supply Ferrite beads for power supply isolation can be used in analog (and ECL) circuitry where there is no di/dt noise due to single ended switching currents. If this not the case, or it is uncertain that the circuitry is operating in a balanced fashion, then using RC filtering or local bulk decoupling to filter local di/dt noise is recommended.
1.5
Regulating the Analog Power Supply (Optional) In applications that provide a +12V supply, a 5V regulator can be used to supply a low-noise analog power supply. The regulator should supply all analog power pins (TAVD1-4 and RAVD1-4); the total power draw of the analog circuitry in the S/UNI-LITE is less than 30mW. At a minimum, the regulator should power RAVD1, RAVD2, TAVD1, and TAVD2.
1.6
Analog Test Pins The Analog test pins must be grounded. ATP1 should be connected to the Receive analog ground plane. ATP2 should be connected to the Transmit analog ground plane.
1.7
Loop Filter Components The loop filter components should be placed such that they sit over the Receive analog ground plane.
1.8
Unused Input Pins All unused input pins should be tied to their appropriate inactive level.
1.9
Dealing with high-speed return currents At low speeds, return current follows the path of least resistance back to the driver. At high speeds, however, the return current follows the path of least inductance which lies on the plane directly under the signal trace, as the total loop area between the outgoing and returning paths is minimized. In other words, the high-speed return current follows a path that is almost the "mirror image" of the signal trace on the plane underneath the trace. This tight coupling provides good flux cancellation so that common-mode current is reduced. High speed traces should not cross cuts or heavily perforated areas (where tight spacing through-hole components reside) on the power and ground planes, as
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APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
any cuts on these planes may interrupt the return currents, causing them to seek alternative paths back to the driver. The different routes taken by the outgoing and return currents will both induce common-mode noise on other nearby signal traces. In addition, by routing high speed signals over continuous power planes, the return current paths of these signals are known and other signals will not cross over these return currents, reducing the possibility of noise coupling. Detailed discussions on high-speed design are provided by the references.
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APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
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SUGGESTIONS FOR S/UNI-LITE PECL TERMINATIONS Figure 3 - S/UNI-LITE to PMD and Reference Oscillator Terminations
S /U N I-L IT E
O p tic s PM D RD+
0 .0 1 u F Zo 330 2 *Z o 0 .0 1 u F Zo G nd 330 G nd Zo Zo V p p = (Z o /((R S 1 + 2 5 )+ Z 0 ) * V d d Zo RS1 VDD R1 V d d * R 2 /(R 1 + R 2 ) = V b b 0 .0 1 u F R2 G nd G nd Zo 0 .0 1 u F
RxD+
RD-
RxD TxD+ 25 TxD25 V
G nd
RS1
0 .0 1 u F
TD+
TD-
V
G nd
ALO S+ ALO S-
SD Re G nd O sc Rs Zo Zo G nd 5 0 0 m V < ( Z o / ( R s + Z o ) ) * V d d < 2 . 5 V o lt s Rs O sc Zo Zo 0 .0 1 u F
RRCLKRRCLK+
0 .0 1 u F TRCLKTRCLK+ G nd
Notes for Figure 3: * * * * * Vpp is minimum input swing required by the optical PMD device. Vbb is the switching threshold of the PMD device (typically Vdd - 1.3 Volts). Vpp is Voh - Vol (typically 800 mVolts). The value of Re is dependent on the signal trace characteristic impedance and the ECL or PECL supply voltage (-4.5 V, +5 V). Values in the range of 200-300 are recommended.
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APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
* 2.1
A single oscillator can be used to drive both RRCLK and TRCLK.
S/UNI-LITE TxD to PMD The TxD outputs from the S/UNI-LITE may also use Thevenin termination resistors that provide the Vbb bias voltage rather than the resistor-divider shown above. While this circuit uses one less component (0.01 F decoupling capacitor), it is more susceptible to common mode noise. Figure 4 -
Optics PM D
VDD R1 RS1 Zo R2 VDD Gnd R1 0.01uF
S/UNI-LITE
TxD+ 25 V
TD+
Vpp = (Zo/((R S1+25)+Z0) * Vdd
RS1 Zo 0.01uF
Gnd TxD25 V
TDR2 Gnd
Vdd * R 2/(R 1+R 2) = Vbb Zo= R1 * R 2/(R1+R2)
Gnd
N otes: Vpp is minimum input swing required by the optical PMD device. Vbb is the sw itching threshold of the PMD device (typically Vdd - 1.3 volts) Vpp is Voh - Vol (typically 800 mVolts) For Z o = 50 , R 1=67 , R2 = 192.3 , RS1=237
2.2
DC coupled TxD+ via CMOS to PECL converter Schemes (1) and (2) above use AC-coupling capacitors on the TXD+/- S/UNILITE outputs. A disadvantage of this scheme is that Diagnostic LOS (DLOS register bit) can no longer be used because the AC-coupled all zero transmit data will cause the PMD inputs to float to the Vbb threshold. This can result in the PMD transmitting pulses due to board noise. A way to eliminate this is to use a CMOS to PECL converter, between the S/UNI-LITE TXD+/- outputs and the ODL. Due to the high data rate, and this single ended CMOS I/F, make sure the converter is located right at the S/UNI-LITE TXD output. Care must be taken to maintain signal integrity for low jitter. Connection 'A' below, must be an extremely short signal trace (less than 1") with no termination. Optionally, for slightly longer trace, a series termination and a controlled
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APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
transmission trace is required. The length limit of such a terminated CMOS trace depends on factors such as system ground noise, Zo and Rs. The value of Rs depends on the SUNI-LITE source driver impedance (about 25) and the Zo of the controlled signal PCB trace (Zo=25+Rs). Figure 5 - CMOS to PECL Converter
155.52 Mbit/s data, keep this trace extremely short U1 IN OUT+ Re Zo Re Transmit Gnd Zo 2*Zo TxDTxD+
TxD+/- are specified as 6 mA at 3.9V
Optics PMD
TxD+ V -5 2
A
TxDV -5 2
NC
CMOS to OUTPECL Converter GND
SUNI-LITE The value of Re is dependent on the signal trace characteristic impedence and the ECL or PECL supply voltage (-4.5V, or +5V). Value in the range of 330 is recommended. Zo= 75 additional optional series termination scheme to reduce reflection and over/under-shoot NOTE: U1 can be a Motorola CMOS to PECL convereter. Either, 1/4 of a Quad CMOS to PECL converter MC10H352, or a single TTL to PECL like MC10ELT20 (MECL10H compatible) ,or the MC100ELT20 (MECL100H compatible). Please note these have tpd=1.5ns and tr=0.5ns
Rs =50
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APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
2.3
Differential Reference Oscillator Terminations For optimum jitter performance on the transmit side and noise immunity on the receive side the reference clocks should be connected differentially. Figure 6 - Reference Oscillator Terminations
0.01uF Osc out Rx + Ref out Zo Re Zo
Gnd
RRCLK+ 2*Zo 0.01uF RRCLK S/UNI-LITE 0.01uF
Re
Gnd
Osc out Tx + Ref out -
Zo Re Zo
Gnd
TRCLK+ 2*Zo 0.01uF TRCLK-
Re
Gnd
The value of Re is dependent on the signal trace characteristic impedence and the ECL or PECL supply voltage (-4.5 V, + 5 V). Values in the range of 200-330 are recommended
2.4
Single TTL/CMOS Reference Oscillator Driving Both RRCLK and TRCLK If a single TTL or CMOS oscillator is used to drive these inputs, the RRCLK- and TRCLK- inputs can be used while RRCLK+ and TRCLK+ signals are connected to their respective grounds. The single clock signal must be properly terminated, however, it is not a good idea to connect the clock trace to either RRCLK- or TRCLK- and then run the trace to the other input and terminate at the far end. The transmit and receive grounds are isolated by channels cut into the ground plane, so potential differences between transmit and receive grounds will affect one of the reference clock inputs. For example, if the reference clock signal is run to the TRCLK input and then is terminated to the receive ground near the RRCLK input, the TRCLK input (which is referenced to the transmit ground) will require the clock swing to be large enough to accommodate the difference between grounds. Otherwise, the TRCLK input will be more sensitive to noise than the RRCLK input. A second problem may arise if the clock signal trace crosses the cuts in the ground plane (i.e. from transmit ground island to receive ground island). In that case the ground return current from the receive side cannot follow the signal trace back to the driver. Instead, it will seek an
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APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
alternative path of least inductance. Consequently, this ground current will induce common-mode noise on signals nearby. The solution is to run two separate reference clock signals and terminate them at 1 each input . The following diagram illustrates how to use a single TTL level oscillator to drive the RRCLK- & TRCLK- signals via a 74FCT541 buffer. The TRCLK+ and RRCLK+ signals are connected to their respective grounds. Figure 7 50
Very Short Trace
100 TTL OSC IN1 IN2 OUT1 OUT2 100
TX GND
50 50
TRCLK+ 0.01F TRCLKS/UNI LITE RRCLKRRCLK+
74FCT541
0.01F
TX GND
RX GND
50
The TTL oscillator should be placed as close to the buffer as possible as it is unterminated. The TTL oscillator is used to match the 74FCT541's TTL input level in order to avoid duty cycle distortion caused by differences in output levels and input switching thresholds.
1
A layout alternative could be to run a 50 ohm clock trace to the vicinity of the RRCLK- & TRCLK- inputs and then split into two 100
ohm traces. Each one of these two traces could then be connected to the RRCLK- or TRCLK- input and each terminated with 100 ohm to the receive or transmit analog ground respectively. However, this is not recommended because the resulting the width of a 100 Ohm trace is very narrow (less than 3 mil). This width will be difficult for board manufacturers to fabricate accurately and reliably. Inaccuracy in the trace impedance will cause the signals to be improperly terminated.
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APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
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S/UNI-LITE CLOCK RECOVERY LOOP FILTER COMPONENTS The asymmetrical loop filter values were chosen to achieve maximum performance in the LAN environment. As well, to eliminate the power drain of the above mentioned emitter-follower and to achieve maximum jitter tolerance, the jitter transfer 20 db/decade, 130 kHz -3dB point can be sacrificed. Since the S/UNI-LITE is a terminating device and will not be used as a regenerator, the jitter transfer -3 dB point is not relevant. All resistors are 1% metal film (1/8 or 1/10 watt) resistors and all capacitors should be 10% and non-polarized since under some cases the capacitors may be reversed biased by up to 2 Volts DC. A non-polarized ceramic capacitor or series connected polarized Tantalum capacitors may be used as shown below. Type X7R or X5R dielectric monolithic ceramic capacitors are recommended as these have the most desirable temperature coefficient, are non-polarized and the 0.47F devices are readily available from several vendors, including AVX, Philips, TDK, Vitramon, and Prestidio. Table 2
Line Rate (Mbit/s) 155.52 & 51.84 25.92 & 12.96 200 200 412 412 0.47 F 2.2 F
- Recommended Component Values
R1 () R2 () C1, C2 (F) min Transfer Function BW 450 kHz 75 kHz
Recommended capacitor values will maintain jitter transfer peaking below the required 0.1 dB level. The capacitor values are the minimum recommended values; larger values of capacitance can be used on any of the line rates.
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APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
Figure 8
- Loop Filter Using Ceramic Non-Polarized Capacitors
RAVD2
R X D + /R R C L K + /-
P h a s e /F req D e tec to r
P re filter
+
O pA m p VCO re c o ve re d c lo c k LF + LFLFO
on -c h ip off-c h ip
RAVS2
R2 C2 RAVS2 GND
R1 C1
3.1
Polarized Tantalum Capacitors Connected in Series For lower line rates, a 2.2 F capacitor is required. Due to footprint requirements, or sourcing constraints, two polarized Tantalum capacitors connected in series may be a more desirable option. Either back to back (-'ve to -'ve) or anode to anode (+'ve to +'ve) may be used to form one non-polar capacitor. Since the effective capacitance will be halved, two 4.7 F capacitors must be used to form a 2.35 F non-polar capacitor. Since the LF+ pin will always have a positive DC bias (about +1 Vdc when in lock), C2 may be a single polarized capacitor with the positive terminal connected to the LF+ pin. However, C1 is made up of a series combination of C1a and C1b as shown in the schematic below. AVX corporation publishes several articles on back to back tantalums. Table 3
Line Rate (Mbit/s) 25.92 & 12.96 200 412 2.2 4.7 4.7
R1 () R2 () C2 (F) min. C1a (F) min. C1b (F) min. Transfer Function BW 75 kHz
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Figure 9
- Loop Filter Using Tantalum Polarized Capacitors
RAVD2
R X D + /R R C L K + /-
P h a s e /F req D e tec to r
P re filter
+
O pA m p VCO re c o ve re d c lo c k LF + LFLFO
OR
on -c h ip off-c h ip
RAVS2
R2 C2
R1
+ -- +
C1a C1b
+ -
- ++ -
RAVS2 GND
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APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
4
REFERENCES 1. PMC-Sierra, Inc., PM5346 S/UNI-LITE Data Sheet, Issue 4, November, 1994. 2. Ott, Henry W., "Noise Reduction Techniques in Electronic Systems", Second Edition, John Wiley & Sons. 3. Montrose, Mark I., "Printed Circuit Board Design Techniques for EMC Compliance", IEEE Press, 1995. 4. Graham, Martin and Johnson, Howard W., "High-Speed Digital Design: A Handbook of Black Magic", PRT Prentice-Hall Inc, 1993.
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NOTES
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APPLICATION NOTE PMC-941031 ISSUE 8 SATURN USER NETWORK INTERFACE
NOTES
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CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
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None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1997 PMC-Sierra, Inc. PM-941031 (R8) Issue date: September 1997
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

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