View 1720F_963397.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LT1720 Dual, 4.5ns, Single Supply 3V/5V Comparator with Rail-to-Rail Outputs
FEATURES
s s s s s
DESCRIPTION
The LT (R)1720 is an UltraFastTM dual comparator optimized for single supply operation, with a supply voltage range of 2.7V to 6V. The input voltage range extends from 100mV below ground to 1.2V below the supply voltage. Internal hysteresis makes the LT1720 easy to use even with slow moving input signals. The rail-to-rail outputs directly interface to TTL and CMOS. Alternatively the symmetric output drive can be harnessed for analog applications or for easy translation to other single supply logic levels. The LT1720 is available in the 8-pin SO package; three pins per comparator plus power and ground. The LT1720 is ideal for systems where small size and low power are paramount. The pinout of the LT1720 minimizes parasitic effects by placing the most sensitive inputs (inverting) away from the outputs, shielded by the power rails.
, LTC and LT are registered trademarks of Linear Technology Corporation. UltraFast is a trademark of Linear Technology Corporation.
s s s
UltraFast: 4.5ns at 20mV Overdrive 7ns at 5mV Overdrive Low Power: 4mA per Comparator Optimized for 3V and 5V Operation Pinout Optimized for High Speed Ease of Use Input Voltage Range Extends 100mV Below Negative Rail TTL/CMOS Compatible Rail-to-Rail Outputs Internal Hysteresis with Specified Limits Low Dynamic Current Drain; 15A/(V-MHz), Dominated by Load In Most Circuits
APPLICATIONS
s s s s s s s
High Speed Differential Line Receiver Crystal Oscillator Circuits Window Comparators Threshold Detectors/Discriminators Line Receivers Zero-Crossing Detectors High Speed Sampling Circuits
TYPICAL APPLICATION
2.7V to 6V Crystal Oscillator with TTL/CMOS Output
2.7V TO 6V 2k 220 DELAY (ns) 1MHz TO 10MHz CRYSTAL (AT-CUT)
Propagation Delay vs Overdrive
8 7 6 5 4 3 2 FALLING EDGE (tPDHL) RISING EDGE (tPDLH) 25C VSTEP = 100mV VCC = 5V CLOAD = 10pF
620
+ -
GROUND CASE OUTPUT
C1 1/2 LT1720
2k
1720 TA01
1 0 0 10 20 30 OVERDRIVE (mV) 40 50
1720 TA02
0.01F
1.8k
U
U
U
1
LT1720
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW +IN A 1 -IN A 2 -IN B 3 +IN B 4 8 7 6 5 VCC OUT A OUT B GND
Supply Voltage, VCC to GND ...................................... 7V Input Current ...................................................... 10mA Output Current (Continuous) ............................. 20mA Operating Temperature Range C Grade .................................................. 0C to 70C I Grade............................................... - 40C to 85C Junction Temperature ........................................... 150C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LT1720CS8 LT1720IS8 S8 PART MARKING 1720 1720I
S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150C, JA = 200C/ W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
VCC = 5V, VCM = 1V, COUT = 10pF, TA = 25C, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL VCC VCMR VTRIP+ VTRIP- VOS VHYST VOS/T IB IOS CMRR PSRR AV VOH VOL ICC tPD20 tPD5 tPD tSKEW tr tf PARAMETER Supply Voltage Input Voltage Range Input Trip Points Input Trip Points Input Offset Voltage Input Hysteresis Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Common Mode Rejection Ratio Power Supply Rejection Ratio Voltage Gain Output High Voltage Output Low Voltage Supply Current (Per Comparator) Propagation Delay Propagation Delay Differential Propagation Delay Propagation Delay Skew Output Rise Time Output Fall Time (Note 3) (Note 4) (Note 5) IO = - 4mA, VIN = VTRIP + 10mV IO = 10mA, VIN = VTRIP- - 10mV VCC = 5V VCC = 3V VOVERDRIVE = 20mV (Note 6)
q
+
CONDITIONS
q q
MIN 2.7 - 0.1 - 2.0 - 3.0 - 5.5 - 6.5
TYP
MAX 6 VCC - 1.2 5.5 6.5 2.0 3.0
UNITS V V mV mV mV mV mV mV mV V/C A A dB dB V
(Note 2)
q
(Note 2)
q
(Note 2)
q
1.0
q q q q q q
3.0 4.5 5.0 0 0.6
(Note 2)
2.0 -6 55 65 VCC - 0.4
3.5 10
70 80
q q q q
0.4 4 3.5 4.5 7 7 6 6.5 8.0 10 13 1.0 1.5
VOVERDRIVE = 5mV (Notes 6, 7)
q
(Note 8) Between Channels (Note 9) Between t PD+/tPD- 10% to 90% 90% to 10%
0.3 0.5 2.5 2.2
2
U
W
U
U
WW
W
V mA mA ns ns ns ns ns ns ns ns
LT1720
ELECTRICAL CHARACTERISTICS
The q denotes specifications that apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1720 comparators include internal hysteresis. The trip points are the input voltage needed to change the output state in each direction. The offset voltage is defined as the average of VTRIP+ and VTRIP-, while the hysteresis voltage is the difference of these two. Note 3: The common mode rejection ratio is measured with VCC = 5V and is defined as the change in offset voltage measured from VCM = - 0.1V to VCM = 3.8V, divided by 3.9V. Note 4: The power supply rejection ratio is measured with VCM = 1V and is defined as the change in offset voltage measured from VCC = 2.7V to VCC = 6V, divided by 3.3V. Note 5: Because of internal hysteresis, there is no small-signal region in which to measure gain. Proper operation of internal circuity is ensured by measuring VOH and VOL with only 10mV of overdrive. Note 6: Propagation delay measurements made with 100mV steps. Overdrive is measured relative to VTRIP. Note 7: t PD cannot be measured in automatic handling equipment with low values of overdrive. The LT1720 is 100% tested with a 100mV step and 20mV overdrive. Correlation tests have shown that t PD limits can be guaranteed with this test, if additional DC tests are performed to guarantee that all internal bias conditions are correct. Note 8: Differential propagation delay is defined as: t PD = |tPDA - t PDB| Note 9: Propagation Delay Skew is defined as: tSKEW = |tPDLH - tPDHL|
PIN FUNCTIONS
+IN A (Pin 1): Noninverting Input of Comparator A. -IN A (Pin 2): Inverting Input of Comparator A. -IN B (Pin 3): Inverting Input of Comparator B. +IN B (Pin 4): Noninverting Input of Comparator B. GND (Pin 5): Ground. OUT B (Pin 6): Output of Comparator B. OUT A (Pin 7): Output of Comparator A. VCC (Pin 8): Positive Supply Voltage.
TYPICAL PERFORMANCE CHARACTERISTICS
Input Offset and Trip Voltages vs Supply Voltage
3 VOS AND TRIP POINT VOLTAGE (mV)
VOS AND TRIP POINT VOLTAGE (mV)
COMMON MODE INPUT VOLTAGE (V)
VTRIP+ 2 1 VOS 0 -1 -2 -3 2.5
VTRIP- 25C VCM = 1V 3.0 5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.5 6.0
UW
U
U
U
Input Offset and Trip Voltages vs Temperature
3 2 1 VOS 0 -1 -2 -3 - 60 - 40 - 20 0 20 40 60 80 100 120 140 TEMPERATURE (C)
1720 G02
Input Common Mode Limits vs Temperature
4.2 VCC = 5V 4.0 3.8 3.6 0.2 0 - 0.2 - 0.4 - 50 - 25
VTRIP+
VTRIP-
50 25 75 0 TEMPERATURE (C)
100
125
1720 G01
1720 G03
3
LT1720 TYPICAL PERFORMANCE CHARACTERISTICS
QUIESCENT SUPPLY CURRENT PER COMPARATOR (mA)
Input Current vs Differential Input Voltage
2 1 0
INPUT BIAS (A)
25C VCC = 5V
5.5 5.0 4.5 VCC = 5V 4.0 VCC = 3V 3.5 3.0 2.5 2.0 - 50 - 25 0 50 75 25 TEMPERATURE (C) 100 125
SUPPLY CURRENT PER COMPARATOR (mA)
-1 -2 -3 -4 -5 -6 -7 - 5 - 4 - 3 - 2 -1 0 1 2 3 4 DIFFERENTIAL INPUT VOLTAGE (V) 5
Propagation Delay vs Load Capacitance
9 8 7 6
PROPAGATION DELAY (ns)
25C VSTEP = 100mV OVERDRIVE = 20mV VCC = 5V
RISING EDGE (tPDLH)
DELAY (ns)
5 4 3 2 1 0 0
FALLING EDGE (tPDHL)
DELAY (ns)
40 30 OUTPUT LOAD CAPACITANCE (pF)
10
20
Output Low Voltage vs Load Current
0.5
OUTPUT VOLTAGE RELATIVE TO VCC (V)
SUPPLY CURRENT PER COMPARATOR (mA)
VCC = 5V VCM = 1V VIN = - 15mV OUTPUT VOLTAGE (V) 0.4 125C VCC = 2.7V
125C
0.3 - 55C 0.2
25C
0.1
0
4 12 16 8 OUTPUT SINK CURRENT (mA)
4
UW
1720 G04
1720 G07
Quiescent Supply Current vs Temperature
6.0
Quiescent Supply Current vs Supply Voltage
7 6 5 4 3 2 1 0 0 1 4 3 2 5 SUPPLY VOLTAGE (V) 6 7
1720 G06
125C
25C - 55C
1720 G05
Propagation Delay vs Temperature
8.0 7.5 VCC = 3V 7.0 6.5 6.0 5.5 VCC = 5V 5.0 OVERDRIVE = 20mV 4.5
50
Propagation Delay vs Supply Voltage
tPDLH VCM = 1V VSTEP = 100mV CLOAD = 10pF 5.0 25C VSTEP = 100mV OVERDRIVE = 20mV CLOAD = 10pF
VCC = 5V OVERDRIVE = 5mV
4.5
RISING EDGE (tPDLH)
FALLING EDGE (tPDHL) 4.0 2.5
VCC = 3V 4.0 0 50 75 25 - 50 - 25 TEMPERATURE (C)
100
125
3.0
5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V)
5.5
6.0
1720 G08
1720 G09
Output High Voltage vs Load Current
0.0 125C VCC = 5V VCM = 1V VIN = 15mV - 55C - 0.4 25C
10 9 8
Supply Current vs Frequency
25C VCC = 5V
- 0.2
CLOAD = 20pF 7 6 NO LOAD 5 4 3
- 0.6
- 0.8 25C VCC = 2.7V -1.0 0 4 12 16 8 OUTPUT SOURCE CURRENT (mA) 20
1720 G11
20
1720 G10
0
10
20 FREQUENCY (MHz)
30
40
1720 G12
LT1720
TEST CIRCUITS
VTRIP Test Circuit
LTC203 BANDWIDTH-LIMITED TRIANGLE WAVE ~ 1kHz, VCM 7.5V 14 VCC 50k 0.1F 10nF 1F 1 8 - VCM 11 10 6 7 1/2 LT1112 + 1000 x VHYST 10k 15 3 2 1000 x VTRIP+ 16 9
+
50 50 DUT 1/2 LT1720
-
200k
1000 x VOS LTC203 10k
3 1/2 LT1638 100k 100k 1 2.4k 8 - + +
2
14
15 1000 x VTRIP-
10nF 16 9
1F
100k
NOTES: LT1638, LT1112, LTC203s ARE POWERED FROM 15V. 200k PULL-DOWN PROTECTS LTC203 LOGIC INPUTS WHEN DUT IS NOT POWERED
- 100k 1/2 LT1638 0.15F 6
1/2 LT1112 - 7 11 10
1720 TC01
+
Response Time Test Circuit
0V -100mV +VCC - VCM
+
25 25 50k 50
0.01F 10 x SCOPE PROBE (CIN 10pF)
DUT 1/2 LT1720
-
0.01F
0.1F PULSE IN
130 2N3866
V1*
0V -3V
1N5711
-VCM 400 750 *V1 = -1000 * (OVERDRIVE + VTRIP+) NOTE: RISING EDGE TEST SHOWN. FOR FALLING EDGE, REVERSE LT1720 INPUTS
50
-5V
1720 TC02
5
LT1720
APPLICATIONS INFORMATION
Input Voltage Considerations The LT1720 is specified for a common mode range of -100mV to 3.8V when used with a single 5V supply. A more general consideration is that the common mode range is -100mV below ground to 1.2V below VCC. The criterion for this common mode limit is that the output still responds correctly to a small differential input signal. Also, if one input is within the common mode limit, the other input signal can go outside the common mode limits, up to the absolute maximum limits (a diode drop past either rail at 10mA input current) and the output will retain the correct polarity. When either input signal falls below the negative common mode limit, the internal PN diode formed with the substrate can turn on, resulting in significant current flow through the die. An external Schottky clamp diode between the input and the negative rail can speed up recovery from negative overdrive by preventing the substrate diode from turning on. When both input signals are below the negative common mode limit, phase reversal protection circuitry prevents false output inversion to at least - 400mV common mode. However, the offset and hysteresis in this mode will increase dramatically, to as much as 15mV each. The input bias currents will also increase. When both input signals are above the positive common mode limit, the input stage will get debiased and the output polarity will be random. However, the internal hysteresis will hold the output to a valid logic level, and because the biasing of the two comparators are completely independent, there will be no impact on the other comparator. When at least one of the inputs returns to within the common mode limits, recovery from this state will take as long as 1s. The input stage is protected against damage from large differential signals, up to and beyond a differential voltage equal to the supply voltage, limited only by the absolute maximum currents noted. External input protection circuitry is only needed if currents would otherwise exceed these absolute maximums. The internal catch diodes can conduct current up to these rated maximums without latchup, even when the supply voltage is at the absolute maximum rating. The propagation delay does not increase significantly when driven with large differential voltages, but with low levels of overdrive, an apparent increase may be seen with large source resistances due to an RC delay caused by the 2pF typical input capacitance. Input Bias Current Input bias current is measured with both inputs held at 1V. As with any PNP differential input stage, the LT1720 bias current flows out of the device. It will go to zero on the higher of the two inputs and double on the lower of the two inputs. With more than two diode drops of differential input voltage, the LT1720's input protection circuitry activates, and current out of the lower input will increase an additional 30% and there will be a small bias current into the higher of the two input pins, of 4A or less. See the Typical Performance curve "Input Current vs Differential Input Voltage." High Speed Design Considerations Application of high speed comparators is often plagued by oscillations. The LT1720 has 4mV of internal hysteresis, which will prevent oscillations as long as parasitic output to input feedback is kept below 4mV. However, with the 2V/ns slew rate of the LT1720 outputs, a 4mV step can be created at a 100 input source with only 0.02pF of output to input coupling. The LT1720's pinout has been arranged to minimize problems by placing the most sensitive inputs (inverting) away from the outputs, shielded by the power rails. The input and output traces of the circuit board should also be separated, and the requisite level of isolation is readily achieved if a topside ground plane runs between the outputs and the inputs. For multilayer boards where the ground plane is internal, a topside ground or supply trace should be run between the inputs and outputs. Figure 1 shows a typical topside layout of the LT1720 on such a multilayer board. Shown is the topside metal etch including traces, pin escape vias, and the land pads for an SO-8 LT1720 and its adjacent X7R 10nF bypass capacitor in a 1206 case. The ground trace from Pin 5 runs under the device up to the bypass capacitor, shielding the inputs from the
6
U
W
U
U
LT1720
APPLICATIONS INFORMATION
VOUT
1720 F01
Figure 1. Typical Topside Metal for Multilayer PCB Layouts.
outputs. Note the use of a common via for the LT1720 and the bypass capacitor, which minimizes interference from high frequency energy running around the ground plane or power distribution traces. The supply bypass should include an adjacent 10nF ceramic capacitor and a 2.2F tantalum capacitor no farther than 5cm away; use more capacitance if driving more than 4mA loads. To prevent oscillations, it is helpful to balance the impedance at the inverting and noninverting inputs; source impedances should be kept low, preferably 1k or less. The outputs of the LT1720 are capable of very high slew rates. To prevent overshoot, ringing and other problems with transmission line effects, keep the output traces shorter than 10cm, or be sure to terminate the lines to maintain signal integrity. The LT1720 can drive DC terminations of 250 or more, but lower characteristic impedance traces can be used with series termination or AC termination topologies. Hysteresis The LT1720 includes internal hysteresis, which makes it easier to use than many other comparable speed comparators. The input-output transfer characteristic is illustrated in Figure 2 showing the definitions of VOS and VHYST based upon the two measurable trip points. The hysteresis band makes the LT1720 well behaved, even with slowly moving inputs. The exact amount of hysteresis will vary from part to part as indicated in the specifications table. The hysteresis level will also vary slightly with changes in supply voltage and common mode voltage. A key advantage of the LT1720 is the significant reduction in these effects, which is important whenever an LT1720 is used to detect a threshold crossing in one direction only. In such a case, the relevant trip point will be all that matters, and a stable
U
W
U
U
VOH VHYST (= VTRIP+ - VTRIP-)
VHYST/2
VOL 0 VTRIP
- + -
VIN = VIN+ - VIN-
VTRIP+
V + VTRIP VOS = TRIP 2
1720 F02
Figure 2. Hysteresis I/O Characteristics
offset voltage with an unpredictable level of hysteresis, as seen in competing comparators, is useless. The LT1720 is many times better than prior comparators in these regards. In fact, the CMRR and PSRR tests are performed by checking for changes in either trip point to the limits indicated in the specifications table. Because the offset voltage is the average of the trip points, the CMRR and PSRR of the offset voltage is therefore guaranteed to be at least as good as those limits. This more stringent test also puts a limit on the common mode and power supply dependence of the hysteresis voltage. Additional hysteresis may be added externally. The rail-torail outputs of the LT1720 make this more predictable than with TTL output comparators due to the LT1720's small variability of VOH (output high voltage). To add additional hysteresis, set up positive feedback by adding additional external resistor R3 as shown in Figure 3. Resistor R3 adds a portion of the output to the threshold set by the resistor string. The LT1720 pulls the outputs to the supply rail and ground to within 200mV of the rails with
VREF R2 R3
+
R1 1/2 LT1720
-
INPUT
1720 F03
Figure 3. Additional External Hysteresis
7
LT1720
APPLICATIONS INFORMATION
light loads, and to within 400mV with heavy loads. For the load of most circuits, a good model for the voltage on the right side of R3 is 300mV or VCC - 300mV. With this in mind, calculation of the resistor values needed is a two-step process. First, calculate the value of R3 based on the additional hysteresis desired, the VCC - 600mV output swing and the impedance of the primary bias string: R3 = (R1R2)(VCC - 0.6V)/(additional hysteresis) Additional hysteresis is the desired overall hysteresis less the internal 3.5mV hysteresis. The second step is to recalculate R2 to set the same average threshold as before. The average threshold before was set at VTH = (VREF)(R1)/(R1 + R2). The new R2 is calculated based on the average output voltage (VCC /2) and the simplified circuit model in Figure 4. To assure that the comparator's noninverting input is, on average, the same VTH as before: R2 = (VREF - VTH)/(VTH/R1 + (VTH - VCC /2)/R3) For additional hysteresis of 10mV or less, it is not uncommon for R2 to be the same as R2 within 1% resistor tolerances. This method will work for additional hysteresis of up to a few hundred millivolts. Beyond that, the impedance of R3 is low enough to effect the bias string, and adjustment of R1 may also be required. Note that the currents through the R1/R2 bias string should be many times the input currents of the LT1720. For 5% accuracy, the current must be at least 120A(6A IB / 0.05) more for higher accuracy. Interfacing the LT1720 to ECL The LT1720 comparators can be used in high speed applications where Emitter-Coupled Logic (ECL) is deployed. To interface the outputs of the LT1720 to ECL logic inputs, standard TTL/CMOS to ECL level translators such as the 10H124, 10H350 and 100124 can be used. These components come at a cost of a few nanoseconds additional delay as well as supply currents of 50mA or more, and are only available in quads. A faster, simpler and lower power translator can be constructed with resistors as shown in Figure 5. Figure 5a shows the standard TTL to Positive ECL (PECL) resistive level translator. This translator cannot be used for the LT1720, or with CMOS logic, because it depends on the 820 resistor to limit the output swing (VOH) of the allNPN TTL gate with its so-called totem-pole output. The LT1720 is fabricated in a complementary bipolar process and the output stage has a PNP driver that pulls the output nearly all the way to the supply rail, even when sourcing 10mA. Figure 5b shows a three resistor level translator for interfacing the LT1720 to ECL running off the same supply rail. No pull-down on the output of the LT1720 is needed, but pull-down R3 limits the VIH seen by the PECL gate. This is needed because ECL inputs have both a minimum and maximum VIH specification for proper operation. Resistor values are given for both ECL interface types; in both cases it is assumed that the LT1720 operates from the same supply rail. Figure 5c shows the case of translating to PECL from an LT1720 powered by a 3V supply rail. Again, resistor values are given for both ECL interface types. This time four resistors are needed, although with 10KH/E, R3 is not needed. In that case, the circuit resembles the standard TTL translator of Figure 5a, but the function of the new resistor, R4, is much different. R4 loads the LT1720 output when high so that the current flowing through R1 doesn't forward bias the LT1720's internal ESD clamp diode. Although this diode can handle 20mA without damage, normal operation and performance of the output stage can be impaired above 100A of forward current. R4 prevents this with the minimum additional power dissipation.
VREF R2 VTH R1 R3 V VAVERAGE = CC 2
+
1/2 LT1720
-
1720 F04
Figure 4. Model for Additional Hysteresis Calculations
8
U
W
U
U
LT1720
APPLICATIONS INFORMATION
Finally, Figure 5d shows the case of driving standard, negative-rail, ECL with the LT1720. Resistor values are given for both ECL interface types and for both a 5V and 3V LT1720 supply rail. Again, a fourth resistor, R4 is needed to prevent the low state current from flowing out of the LT1720, turning on the internal ESD/substrate diodes. Not only can the output stage functionality and speed suffer, but in this case the substrate is common to the two comparators in the LT1720, so operation of the other comparator in the same package could also be affected.
5V 180 5V
LSTTL
270
10KH/E
820
(a) STANDARD TTL TO PECL TRANSLATOR VCC
R1 1/2 LT1720
R2 10KH/E 100K/E R1 VCC R2 R3 5V OR 5.2V 510 180 750 4.5V 620 180 510
R3
(b) LT1720 OUTPUT TO PECL TRANSLATOR VCC 3V R2 10KH/E 100K/E R4 R1 VCC R2 R3 5V OR 5.2V 300 180 OMIT 560 4.5V 330 180 1500 1000
R1 1/2 LT1720 R4
R3
(c) 3V LT1720 OUTPUT TO PECL TRANSLATOR VCC
R4 1/2 LT1720
R1 R2 R3
(d) LT1720 OUTPUT TO STANDARD ECL TRANSLATOR
U
W
U
U
Resistor R4 again prevents this with the minimum additional power dissipation. For all the dividers shown, the output impedance is about 110. This makes these fast, less than a nanosecond, with most layouts. Avoid the temptation to use speedup capacitors. Not only can they foul up the operation of the ECL gate because of overshoots, they can damage the ECL inputs, particularly during power-up of separate supply configurations.
ECL FAMILY 10KH/E 100K/E VEE
VEE - 5.2V - 4.5V
VCC 5V 3V 5V 3V
R1 560 270 680 330
R2 270 510 270 390
R4 R3 330 1200 300 330 300 1500 270 430
1720 F05
Figure 5
9
LT1720
APPLICATIONS INFORMATION
The level translator designs assume one gate load. Multiple gates can have significant IIH loading, and the transmission line routing and termination issues also make this case difficult. ECL, and particularly PECL, is valuable technology for high speed system design, but it must be used with care. With less than a volt of swing, the noise margins need to be evaluated carefully. Note that there is some degradation of noise margin due to the 5% resistor selections shown. With 10KH/E, there is no temperature compensation of the logic levels, whereas the LT1720 and the circuits shown give levels that are stable with temperature. This will lower the noise margin over temperature. In some configurations it is possible to add compensation with diode or transistor junctions in series with the resistors of these networks. For more information on ECL design, refer to the ECLiPS data book (DL140), the 10KH system design handbook (HB205) and PECL design (AN1406), all from Motorola. Circuit Description The block diagram of one comparator in the LT1720 is shown in Figure 6. There are differential inputs (+ IN/- IN), an output (OUT), a single positive supply (VCC) and ground (GND). The two comparators are completely independent, sharing only the power and ground pins. The circuit topology consists of a differential input stage, a gain stage with hysteresis and a complementary
NONLINEAR STAGE
+
+IN
+
AV1
+
+
AV2 OUT
-IN
-
- + -
GND
1720 F06
Figure 6. LT1720 Block Diagram
10
U
W
U
U
common-emitter output stage. All of the internal signal paths utilize low voltage swings for high speed at low power. The input stage topology maximizes the input dynamic range available without requiring the power, complexity and die area of two complete input stages such as are found in rail-to-rail input comparators. With a 2.7V supply, the LT1720 still has a respectable 1.6V of input common mode range. The differential input voltage range is rail-torail, without the large input currents found in competing devices. The input stage also features phase reversal protection to prevent false outputs when the inputs are driven below the -100mV common mode voltage limit. The internal hysteresis is implemented by positive, nonlinear feedback around a second gain stage. Until this point, the signal path has been entirely differential. The signal path is then split into two drive signals for the upper and lower output transistors. The output transistors are connected common emitter for rail-to-rail output operation. The Schottky clamps limit the output voltages at about 300mV from the rail, not quite the 50mV or 15mV of Linear Technology's rail-to-rail amplifiers and other products. But the output of a comparator is digital, and this output stage can drive TTL or CMOS directly. It can also drive ECL, as described earlier, or analog loads as demonstrated in the applications to follow. The bias conditions and signal swings in the output stages are designed to turn their respective output transistors off faster than on. This nearly eliminates the surge of current
VCC
+ -
LT1720
APPLICATIONS INFORMATION
from VCC to ground that occurs at transitions, keeping the power consumption low even with high output-toggle frequencies. The load surge current is what keeps the power consumption low at high output-toggle frequencies. The frequency dependence of the supply current is shown in the Typical Performance Characteristics. Just 20pF of capacitive load on the output more than triples the frequency dependent rise. The slope of the no-load curve is just 32A/MHz. With a 5V supply, this current is the equivalent of charging and discharging just 6.5pF. The slope of the 20pF load curve is 133A/MHz, an addition of 101A/MHz, or 20A/MHz-V, units that are equivalent to picoFarads. The LT1720 dynamic current can be estimated by adding the capacitive loading to an internal equivalent capacitance of 5pF to 15pF, multiplied by the toggle frequency and the supply voltage. Because the capacitance of routing traces can easily approach these values, the dynamic current is dominated by the load in most circuits. Speed Limits The LT1720 comparators are intended for high speed applications, where it is important to understand a few limitations. These limitations can roughly be divided into three categories: input speed limits, output speed limits, and internal speed limits. There are no significant input speed limits except the shunt capacitance of the input nodes. If the 2pF typical input nodes are driven, the LT1720 will respond. The output speed is constrained by the slew currents available from the output transistors. To maintain low power quiescent operation, the LT1720 output transistors are sized to deliver 25mA to 45mA typical slew currents. This is sufficient to drive small capacitive loads and logic gate inputs at extremely high speeds. But the slew rate will slow dramatically with heavy capacitive loads. Because the propagation delay (tPD) definition ends at the time the output voltage is halfway between the supplies, the fixed slew current actually makes the LT1720 faster at 3V than 5V with 20mV of input overdrive. Another manifestation of the output speed limits is skew, the difference between tPD+ and tPD-. The slew currents of the LT1720 vary with the process variations of the PNP and NPN transistors, for rising edges and falling edges respectively. The typical 0.5ns skew can have either polarity, rising edge or falling edge faster. Again, the skew will increase dramatically with heavy capacitive loads. The skews of the two comparators in a single package are correlated, but not identical. Besides some random variability, there is a small (100ps to 200ps) systematic skew due to physical parasitics of the package itself. Comparator A, whose output is adjacent to the VCC pin, will have a relatively faster rising edge than comparator B. Likewise, comparator B, by virtue of an output adjacent to the ground pin will have a relatively faster falling edge. Of course, if the capacitive loads on the two comparators of a single package are not identical, the differential timing will degrade further. The internal speed limits manifest themselves as dispersion. All comparators have some degree of dispersion, defined as a change in propagation delay versus input overdrive. The propagation delay of the LT1720 will vary with overdrive, from a typical of 4.5ns at 20mV overdrive to 7ns at 5mV overdrive (typical). The LT1720's primary source of dispersion is the hysteresis stage. As a change of polarity arrives at the gain stage, the positive feedback of the hysteresis stage subtracts from the overdrive available. Only when enough time has elapsed for a signal to propagate forward through the gain stage, backwards through the hysteresis stage and forward through the gain stage again, will the output stage receive the same level of overdrive that it would have received in the absence of hysteresis. With 5mV of overdrive, the LT1720 is faster with a 5V supply than with a 3V supply, the opposite of what is true with 20mV overdrive. This is due to the internal speed limit, because the gain stage is faster at 5V than 3V due primarily to the reduced junction capacitances with higher reverse voltage bias. In many applications, as shown in the following examples, there is plenty of input overdrive. Even in applications providing low levels of overdrive, the LT1720 is fast enough that the absolute dispersion of 2.5ns (= 7 - 4.5) is small enough to ignore.
U
W
U
U
11
LT1720
APPLICATIONS INFORMATION
The gain and hysteresis stage of the LT1720 is simple, short and high speed to help prevent parasitic oscillations while adding minimum dispersion. This internal "self-latch" can be usefully exploited in many applications because it occurs early in the signal chain, in a low power, fully differential stage. It is therefore highly immune to disturbances from other parts of the circuit, either in the same comparator, on the supply lines or from the other comparator in the same package. Once a high speed signal trips the hysteresis, the output will respond, after a fixed propagation delay, without regard to these external influences that can cause trouble in nonhysteretic comparators. VTRIP Test Circuit The input trip points test circuit uses a 1kHz triangle wave to repeatedly trip the comparator being tested. The LT1720 output is used to trigger switched capacitor sampling of the triangle wave, with a sampler for each direction. Because the triangle wave is attenuated 1000:1 and fed to the LT1720's differential input, the sampled voltages are therefore 1000 times the input trip voltages. The hysteresis and offset are computed from the trip points as shown. Crystal Oscillators A simple crystal oscillator using one half of an LT1720 is shown on the first page of this data sheet. The 2k-620 resistor pair set a bias point at the comparator's noninverting input. The 2k-1.8k-0.1F path sets the inverting input node at an appropriate DC average level based on the output. The crystal's path provides resonant positive feedback and stable oscillation occurs. Although the LT1720 will give the correct logic output when one input is outside the common mode range, additional delays may occur when it is so operated, opening the possibility of spurious operating modes. Therefore, the DC bias voltages at the inputs are set near the center of the LT1720's common mode range and the 220 resistor attenuates the feedback to the noninverting input. The circuit will operate with any AT-cut crystal from 1MHz to 10MHz over a 2.7V to 6V supply range. As the power is applied, the circuit remains off until the LT1720 bias circuits activate, at a typical VCC of 2V to 2.2V (25C), at which point the desired frequency output is generated. The output duty cycle for this circuit is roughly 50%, but it is affected by resistor tolerances and, to a lesser extent, by comparator offsets and timings. If a 50% duty cycle is required, the circuit of Figure 7 creates a pair of complementary outputs with a forced 50% duty cycle. Crystals are narrow-band elements, so the feedback to the noninverting input is a filtered analog version of the square wave output. Changing the noninverting reference level can therefore vary the duty cycle. C1 operates as in the previous example, whereas C2 creates a complementary output by comparing the same two nodes with the opposite input polarity. A1 compares band-limited versions of the outputs and biases C1's negative input. C1's only degree of freedom to respond is variation of pulse width; hence the outputs are forced to 50% duty cycle. Again, the
VCC 2.7V TO 6V 2k 220 620 1MHz TO 10MHz CRYSTAL (AT-CUT)
12
U
W
U
U
+ -
GROUND CASE OUTPUT 100k 2k 0.1F 1.8k 0.1F
C1 1/2 LT1720
+
A1 LT1636 0.1F
-
1k
+
C2 1/2 LT1720
100k OUTPUT
-
1720 F07
Figure 7. Crystal Oscillator with Complementary Outputs and 50% Duty Cycle
LT1720
APPLICATIONS INFORMATION
circuit operates from 2.7V to 6V, and the skew between the edges of the two outouts are shown in Figure 8. There is a slight duty cycle dependence on comparator loading, so equal capacitive and resistive loading should be used in critical applications. This circuit works well because of the two matched delays and rail-to-rail style outputs of the LT1720. The circuit in Figure 9 shows a crystal oscillator circuit that generates two nonoverlapping clocks by making full use of
1000
800
OUTPUT SKEW (ps)
600
400
200
0 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0
1720 F08
Figure 8. Timing Skew of Figure 7's Circuit
VCC 2.7V TO 6V 2k 220 620 10MHz CRYSTAL (AT-CUT)
+ -
GROUND CASE OUTPUT 0 OPTIONAL-- SEE TEXT 100k
C1 1/2 LT1720
2k 1.3k
0.1F 1k
2.2k
+
C2 1/2 LT1720
-
Figure 9. Crystal-Based Nonoverlapping 10MHz Clock Generator
U
W
U
U
the two independent comparators of the LT1720. C1 oscillates as before, but with a lower reference level, C2's output will toggle at different times. The resistors set the degree of separation between the output's high pulses. With the values shown, each output has a 44% high and 56% low duty cycle, sufficient to allow 2ns between the high pulses where both are at logic low. Figure 10 shows the two outputs. The optional A1 feedback network shown can be used to force identical output duty cycles. Because the reference level set for C2 is lower than that set for C1, the steady state
Q0 2V/DIV
Q1 2V/DIV
20ns/DIV
Figure 10. Nonoverlapping Outputs of Figure 9's Circuit
+
A1 LT1636 0.1F
-
0.1F
100k OUTPUT 1
1720 F09
13
LT1720
APPLICATIONS INFORMATION
duty cycles will be 44% rather than 50%. Note, though, that the addition of this network only adjusts the percentage of time each output is high to be the same, which can be important in switching circuits requiring identical settling times. It cannot adjust the relative phases between the two outputs to be exactly 180 apart, because the signal at the input node driven by the crystal is not a pure sinusoid. Timing Skews For a number of reasons, the LT1720's superior timing specifications make it an excellent choice for applications requiring accurate differential timing skew. The two comparators in a single package are inherently well matched, with just 300ps tPD typical. Monolithic construction keeps the delays well matched vs supply voltage and temperature. Crosstalk between the comparators, usually a disadvantage in monolithic duals, has minimal effect on the LT1720 timing due to the internal hysteresis, as described in the Speed Limits section. The circuits of Figure 11 show basic building blocks for differential timing skews. The 2.5k resistance interacts with the 2pF typical input capacitance to create at least 4ns delay, controlled by the potentiometer setting. A differential and a single-ended version are shown. In the differential configuration, the output edges can be smoothly scrolled through t = 0 with negligible interaction.
LT1720 CIN CIN
+ -
CIN INPUT 2.5k CIN DIFFERENTIAL 4ns RELATIVE SKEW
CIN VREF VREF
CIN
1720 F11
Figure 11. Building Blocks for Timing Skew Generation with the LT1720
14
+
-
U
W
+
-
U
U
Fast Waveform Sampler Figure 12 uses a diode-bridge-type switch for clean, fast waveform sampling. The diode bridge, because of its inherent symmetry, provides lower AC errors than other semiconductor-based switching technologies. This circuit features 20dB of gain, 10MHz full power bandwidth and 100V/C baseline uncertainty. Switching delay is less than 15ns and the minimum sampling window width for full power response is 30ns. The input waveform is presented to the diode bridge switch, the output of which feeds the LT1227 wideband amplifier. The LT1720 comparators, triggered by the sample command, generate phase-opposed outputs. These signals are level shifted by the transistors, providing complementary bipolar drive to switch the bridge. A skew compensation trim ensures bridge-drive signal simultaneity within 1ns. The AC balance corrects for parasitic capacitive bridge imbalances. A DC balance adjustment trims bridge offset. The trim sequence involves grounding the input via 50 and applying a 100kHz sample command. The DC balance is adjusted for minimal bridge ON vs OFF variation at the output. The skew compensation and AC balance adjustments are then optimized for minimum AC disturbance in the output. Finally, unground the input and the circuit is ready for use.
LT1720
INPUT
+
2.5k CIN 0ns TO 4ns SINGLE-ENDED DELAY CIN
-
LT1720
APPLICATIONS INFORMATION
5V 2.2k 2.2k
INPUT 100mV FULL SCALE 1k = 1N5711 = CA3039 DIODE ARRAY (SUBSTRATE TO - 5V) 1.5k 3.6k 1.1k 0.1F AC BALANCE 3pF
+
CIN 1/2 LT1720
-
SAMPLE COMMAND 2k 10pF SKEW COMP 2.5k
+
1/2 LT1720 11 820 9 6 8
2k CIN
-
Figure 12. Fast Waveform Sampler Using the LT1720 for Timing-Skew Compensation
U
W
U
U
+
LT1227 OUTPUT 1V FULL SCALE 909
-
100 5V
1.1k
1.1k
1.1k MRF501 MRF501
DC BALANCE 500 680 820
LM3045 10 51 13 7 51
1720 F12
-5V
15
LT1720
APPLICATIONS INFORMATION
Voltage-Controlled Clock Skew Generator A tuning voltage of 0V to 2V creates approximately 10ns of skew between two output clocks. Refer to the circuit shown in Figure 13 which operates from 2.7V to 6V. It is sometimes necessary to generate pairs of identical clock signals that are phase skewed in time. Further, it is desirable to be able to set the amount of time skew via a tuning voltage. Figure 13's circuit does this by utilizing the LT1720 to digitize phase information from a varactortuned time domain bridge. A 0V to 2V control signal provides 10ns of output skew.
CLOCK INPUT VCC 2.7V TO 6V
2k 2.5k* 10ns TRIM "FIXED" "SKEWED" 12pF MV-209 VARACTOR DIODE 0.005F 36pF 2k* 14k 2.5k 2.5k
INPUT 0V TO 2V 10ns SKEW = 1N4148 = 74HC04 * 1% FILM RESISTOR ** SUMIDA CD43-100 POLYSTYRENE, 5%
+
A1 LT1077
L1** VCC 2.2F 6.2M* VC 1.82M* 200pF
+
VIN LT1317 SW FB GND
+
1.1M 100k
-
Figure 13. Voltage-Controlled Clock Skew
16
U
W
U
U
+
C1 1/2 LT1720 Q VCC FIXED OUTPUT
-
+
C2 1/2 LT1720 Q SKEWED OUTPUT
-
1M 0.1F 1M
47F
1720 F13
LT1720
APPLICATIONS INFORMATION
Coincidence Detector High speed comparators are especially suited for interfacing pulse-output transducers, such as particle detectors, to logic circuitry. The matched delays of a monolithic dual are well suited for those cases where the coincidence of two pulses needs to be detected. The circuit of Figure 14 is a coincidence detector that uses an LT1720 and discrete components as a fast AND gate. The reference level is set to 1V, an arbitrary threshold. Only when both input signals exceed this will a coincidence be detected. The Schottky diodes from the comparator outputs to the base of the MRF-501 form the AND gate, while the other two Schottkys provide for fast turn-off. A logic AND gate could instead be used, but would add considerably more delay than the 300ps contributed by this discrete stage. This circuit can detect coincident pulses as narrow as 2.5ns. For narrower pulses, the output will degrade gracefully, responding, but with narrow pulses that don't rise all the way to high before starting to fall. The decision delay is 4.5ns with input signals 50mV or more above the reference level. This circuit creates a TTL compatible output but it can typically drive CMOS as well.
51 5V
3.9k 1k 0.1F
51
COINCIDENCE COMPARATORS
Figure 14. A 2.5ns Coincidence Detector
+
-
U
W
U
U
5V
5V 300
GROUND CASE LEAD
+
1/2 LT1720
MRF501 OUTPUT
-
1/2 LT1720 4x 1N5711 300
1720 F14
300ps AND GATE
17
LT1720
SI PLIFIED SCHE ATIC W
VCC
150
-IN
150
OUTPUT
+IN
GND
1720 SS
W
18
LT1720
PACKAGE DESCRIPTION
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0- 8 TYP
0.016 - 0.050 0.406 - 1.270 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 8 7 6 5
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157** (3.810 - 3.988)
1
2
3
4
0.053 - 0.069 (1.346 - 1.752)
0.004 - 0.010 (0.101 - 0.254)
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) TYP
SO8 0996
19
LT1720
TYPICAL APPLICATION
Pulse Stretcher For detecting short pulses from a single sensor, a pulse stretcher is often required. The circuit of Figure 15 acts as a one-shot, stretching the width of an incoming pulse to a consistent 100ns. Unlike a logic one-shot, this LT1720based circuit requires only 100pV-s of stimulus to trigger. The circuit works as follows: Comparator C1 functions as a threshold detector, whereas comparator C2 is configured as a one-shot. The first comparator is prebiased with a threshold of 8mV to overcome comparator and system offsets and establish a low output in the absence of an input signal. An input pulse sends the output of C1 high, which in turn latches C2's output high. The output of C2 is fed back to the input of the first comparator, causing regeneration and latching both outputs high. Timing capacitor C now begins charging through R and, at the end
5V
51
24 R 1k 6.8k 1N5711 C 100pF C2 1/2 LT1720
2k 2k
Figure 15. A 1ns Pulse Stretcher
RELATED PARTS
PART NUMBER LT1016 LT1116 LT1394 LT1671 DESCRIPTION UltraFast Precision Comparator 12ns Single Supply Ground-Sensing Comparator 7ns, UltraFast, Single Supply Comparator 60ns, Low Power, Single Supply Comparator COMMENTS Industry Standard 10ns Comparator Single Supply Version of LT1016 6mA Single Supply Comparator 450A Single Supply Comparator
1720F LT/TP 1298 4K * PRINTED IN USA
20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
-
+
+
PULSE SOURCE 50
-
U
of 100ns, C2 resets low. The output of C1 also goes low, latching both outputs low. A new pulse at the input of C1 can now restart the process. Timing capacitor C can be increased without limit for longer output pulses. This circuit has an ultimate sensitivity of better than 14mV with 5ns to 10ns input pulses. It can even detect an avalanche generated test pulse of just 1ns duration with sensitivity better than 100mV.1 It can detect short events better than the coincidence detector of Figure 14 because the one-shot is configured to catch just 100mV of upward movement from C1's VOL, whereas the coincidence detector's 2.5ns specification is based on a full, legitimate logic high, without the help of a regenerative one-shot.
1 See Linear Technology Application Note 47, Appendix B. This circuit can detect the output of the
pulse generator described after 40dB attenuation.
15k C1 1/2 LT1720
0.01F OUTPUT
100ns
2k
1720 F15
(c) LINEAR TECHNOLOGY CORPORATION 1998

▲Up To Search▲

Price & Availability of 1720F

	To Download 1720F Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .