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| SPICE Device Model SI7392ADP Vishay Siliconix N-Channel Reduced Qg, Fast Switching WFET CHARACTERISTICS * N-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 73517 S-61151Rev. B, 26-Jun-06 www.vishay.com 1 SPICE Device Model SI7392ADP Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Condition Simulated Data 1.9 686 0.006 0.009 45 0.73 Measured Data Unit VGS(th) ID(on) rDS(on) gfs VSD VDS = VGS, ID = 250 A VDS 5 V, VGS = 10 V VGS = 10 V, ID = 12.5A VGS = 4.5 V, ID = 10A VDS = 15 V, ID = 12.5A IS = 2.7A V A 0.006 0.009 46 0.73 S V Drain-Source On-State Resistancea Forward Transconductancea Diode Forward Voltagea Dynamicb Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Ciss Coss Crss Qg Qgs Qgd VDS = 15 V, VGS = 10 V, ID = 12.5A VDS = 15 V, VGS = 0 V, f = 1 MHz 1626 360 136 22 11 VDS = 15 V, VGS = 4.5 V, ID = 12.5A 3.7 3.1 1465 360 150 25 12 3.7 3.1 nC pF Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 73517 S-61151Rev. B, 26-Jun-06 SPICE Device Model SI7392ADP Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 73517 S-61151Rev. B, 26-Jun-06 www.vishay.com 3 |
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