![]() |
|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
Final Electrical Specifications LTC1591 14-Bit Parallel, Low Glitch Multiplying DAC with 4-Quadrant Resistors November 1998 FEATURES s s DESCRIPTION The LTC (R)1591 is a parallel input 14-Bit multiplying current output DAC that operates from a single 5V supply. INL and DNL are accurate to 1LSB over the industrial temperature range in both 2- and 4-quadrant multiplying modes. 14-bit 4-quadrant multiplication is achieved with onchip 4-quadrant multiplication resistors. The LTC1591 is available in 28-pin SSOP package and is specified over the commercial and industrial temperature ranges. The device includes an internal deglitcher circuit that reduces the glitch impulse to less than 2nV-s (typ). The asynchronous CLR pin resets the LTC1591 to zero scale and the LTC1591-1 to midscale. The LTC1591 is pin compatible with the LTC1597, 16-bit parallel current output DAC. , LTC and LT are registered trademarks of Linear Technology Corporation. s s s s s DNL and INL: 1LSB Max On-Chip 4-Quadrant Resistors Allow Precise 0V to 10V, 0V to - 10V or 10V Outputs Asynchronous Clear Pin LTC1591: Reset to Zero Scale LTC1591-1: Reset to Midscale Glitch Impulse < 2nV-s 28-Lead SSOP Package Low Power Consumption: 10W Typ Power-On Reset APPLICATIONS s s s s Process Control and Industrial Automation Direct Digital Waveform Generation Software-Controlled Gain Adjustment Automatic Test Equipment TYPICAL APPLICATION 14-Bit, 4-Quadrant Multiplying DAC with a Minimum of External Components VREF 5V 0.1F 1/2 LT1112 INTEGRAL NONLINEARITY (LSB) 3 R1 R1 14 DATA INPUTS 10 TO 21, 24, 25 2 RCOM R2 1 REF 23 4 VCC ROFS ROFS RFB 5 RFB 33pF IOUT1 6 LTC1591-1 14-BIT DAC AGND DGND 22 7 1/2 LT1112 VOUT = -VREF TO VREF 1591 TA01 WR LD CLR WR LD CLR 9 8 28 NC 26 NC 27 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U + - U U LTC1591/LTC1591-1 Integral Nonlinearity 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 12288 8192 4096 DIGITAL INPUT CODE 16384 1591 TA02 VREF = 10V VOUT = 10V BIPOLAR + - 1 LTC1591 ABSOLUTE MAXIMUM RATINGS (Note 1) PACKAGE/ORDER INFORMATION TOP VIEW REF RCOM R1 ROFS RFB IOUT1 AGND LD WR 1 2 3 4 5 6 7 8 9 28 CLR 27 NC 26 NC 25 D0 24 D1 23 VCC 22 DGND 21 D2 20 D3 19 D4 18 D5 17 D6 16 D7 15 D8 G PACKAGE 28-LEAD PLASTIC SSOP N PACKAGE 28-LEAD PDIP VCC to AGND ............................................... - 0.5V to 7V VCC to DGND .............................................. - 0.5V to 7V AGND to DGND ............................................. VCC + 0.5V DGND to AGND ............................................. VCC + 0.5V REF, ROFS, RFB, R1, RCOM to AGND, DGND .......... 25V Digital Inputs to DGND ............... - 0.5V to (VCC + 0.5V) IOUT1 to AGND ............................ - 0.5V to( VCC + 0.5V) Maximum Junction Temperature .......................... 125C Operating Temperature Range Commercial ............................................ 0C to 70C Industrial ........................................... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C ORDER PART NUMBER LTC1591CG LTC1591CN LTC1591IG LTC1591IN LTC1591-1CG LTC1591-1CN LTC1591-1IG LTC1591-1IN D13 10 D12 11 D11 12 D10 13 D9 14 TJMAX = 125C, JA = 95C/ W (G) TJMAX = 125C, JA = 70C/ W (N) Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS VDD = 5V 10%, VREF = 10V, IOUT1 = AGND = DGND = 0V, TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER Accuracy Resolution Monotonicity INL DNL GE Integral Nonlinearity Differential Nonlinearity Gain Error (Note 2) TA = 25C TMIN to TMAX TA = 25C TMIN to TMAX Unipolar Mode (Note 3) TA = 25C TMIN to TMAX Bipolar Mode (Note 3) TA = 25C TMIN to TMAX Gain Temperature Coefficient Bipolar Zero Error ILKG PSRR OUT1 Leakage Current Power Supply Rejection (Note 4) Gain/Temperature TA = 25C TMIN to TMAX (Note 5) TA = 25C TMIN to TMAX VCC = 5V 10% q q q q CONDITIONS MIN 14 14 LTC1591/LTC1591-1 TYP MAX UNITS Bits Bits 1 1 1 1 4 6 4 6 1 2 3 5 5 15 0.1 1 q q q q q q ppm/C LSB LSB nA nA LSB/V 2 U W U U WW W LSB LSB LSB LSB LSB LSB LSB LSB LSB LTC1591 ELECTRICAL CHARACTERISTICS VCC = 5V, VREF = 10V, IOUT1 = AGND = DGND = 0V, TA = TMIN to TMAX, unless otherwise noted. SYMBOL RREF R1/R2 ROFS, RFB PARAMETER DAC Input Resistance (Unipolar) R1/R2 Resistance (Bipolar) Feedback and Offset Resistances Output Current Settling Time Midscale Glitch Impulse Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error THD Total Harmonic Distortion Output Noise Voltage Density Analog Outputs (Note 4) COUT Output Capacitance (Note 4) DAC Register Loaded to All 1s: COUT1 DAC Register Loaded to All 0s: COUT1 q q CONDITIONS (Note 6) (Notes 6, 13) (Note 6) (Notes 7, 8) (Note 12) (Note 9) VREF = 10V, 10kHz Sine Wave (Note 10) (Note 11) q q q MIN 4.5 9 9 TYP 6 12 12 1 2 1 1 108 10 115 70 MAX 10 20 20 UNITS k k k s nV-s nV-s mVP-P dB nV/Hz Reference Input AC Performance (Note 4) 130 80 pF pF V Digital Inputs VIH VIL IIN CIN tDS tDH tWR tLD tCLR tLWD VDD IDD Digital Input High Voltage Digital Input Low Voltage Digital Input Current Digital Input Capacitance Data to WR Setup Time Data to WR Hold Time WR Pulse Width LD Pulse Width Clear Pulse Width WR to LD Delay Time Supply Voltage Supply Current Digital Inputs = 0V or VCC (Note 4) VIN = 0V q q q q 2.4 0.8 0.001 1 8 60 0 60 110 60 0 4.5 5 5.5 10 20 -12 25 55 40 V A pF ns ns ns ns ns ns V A Timing Characteristics q q q q q q Power Supply q q The q denotes specifications that apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: 1LSB = 0.006% of full scale = 61ppm of full scale. Note 3: Using internal feedback resistor. Note 4: Guaranteed by design, not subject to test. Note 5: I(OUT1) with DAC register loaded to all 0s. Note 6: Typical temperature coefficient is 100ppm/C. Note 7: IOUT1 load = 100 in parallel with 13pF. Note 8: To 0.006% for a full-scale change, measured from the rising edge of LD. Note 8: VREF = 0V. DAC register contents changed from all 0s to all 1s or all 1s to all 0s. Note 10: VREF = 6VRMS at 1kHz. DAC register loaded with all 1s. Note 11: Calculation from en = 4kTRB where: k = Boltzmann constant (J/K), R = resistance (), T = temperature (K), B = bandwidth (Hz). Note 12: Midscale transition code 0111 1111 1111 11 to 1000 0000 0000 00. Note 13: R1 and R2 are measured between R1 and RCOM, REF and RCOM. 3 LTC1591 PIN FUNCTIONS REF (Pin 1): Reference Input and 4-Quadrant Resistor R2. Typically 10V, accepts up to 25V. In 2-quadrant mode, this pin is the reference input. In 4-quadrant mode, this pin is driven by an external inverting reference amplifier. RCOM (Pin 2): Center Tap Point of the Two 4-Quadrant Resistors R1 and R2. Normally tied to the inverting input of an external amplifier in 4-quadrant operation, otherwise shorted to the REF pin. See Figures 1 and 3. R1 (Pin 3): 4-Quadrant Resistor R1. In 2-quadrant operation short to the REF pin. In 4-quadrant mode tie to the reference input. ROFS (Pin 4): Bipolar Offset Resistor. Typically swings 10V, accepts up to 25V. In 2-quadrant operation tie to RFB. In 4-quadrant operation tie to R1. RFB (Pin 5): Feedback Resistor. Normally tied to the output of the current to voltage converter op amp. Swings to VREF. Typically VREF is 10V. IOUT1 (Pin 6): DAC Current Output. Tie to the inverting input of the current to voltage converter op amp. AGND (Pin 7): Analog Ground. Tie to ground. LD (Pin 8): DAC Digital Input Load Control Input. When LD is taken to a logic high, data is loaded from the input register into the DAC register, updating the DAC output. WR (Pin 9):DAC Digital Write Control Input. When WR is taken to a logic low, data is loaded from the digital input pins into the 14-bit wide input register. D13 to D2 (Pins 10 to 21): Digital Input Data Bits. DGND (Pin 22): Digital Ground. Tie to ground. VCC (Pin 23): The Positive Supply Input. 4.5V VCC 5.5V. Requires a bypass capacitor to ground. D1, D0 (Pins 24, 25): Digital Input Data Bits. NC (Pins 26, 27): Do not connect pins. CLR (Pin 28):Digital Clear Control Function for the DAC. When CLR is taken to a logic low, it sets the DAC output and all internal registers to zero code for the LTC1591 and midscale code for the LTC1591-1. BLOCK DIAGRA REF 1 12k RCOM 2 12k R1 3 48k 48k VCC 23 DECODER LD 8 WR 9 4 W U U U 48k 48k 5 RFB 12k 48k 48k 48k 48k 48k 96k 96k 96k 96k 12k 4 ROFS 6 IOUT1 7 AGND 22 DGND D12 D11 D10 D9 *** D0 (LSB) RST LOAD D13 (MSB) DAC REGISTER 28 CLR WR INPUT REGISTER RST 1591 BD 10 D13 11 D12 **** 21 D2 24 D1 25 D0 26 NC 27 NC LTC1591 TRUTH TABLE Table 1 CONTROL INPUTS CLR WR LD 0 1 1 1 1 1 1 0 X 0 1 0 X 0 1 1 REGISTER OPERATION Reset Input and DAC Register to All 0s for LTC1591 and midscale for LTC1591-1 (Asynchronous Operation) Load Input Register with All 14 Data Bits Load DAC Register with the Contents of the Input Register Input and DAC Register Are Transparent CLK = LD and WR Tied Together. The 14 Data Bits Are Loaded into the Input Register on the Falling Edge of the CLK and Then Loaded into the DAC Register on the Rising Edge of the CLK No Register Operation TI I G DIAGRA APPLICATIONS INFORMATION Description The LTC1591 is a 14-bit multiplying, current output DAC with a full parallel 14-bit digital interface. The device operates from a single 5V supply and provides both unipolar 0V to - 10V or 0V to 10V and bipolar 10V output ranges from a 10V or -10V reference input. It has three additional precision resistors on chip for bipolar operation. Refer to the block diagram regarding the following description. The 14-bit DAC consists of a precision R-2R ladder for the 11LSBs. The 3MSBs are decoded into seven segments of resistor value R. Each of these segments and the R-2R ladder carries an equally weighted current of one eighth of full scale. The feedback resistor RFB and 4-quadrant resistor ROFS have a value of R/4. 4-quadrant resistors R1 and R2 have a magnitude of R/4. R1 and R2 together with an external op amp (see Figure 3) inverts the reference input voltage and applies it to the 14-bit DAC input REF, in 4-quadrant operation. The REF pin presents a constant input impedance of R/8 in unipolar mode and R/12 in bipolar mode. The output impedance of the current output pin IOUT1 varies with DAC input code. The IOUT1 capacitance due to the NMOS current steering switches also varies with input code from 70pF to 115pF. An added feature of the LTC1591, especially for waveform generation, is a proprietary deglitcher that reduces glitch energy to below 2nV-s over the DAC output voltage range. Digital Section The LTC1591 has a 14-bit wide, full parallel data input bus. The device is double-buffered with two 14-bit registers. The double-buffered feature permits the update of several DACs simultaneously. The input register is loaded directly U W W tWR WR DATA tDS tDH tLWD LD tLD tCLR CLR 1591TD U U UW 5 LTC1591 APPLICATIONS INFORMATION from a 14-bit microprocessor bus when the WR pin is brought to a logic low level. The second register (DAC register) is updated with the data from the input register when the LD pin is brought to a logic high level. Updating the DAC register updates the DAC output with the new data. To make both registers transparent for flowthrough mode, tie WR low and LD high. However, this defeats the deglitcher operation and output glitch impulse may increase. The deglitcher is activated on the rising edge of the LD pin. The versatility of the interface also allows the use of the input and DAC registers in a master slave or edge-triggered configuration. This mode of operation occurs when WR and LD are tied together. The asynchronous clear pin resets the LTC1591 to zero scale and the LTC1591-1 to midscale. CLR resets both the input and DAC registers. The device also has a power-on reset. Table 1 shows the truth table for the device. Unipolar Mode (2-Quadrant Multiplying, VOUT = 0V to - VREF) The LTC1591 can be used with a single op amp to provide 2-quadrant multiplying operation as shown in Figure 1. With a fixed - 10V reference, the circuit shown gives a precision unipolar 0V to 10V output swing. Bipolar Mode (4-Quadrant Multiplying, VOUT = - VREF to VREF) The LTC1591 contains on chip all the 4-quadrant resistors necessary for bipolar operation. 4-quadrant multiplying operation can be achieved with a minimum of external 5V 0.1F VREF 3 R1 R1 14 DATA INPUTS 10 TO 21, 24, 25 WR LD CLR WR LD CLR 9 8 28 NC 26 NC 27 2 RCOM R2 1 REF 23 VCC 4 ROFS ROFS RFB 5 RFB 33pF IOUT1 LTC1591 14-BIT DAC 6 DGND 22 Figure 1. Unipolar Operation (2-Quadrant Multiplication) VOUT = 0V to - VREF 6 + AGND 7 - U W U U components, a capacitor and a dual op amp, as shown in Figure 3. With a fixed 10V reference, the circuit shown gives a precision bipolar - 10V to 10V output swing. Op Amp Selection Because of the high accuracy of the 14-bit LTC1591, thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. Fortunately, the sensitivity of INL and DNL to op amp offset has been greatly reduced compared to previous generations of multiplying DACs. Op amp offset will contribute mostly to output offset and gain and will have minimal effect on INL and DNL. For the LTC1591, a 1mV op amp offset will cause about 0.28LSB INL degradation and 0.08LSB DNL degradation with a 10V full-scale range. The main effects of op amp offset will be a degradation of zero-scale error equal to the op amp offset, and a degradation of full-scale error equal to twice the op amp offset. For the LTC1591, the same 1mV op amp offset will cause a 1.65LSB zero-scale error and a 3.25LSB full-scale error with a 10V full-scale range. Op amp input bias current (IBIAS) contributes only a zeroscale error equal to IBIAS(RFB//ROFS) = IBIAS(6k). Grounding As with any high resolution converter, clean grounding is important. A low impedance analog ground plane and star grounding should be used. AGND must be tied to the star ground with as low a resistance as possible. Unipolar Binary Code Table DIGITAL INPUT BINARY NUMBER IN DAC REGISTER MSB VOUT = 1111 1111 0V TO 1000 0000 -VREF 0000 0000 0000 0000 LSB 1111 0000 0000 0000 11 00 01 00 -VREF (16,383/16,384) -VREF (8,192/16,384) = -VREF/ 2 -VREF (1/16,384) 0V 1591 F01 ANALOG OUTPUT VOUT LT1001 LTC1591 APPLICATIONS INFORMATION 5V 0.1F 1/2 LT1112 2 RCOM VREF 3 R1 R1 14 DATA INPUTS 10 TO 21, 24, 25 WR LD CLR WR LD CLR 9 8 28 R2 1 REF LTC1591 14-BIT DAC AGND DGND NC 26 NC 27 22 7 Figure 2. Noninverting Unipolar Operation (2-Quadrant Multiplication) VOUT = 0V to VREF PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N Package 28-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 1.370* (34.789) MAX 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.255 0.015* (6.477 0.381) 1 0.300 - 0.325 (7.620 - 8.255) 0.130 0.005 (3.302 0.127) 0.020 (0.508) MIN 0.009 - 0.015 (0.229 - 0.381) 2 3 4 5 6 7 8 9 0.045 - 0.065 (1.143 - 1.651) ( +0.035 0.325 -0.015 8.255 +0.889 -0.381 ) 0.125 (3.175) MIN 0.005 (0.127) MIN 0.100 0.010 (2.540 0.254) 0.018 0.003 (0.457 0.076) N28 1197 *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) + - U U W + - U U 23 4 VCC ROFS ROFS RFB 5 RFB 33pF IOUT1 6 1/2 LT1112 VOUT = 0V TO VREF 15/97 F02 10 11 12 13 14 0.065 (1.651) TYP 7 LTC1591 PACKAGE DESCRIPTION 0.205 - 0.212** (5.20 - 5.38) 0 - 8 0.301 - 0.311 (7.65 - 7.90) 0.002 - 0.008 (0.05 - 0.21) 0.005 - 0.009 (0.13 - 0.22) 0.022 - 0.037 (0.55 - 0.95) 0.0256 (0.65) BSC *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE TYPICAL APPLICATION VREF 5V 0.1F 1/2 LT1112 3 R1 R1 14 DATA INPUTS 10 TO 21, 24, 25 2 RCOM R2 1 REF 23 4 VCC ROFS ROFS RFB LTC1591-1 14-BIT DAC AGND DGND 22 7 WR LD CLR WR LD CLR 9 8 28 NC 26 NC 27 Figure 3. Bipolar Operation (4-Quadrant Multiplication) VOUT = - VREF to VREF RELATED PARTS PART NUMBER Op Amps LT1001 LT1112 LT1468 DACs LTC1595/LTC1596 LTC1597/LTC1597-1 LTC1650 LTC1658 ADCs LTC1418 LTC1604 LTC1605 DESCRIPTION Precision Operational Amplifier Dual Low Power, Precision Picoamp Input Op Amp 90MHz, 22V/s, 16-Bit Accurate Op Amp Serial 16-Bit Current Output DACs Parallel 16-Bit Current Output DACs Serial 16-Bit Voltage Output DAC Serial 14-Bit Voltage Output DAC 14-Bit, 200ksps, 5V Sampling ADC 16-Bit, 333ksps Sampling ADC Single 5V, 16-Bit 100ksps ADC COMMENTS Low Offset, Low Drift Low Offset, Low Drift Precise, 1s Settling to 0.0015% Low Glitch, 1LSB Maximum INL, DNL On-Chip 4-Quadrant Resistors Low Noise and Glitch Rail-to-Rail VOUT Low Power, 8-Lead MSOP Rail-to-Rail VOUT 15mW Dissipation, Serial and Parallel Outputs 2.5V Input, SINAD = 90dB, THD = 100dB Low Power, 10V Inputs 1591I LT/TP 1198 4K * PRINTED IN USA 8 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com + - U Dimensions in inches (millimeters) unless otherwise noted. G Package 28-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 0.397 - 0.407* (10.07 - 10.33) 0.068 - 0.078 (1.73 - 1.99) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.010 - 0.015 (0.25 - 0.38) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 G28 SSOP 0694 U + - Bipolar Offset Binary Code Table 5 RFB 33pF IOUT1 6 DIGITAL INPUT BINARY NUMBER IN DAC REGISTER MSB 1111 1000 1000 0111 0000 LSB 1111 0000 0000 1111 0000 1111 0000 0000 1111 0000 11 01 00 11 00 VREF (8,191/8,192) VREF (1/8,192) 0V -VREF (1/8,192) -VREF 1591 F03 ANALOG OUTPUT VOUT 1/2 LT1112 VOUT = -VREF TO VREF (c) LINEAR TECHNOLOGY CORPORATION 1998 |
Price & Availability of 1591I
![]() |
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |