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| Ordering number : ENN5227B Thick-Film Hybrid IC STK672-040 Stepping Motor Driver (Sine Wave Drive) Output Current: 1.5 A (No Heat Sink*) Unipolar constant-current chopper (external excitation PWM) circuit with built-in microstepping controller Overview The STK672-040 is a stepping motor driver hybrid IC that uses power MOSFETs in the output stage. It includes a built-in microstepping controller and is based on a unipolar constant-current PWM system. The STK672-040 supports application simplification and standardization by providing a built-in 4 phase distribution stepping motor controller. It supports five excitation methods: 2 phase, 1-2 phase, W1-2 phase, 2W1-2 phase, and 4W1-2 phase excitations, and can provide control of the basic stepping angle of the stepping motor divided into 1/16 step units. It also allows the motor speed to be controlled with only a clock signal. The use of this hybrid IC allows designers to implement systems that provide high motor torques, low vibration levels, low noise, fast response, and high-efficiency drive. Compared to the earlier Sanyo STK672-010 Series, the STK672-040 features a smaller package, fewer external components, and controller improvements for even higher efficiency and even higher performance microstepping motor drive. Continued on next page. Applications * Facsimile stepping motor drive (send and receive) * Paper feed and optical system stepping motor drive in copiers * Laser printer drum drive * Printer carriage stepping motor drive * X-Y plotter pen drive * Industrial robots and other stepping motor applications Package Dimensions unit: mm 4161 [STK672-040] 53.0 9.0 22.0 Features * Can implement stepping motor drive systems simply by providing a DC power supply and a clock pulse generator. 1 2.0 21 x 2 = 42 22 4.0 0.5 0.4 2.9 Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 60200RM (OT) No. 5227-1/19 1.0 STK672-040 Continued from preceding page. * The CLK and RETURN input pins include built-in malfunction prevention circuits for external pulse noise. * ENABLE and RESET pins provided. These are Schmitt trigger inputs with built-in 20 k (typical) pull-up resistors. * No noise generation due to the difference between the A and B phase time constants during motor hold since external excitation is used. * Microstepping operation supported even for small motor currents, since the reference voltage Vref can be set to any value between 0 V and 1/2VCC2. Specifications Absolute Maximum Ratings at Ta = 25C Parameter Maximum supply voltage 1 Maximum supply voltage 2 Input voltage Phase output current Repeatable avalanche Power loss Operating temperature Junction temperature Storage temperature Symbol VCC1 max VCC2 max VIN max IOH max Ear max Pd max Tc max Tj max Tstg c-a = 0 No signal No signal Logic input pins 0.5 seconds, single pulse, with VCC1 applied. Load: R = 5 , L = 10 mH for each phase. Conditions Ratings 52 -0.3 to +7.0 -0.3 to +7.0 2.2 38 12 105 150 -40 to +125 Unit V V V A mJ W C C C Allowable Operating Ranges at Ta = 25C Parameter Supply voltage 1 Supply voltage 2 Input voltage Phase driver voltage handling Phase current Symbol VCC1 VCC2 VIH VDSS IOH max Tr1, 2, 3, and 4 (the A, A, B, and B outputs) Duty 50% Conditions With input signals present With input signals present Ratings 10 to 45 5 5% 0 to VCC2 100 (min) 1.5 (max) Unit V V V V A Electrical Characteristics at Tc = 25C, VCC1 = 24 V, VCC2 = 5 V Parameter Control supply current Output saturation voltage Average output current FET diode forward voltage [Control Inputs] Input voltage VIH VIL IIH IIL VI II VOH VOL Except for the Vref pin Except for the Vref pin Except for the Vref pin Except for the Vref pin 0 125 1 250 4 1 10 510 V V A A Symbol ICC Vsat Io ave Vdf Conditions Pin 7, with ENABLE pin held low. RL = 15 (I 1.5 A) Load: R = 3.5 W/L = 3.8 mH For each phase, Vref 1 V If = 1 A 0.465 Ratings min typ 4.5 1.4 0.517 1.2 max 15 1.9 0.569 1.8 Unit mA V A V Input current [Vref Input Pin] Input voltage Input current [Control Outputs] Output voltage Pin 8 Pin 8 0 1 2.5 V A I = -3 mA, pins MOI, MO1, MO2 I = +3 mA, pins MOI, MO1, MO2 2.4 0.4 V V Continued on next page. No. 5227-2/19 STK672-040 Continued from preceding page. Parameter [Current Distribution Ratio (A*B)] 2W1-2, W1-2, 1-2 2W1-2, W1-2 2W1-2 2W1-2, W1-2, 1-2 2W1-2 2W1-2, W1-2 2W1-2 2 PWM frequency Vref Vref Vref Vref Vref Vref Vref Vref fc 37 = 1/8 = 2/8 = 3/8 = 4/8 = 5/8 = 6/8 = 7/8 100 92 83 71 55 40 20 100 47 57 % % % % % % % % kHz Symbol Conditions Ratings min typ max Unit Note: A constant-voltage power supply must be used. The design target value is shown for the current distribution ratio. No. 5227-3/19 VCC2 7 12 13 8 6 5 2 1 Internal Block Diagram M4 M5 Vref A A B B M1 + - 9 Current distribution ratio switching + M2 10 Excitation mode control CWB 15 Phase advance counter Pseudo-sine wave generator - + - CLK 14 Rise/fall detection and switching M3 11 RETURN 17 Rise detection RESET 16 Phase excitation drive signal generation MoI 19 STK672-040 Mo1 20 - Excitation state monitor Mo2 21 + ENABLE 18 Reference clock generation PWM control + - RC oscillator 3 PG SUB 4 SG 22 A12389 No. 5227-4/19 STK672-040 Test Circuit Diagrams Vsat VCC2 7 Start 14 6 5 9 10 STK672-040 Vref = 2.5 V VCC2 4 + Vdf VCC1 7 A A B B STK672-040 V 4 3 22 A V 15 6 5 2 1 A A B B 2 1 8 16 22 3 A12390 A12391 IIH, IIL Ioave, Icc, fc VCC2 VCC2 7 9 10 11 12 13 14 STK672-040 15 14 16 14 17 14 18 14 14 8 22 + VCC1 A 7 Start 14 9 10 Vref = 1 V 5V 0V 8 18 STK672-040 6 2 5 1 A A B B a ba SW1 b M1 M2 M3 M4 IIH A IIL M5 CLK CWB RESET RETURN ENABLE Vref SW2 VCC1 Low when 0V measuring ICC VCC2 16 22 A A12392 A12393 When measuring Io ave: With SW1 set to `a', Vref = 1 V When measuring fc: With SW1 set to `b', Vref = 0 V When measuring Icc: Set ENABLE low. No. 5227-5/19 STK672-040 Operation Description 2W1-2 Phase Excitation Drive (microstepping operation) VCC2 = 5 V VCC1 = 10 V to 45 V 7 9 10 14 11 14 12 14 13 14 VCC2 = 5 V CLK 1 k + 6 5 2 1 Two-phase stepping motor A 100 F or higher SG PG VCC2 = 5 V A B B + 15 14 14 STK672-040 18 16 RESET RET MoI Mo1 Mo2 17 19 20 21 22 8 Vref 3 4 ENABLE A12394 Note: This hybrid IC must be initialized with a power on reset when power is first applied. [Setting the Motor Current] The motor current IOH is set by the Vref voltage on the hybrid IC pin 8. The following formula gives the relationship between IOH and Vref. 1 IOH = -- x Vref/Rs, Rs: The hybrid IC internal current detection resistor (0.33 3%) 3 Applications can use motor currents from the current (0.05 to 0.1 A) set by the duty of the frequency set by the oscillator up to the limit of the allowable operating range, IOH = 1.5 A IOL Ioave 0A Motor current waveform IOH A12395 [Function Table] M2 M1 M3 1 0 0 0 2 phase excitation 1-2 phase excitation 0 1 1-2 phase excitation W1-2 phase excitation 1 0 W1-2 phase excitation 1 1 2W1-2 phase excitation Phase switching clock edge timing Rising edge only Rising and falling edges 2W1-2 phase excitation 4W1-2 phase excitation Forward CWB 0 Reverse 1 ENABLE RESET Motor current is cut off when low Active low A Mo1 Mo2 1 0 A 0 0 B 0 1 B 1 1 No. 5227-6/19 STK672-040 Printed Circuit Board Design Recommendations This hybrid IC has two grounds, the PG pins (pins 3 and 4) and the SG pin (pin 22). These are connected internally in the hybrid IC. Two power supplies are required: a motor drive supply and a 5 V supply for the hybrid IC itself. If the ground connections for these supplies are not good, the motor current waveforms may become unstable, motor noise may increase, and vibration levels may increase. Use appropriate wiring for these grounds. Here we present two methods for implementing these ground connections. If the grounds for the motor drive supply and the hybrid IC 5 V supply are connected in the immediate vicinity of the power supplies: * If PG and SG are shorted at the power supply, connect only the PG line to pins 3 and 4 on the hybrid IC. Also, be sure that no problems occur due to voltage drops due to common impedances. In the specifications, this must be VCC2 5%. * The current waveforms will be more stable if the Vref ground is connected to pin 22. * For initial values, use 100 F or over for C1 and 10 F or over for C2. Locate C1 as close to the hybrid IC as possible, and the capacitor ground line must be as short as possible. Stepping motor Motor drive power supply PG 100 F or over STK672-040 C1 + 3 PG 4 7 VCC2 C2 10 F or over 5V power supply SG Oscillator circuit (CLK) + 8 Vref 14 CLK 22 SG A12396 If the grounds for the motor drive supply and the hybrid IC 5 V supply are separated: * Insert a capacitor (C1) of 100 F or over as close as possible to the hybrid IC. The capacitor ground line must be as short as possible. The capacitor C2 may be included if necessary. Its ground line should also be as short as possible. Stepping motor Motor drive power supply PG Separation 100 F or over STK672-040 C1 + 3 PG 4 7 VCC2 C2 10 F or over 5V power supply SG Oscillator circuit (CLK) + 8 Vref 14 CLK 22 SG A12397 No. 5227-7/19 STK672-040 Functional Description External Excitation Chopper Drive Block Description VCC1 M4 M5 IOFF ION Enable OA (control signal) Current divider Vref L2 OA L1 OA Divider CR oscillator 800 kHz A=1 45 kHz S D1 MOSFET AND Q Latch circuit R Noise filter - + Rs A12398 Driver Block Basic Circuit Structure Since this hybrid IC adopts an external excitation method, no external oscillator circuit is required. When a high level is input to oA in the basic driver block circuit shown in the figure and the MOSFET is turned on, the comparator + input will go low and the comparator output will go low. Since a set signal with the PWM period will be input, the Q output will go high, and the MOSFET will be turned on as its initial value. The current ION flowing in the MOSFET passes through L1 and generates a potential difference in Rs. Then, when the Rs potential and the Vref potential become the same, the comparator output will invert, and the reset signal Q output will invert to the low level. Then, the MOSFET will be turned off and the energy stored in L1 will be induced in L2 and the current IOFF will be regenerated to the power supply. This state will be maintained until the time when an input to the latch circuit set pin occurs. In this manner, the Q output is turned off and on repeatedly by the reset and set signals, thus implementing constant current control. The resistor and capacitor on the comparator input are spike removal circuit elements and synchronize with the PWM frequency. Since this hybrid IC uses a fixed frequency due to the external excitation method and at the same time also adopts a synchronized PWM technique, it can suppress the noise associated with holding a position when the motor is locked. Input Pin Functions Pin No. 14 15 17 18 9, 10, 11 12, 13 16 8 Symbol CLK CWB RETURN ENABLE M1, M2, M3 M4, M5 RESET Vref Function Phase switching clock Rotation direction setting (CW/CCW) Forced phase origin return Output cutoff Excitation mode setting Vector locus setting System reset Current setting Pin circuit type Built-in pull-up resistor CMOS Schmitt trigger input Built-in pull-up resistor CMOS Schmitt trigger input Built-in pull-up resistor CMOS Schmitt trigger input Built-in pull-up resistor CMOS Schmitt trigger input Built-in pull-up resistor CMOS Schmitt trigger input Built-in pull-up resistor CMOS Schmitt trigger input Built-in pull-up resistor CMOS Schmitt trigger input Operational amplifier input No. 5227-8/19 STK672-040 Input Signal Functions and Timing * CLK (phase switching clock) Input frequency range: DC to 50 kHz Minimum pulse width: 10 s Duty: 40 to 60% (However, the minimum pulse width takes precedence when M3 is high.) Pin circuit type: Built-in pull-up resistor (20 k, typical) CMOS Schmitt trigger structure Built-in multi-stage noise rejection circuit Function --When M3 is high or open: The phase excited (driven) is advanced one step on each CLK rising edge. --When M3 is low: The phase moves on both the rising and falling edges of the CLK signal, for a total of two steps per cycle. CLK Input Acquisition Timing (M3 = Low) CLK input System clock Phase excitation counter clock Excitation counter up/down Control output timing Control output switching timing A06845 * CWB (Method for setting the rotation direction) Pin circuit type: Built-in pull-up resistor (20 k, typical) CMOS Schmitt trigger structure Function --When CWB is high: The motor turns in the clockwise direction. --When CWB is low: The motor turns in the counterclockwise direction. Notes: When M3 is low, the CWB input must not be changed for about 6.25 s before or after a rising or falling edge on the CLK input. * RETURN (Forcible return to the origin for the currently excited phase) Pin circuit type: Built-in pull-up resistor (20 k, typical) CMOS Schmitt trigger structure Built-in noise rejection circuit Notes: The currently excited (driven) phase can be forcibly moved to the origin by switching this input from low to high. Normally, if this input is unused, it must be left open or connected to VCC2. * ENABLE (Controls the on/off state of the A, A, B, and B excitation drive outputs and selects either operating or hold as the internal state of this hybrid IC.) Pin circuit type: Built-in pull-up resistor (20 k, typical) CMOS Schmitt trigger structure Function --When ENABLE is high or open: Normal operating state --When ENABLE is low: This hybrid IC goes to the hold state and excitation drive output (motor current) is forcibly turned off. In this mode, the hybrid IC system clock is stopped and no inputs other than the reset input have any effect on the hybrid IC state. No. 5227-9/19 STK672-040 * M1, M2, and M3 (Excitation mode and CLK input edge timing selection) Pin circuit type: Built-in pull-up resistor (20 k, typical) CMOS Schmitt trigger structure Function: M2 M1 M3 1 0 0 0 2 phase excitation 1-2 phase excitation 0 1 1-2 phase excitation W1-2 phase excitation 1 0 W1-2 phase excitation 1 1 2W1-2 phase excitation Phase switching clock edge timing Rising edge only Rising and falling edges 2W1-2 phase excitation 4W1-2 phase excitation Valid mode setting timing: Applications must not change the mode in the period 5 s before or after a CLK signal rising or falling edge. Mode Setting Acquisition Timing CLK input System clock Mode setting M1 to M3 Mode switching clock Mode switching timing Hybrid IC internal setting state Phase excitation clock Excitation counter up/down A06846 * M4 and M5 (Microstepping mode rotation vector locus setting) M4 M5 Mode 1 1 Circular 0 0 1 0 0 1 Phase B 1 See page 10 for details on the current division ratio. Circular 2 3 Phase A A06847 * RESET (Resets all parts of the system.) Pin circuit type: Built-in pull-up resistor (20 k, typical) CMOS Schmitt trigger structure Function: --All circuit states are set to their initial values by setting the RESET pin low. (Note that the pulse width must be at least 10 s.) At this time, the A and B phases are set to their origin, regardless of the excitation mode. The output current goes to about 71% after the reset is released. Notes: When power is first applied to this hybrid IC, Vref must be established by applying a reset. Applications must apply a power on reset when the VCC2 power supply is first applied. * Vref (Sets the current level used as the reference for constant-current detection.) Pin circuit type: Analog input structure Function: --Constant-current control can be applied to the motor excitation current at 100% of the rated current by applying a voltage less than the control system power supply voltage VCC2 minus 2.5 V. --Applications can apply constant-current control proportional to the Vref voltage, with this value of 2.5 V as the upper limit. No. 5227-10/19 STK672-040 Output Pin Functions Pin No. 19 20, 21 Symbol MoI Mo1, Mo2 Function Phase excitation origin monitor Phase excitation state monitor Pin circuit type Standard CMOS structure Standard CMOS structure Output Signal Functions and Timing * A, A, B, and B (Motor phase excitation outputs) Function: --In the 4 phase and 2 phase excitation modes, a 3.75 s (typical) interval is set up between the A and A and B and B output signal transition times. * MO1, MO2, and MOI (Phase excitation state monitors) Pin circuit type: Standard CMOS structure Function: --Output of the current phase excitation output state. Phase coordinate Mo1 Mo2 Phase A 1 0 Phase B 0 1 Phase A 0 0 Phase B 1 1 MOI outputs a 0 when each phase is at the origin, and outputs a 1 otherwise. * Current division ratios set by M3, M4, and M5 ********* Values provided for reference purposes. Mode Setting M3 = 0 M3 = 1 Circular M4 = 1 M5 = 1 14 2W1-2 20 31 2W1-2 40 48 Current division ratio 4W1-2 2W1-2 2W1-2 55 65 71 77 2W1-2 83 88 2W1-2 92 97 2W1-2 100 M4 = 0 M5 = 0 15 25 34 44 51 62 69 77 82 88 92 95 98 100 M4 = 1 M5 = 0 15 23 33 42 49 57 65 71 77 85 89 95 98 100 M4 = 1 M5 = 1 13 19 28 39 45 54 62 69 74 82 85 92 94 100 7/8 6/8 5/8 % 4/8 3/8 2/8 1/8 1/16 2/16 3/16 4/16 5/16 6/16 7/16 8/16 9/16 10/16 11/16 12/16 13/16 14/16 Units Number of steps [Load conditions] VCC1 = 24 V, VCC2 = 5 V, R/L = 3.5/3.8mH No. 5227-11/19 STK672-040 Phase States During Excitation Switching * Excitation phases before and after excitation mode switching 2W1-2 phase 2 phase A 0 1 28 27 25 B 24 20 8B 12 9 20 17 19 16 A 16 A W1-2 phase 1-2 phase 30 4 28 B 24 20 22 20 18 16 A 1-2 phase 2 phase A 0 28 28 20 20 16 A 2 phase 1-2 phase A 0 4 B 12 12 18 A 2 phase W1-2 phase A 30 6 B 24 28 20 4 12 8B 22 B 28 20 4 12 B 20 21 16 A A 14 13 17 12 B 29 5 28 4 B 14 8B 22 4 26 0 28 20 4 6 B 12 16 B 10 21 13 17 A 2 phase 2W1-2 phase A 25 28 0 4 24 8 20 12 16 B 9 14 8B 12 12 10 22 20 18 16 A 1-2 phase W1-2 phase A 30 2 29 14 6 4 28 26 B 24 A 0 2 4 28 0 4 24 20 12 16 8 6 B 8B 10 12 23 21 19 17 A 1-2 phase 2W1-2 phase A 1 5 15 13 27 25 30 0 2 28 4 26 6 24 22 8 20 10 18 12 16 14 2W1-2 phase 1-2 phase 31 A 3 28 0 4 8 24 20 16 12 4 5 8B 11 12 2W1-2 phase W1-2 phase A 30 31 0 1 2 3 29 4 28 5 27 30 0 2 26 6 28 4 25 26 7 6 B 24 24 8 8B 22 10 23 20 9 1816 1412 22 10 11 21 20 12 13 19 18 17 161514 A W1-2 phase 2W1-2 phase A 29 31 1 3 5 7 B 9 11 28 4 B 24 15 W1-2 phase 2 phase 30 28 26 A 0 2 B 24 A A Excitation phase according to the first clock input pulse after changing the excitation mode setting (M1 and M2) Excitation phase immediately before setting the excitation mode A12399 No. 5227-12/19 STK672-040 * Excitation phases before and after excitation mode switching 2W1-2 phase 2 phase 31 A 0 28 28 B 24 23 20 8B 12 21 20 16 A W1-2 phase 2 phase 30 A 0 28 28 B 24 20 22 8B 12 22 20 16 A 1-2 phase 2 phase A 0 28 28 20 20 16 A 2 phase 1-2 phase A 0 4 B 12 12 18 A 2 phase W1-2 phase A 2 3 27 B 24 28 20 4 12 8B 26 B 28 20 4 12 B 10 19 A A A12400 2W1-2 phase 1-2 phase A 01 4 5 28 0 4 8 24 20 16 12 13 12 8B 9 2W1-2 phase W1-2 phase A 30 31 0 1 2 3 30 0 2 28 4 26 6 24 8 22 10 20 12 1816 14 29 4 7 25 B 24 29 28 27 26 25 B 24 23 22 21 20 4 5 6 7 15 1716 A 8B 9 10 11 12 13 19 18 17 161514 A W1-2 phase 1-2 phase 30 6 A 02 4 28 0 4 24 20 12 16 8 6 B 8B 10 12 18 16 A 1-2 phase W1-2 phase A 30 2 14 W1-2 phase 2W1-2 phase A 29 27 25 30 0 2 28 4 26 6 24 22 8 20 10 18 12 16 14 31 1 3 5 7 B 9 11 13 4 26 B 24 23 21 19 14 17 A 15 1-2 phase 2W1-2 phase A 30 27 B B 3 4 26 8B 22 28 0 4 24 20 16 12 10 14 6 28 0 4 24 8 20 12 16 B 24 7 B 11 23 19 A 15 2 phase 2W1-2 phase A B 28 20 4 12 11 B 16 A 18 No. 5227-13/19 STK672-040 Excitation Time and Timing Charts * CLK rising edge operation 2 Phase Excitation Timing Chart (M3 = 1) M1 0 M2 0 1 1-2 Phase Excitation Timing Chart (M3 = 1) 1 M1 0 M2 0 1 M3 0 RESET CWB CLK MOSFET gate signal M3 0 RESET CWB CLK MOSFET gate signal Comparator reference voltage A A B B A A B B MO1 MO2 MOI 100% MO1 MO2 MOI 100% 71% 71% Comparator reference voltage Vref A 100% Vref A 100% 71% 71% Vref B Vref B W1-2 Phase Excitation Timing Chart (M3 = 1) M1 0 1 2W1-2 Phase Excitation Timing Chart (M3 = 1) 1 M1 0 1 M2 0 1 M2 0 1 M3 0 RESET CWB CLK MOSFET gate signal M3 0 RESET CWB CLK MOSFET gate signal Comparator reference voltage A A B B A A B B MO1 MO2 MOI 100% 92% 71% MO1 MO2 MOI 100% 92% 83% 71% 55% 40% 20% Comparator reference voltage 40% Vref A 100% 92% 71% Vref A 100% 92% 83% 71% 55% 40% 20% 40% Vref B Vref B No. 5227-14/19 STK672-040 * CLK rising and falling edge operation 1-2 Phase Excitation Timing Chart (M3 = 0) M1 0 W1-2 Phase Excitation Timing Chart (M3 = 0) 1 M1 0 M2 0 M3 0 RESET CWB CLK MOSFET gate signal Comparator reference voltage M2 0 M3 0 RESET CWB CLK MOSFET gate signal A A B B A A B B MO1 MO2 MOI 100% MO1 MO2 MOI 100% 92% 71% 71% Comparator reference voltage 40% Vref A 100% Vref A 100% 92% 71% 71% 40% Vref B Vref B 2W1-2 Phase Excitation Timing Chart (M3 = 0) M1 0 1 4W1-2 Phase Excitation Timing Chart (M3 = 0) 1 M1 0 1 M2 0 M3 0 RESET CWB CLK MOSFET gate signal M2 0 M3 0 RESET CWB CLK MOSFET gate signal Comparator reference voltage 14% 14% A A B B A A B B MO1 MO2 MOI 100% 92% 83% 71% MO1 MO2 MOI 97% 92% 88% 83% 77% 100% 71% 65% 55% 48% 40% 31% 20% Comparator reference voltage 55% 40% 20% Vref A 100% 92% 83% 71% 55% 40% 20% Vref A 97% 92% 88% 83% 77% 100% 71% 65% 55% 48% 40% 31% 20% Vref B Vref B No. 5227-15/19 STK672-040 Thermal Design 1-2 phase excitation W1-2 phase excitation 2W1-2 phase excitation 4W1-2 phase excitation Here, t1 and t3 can be determined from the same formulas for all excitation methods. -L t1 = -------- * R + 0.88 R + 0.88 n (1 - ---------- * IOH) VCC1 -L t3 = ---- * R VCC1 + 0.88 n (--------------------) IOH * R + VCC1 + 0.88 However, the formula for t2 differs with the excitation method. 2 phase excitation 2 t2 = ------ - (t1 +t3) fclock 1-2 phase excitation 3 t2 = ------ - t1 fclock 15 t2 = ------ - t1 fclock IOH 7 W1-2 phase excitation t2 = ------ - t1 fclock 2W1-2 phase excitation 4W1-2 phase excitation t3 t1 t2 A12401 Motor Phase Current Model Figure (2 Phase Excitation) fclock: CLK input frequency (Hz) Vsat: The voltage drop of the power MOSFET and the current detection resistor (V) Vdf: The voltage drop of the body diode and the current detection resistor (V) IOH: Phase current peak value (A) t1: Phase current rise time (s) VCC1: Supply voltage applied to the motor (V) t2: Constant-current operating time (s) L: Motor inductance (H) t3: Phase switching current regeneration time (s) R: Motor winding resistance (W) No. 5227-16/19 STK672-040 Tc max: Hybrid IC substrate temperature (C) Ta: Application internal temperature (C) PdEX: Hybrid IC internal average loss (W) Determine c-a from the above formula and then size S (in cm2) of the heat sink from the graphs shown below. The ambient temperature of the device will vary greatly according to the air flow conditions within the application. Therefore, always verify that the size of the heat sink is adequate to assure that the Hybrid IC back surface (the aluminum plate side) will never exceed a Tc max of 105C, whatever the operating conditions are. Pd -- c-a 20 S -- c-a 2 Heat sink thermal resistance, c-a -- C/W Heat sink thermal resistance, c-a -- C/W Tc max - Ta c - a= ---------- ( (C/W) Pd Tc max = 105C m da tee re an tu ar era Gu mp te 16 2m 10 7 5 mA l pl ate 12 (fla (no Vertical standing type Natural convection air cooling sur fac e fi nis tb lac ks urf ace h) fin 8 ish bi en t 3 ) 60 4 C 40C 50C 2 No. Fin 23.0(C/W) 0 0 2 4 6 8 10 12 14 16 No. Fin 23.0(C/W) 1.0 10 2 3 5 7 100 2 3 5 IC internal average power loss, Pd -- W Heat sink surface area, S -- cm2 Next we determine the usage conditions with no heat sink by determining the allowable hybrid IC internal average loss from the thermal resistance of the hybrid IC substrate, namely 23 C/W. 105 - 50 For a Tc max of 105C at an ambient temperature of 50C PdEX = -------- = 2.3 W 23 For a Tc max of 105C at an ambient temperature of 40C 105 - 40 PdEX = -------- = 2.8 W 23 This hybrid IC can be used with no heat sink as long as it is used at operating conditions below the losses listed above. (See Tc - Pd curve in the graph on page 19.) No. 5227-17/19 STK672-040 fc -- VCC2 Tc = 25C 56 56 fc -- Tc 58 58 VCC2 = 5 V (fixed) PWM frequency, fc -- kHz 52 50 48 46 44 42 40 0 0 4.5 5.0 5.5 6.0 PWM frequency, fc -- kHz 54 54 52 50 48 46 44 42 40 0 0 20 40 60 80 100 120 140 Supply voltage, VCC2 -- V 4 Substrate temperature, Tc -- C 4 IOH -- Vsat VCC2 = 5 V (fixed) IOH -- Vdf VCC2 = 5 V (fixed) Tc = 105C Tc = 25C Output saturation voltage, Vsat -- V 3 Tc = 105C Phase output current, IOH -- A 3 Tc = 25C 2 2 1 1 0 0 1.0 2.0 3.0 0 0 1.0 2.0 3.0 Phase output current, IOH -- A 1.8 1.6 FET diode forward voltage, Vdf -- V 1.8 IOH -- VCC1 Test motor: PK244-01B Tc = 25C 1.5 A Phase output current, IOH -- A IOH -- Tc 1.5 A Test motor: PK244-01B VCC1 = 24V VCC2 = 5V 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 30 40 50 0 0 20 Motor output current, IOH -- A 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 1.0 A 1.0 A 0.5 A 0.5 A Vref = 0V 20 Vref = 0 V 40 60 80 100 120 140 Supply voltage, VCC1 -- V Substrate temperature, Tc -- C No. 5227-18/19 STK672-040 Tc -- PPS 60 1.2 IM -- VCC1 Tc = 25C VCC2 = 5 V PK244-01B Motor common pin current With one phase held. Substrate temperature increase, Tc -- C 2EX(VCC = 46 V IOH = 1.0 A) 40 Motor COM current, IM -- A 50 VCC1 = 24 V VCC2 = 5 V Test motor: PK244-01B (R = 3.3 /L = 3 mH) With IOH set at 1.0 A 1.0 0.8 30 2EX 2W1-2EX, 4W1-2EX W1-2EX 1-2EX 1k 10k 50k 0.6 IOH = 1.0 A 0.4 20 10 0.2 IOH = 0.5 A 0 100 0 10 20 30 40 50 Input PPS -- Hz Supply voltage, VCC1 -- V 90 Vref -- I 1.6 Tc -- Pd(typ) Self cooling for the independent (free standing) IC With no heat sink Substrate temperature increase, Tc -- C Motor current setting voltage, Vref -- V 1.4 loave 1.2 1.0 0.8 0.6 0.4 0.2 0 0 Tc = 25C VCC1 = 24 V VCC2 = 5 V IOL PK244-01B IOH In hold mode 80 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 1 2 3 4 5 6 Motor output current, IOH, IOL, Ioave -- A Power loss, Pd -- W Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 2000. Specifications and information herein are subject to change without notice. PS No. 5227-19/19 |
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