 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| .D w w w SymbiosTMm co . U t4 SYM53C140 Ultra2 ee ShBus Expander SCSI ta a June 1999 Version 1.0 m o .c Technical Manual U t4 e e h S ta a .D om .c w 4U w et w he aS (R) Order Number S14006 at .D w w w This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation. Document DB14-000087-00, First Edition (June 1999) This document describes version 1.0 of LSI Logic Corporation's SYM53C140 Ultra2 SCSI Bus Expander and will remain the official reference source for all revisions/releases of this product until rescinded by an update. The products in this manual are not intended for use in life-support appliances, devices, or systems. Use of these products in such applications without the written consent of the appropriate LSI Logic Corporation officer is prohibited. To receive product literature, visit us at http://www.lsilogic.com. LSI Logic Corporation reserves the right to make changes to any products herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties. Copyright (c) 1998, 1999 by LSI Logic Corporation. All rights reserved. TRADEMARK ACKNOWLEDGMENT The LSI Logic logo design, LVDlink, Symbios, and TolerANT are trademarks or registered trademarks of LSI Logic Corporation. All other brand and product names may be trademarks of their respective companies. SR ii Preface This manual provides a description and electrical characteristics of the SYM53C140 Ultra2 SCSI Bus Expander chip that supports all combinations of Single-Ended, Low-Voltage Differential, and HighVoltage Differential SCSI bus conversions. Audience This manual assumes some prior knowledge of current and proposed SCSI standards. For background information, please contact: ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3.131-199X (SCSI-2) Global Engineering Documents 15 Inverness Way East Englewood, CO 80112 (800) 854-7179 or (303) 397-7956 (outside U.S.) FAX (303) 397-2740 Ask for document number X3.131-1994 (SCSI-2) or X3.253 (SCSI-3 Parallel Interface) ENDL Publications 14426 Black Walnut Court Saratoga, CA 95070 (408) 867-6642 Document names: SCSI Bench Reference, SCSI Encyclopedia, SCSI Tutor Prentice Hall 113 Sylvan Avenue Englewood Cliffs, NJ 07632 (800) 947-7700 Preface iii Ask for document number ISBN 0-13-796855-8, SCSI: Understanding the Small Computer System Interface LSI Logic (Storage Components) Electronic Bulletin Board (719) 533-7235 SCSI Electronic Bulletin Board (719) 533-7950 LSI Logic World Wide Web Home Page www.lsil.com LSI Logic Internet Anonymous FTP Site ftp.symbios.com (204.131.200.1) Directory: /pub/symchips/scsi Organization This document has the following chapters and appendixes: * * Chapter 1, Introduction, contains the general information about the SYM53C140 product. Chapter 2, Functional Descriptions, describes the main functional areas of the chip in more detail, including the interfaces to the SCSI bus and external memory. Chapter 3, Specifications, contains the pin diagram, signal descriptions, electrical characteristics, AC timing diagrams, and mechanical drawing of the SYM53C140. Appendix A, Wiring Diagrams, contain wiring diagrams that show typical SYM53C140 usage. Appendix B, Glossary, contains commonly used terms and their definitions. * * * Revision Record Page No. Date Version Remarks All All 5/98 6/99 0.5 1.0 First draft of complete Data Manual. Misc. changes / corrections for product introduction. iv Preface Contents Chapter 1 Introduction 1.1 General Description 1.1.1 Applications 1.1.2 Features 1.1.3 Specifications 1.2 Benefits of LVDlink Functional Descriptions 2.1 Interface Signal Descriptions 2.1.1 SCSI A Side and B Side Control Blocks 2.1.2 Retiming Logic 2.1.3 State Machine Control 2.1.4 Precision Delay Control 2.1.5 DIFFSENS Receiver 2.1.6 Dynamic Transmission Mode Changes 2.1.7 SCSI Signal Descriptions 2.1.8 SCSI Termination Specifications 3.1 Signal Descriptions 3.2 Electrical Characteristics 3.2.1 DC Characteristics 3.2.2 TolerANT Technology Electrical Characteristics 3.2.3 AC Characteristics 3.2.4 SCSI Interface Timing 3.3 Mechanical Drawings 3.3.1 SYM53C140 160-pin PQFP Mechanical Drawing 1-1 1-2 1-4 1-5 1-6 Chapter 2 2-1 2-2 2-4 2-4 2-4 2-5 2-5 2-6 2-13 Chapter 3 3-1 3-7 3-7 3-11 3-15 3-15 3-17 3-18 Contents v Appendix A Wiring Diagrams A.1 SYM53C140 Wiring Diagrams Glossary Index Customer Feedback A-1 Appendix B Figures 1.1 1.2 1.3 2.1 2.2 2.3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 A.1 Tables 1.1 1.2 1.3 Types of Operation SCSI Bus Distance Requirements Transmission Mode Distance Requirements 1-2 1-3 1-4 SYM53C140 SCSI Bus Modes SYM53C140 Server Clustering SYM53C140 SCSI Bus Device SYM53C140 Block Diagram SYM53C140 Signal Grouping SCSI Termination SYM53C140 160-pin PQFP Pin Diagram SYM53C140 Functional Signal Grouping LVD Driver LVD Receiver External Reset Circuit Rise and Fall Time Test Conditions SCSI Input Filtering Hysteresis of SCSI Receivers Input Current as a Function of Input Voltage Output Current as a Function of Output Voltage Clock Timing Input/Output Timing SYM53C140 160 Pin PQFP (PF) Mechanical Drawing SYM53C140 Wiring Diagram 1 of 4 1-1 1-3 1-4 2-2 2-6 2-14 3-2 3-3 3-8 3-9 3-11 3-13 3-13 3-13 3-14 3-14 3-15 3-16 3-18 A-2 vi Contents 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 DIFFSENS Voltage Levels Direction Control Signal Polarities HVD_MODE Control Signal Polarity RESET/ Control Signal Polarity Mode Sense Control Voltage Levels WS_ENABLE Signal Polarity XFER_ACTIVE Signal Polarity SCSI A Side Interface Pins SCSI B Side Interface Pins Chip Interface Control Pins Power and Ground Pins Absolute Maximum Stress Ratings Operating Conditions LVD Driver SCSI Signals -- B_SD[15:0] ,B_SDP[1:0] , B_SCD ,B_SIO ,B_SMSG ,B_SREQ ,B_SACK , B_SBSY ,B_SATN ,B_SSEL ,B_SRST LVD Receiver SCSI Signals -- B_SD[15:0] ,B_SDP[1:0] , B_SCD ,B_SIO ,B_SMSG ,B_SREQ ,B_SACK , B_SBSY ,B_SATN ,B_SSEL ,B_SRST DIFFSENS SCSI Signal Input Capacitance Bidirectional SCSI Signals -- A_SD[15:0]/, A_SDP[1:0]/, A_SREQ/, A_SACK/, B_SD[15:0] ,B_SDP[1:0] , B_SREQ ,B_SACK Bidirectional SCSI Signals -- A_SCD/, A_SIO/, A_SMSG/, A_SBSY/, A_SATN/, A_SSEL/, A_SRST/, B_SCD , B_SIO ,B_SMSG ,B_SBSY ,B_SATN ,B_SSEL ,B_SRST Input Control Signals -- CLOCK, RESET/, WS_ENABLE Output Control Signals -- BSY_LED, XFER_ACTIVE TolerANT Technology Electrical Characteristics Clock Timing Input Timing Output Timing 2-5 2-11 2-11 2-12 2-12 2-13 2-13 3-4 3-5 3-5 3-6 3-7 3-8 3-8 3-9 3-9 3-9 3-10 3-10 3-10 3-11 3-11 3-15 3-15 3-16 Contents vii viii Contents Chapter 1 Introduction 1.1 General Description The SYM53C140 Ultra2 SCSI Bus Expander is a single chip solution allowing the extension of SCSI device connectivity and/or cable length limits. A SCSI bus expander couples bus segments together without any impact to the SCSI protocol, software, or firmware. The SYM53C140 Ultra2 SCSI Bus Expander connects Single-Ended (SE) Ultra, LowVoltage Differential (LVD) Ultra2 or High-Voltage Differential (HVD) peripherals together in any combination. The SYM53C140 is capable of supporting any combination of bus mode SE, HVD, or LVD on either the A or B Side port. This provides the system designer with maximum flexibility in designing SCSI backplanes to accommodate any SCSI bus mode. Figure 1.1 A-Side LVD HVD (*) SE SCSI Expander 160 PQFP SYM53C140 SYM53C140 SCSI Bus Modes B-Side LVD HVD (*) SE Figure 1.1 shows the three SCSI bus modes available on the A or B Side. LVDlinkTM transceivers provide the multimode LVD, SE, or HVD capability. The SYM53C140 operates either as a expander or converter. In both SCSI Bus Expander and Converter modes, cable segments are electrically isolated from each other. This feature maintains the signal integrity of each cable segment. Symbios SYM53C140 Ultra2 SCSI Bus Expander 1-1 As shown in Table 1.1, the SYM53C140 operates in all modes: singleended, low-voltage differential, and high-voltage differential. Table 1.1 Signal Type LVD to LVD HVD to HVD1 Types of Operation Mode Repeater Repeater Repeater Speed Ultra2 Ultra Ultra SE to SE Or any combination above for Repeater. LVD to HVD1 LVD to SE HVD1 to SE Converter Converter Converter Ultra Ultra Ultra Or any combination above for Converter. 1. All HVD requires external differential transceivers and terminations. The SYM53C140 provides additional control capability through the pin level electrical isolation mode. This feature permits logical disconnection of both the A Side bus and the B Side bus without disrupting SCSI transfers currently in progress. For example, devices on the logically disconnected B Side can be swapped out while the A Side bus remains active. The SYM53C140 is based on bus expander technology resulting in some signal filtering and re-timing to maintain signal skew budgets. The SYM53C140 is independent of software. 1.1.1 Applications * * Server clustering environments Expanders creating distinct SCSI cable segments which are electrically isolated from each other 1-2 Introduction Figure 1.2 SYM53C140 Server Clustering Segment A Segment B SCSI Bus Expander SCSI Bus Expander Primary Server Secondary Server Segment C Shared Disk Subsystem Figure 1.2 demonstrates how SCSI bus expanders are used to couple bus segments together without any impact of the SCSI protocol or software. Configurations that use the SYM53C140 SCSI Bus Expander in the Ultra2 mode (LVD to LVD) allow the system designer to take advantage of the inherent cable distance, device connectivity, data reliability, and increased transfer rate benefits of LVD signaling with Ultra2 SCSI peripherals. In Figure 1.2 example, the SYM53C140 is configured as a three port expander board. This configuration allows segments A and B to be treated as a point-to-point segment. Segment C is treated as a load segment with at least 8 inches between every node. Table 1.2 shows the various distance requirements for each SCSI bus mode. Table 1.2 Segment A, B SCSI Bus Distance Requirements Mode LVD (Ultra2) SE (Ultra) HVD (Ultra) Length Limit 25 meters 20 meters 25 meters 12 meters 1.5 meters 25 meters Segment C LVD (Ultra2) SE (Ultra) HVD (Ultra) General Description 1-3 In the second example, Figure 1.3, the SYM53C140 is cascaded to achieve four distinct SCSI segments. Segments A and D can be treated as point-to-point segments. Segments B and C are treated as load segments with at least 8 inch spacing between every node. Table 1.3 shows the various distance requirements for each transmission mode. Figure 1.3 SYM53C140 SCSI Bus Device Segment A SCSI Bus Segment B SCSI Bus Segment C SCSI Bus Segment D Expander Expander Expander Primary Server Secondary Server Shared Disk Subsystem Shared Disk Subsystem Table 1.3 Segment A, D Transmission Mode Distance Requirements Mode LVD (Ultra2) SE (Ultra) HVD (Ultra) Length Limit 25 meters 20 meters 25 meters 12 meters 1.5 meters 25 meters B, C LVD (Ultra2) SE (Ultra) HVD (Ultra) 1.1.2 Features * A flexible SCSI bus expander that supports any combination of LowVoltage Differential (LVD), Single-Ended (SE), or High-Voltage Differential Transceivers (HVD) Creates distinct SCSI bus segments that are electrically isolated from each other * 1-4 Introduction * * Integrated LVDlink transceivers for direct attachment to either LVD, SE, or HVD bus segments Operates as a SCSI Bus Expander - - - LVD to LVD (Ultra2 SCSI) HVD to HVD (Ultra SCSI) SE to SE (Ultra SCSI) * Operates as a SCSI Bus Converter - - - LVD to HVD (Ultra SCSI) LVD to SE (Ultra SCSI) HVD to SE (Ultra SCSI) * * * * * * * * * Targets and initiators may be located on either the A or B Side of the device Accepts any asynchronous or synchronous transfer speed up to Ultra2 SCSI (for LVD to LVD mode only) Supports dynamic addition/removal of SCSI bus segments via the electrical isolation mode Does not consume a SCSI ID Propagates the RESET/ signal from one side to the other regardless of the SCSI bus state Notifies initiator(s) of changes in transmission mode (SE/LVD/HVD) on A or B side segments via SCSI bus RESET SCSI Busy LED driver for activity indicator Up to four SYM53C140s may be cascaded Completely independent of software 1.1.3 Specifications * * * * 40 MHz Input Clock 160-pin Plastic Quad Flat Pack (PQFP) Compliant with the SCSI Parallel Interconnect 2(SPI-2) Compliant with SCSI Enhanced Parallel Interface (EPI) Specifications General Description 1-5 1.2 Benefits of LVDlink The SYM53C140 supports Low-Voltage Differential (LVD) technology for SCSI, a signaling technology that increases the reliability of SCSI data transfers over longer distances than those supported by single-ended SCSI technology. The low current output of LVD allows the I/O transceivers to be integrated directly onto the chip. LVD provides the reliability of High-Voltage Differential (HVD) SCSI technology without the added cost of external differential transceivers. LVD allows a longer SCSI cable and more devices on the bus. LVD provides a long-term migration path to even faster SCSI transfer rates without compromising signal integrity, cable length, or connectivity. For backward compatibility to existing single-ended devices, the SYM53C140 features multimode LVDlink transceivers that can switch between LVD and single-ended modes. * Integrated LVDlink Multimode transceivers - - - - Supports single-ended, LVD, or HVD technology (HVD must have external transceivers) Allows greater device connectivity and longer cable length LVDlink transceivers save the cost of external differential transceivers Supports a long-term performance migration path 1-6 Introduction Chapter 2 Functional Descriptions 2.1 Interface Signal Descriptions The SYM53C140 has no programmable registers, and therefore, no software requirements. SCSI control signals control all SYM53C140 functions. This chapter describes all signals, their groupings and their functions. Figure 2.1 shows a block diagram of the SYM53C140 device divided into the following blocks: * * * * * A Side SCSI Control Block - LVD, SE, and HVD Drivers and Receivers B Side SCSI Control Block - LVD, SE, and HVD Drivers and Receivers Retiming Logic Precision Delay Control State Machine Control Symbios SYM53C140 Ultra2 SCSI Bus Expander 2-1 Figure 2.1 Control Signals SYM53C140 Block Diagram SCSI Control Block SCSI Control Block LVDinkTM Transceivers LVD, Single-ended, HVD Wide Ultra SCSI Bus (A Side) LVDinkTM Transceivers Retiming Logic LVD, Single-ended, HVD Wide Ultra SCSI Bus (B Side) LVD DIFFSENS Receiver A_DIFFSENS Precision Delay Control State Machine Control LVD DIFFSENS Receiver B_DIFFSENS 40 MHz Clock Input In its simplest form, the SYM53C140 passes data and parity from a source bus to a load bus. The side asserting, deasserting, or releasing the SCSI signals is the source side. The model of the SYM53C140 is pieces of wire that allow corresponding SCSI signals to flow from one side to the other side. The SYM53C140 needs to know which signals are being driven by another device so it can enable the proper drivers to pass the signals along. In addition, the SYM53C140 does some signal retiming to maintain the signal skew budget from the source bus to the load bus as if the source was a local bus member. 2.1.1 SCSI A Side and B Side Control Blocks The SCSI A Side pins are connected internally to the corresponding SCSI B Side pins, forming bidirectional connections to the SCSI bus. In the LVD/LVD mode, the SCSI A Side and B Side control blocks connect to both targets and initiators and accept any asynchronous or synchronous data transfer rates up to the 80 Mbytes/s rate of Wide Ultra2 SCSI. TolerANT(R) and LVDlink technologies are part of both the A Side and B Side control blocks. 2-2 Functional Descriptions 2.1.1.1 SYM53C140 Requirements for Synchronous Negotiation The SYM53C140 builds a table of information regarding devices on the bus in on-chip RAM. The SDTR and WDTR information for each device is taken from the MSG byte during negotiation. For all devices in the configuration to communicate accurately with each other through the SYM53C140 at Ultra2 (Fast 40) rates, it is necessary for a complete synchronous negatiation to take place between the initatiator(s) and target(s) prior to any data transfer. Otherwise, the SYM53C140 defaults to Fast 20 rates. 2.1.1.2 TolerANT Technology In the single-ended mode, the SYM53C140 features TolerANT technology, which includes active negation on the SCSI drivers and input signal filtering on the SCSI receivers. Active negation causes the SCSI Request, Acknowledge, Data, and Parity signals to be actively driven HIGH rather than passively pulled up by terminators. TolerANT receiver technology improves data integrity in unreliable cabling environments, where other devices would be subject to data corruption. TolerANT receivers filter the SCSI bus signals to eliminate unwanted transitions without the long signal delays associated with RCtype input filters. This improved driver and receiver technology helps eliminate double clocking of data, the single biggest reliability issue with SCSI operations. The benefits of TolerANT technology include increased immunity to noise on the deasserting signal edge, better performance due to balanced duty cycles, and improved SCSI transfer rates. In addition, TolerANT SCSI devices prevent glitches on the SCSI bus at power-up or power-down, so other devices on the bus are also protected from data corruption. 2.1.1.3 LVDlink Technology To support greater device connectivity and longer SCSI cables, the SYM53C140 features LVDlink technology, the LSI Logic implementation of multimode LVD SCSI. LVDlink transceivers provide the inherent reliability of differential SCSI, and a long-term migration path of faster SCSI transfer rates. Interface Signal Descriptions 2-3 LVDlink technology is based on current drive. Its low output current reduces the power needed to drive the SCSI bus. Therefore, the I/O drivers can be integrated directly onto the chip. This reduces the cost and complexity compared to traditional (high power) differential designs. LVDlink lowers the amplitude of noise reflections and allows higher transmission frequencies. The LVDlink transceivers in side A and side B operate in the LVD, HVD (external differential transceivers), or single-ended modes. The SYM53C140 automatically detects the type of signal connected, based on the voltages detected by A_DIFFSENS and B_DIFFSENS. 2.1.2 Retiming Logic The SCSI signals, as they propagate from one side of the SYM53C140 to the other side, are processed by logic circuits that re-time the bus signals, as needed, to guarantee or improve the required SCSI timings. The logic circuitry is governed by the State Machine Controls that keep track of SCSI phases, the location of initiator and target devices, and various timing functions. In addition, the logic circuitry contains numerous delay elements that are periodically calibrated by the Precision Delay Control block in order to guarantee specified timing such as output pulse widths, setup and hold times, and others. 2.1.3 State Machine Control The State Machine Control keeps track of the SCSI bus phase protocol and other internal operating conditions. This block provides signals to the Retiming Logic that identify how to properly handle SCSI bus signal retiming and protocol, based on observed bus conditions. 2.1.4 Precision Delay Control The Precision Delay Control block provides calibration information to the precision delay elements in the Retiming Logic block in order to maintain precise timing as signals propagate through the device. As the SYM53C140 operating conditions (such as voltage and temperature) vary over time, the Precision Delay Control block will periodically update the delay settings in the Retiming Logic to maintain constant and precise control over bus timing. 2-4 Functional Descriptions 2.1.5 DIFFSENS Receiver The SYM53C140 contains LVD DIFFSENS Receivers that detect the voltage level on the A Side or B Side DIFFSENS lines to inform the SYM53C140 of the transmission mode being used by the SCSI buses. The LVD DIFFSENS Receivers are capable of detecting the voltage level of incoming SCSI signals to determine whether it is from a single-ended, LVD, or HVD device. A device will not change its present signal driver or receiver mode based on the DIFFSENS voltage levels unless a new mode is sensed continuously for at least 100 ms. Transmission mode detection for SE, LVD, or HVD is accomplished through the use of the DIFFSENS lines. Table 2.1 shows the voltages on the DIFFSENS lines and modes they will cause. Table 2.1 DIFFSENS Voltage Levels Mode SE LVD HVD Voltage -0.35 to +0.5 +0.7 to +1.9 +2.4 to +5.5 2.1.6 Dynamic Transmission Mode Changes Any dynamic mode change (SE/LVD/HVD) on a bus segment is considered to be a catastrophic event that requires the initiator to determine whether the mode change meets the requirements for that bus segment. The SYM53C140 supports dynamic transmission mode changes by notifying the initiator(s) of changes in transmission mode (SE/LVD/HVD) on A or B side segments via SCSI bus RESET. The DIFFSENS line is used to detect a valid mode switch on the bus segments. After the DIFFSENS state is present for 100 ms, the SYM53C140 generates a SCSI reset on the opposite bus from the one that the transmission mode change occurred on. This reset is used to inform any initiators residing on the opposite segment about the change in the transmission mode. The initiator(s) will then renegotiate synchronous transfer rates with each device on that segment to ensure that there is a valid bus segment for that mode. Interface Signal Descriptions 2-5 2.1.7 SCSI Signal Descriptions Figure 2.2 shows the SYM53C140 signal grouping. A description of the signal groups follow. For a description of a specific signal, see Section 3.1, "Signal Descriptions" in Chapter 3. For a signal electrical characteristics, see Section 3.2, "Electrical Characteristics" in Chapter 3. For SCSI bus signal timing, see Section 3.2.4, "SCSI Interface Timing" in Chapter 3. Figure 2.2 SYM53C140 Signal Grouping A_SSEL+ B_SSEL+ A_SSELB_SSELA_SBSY+ B_SBSY+ A_SBSYB_SBSYA_SRST+ B_SRST+ A_SRSTB_SRSTA_SREQ+ B_SREQ+ A_SREQB_SREQA_SACK+ B_SACK+ A_SACKB_SACKA_SMSG+ B_SMSG+ A_SMSGB_SMSGA_SCD+ B_SCD+ A_SCDB_SCDA_SIO+ B_SIO+ SYM53C140 A_SIOB_SIOA_SATN+ B_SATN+ A_SATNB_SATNA_SDP[1:0]+ B_SDP[1:0]+ A_SDP[1:0]B_SDP[1:0]A_SD[15:0]+ B_SD[15:0]+ A_SD[15:0]B_SD[15:0]A_DIFFSENS A_HVD_MODE RESET/ WS_ENABLE XFER_ACTIVE CLOCK B_DIFFSENS B_HVD_MODE A-Side LVD, HVD, or SE SCSI Interface B-Side LVD, HVD, or SE SCSI Interface Control Signals BSY_LED 2.1.7.1 Data and Parity (SD and SDP) The signals named A_SD[15:0] and A_SDP[1:0] are the data and parity signals from the A Side, and B_SD[15:0] and B_SDP[1:0] are the data and parity signals from the B Side of the SYM53C140. These signals are sent and received from the SYM53C140 via SCSI compatible drivers and receiver logic designed into the SYM53C140 interfaces. This logic provides the necessary drive, sense thresholds, and input hysteresis to function correctly in a SCSI bus environment. 2-6 Functional Descriptions The SYM53C140 receives data and parity signals and passes them from the source bus to the load bus and provides any necessary edge shifting to guarantee the skew budget for the load bus. Either side of the SYM53C140 may be the source bus or the load bus. The side that is asserting, deasserting or releasing the SCSI signals is the source side. The following steps describe the SYM53C140 data processing: 1. Asserted data is accepted from the receiver logic as soon as it is received. Once the clock signal has been received, data is gated from the receiver latch. 2. The path is next tested to be sure the data was not driven by the SYM53C140. This is because valid data needs to be generated by another node on the source bus to be passed through the SYM53C140 to the load bus. 3. The data is then leading edge filtered. The assertion edge is held for a specified time to prevent any signal bounce. The duration is controlled by the input signal. 4. The next stage uses a latch to sample the signal. This provides a stable data window for the load bus. 5. The final step develops pull-up and pull-down controls for the SCSI I/O logic, including 3-state controls for the pull-up. 6. A parallel function ensures that bus (transmission line) recovery occurs for a specified time after the last signal deassertion on each signal line. 2.1.7.2 SCSI Bus Activity LED (BSY_LED) Internal logic is used to detect SCSI bus activity and generate a signal that will produce an active HIGH output. This output can be used to drive a LED to indicate SCSI activity. The internal circuitry is a digital one shot that is an active HIGH with a minimum pulse width of 16 ms. The BSY_LED output current is 8 mA. This output may have an LED attached to it with the other lead of the LED grounded through a suitable resistor. 2.1.7.3 Busy Control (SBSY) A_SBSY and B_SBSY signals are propagated from the source bus to the load bus. These signals go through the following process: Interface Signal Descriptions 2-7 1. The bus is tested to be sure the data lines were not driven by the SYM53C140. This is because valid data needs to be generated by another node on the source bus to be passed through the SYM53C140 to the load bus. 2. The data is then leading edge filtered. The assertion edge is held for a specified time to prevent any signal bounce. The duration is controlled by the input signal. 3. The next stage has two modes. One mode simply passes data through. The other mode behaves like a large filter. The mode is selected by the current state in the SYM53C140 State Machine that tracks SCSI phases. The large filter mode is used when the Busy (SBSY) and Select (SSEL) sources switch from side to side. This output is then fed to the output driver which is a pull-down open collector only. 4. A parallel function ensures that bus (transmission line) recovery is available for a specified time after the last signal deassertion on each signal line. 2.1.7.4 Request and Acknowledge Control (SREQ and SACK) A_SREQ, A_SACK, B_SREQ, and B_SACK are clock and control signals. Their signal paths contain controls to guarantee minimum pulse widths, filter edges, and does some retiming when used as data transfer clocks. SREQ and SACK have paths from the A Side to the B Side and from the B Side to the A Side. The received signal goes through the following processing steps before being sent to the opposite bus: 1. The asserted input signal is sensed and forwarded to the next stage if the direction control permits it. The direction controls are developed from state machines that are driven by the sequence of bus control signals. 2. The signal must then pass the test of not being generated by the SYM53C140. 3. In the A Side to B Side direction, the next stage is a leading edge filter. This ensures that the output will not switch during the specified hold time after the leading edge. The duration of the input signal determines the duration of the output after the hold time. In the B Side to A Side direction, the circuit guarantees a minimum pulse width. 2-8 Functional Descriptions 4. The next stage passes the signal if it is not a data clock. If SREQ or SACK is a data clock, it delays the leading edge to improve data output setup times. The duration is again controlled by the input signal. 5. The following stage is a trailing edge signal filter. When the signal deasserts, the filter will not permit any signal bounce. The output signal deasserts at the first deasserted edge of the input signal. 6. The last stage develops pull-up and pull-down signals with drive and 3-state control. 7. A parallel function ensures that bus (transmission line) recovery occurs for a specified time after the last signal deassertion on each signal line. 2.1.7.5 Reset Control (SRST) A_SRST and B_SRST are also passed from the source to the load bus. This output has pull-down control for an open collector driver. These reset signals are processed using the following steps: 1. The input signal is blocked if it is already being driven by the SYM53C140. 2. The next stage is a leading edge filter. This ensures that the output will not switch during a specified time after the leading edge. The duration of the input signal then determines the duration of the output. 3. A parallel function ensures that bus (transmission line) recovery occurs for a specified time after the last signal deassertion on each signal line. 2.1.7.6 Control/Data, Input/Output, Message, and Attention Controls (SCD, SIO, SMSG, and SATN) A_SCD, A_SIO, A_SMSG, A_SATN, B_SCD, B_SIO, B_SMSG and B_SATN are control signals that have the following processing steps: 1. The input signal is blocked if it is being driven by the SYM53C140. 2. The next stage is a leading edge filter. This ensures the output will not switch for a specified time after the leading edge. The duration of the input signal determines the duration of the output. Interface Signal Descriptions 2-9 3. The final stage develops pull-up and pull-down controls for the SCSI I/O logic, including 3-state controls for the pull-up. 4. A parallel function ensures that bus (transmission line) recovery is for a specified time after the last signal deassertion on each signal line. 2.1.7.7 Select Control (SSEL) A_SSEL and B_SSEL are control signals used during bus arbitration and selection. Whichever side asserts, SSEL propagates it to the other side. If both signals are asserted at the same time, the A Side receives SSEL and sends it to the B Side. This output has pull-down control for an open collector driver. The signal goes through the following processing steps: 1. The input signal is blocked if it is being driven by the SYM53C140. 2. The next stage is a leading edge filter. This ensures that the output will not switch for a specified time after the leading edge. The duration of the input signal then determines the duration of the output. 3. A parallel function ensures that bus (transmission line) recovery occurs for a specified time after the last signal deassertion on each signal line. 2.1.7.8 Differential Direction Controls A_SD[15:0], A_SDP[1:0], A_SBSY, A_SSEL, A_SCD, A_SIO, A_SMSG, A_SREQ, A_SACK, A_SATN, A_SRST, B_SD[15:0], B_SDP[1:0], B_SBSY, B_SSEL, B_SCD, B_SIO, B_SMSG, B_SREQ, B_SACK, B_SATN, and B_SRST are all multimode signals. The mode is controlled by the HVD_MODE input pins and the voltage is sensed at the DIFFSENS inputs. When High-Voltage Differential signaling is selected and the DIFFSENS line sees the proper voltage input, all the minus signal leads become single-ended inputs/outputs to HVD drivers/receivers. All plus signals 2-10 Functional Descriptions become the HVD driver/receiver direction control signals. The A and B Sides are independently controlled. Table 2.2 Signal Level LOW = 0 HIGH = 1 Direction Control Signal Polarities State Deasserted Asserted Effect Input signals into the SYM53C140 Drive the SYM53C140 signals onto the bus When the single-ended mode is selected by the lack of HVD_MODE and the correct DIFFSENS voltage, the plus signal leads are internally tied to ground and the minus SCSI signals become the single-ended input/outputs. When the Low-Voltage Differential mode is selected by the lack of HVD_MODE and the correct DIFFSENS voltage, the plus and minus signal leads are differential signal pairs. 2.1.7.9 Clock (CLOCK) This is the 40 MHz oscillator input to the SYM53C140. It is the clock source for the protocol control state machines and timing generation logic. This clock is not used in any bus signal transfer paths. 2.1.7.10 A and B High-Voltage Differential Mode (A_HVD_MODE and B_HVD_MODE) These inputs inform the SYM53C140 that external drivers and receivers are used in this particular application. The effect of this control is to disable the LVD and single-ended modes of operation from the corresponding port. Table 2.3 Signal Level LOW = 0 HIGH = 1 HVD_MODE Control Signal Polarity State Deasserted Asserted Effect SYM53C140 drivers function in single-ended or LVD mode. High-Voltage Differential Signals and Controls are enabled from the port. Interface Signal Descriptions 2-11 2.1.7.11 Chip Reset (RESET/) This general purpose chip reset is intended to force all of the internal elements of the SYM53C140 into a known state. It will bring the State Machine to an idle state and force all controls to a passive state. The minimum RESET/ input asserted pulse width is 100 ns. The SYM53C140 also contains an internal Power On Reset (POR) function that is ORed with the chip reset pin. This eliminates the need for an external chip reset. Table 2.4 RESET/ Control Signal Polarity Effect Reset is forced to all internal SYM53C140 elements. Signal Level State LOW = 0 HIGH = 1 Asserted Deasserted SYM53C140 is not in a forced reset state. 2.1.7.12 A and B Differential Sense (A_DIFFSENS and B_DIFFSENS) These control pins are used to determine the mode of SCSI bus signaling that will be expected. Table 2.5 Voltage -0.35 to +0.5 +0.7 to +1.9 +2.4 to +5.5 Mode Sense Control Voltage Levels Mode SE LVD HVD For example, if a differential source is plugged into the B Side that has been configured to run in the differential mode and if a single-ended source is detected, then the B Side is disabled and no B Side signals will be driven. This is a protection mechanism for single-ended interfaces that are connected to differential drivers. 2.1.7.13 Warm Swap Enable (WS_ENABLE) This input is used to remove the chip from an active bus without disturbing the current SCSI transaction (for Warm Swap). When asserted 2-12 Functional Descriptions LOW, the chip will wait until the next SCSI Bus Free state, then reset internally. Once reset, all SCSI activity will be ignored until the WS_ENABLE pin is deasserted HIGH and both SCSI busses enter the Bus Free state. As an indication that the chip is idle, or ready to be warm swapped, the XFER_ACTIVE signal will deassert LOW. An LED or some other indicator could be connected to the XFER_ACTIVE signal. Table 2.6 Signal Level HIGH = 1 LOW = 0 WS_ENABLE Signal Polarity State Asserted Deasserted Effect The SYM53C140 performs normal transfers through the device The SYM53C140 discontinues transfers through the device (off-line) upon detection of a SCSI Bus Fee state 2.1.7.14 Transfer Active (XFER_ACTIVE) This output is an indication that the chip has finished its internal testing, the SCSI bus has entered a Bus Free state, and SCSI traffic can now pass from one bus to the other. The signal is asserted HIGH when the chip is active. Table 2.7 Signal Level HIGH = 1 LOW = 0 XFER_ACTIVE Signal Polarity State Asserted Deasserted Effect Indicates normal operation, transfers through the SYM53C140 are enabled The SYM53C140 has detected a Bus Free state do to WS_ENABLE being low disabling transfers through the device 2.1.8 SCSI Termination The terminator networks provide the biasing needed to pull signals to an inactive voltage level, and to match the impedance seen at the end of the cable with the characteristic impedance of the cable. Terminators must be installed at the extreme ends of each SCSI segment, and only at the ends. No SCSI segment should ever have more or less than two terminators installed and active. SCSI host adapters should provide a Interface Signal Descriptions 2-13 means of accommodating terminators. The terminators should be socketed, so they may be removed if not needed. Or, there should be a means of disabling them with software. Multi-mode terminators are required because they provide both LVD and single-ended termination, depending on what mode of operation is detected by the DIFFSENS pins. HVD requires a different termination configuration. The use of active termination is highly recommended. Figure 2.3 SCSI Termination UCC5630 SD0+ SD0SD1+ SD1SD2+ SD2SD3+ SD3SD4+ SD4LINE9+ 32 LINE9- 31 LINE8+ 30 LINE8- 29 LINE7+ 25 LINE7- 24 LINE6+ 23 LINE6- 22 SE 33 LVD 34 HVD 35 SDP0+ SDP0SD7+ SD7SD6+ SD6SD5+ SD5To LED Drivers 4 5 6 7 LINE1+ LINE1LINE2+ LINE2- 11 LINE3+ 12 LINE313 LINE4+ 14 LINE415 LINE5+ 16 LINE5- DIFFSENS 20 22K 17 DISCNCT DIFF B 21 0.1 F DIFFSENS connects to the SCSI bus DIFFSENS line to detect what type of devices (single-ended, LVD, or high-voltage differential) are connected to the SCSI bus. DISCNCT shuts down the terminator when it is not at the end of the bus. The disconnect pin low enables the terminator. *Use additional UCC5630 terminators to terminate the SCSI control signals and wide SCSI data byte as needed. 2-14 Functional Descriptions Chapter 3 Specifications 3.1 Signal Descriptions The SYM53C140 is packaged in a 160-pin Plastic Quad Flat Pack (PQFP) shown in Figure 3.1. The SYM53C140 signal grouping is shown in Figure 3.2 and Tables 3.1 through 3.4 list the signal descriptions grouped by function: * * * * SCSI A Side Interface Pins (Table 3.1) SCSI B Side Interface Pins (Table 3.2) Chip Interface Control Pins (Table 3.3) Power and Ground Pins (Table 3.4) Symbios SYM53C140 Ultra2 SCSI Bus Expander 3-1 The decoupling capacitor arrangement shown below is recommended to maximize the benefits of the internal split ground system. Capacitor values should be between 0.01 Fand 0.1 F . Figure 3.1 SYM53C140 160-pin PQFP Pin Diagram VSSSCSI B_DIFFSENS VDDIO B_HVD_MODE NC NC NC NC NC NC WS_ENABLE XFER_ACTIVE BSY_LED CLOCK RESET/ A_HVD_MODE VSSIO A_DIFFSENS ASD12- ASD12+ ASD13- ASD13+ ASD14- ASD14+ VSSSCSI ASD15- ASD15+ VDDSCSI ASDP1- ASDP1+ ASD0- ASD0+ VSSSCSI ASD1- ASD1+ ASD2- ASD2+ ASD3- ASD3+ VDDSCSI BSD11+ BSD11- BSD10+ BSD10- BSD9+ BSD9- VSSSCSI BSD8+ BSD8- VDDSCSI BSIO+ BSIO- BSREQ+ BSREQ- VSSSCSI BSCD+ BSCD- BSSEL+ BSSEL- BSMSG+ BSMSG- VSSSCSI VSSCORE BSRST+ BSRST- VDDCORE VDDSCSI BSACK+ BSACK- BSBSY+ BSBSY- VSSSCSI BSATN+ BSATN- BSDP0+ BSDP0- VDDSCSI RBIAS BSD7+ BSD7- 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Top View 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 VSSSCSI ASD4- ASD4+ ASD5- ASD5+ ASDD6- ASD6+ VDDSCSI ASD7- ASD7+ VSSSCSI ASDP0- ASDP0+ ASATN- ASATN+ ASBSY- ASBSY+ VSSCORE VSSSCSI ASACK- ASACK+ VDDSCSI VDDCORE ASRST- ASRST+ VSSSCSI ASMSG- ASMSG+ ASSEL- ASSEL+ ASCD- ASCD+ VSSSCSI ASREQ- ASREQ+ ASIO- ASIO+ ASD8- ASD8+ VDDSCSI 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 98.SYM53C140 1. NC pins are not connected. 3-2 VSSSCSI BSD6+ BSD6- BSD5+ BSD5- BSD4+ BSD4- VSSSCSI BSD3+ BSD3- VDDSCSI BSD2+ BSD2- BSD1+ BSD1- VSSSCSI BSD0+ BSD0- BSDP1+ BSDP1- BSD15+ BSD15- VSSSCSI BSD14+ BSD14- VDDSCSI BSD13+ BSD13- BSD12+ BSD12- VSSSCSI VSSSCSI ASD11+ ASD11- VDDSCSI ASD10+ ASD10- ASD9+ ASD9- VSSSCSI Specifications Figure 3.2 SYM53C140 Functional Signal Grouping A_SSEL+ B_SSEL+ A_SSELB_SSELA_SBSY+ B_SBSY+ A_SBSYB_SBSYA_SRST+ B_SRST+ A_SRSTB_SRSTA_SREQ+ B_SREQ+ A_SREQB_SREQA_SACK+ B_SACK+ A_SACKB_SACKA_SMSG+ B_SMSG+ A_SMSGB_SMSGA_SCD+ B_SCD+ A_SCDB_SCDA_SIO+ B_SIO+ SYM53C140 A_SIOB_SIOA_SATN+ B_SATN+ A_SATNB_SATNA_SDP[1:0]+ B_SDP[1:0]+ A_SDP[1:0]B_SDP[1:-0]A_SD[15:0]+ B_SD[15:0]+ A_SD[15:0]B_SD[15:0]A_DIFFSENS A_HVD_MODE RESET/ WS_ENABLE XFER_ACTIVE CLOCK B_DIFFSENS B_HVD_MODE A-Side LVD, HVD, or SE SCSI Interface B-Side LVD, HVD, or SE SCSI Interface Control Signals BSY_LED Signal Descriptions 3-3 Table 3.1 SCSI A A_SSEL+,A_SBSY+,A_SRST+,A_SREQ+,A_SACK+,A_SMSG+,A_SCD+,A_SIO+,A_SATN+,- SCSI A Side Interface Pins Pin 91, 92 104, 105 96, 97 86, 87 100, 101 93, 94 89, 90 84, 85 106, 107 108, 109, 131, 132 73, 74, 76-79, 82, 83, 111, 112, 114-119, 122-127, 129, 130, 134, 135, 137-142 143 145 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Description A Side SCSI bus Select control signal. A Side SCSI bus Busy control signal. A Side SCSI bus Reset control signal. A Side SCSI bus Request control signal. A Side SCSI bus Acknowledge control signal. A Side SCSI bus Message control signal. A Side SCSI bus Control and Data control signal. A Side SCSI bus Input and Output control signal. A Side SCSI bus Attention control signal. A Side SCSI bus Data Parity signal. A Side SCSI bus Data signals. A_SDP[1:0]+,A_SD[15:0]+,- A_DIFFSENS A_HVD_MODE I I A Side SCSI bus Differential Sense signal. A Side SCSI bus HVD Mode control signal. 3-4 Specifications Table 3.2 SCSI B B_SSEL+,B_SBSY+,B_SRST+,B_SREQ+,B_SACK+,B_SMSG+,B_SCD+,B_SIO+,B_SATN+,- SCSI B Side Interface Pins Pin 18, 19 30, 31 24, 25 13, 14 28, 29 20, 21 16, 17 11, 12 33, 34 59, 60, 35, 36 1-6, 8, 9, 39, 40, 42-47, 49, 50, 52-55, 57, 58, 61, 62, 64, 65, 67-70, 159 157 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Description B Side SCSI bus Select control signal. B Side SCSI bus Busy control signal. B Side SCSI bus Reset control signal. B Side SCSI bus Request control signal. B Side SCSI bus Acknowledge control signal. B Side SCSI bus Message control signal. B Side SCSI bus Control and Data control signal. B Side SCSI bus Input and Output control signal. B Side SCSI bus Attention control signal. B Side SCSI bus Data Parity signal. B Side SCSI bus Data signals. B_SDP[1:0]+,B_SD[15:0]+,- B_DIFFSENS B_HVD_MODE I I B Side SCSI bus Differential Sense signal. B Side SCSI bus HVD Mode control signal. Table 3.3 Control RESET/ WS_ENABLE Chip Interface Control Pins Pin 146 150 149 147 148 Type I I/O I/O I O Description Master Reset for SYM53C140, active LOW. Enable/disable SCSI transfers through the SYM53C140. Transfers through the SYM53C140 are enabled/disabled. Oscillator input for SYM53C140 (40 MHz). SCSI activity LED output, 8 mA. XFER_ACTIVE CLOCK BSY_LED Signal Descriptions 3-5 Table 3.4 Power and Ground Pins Type I I Description Power supplies to the SCSI bus I/O pins. Ground for the SCSI bus I/O pins. Power and Ground Pin VDDSCSI VSSSCSI 10, 27, 37, 51, 66, 75, 81, 99, 113, 121, 133 7, 15, 22, 32, 41, 48, 56, 63, 71, 72, 80, 88, 95, 102, 110, 120, 128, 136, 160 26, 98 23, 103 158 144 38 151-156 VDDCORE VSSCORE VDDIO VSSIO RBIAS NC I I I I I N/A Power supplies to the CORE logic. Ground for the CORE logic. Power supplies to the I/O logic. Ground for the I/O logic. Receiver bias control, R = 9.76 K 1%. No Connections. Note: * All VDD pins must be supplied 3.3 V. The SYM53C140 output signals drive 3.3 V. * If the power supplies to the VDDIO and VDDCORE pins in a chip testing environment are separated, either power up the pins simultaneously or power up VDDCORE before VDDIO. The VDDIO pin must always power down before the VDDCORE pin. 3-6 Specifications 3.2 Electrical Characteristics This section specifies the DC and AC electrical characteristics of the SYM53C140. These electrical characteristics are in the following four categories: * * * * DC Characteristics TolerANT Technology Electrical Characteristics AC Characteristics SCSI Interface Timing 3.2.1 DC Characteristics Table 3.5 Absolute Maximum Stress Ratings1 Test Unit Conditions C V V mA V - - - - MIL-STD 883C, Method 3015.7 Symbol Parameter TSTG VDD VIN ILP2 ESD Storage temperature Supply voltage Input Voltage Latch-up current Electrostatic discharge Min -55 -0.5 Max 150 4.5 VSS - 0.3 VDD + 0.3 150 - - 2K 1. Stresses beyond those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the Operating Conditions section of the manual is not implied. 2. -2 V < VPIN < 8 V. Electrical Characteristics 3-7 Table 3.6 Operating Conditions1 Min Max Unit V mA mA mA C C/ W Test Conditions - - RBIAS = 9.76 K 1% VDD = 3.3 V - - - Symbol Parameter VDD IDD Supply voltage Supply current (dynamic SE) Supply current (dynamic LVD) Supply current (static) TA JA Operating free air Thermal resistance (junction to ambient air) 3.13 3.47 - - - 0 - 130 600 1 70 35 1. Conditions that exceed the operating limits may cause the device to function incorrectly. Table 3.7 LVD Driver SCSI Signals -- B_SD[15:0], B_SDP[1:0], B_SCD, B_SIO, B_SMSG, B_SREQ, B_SACK, B_SBSY, B_SATN, B_SSEL, B_SRST1 Parameter Source (+) current Sink (-) current Source (+) current Sink (-) current 3-state leakage Min 7 -7 -3.5 3.5 -20 Max 12 -12 -6 6 20 Units mA mA mA mA A Test Conditions Asserted state Asserted state Negated state Negated state - Symbol IO+ IOIO+ IOIOZ 1. VCM = 0.7 - 1.8 V, RL = 0 - 110 , Rbias = 9.76 K. Figure 3.3 LVD Driver RL IO+ 2 + VCM + - IO- - RL 2 3-8 Specifications Table 3.8 LVD Receiver SCSI Signals -- B_SD[15:0], B_SDP[1:0] , B_SCD, B_SIO, B_SMSG, B_SREQ, B_SACK, B_SBSY, B_SATN, B_SSEL, B_SRST1 Min Max Units Test Conditions 60 - - -60 mV mV - - Symbol Parameter VI VI LVD receiver voltage asserting LVD receiver voltage negating 1. VCM = 0.7 - 1.8 V Figure 3.4 LVD Receiver + VI + VCM - 2 - + + VI 2 - - Table 3.9 DIFFSENS SCSI Signal Test Conditions - - - - Symbol Parameter VIH VS VIL IOZ High-voltage differential sense voltage LVD sense voltage Single-ended sense voltage 3-state leakage Min 2.4 0.7 VSS -0.3 -10 Max VDD + 0.3 1.9 0.5 10 Unit V V V A Table 3.10 Input Capacitance Test Unit Conditions pF pF - - Symbol CI CIO Parameter Input capacitance of input pads Input capacitance of I/O pads Min - - Max 7 10 Electrical Characteristics 3-9 Table 3.11 Bidirectional SCSI Signals -- A_SD[15:0]/, A_SDP[1:0]/, A_SREQ/, A_SACK/, B_SD[15:0], B_SDP[1:0], B_SREQ, B_SACK Test Conditions - - IOH = 7.0 mA 48 mA - Symbol VIH VIL VOH1 VOL IOZ Parameter Input high voltage Input low voltage Output high voltage Output low voltage 3-state leakage Min 1.9 VSS 2.0 VSS -10 Max VDD 1.0 VDD 0.5 10 Unit V V V V A 1. TolerANT active negation enabled. Table 3.12 Bidirectional SCSI Signals -- A_SCD/, A_SIO/, A_SMSG/, A_SBSY/, A_SATN/, A_SSEL/, A_SRST/, B_SCD, B_SIO, B_SMSG, B_SBSY, B_SATN, B_SSEL, B_SRST Parameter Input high voltage Input low voltage Output low voltage 3-state leakage Min 1.9 VSS VSS -10 Max VDD 1.0 0.5 10 Unit V V V A Test Conditions - - 48 mA - Symbol VIH VIL VOL IOZ Table 3.13 Symbol VIH VIL IOZ Input Control Signals -- CLOCK, RESET/, WS_ENABLE Min 2.0 VSS -10 Max VDD 0.8 10 Unit V V A Test Conditions - - - Parameter Input high voltage Input low voltage 3-state leakage 3-10 Specifications Figure 3.5 External Reset Circuit 3.3 V 3.3 V Input 0.1 F Reset Pin 146 Table 3.14 Symbol VOH VOL IOZ Output Control Signals -- BSY_LED, XFER_ACTIVE Parameter Output high voltage Output low voltage 3-state leakage Min 2.4 VSS -10 Max VDD 0.4 10 Unit V V A Test Conditions 8 mA 8 mA - 3.2.2 TolerANT Technology Electrical Characteristics Table 3.15 Symbol VOH2 VOL VIH VIL VIK VTH VTL VTH-VTL IOH2 TolerANT Technology Electrical Characteristics1 Parameter Output high voltage Output low voltage Input high voltage Input low voltage Input clamp voltage Threshold, HIGH to LOW Threshold, LOW to HIGH Hysteresis Output high current Min 2.0 VSS 2.0 VSS - 0.3 -0.66 1.0 1.4 300 2.5 Max VDD + 0.3 0.5 VDD + 0.3 0.8 -0.77 1.2 1.6 500 24 Units V V V V V V V mV mA Test Conditions IOH = 7 mA IOL = 48 mA - Referenced to VSS VDD = 4.75; II = -20 mA - - - VOH = 2.5 V (Sheet 1 of 2) Electrical Characteristics 3-11 Table 3.15 Symbol IOL IOSH2 TolerANT Technology Electrical Characteristics1 (Cont.) Parameter Output low current Short-circuit output high current Short-circuit output low current Input high leakage Min 100 - Max 200 625 Units mA mA Test Conditions VOL = 0.5 V Output driving low, pin shorted to VDD supply3 Output driving high, pin shorted to VSS supply -0.5 - 95 mA ILH - 20 A ILL Input low leakage - -20 A RI CP tR2 tF dVH/dt dVL/dt ESD Input resistance Capacitance per pin Rise time, 10% to 90% Fall time, 90% to 10% Slew rate, LOW to HIGH Slew rate, HIGH to LOW Electrostatic discharge Latch-up Filter delay Ultra filter delay Ultra2 filter delay Extended filter delay 20 - 4.0 4.0 0.15 0.15 2 100 20 10 5 40 - 15 18.5 18.5 0.50 0.50 - - 30 15 8 60 M pF ns ns V/ns V/ns KV mA ns ns ns ns (Sheet 2 of 2) 1. 2. 3. 4. These values are guaranteed by periodic characterization; they are not 100% tested on every device. Active negation outputs only: Data, Parity, SREQ/, SACK/. (Minus Pins) SCSI mode only. Single pin only; irreversible damage may occur if sustained for one second. SCSI RESET pin has 10 k pull-up resistor. 3-12 Specifications Figure 3.6 Rise and Fall Time Test Conditions 47 20 pF + - 2.5 V Figure 3.7 SCSI Input Filtering t1 REQ/ or ACK/ Input VTH Note: t1 is the input filtering period. Figure 3.8 Hysteresis of SCSI Receivers 1.1 1.3 Received Logic Level 1 0 1.5 1.7 Input Voltage (Volts) Electrical Characteristics 3-13 Figure 3.9 +40 Input Current as a Function of Input Voltage Input Current (milliamperes) +20 14.4 V 8.2 V 0 -0.7 V -20 OUTPUT ACTIVE HI-Z -40 -4 0 4 8 12 16 Input Voltage (Volts) Figure 3.10 Output Current as a Function of Output Voltage 0 Output Source Current (milliamperes) 0 1 2 3 Output Voltage (Volts) 4 5 Output Sink Current (milliamperes) 100 80 -200 60 -400 40 -600 20 -800 0 0 1 2 3 4 Output Voltage (Volts) 5 3-14 Specifications 3.2.3 AC Characteristics The AC characteristics described in this section apply over the entire range of operating conditions (refer to DC Characteristics in this chapter). Chip timing is based on simulation at worst case voltage, temperature, and processing. The SYM53C140 requires a 40 MHz clock input. Table 3.16 Symbol t1 t2 t3 t4 Clock Timing Parameter Clock period Clock low time Clock high time Clock rise time Min 24.75 10 10 1 Max 25.25 15 15 - Units ns ns ns V/ns Figure 3.11 Clock Timing t1 t3 Clock t4 t2 3.2.4 SCSI Interface Timing Table 3.17 Symbol t1 t2 t3 t4 Input Timing Parameter Input data setup Input data hold Input REQ/ACK assertion pulse width Input REQ/ACK deassertion pulse width Min 1 4.75 11 11 Max - - - - Units ns ns ns ns Electrical Characteristics 3-15 Table 3.18 Output Timing Min min [t1 + 17ns, t4+5] max [24, (t2 - 20), t3] Max - - max [30 ns, t3 +5] 50 ns if REQ/ACK is clock for input data, 30 ns if not [t3 +35] Units ns ns ns ns Symbol Parameter t5 t6 t7 t8 Output data setup Output data hold Output REQ/ACK pulse width max [20 ns, t3 -5] REQ/ACK transport delay 25 ns if REQ/ACK is clock for input data, 10 ns if not 6 t9 Data transport delay ns Figure 3.12 Input/Output Timing Input Timing REQ or ACK t1 Data Valid Data t8 Output Timing REQ or ACK t9 Data t5 Valid Data t6 t7 t2 t3 t4 3-16 Specifications 3.3 Mechanical Drawings LSI Logic component dimensions conform to a current revision of the JEDEC Publication 95 standard package outline, using ANSI 14.5Y "Dimensioning and Tolerancing" interpretations. As JEDEC drawings are balloted and updated, changes may have occurred. To ensure the use of a current drawing, the JEDEC drawing revision level should be verified. Visit www.eia.org/jedec for review of Publication 95 drawings and revision levels. For printed circuit board land patterns that will accept LSI Logic components, it is recommended that customers refer to the IPC standards (Institute for Interconnecting and Packaging Electronic Circuits). Specification number IPC-SM-782, "Surface Mount Design and Land Pattern Standard" is an established method of designing land patterns. Feature size and tolerances are industry standards based on IPC assumptions. Mechanical Drawings 3-17 3.3.1 SYM53C140 160-pin PQFP Mechanical Drawing The SYM53C140 is packaged in a 160-pin metric Plastic Quad Flat Pack (PQFP). Figure 3.13 SYM53C140 160 Pin PQFP (PF) Mechanical Drawing Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code PF. 3-18 Specifications Figure 3.13 SYM53C140 Pin 160 PQFP (PF) Mechanical Drawing (Cont.) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code PF. Mechanical Drawings 3-19 3-20 Specifications Appendix A Wiring Diagrams A.1 SYM53C140 Wiring Diagrams The following four pages of wiring diagrams are of a typical SYM53C140 in a evaluation test board application. Symbios SYM53C140 Ultra2 SCSI Bus Expander A-1 Figure A.1 SYM53C140 Wiring Diagram 1 of 4 A-2 SYM53C140 Wiring Diagrams Figure A.1 SYM53C140 Wiring Diagram 2 of 4 SYM53C140 Wiring Diagrams A-3 Figure A.1 SYM53C140 Wiring Diagram 3 of 4 A-4 SYM53C140 Wiring Diagrams Figure A.1 SYM53C140 Wiring Diagram 4 of 4 Connector Page SYM53C140 Wiring Diagrams Test circuit switch only. Test circuit switch only. A-5 A-6 Wiring Diagrams Appendix B Glossary ACK/ Acknowledge - Driven by an initiator, ACK/ indicates an acknowledgment or a SCSI data transfer. In the target mode, ACK/ is received as a response to the REQ/ Signal. American National Standards Institute. The process of selecting one respondent from a collection of several candidates that request service concurrently. A signal is asserted when it is in the state that is indicated by the name of the signal. Opposite of negated or deasserted. The act of driving a signal to the true state. Transmission in which each byte of the information is synchronized individually through the use of Request (REQ/) and Acknowledge (ACK/) signals. Attention - Driven by an initiator, indicates an attention condition. In the target role, ATN/ is received and is responded to by entering the Message Out Phase. A block is the basic 512 byte size of storage that the storage media is divided into. The Logical Block Address protocol uses sequential block addresses to access the media. Busy - Indicates that the SCSI Bus is being used. BSY/ can be driven by the initiator or the target device. A collection of unbroken signal lines that interconnect computer modules. The connections are made by taps on the lines. Bus expander technology permits the extension of a bus by providing some signal filtering and retiming to maintain signal skew budgets. ANSI Arbitration Asserted Assertion Asynchronous Transmission ATN/ Block BSY/ Bus Bus Expander Symbios SYM53C140 Ultra2 SCSI Bus Expander B-1 Cable Skew Delay C_D/ Cable skew delay is the minimum difference in propagation time allowed between any two SCSI bus signals measured between any two SCSI devices. Control/Data - Driven by a target. When asserted, indicates Control or Data Information is on the SCSI Bus. This signal is received by the initiator. The function that occurs when an initiator selects a target to start an operation, or a target reselects an initiator to continue an operation. The set of nine lines used to put the SCSI bus into its different phases. The combinations of asserted and negated control signals define the phases. A computer module that interprets signals between a host and a peripheral device. Often, the controller is a part of the peripheral device, such as circuitry on a disk drive. SCSI Data Bits - These eight Data Bits (DB[7:0]/), plus a Parity Bit (DBP/), form the SCSI Bus. DB7/ is the most significant bit and has the highest priority ID during the Arbitration Phase. Data parity is odd. Parity is always generated and optionally checked. Parity is not valid during arbitration. The act of driving a signal to the false state or allowing the cable terminators to bias the signal to the false state (by placing the driver in the high impedance condition). A signal is deasserted or negated when it is in the state opposite to that which is indicated by the name of the signal. Opposite of asserted. Connect Control Signals Controller DB[7:0]/ Deasserted Device A single unit on the SCSI bus, identifiable by a SCSI address. It can be a processor unit, a storage unit (such as a disk or tape controller or drive), an output unit (such as a controller or printer), or a communications unit. A signaling alternative that employs differential drivers and receivers to improve signal-to-noise ratios and increase maximum cable lengths. The function that occurs when a target releases control of the SCSI bus, allowing the bus to go to the Bus Free phase. When used in the context of electrical configuration, "driver" is the circuitry that creates a signal on a line. Differential Disconnect Driver B-2 Glossary External Configuration External Terminator Free Host All SCSI peripheral devices are external to the host enclosure. The terminator that exists on the last peripheral device that terminates the end of the external SCSI bus. In the context of Bus Free phase, "free" means that no SCSI device is actively using the SCSI bus and, therefore, the bus is available for use. A processor, usually consisting of the central processing unit and main memory. Typically, a host communicates with other devices, such as peripherals and other hosts. On the SCSI bus, a host has a SCSI address. Circuitry that translates between a processor's internal bus and a different bus, such as SCSI. On the SCSI bus, a host adapter usually acts as an initiator. A SCSI device that requests another SCSI device (a target) to perform an operation. Usually, a host acts as an initiator and a peripheral device acts as a target. All SCSI peripheral devices are internal to the host enclosure. The terminator that exists within the host that terminates the internal end of the SCSI bus. Input/Output - Driven by a target. I/O controls the direction of data transfer on the SCSI Bus. When active, this signal indicates input to the initiator. When inactive, this signal indicates output from the initiator. This signal is also used to distinguish between the Selection and Reselection Phases. An I/O cycle is an Input (I/O Read) operation or Output (I/O Write) operation that accesses the PC Card's I/O address space. The logical representation of a physical or virtual device, addressable through a target. A physical device can have more than one logical unit. A signal is at the low logic level when it is below approximately 0.5 volts. Host Adapter Initiator Internal Configuration Internal Terminator I/O/ I/O Cycle Logical Unit Low (logical level) B-3 LSB Abbreviation for Least Significant Bit or Least Significant Byte. That portion of a number, address or field that occurs right-most when its value is written as a single number in conventional hexadecimal or binary notation. The portion of the number having the least weight in a mathematical calculation using the value. Logical Unit Number. Used to identify a logical unit. A characteristic or feature that must be present in every implementation of the standard. MegaHertz - Measurement in millions of Hertz per second. Used as a measurement of data transfer rate. One millionth of a second. Abbreviation for Most Significant Bit or Most Significant Byte. That portion of a number, address or field that occurs left-most when its value is written as a single number in conventional hexadecimal or binary notation. The portion of the number having the most weight in a mathematical calculation using the value. Message - Driven active by a target during the Message Phase. This signal is received by the initiator. One billionth of a second. A signal is negated or deasserted when it is in the state opposite to that which is indicated by the name of the signal. Opposite of asserted. The act of driving a signal to the false state or allowing the cable terminators to bias the signal to the false state. A method of checking the accuracy of binary numbers. An extra bit, called a parity bit, is added to a number. If even parity is used, the sum of all 1s in the number and its corresponding parity is always even. If odd parity is used, the sum of the 1s and the parity bit is always odd. A device that can be attached to the SCSI bus. Typical peripheral devices are disk drives, tape drives, printers, CD ROMs, or communications units. One of the eight states to which the SCSI bus can be set. During each phase, different communication tasks can be performed. A connection into a bus. LUN Mandatory MHz microsecond (s) MSB MSG/ nanosecond (ns) Negated Negation Parity Peripheral device Phase Port B-4 Glossary Priority Protocol Receiver Reconnect Release REQ/ Reselect The ranking of the devices on the bus during arbitration. A convention for data transmission that encompasses timing control, formatting, and data representation. The circuitry that receives electrical signals on a line. The function that occurs when a target reselects an initiator to continue an operation after a disconnect. The act of allowing the cable terminators to bias the signal to the false state (by placing the driver in the high impedance condition). Request - Driven by a target, indicates a request for a SCSI data-transfer handshake. This signal is received by the initiator. A target can disconnect from an initiator in order to perform a timeconsuming function, such as a disk seek. After performing the operation, the target can "reselect" the initiator. Reset - Clears all internal registers when active. It does not assert the SCSI RST/ signal and therefore does not reset the SCSI bus. Reset - Indicates a SCSI Bus reset condition. The octal representation of the unique address ([7:0]) assigned to an SCSI device. This address is normally assigned and set in the SCSI device during system installation. The bit-significant representation of the SCSI address referring to one of the signal lines DB7/ through DB0/. RESET RST SCSI Address SCSI ID (Identification) or SCSI Device ID SCSI SCAM Small Computer System Interface. An acronym for SCSI Configured AutoMatically. SCAM is the new SCSI automatic ID assignment protocol. SCAM frees SCSI users from locating and setting SCSI ID switches and jumpers. SCAM is the key part of Plug and Play SCSI. Select - Used by an initiator to select a target, or by a target to reselect an initiator. An electrical signal configuration that uses a single line for each signal, referenced to a ground path common to the other signal lines. The advantage of a single-ended configuration is that it uses half the pins, chips, and board area that differential/low-voltage differential SEL/ Single-ended configuration B-5 configurations require. The main disadvantage of single-ended configurations is that they are vulnerable to common mode noise. Also, cable lengths are limited. Synchronous transmission Transmission in which the sending and receiving devices operate continuously at the same frequency and are held in a desired phase relationship by correction devices. For buses, synchronous transmission is a timing protocol that uses a master clock and has a clock period. A SCSI device that performs an operation requested by an initiator. The electrical connection at each end of the SCSI bus, composed of a set of resistors. Microsecond. One millionth of a second. Target Termination s B-6 Glossary Index Symbol s B-6 Numerics 160-pin Plastic Quad Flat Pack 1-5 3-state 2-7 leakage 3-10 A A_SACK 2-8, 3-4 A_SATN 2-9, 3-4 A_SBSY 2-7, 3-4 A_SCD 2-9, 3-4 A_SD[15:0] 2-6, 3-4 A_SDP[1:0] 2-6, 3-4 A_SIO 2-9, 3-4 A_SMSG 2-9, 3-4 A_SREQ 2-8, 3-4 A_SRST 2-9 A_SSEL 2-10 Absolute Maximum Stress Ratings 3-7 AC characteristics 3-15 ACK B-1 Acknowledge 2-3 (ACK) 2-8 Active negation 2-3 ANSI B-1 Applications 1-2 Arbitration B-1 Asserted B-1 Assertion B-1 Asynchronous transmission B-1 ATN B-1 Attention (SATN) 2-9 B B_SACK 2-8, 3-5 B_SATN 2-9 B_SBSY 2-7, 3-5 B_SCD 2-9, 3-5 B_SD[15:0] 2-6, 3-5 B_SDP[1:0] 2-6, 3-5 B_SIO 2-9, 3-5 B_SMSG 2-9, 3-5 B_SREQ 2-8 B_SRST 2-9 B_SSEL 2-10, 3-5 Backward compatibility 1-6 Balanced duty cycles 2-3 Bidirectional connections 2-2 SCSI Signals 3-10 Block B-1 BSY B-1 BSY_LED 2-7 Bus B-1 timing 2-4 Bus Expander B-1 Busy (BSY) 2-7 C C_D B-2 Cable Skew Delay B-2 Calibration 2-4 Chip Reset (RESET/) 2-12 Clock (CLOCK) 2-11 signal 2-7 Timing 3-15 Symbios SYM53C140 Ultra2 SCSI Bus Expander IX-1 Connect B-2 Control Signals B-2 Control/Data (SCD) 2-9 Controller B-2 D Data 2-3, 2-6 DB[7:0] B-2 DC Characteristics 3-7 Deasserted B-2 Delay settings 2-4 Device B-2 Differential transceivers 1-6 Differntial B-2 DIFFSENS 2-4, 2-5, 3-9 Receiver 2-5 Direction Control Signal Polarities 2-11 Disconnect B-2 Double clocking of data 2-3 Driver B-2 E Electrical Characteristics 3-7 Electrostatic discharge 3-7 Enable/disable SCSI transfers 3-5 ESD 3-7 External Configuration B-3 External Terminator B-3 F Filter edges 2-8 Free B-3 G Glitches 2-3 H High-Voltage Differential SCSI 1-6 Host B-3 Adapter B-3 HVD_MODE Control Signal Polarity 2-11 Hysteresis 2-6 I I/O B-3 Cycle B-3 Identification B-5 Initiator B-3 Input capacitance 3-9 I/O pads 3-9 input pads 3-9 Control Signals 3-10 high voltage 3-10 low voltage 3-10 Timing 3-15 Voltage 3-7 Input/Output (SIO) 2-9 Internal Configuration B-3 Internal Terminator B-3 L Latch-up current 3-7 Leading edge filter 2-7, 2-9 Load bus 2-7 Logical Unit B-3 Low (logical level) B-3 LSB B-4 LUN B-4 LVD DIFFSENS 2-5 Driver SCSI Signals 3-8 Receiver SCSI Signals 3-9 LVDlink 1-6 Benefits 1-6 technology 2-4 transceivers 1-6, 2-4 M Mandatory B-4 Master Reset 3-5 Message (SMSG) 2-9 MHz B-4 Microsecond B-4 Migration path 1-6 MSB B-4 IX-2 Index MSG B-4 N nanosecond B-4 Negated B-4 Negation B-4 O Operating Conditions 3-8 Operating free air 3-8 Output Control Signals 3-11 high voltage 3-10 low voltage 3-10 Timing 3-16 P Parallel function 2-8, 2-9 Parity 2-3, 2-6, B-4 Peripheral device B-4 Phase B-4 Plastic Quad Flat Pack (PQFP) 3-1 Port B-4 Power down 2-3 On Reset (POR) 2-12 up 2-3 PQFP 1-5 Precision Delay Control 2-1, 2-4 Priority B-5 Protocol B-5 Pull-down 2-7, 2-10 Pull-up 2-7, 2-10 Pulse width 2-8 R RC-type input filters 2-3 Receiver B-5 latch 2-7 Reconnect B-5 Recovery 2-9 Release B-5 Reliability issue 2-3 REQ B-5 Request 2-3 (REQ) 2-8 Reselect B-5 Reserved B-5 RESET B-5 Reset (RST) 2-9 RESET/ 2-12, 3-5 Control Signal Polarity 2-12 Retiming 2-8 Logic 2-1, 2-4 RST B-5 S SACK 2-8, 2-9 SCAM B-5 SCSI B-5 Address B-5 bus protocol 2-4 Device ID B-5 I/O logic 2-10 ID B-5 Interface Timing 3-15 Parallel Interconnect 2 1-5 phases 2-4 Signal Description 3-4 TolerANT technology 2-3 SCSI bus free state 2-13 SEL B-5 Select (SSEL) 2-10 Server Clustering 1-2 Signal Descriptions 3-1 groupings 2-6, 3-1 skew 2-2 Single-ended configuration B-5 Source bus 2-2, 2-7 SREQ 2-8, 2-9 SSEL 2-10 State Machine 2-8 Control 2-1, 2-4 Storage temperature 3-7 Supply voltage 3-7 Index IX-3 SYM53C140 SCSI Bus Expander 1-1 Synchronous transmission B-6 T Target B-6 Temperature 2-4 Termination B-6 Thermal resistance 3-8 TolerANT Drivers and Receivers 2-3 receiver technology 2-3 SCSI 2-3 Technology 2-3 Benefits 2-3 V VDD_CORE 3-6 VDD_SCSI 3-6 Voltage 2-4 VSS_CORE 3-6 VSS_SCSI 3-6 W Warm Start Enable 2-12 Wide Ultra2 SCSI 2-2 WS_ENABLE 2-12, 3-5 Signal Polarity 2-13 X XFER_ACTIVE 2-13, 3-5 Signal Polarity 2-13 IX-4 Index Customer Feedback We would appreciate your feedback on this document. Please copy the following page, add your comments, and fax it to us at the number shown. If appropriate, please also fax copies of any marked-up pages from this document. Important: Please include your name, phone number, fax number, and company address so that we may contact you directly for clarification or additional information. Thank you for your help in improving the quality of our documents. Reader's Comments Fax your comments to: LSI Logic Corporation Technical Publications M/S E-198 Fax: 408.433.4333 Please tell us how you rate this document: Symbios SYM53C140 Ultra2 SCSI Bus Expander. Place a check mark in the appropriate blank for each category. Excellent Good Average Completeness of information Clarity of information Ease of finding information Technical content Usefulness of examples and illustrations Overall manual ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ Fair ____ ____ ____ ____ ____ ____ Poor ____ ____ ____ ____ ____ ____ What could we do to improve this document? If you found errors in this document, please specify the error and page number. If appropriate, please fax a marked-up copy of the page(s). Please complete the information below so that we may contact you directly for clarification or additional information. Name Telephone Title Department Company Name Street City, State, Zip Date Fax Mail Stop Customer Feedback U.S. Distributors by State A. E. W. E. Avnet Electronics Wyle Electronics Alabama Huntsville A. E. Tel: 205.837.8700 W. E. Tel: 800.964.9953 Alaska A. E. Tel: 800.332.8638 Illinois North/South A. E. Tel: 847.797.7300 Tel: 314.291.5350 Chicago W. E. Tel: 800.853.9953 Indiana Indianapolis A. E. Tel: 317.575.3500 W. E. Tel: 888.358.9953 Iowa Cedar Rapids A. E. Tel: 319.393.0033 Kansas Kansas City A. E. Tel: 913.663.7900 Kentucky Central/Northern/ Western A. E. Tel: 800.984.9503 Tel: 800.767.0329 Tel: 800.829.0146 Louisiana North/South A. E. Tel: 800.231.0253 Tel: 800.231.5575 Maine A. E. Tel: 800.272.9255 New Jersey North/South A. E. Tel: 201.515.1641 Tel: 609.222.6400 Oradell W. E. Tel: 201.261.3200 Pine Brook W. E. Tel: 800.862.9953 New Mexico Albuquerque A. E. Tel: 505.293.5119 New York Long Island A. E. Tel: 516.434.7400 W. E. Tel: 800.861.9953 Rochester A. E. Tel: 716.475.9130 W. E. Tel: 800.319.9953 Syracuse A. E. Tel: 315.453.4000 North Carolina Raleigh A. E. Tel: 919.872.0712 W. E. Tel: 800.560.9953 North Dakota A. E. Tel: 800.829.0116 Ohio Cleveland A. E. Tel: 216.498.1100 W. E. Tel: 800.763.9953 Dayton A. E. Tel: 614.888.3313 W. E. Tel: 800.763.9953 Oklahoma Tulsa A. E. Tel: 918.459.6000 Oregon Portland A. E. Tel: 503.526.6200 W. E. Tel: 800.879.9953 Pennsylvania Pittsburgh A. E. Tel: 412.281.4150 Philadelphia A. E. Tel: 800.526.4812 W. E. Tel: 800.871.9953 Rhode Island A. E. 800.272.9255 South Carolina A. E. Tel: 919.872.0712 South Dakota A. E. Tel: 800.829.0116 Tennessee East/West A. E. Tel: 800.241.8182 Tel: 800.633.2918 Arizona Phoenix A. E. Tel: 602.736.7000 W. E. Tel: 800.528.4040 Tucson A. E. Tel: 520.742.0515 California Irvine A. E. Tel: 949.789.4100 W. E. Tel: 800.626.9953 Los Angeles A. E. Tel: 818.594.0404 W. E. Tel: 800.288.9953 Sacramento A. E. Tel: 916.632.4500 W. E. Tel: 800.627.9953 San Diego A. E. Tel: 619.571.7540 W. E. Tel: 800.829.9953 San Jose A. E. Tel: 408.435.3500 Santa Clara W. E. Tel: 800.866.9953 Woodland Hills A. E. Tel: 818.594.0404 Colorado Denver A. E. Tel: 303.790.1662 W. E. Tel: 800.933.9953 Connecticut Chesire A. E. Tel: 203.271.5700 Wallingford W. E. Tel: 800.605.9953 Delaware North/South A. E. Tel: 800.526.4812 Tel: 800.638.5988 Florida Fort Lauderdale A. E. Tel: 305.484.5482 W. E. Tel: 800.568.9953 Orlando A. E. Tel: 407.657.3300 W. E. Tel: 407.740.7450 Tampa W. E. Tel: 800.395.9953 St. Petersburg A. E. Tel: 813.507.5000 Georgia Atlanta A. E. Tel: 770.623.4400 W. E. Tel: 800.876.9953 Hawaii A. E. Idaho A. E. Tel: 800.851.2282 Tel: 801.266.2022 Texas Austin A. E. Tel: 512.219.3700 W. E. Tel: 800.365.9953 Dallas A. E. Tel: 214.553.4300 W. E. Tel: 800.955.9953 El Paso A. E. Tel: 800.526.9238 Houston A. E. Tel: 713.781.6100 W. E. Tel: 800.888.9953 Rio Grande Valley A. E. Tel: 210.412.2047 Utah Draper W. E. Tel: 800.414.4144 Salt Lake City A. E. Tel: 801.365.3800 W. E. Tel: 800.477.9953 Vermont A. E. Tel: 800.272.9255 Virginia A. E. Tel: 800.638.5988 Washington Seattle A. E. Tel: 206.882.7000 W. E. Tel: 800.248.9953 West Virginia A. E. Tel: 800.638.5988 Wisconsin Milwaukee A. E. Tel: 414.513.1500 W. E. Tel: 800.867.9953 Wyoming A. E. Tel: 800.332.9326 Maryland Baltimore A. E. Tel: 410.720.3400 W. E. Tel: 800.863.9953 Massachusetts Boston A. E. Tel: 978.532.9808 W. E. Tel: 800.444.9953 Michigan Detroit A. E. Tel: 313.416.5800 W. E. Tel: 888.318.9953 Grandville A. E. Tel: 616.531.0345 Minnesota Minneapolis A. E. Tel: 612.881.2600 W. E. Tel: 800.860.9953 Mississippi A. E. Tel: 800.633.2918 Missouri St. Louis A. E. Tel: 314.291.5350 Montana A. E. Tel: 800.526.1741 Nebraska A. E. Tel: 800.332.4375 Nevada Las Vegas A. E. Tel: 800.528.8471 W. E. Tel: 702.765.7117 New Hampshire A. E. Tel: 800.272.9255 Sales Offices and Design Resource Centers LSI Logic Corporation Corporate Headquarters Tel: 408.433.8000 Fax: 408.433.8989 NORTH AMERICA California Irvine 949.553.5600 Fax: 949.474.8101 Pleasanton Design Center Tel: 925.730.8800 Fax: 925.730.8700 San Diego Tel: 619.613.8300 Fax: 619.613.8350 Wireless Design Center Tel: 619.350.5560 Fax: 619.350.0171 New York Fairport Tel: 716.218.0020 Fax: 716.218.9010 North Carolina Raleigh Tel: 919.785.4520 Fax: 919.783.8909 Oregon Beaverton Tel: 503.645.0589 Fax: 503.645.6612 Texas Austin Tel: 512.388.7294 Fax: 512.388.4171 Dallas Tel: 972.503.3205 Fax: 972.503.2258 Tel: Germany Munich LSI Logic GmbH 49.89.4.58.33.0 Fax: 49.89.4.58.33.108 Stuttgart Tel: 49.711.13.96.90 Fax: 49.711.86.61.428 Hong Kong Hong Kong AVT Industrial Ltd Tel: 852.2428.0008 Fax: 852.2401.2105 India Bangalore Spike Technologies India Private Ltd 91.80.664.5530 Fax: 91.80.664.9748 Israel Ramat Hasharon LSI Logic 972.3.5.480480 Fax: 972.3.5.403747 Netanya VLSI Development Centre Tel: 972.9.657190 Fax: 972.9.657194 Italy Milano LSI Logic S.P.A. 39.039.687371 Fax: 39.039.6057867 Japan Tokyo LSI Logic K.K. 81.3.5463.7821 Fax: 81.3.5463.7820 Osaka 81.6.947.5281 Fax: 81.6.947.5287 Korea Seoul LSI Logic Corporation of Korea Ltd 82.2.528.3400 Fax: 82.2.528.2250 The Netherlands Eindhoven LSI Logic Europe Ltd Tel: 31.40.265.3580 Fax: 31.40.296.2109 Singapore Singapore LSI Logic Pte Ltd 65.334.9061 Fax: 65.334.4749 Tel: 65.835.5040 Fax: 65.732.5047 Tel: Sweden Stockholm LSI Logic AB 46.8.444.15.00 Fax: 46.8.750.66.47 Switzerland Brugg/Biel LSI Logic Sulzer AG Tel: 41.32.536363 Fax: 41.32.536367 Taiwan Taipei LSI Logic Asia-Pacific 886.2.2718.7828 Fax: 886.2.2718.8869 Avnet-Mercuries Corporation, Ltd Tel: 886.2.2503.1111 Fax: 886.2.2503.1449 Jeilin Technology Corporation, Ltd Tel: 886.2.2248.4828 Fax: 886.2.2242.4397 Lumax International Corporation, Ltd Tel: 886.2.2788.3656 Fax: 886.2.2788.3568 Prospect Technology Corporation, Ltd Tel: 886.2.2721.9533 Fax: 886.2.2773.3756 United Kingdom Bracknell LSI Logic Europe Ltd 44.1344.426544 Fax: 44.1344.481039 Tel: Tel: Tel: Tel: 408.433.8000 Silicon Valley Tel: 972.244.5000 Fax: 972.244.5001 Houston Tel: 281.379.7800 Fax: 281.379.7818 Washington Issaquah Tel: 425.837.1733 Fax: 425.837.1734 Canada Ontario Ottawa 613.592.1263 Fax: 613.592.3253 Toronto Tel: 416.620.7400 Fax: 416.620.5005 Quebec Montreal 514.694.2417 Fax: 514.694.2699 Fax: 408.954.3353 Colorado Boulder Tel: 303.447.3800 Fax: 303.541.0641 Florida Boca Raton Tel: 561.989.3236 Fax: 561.989.3237 Georgia Roswell Tel: 770.641.8001 Fax: 770.641.8005 Illinois Schaumburg Tel: Tel: Tel: Tel: 847.995.1600 Tel: Tel: Tel: Fax: 847.995.1622 Kentucky Bowling Green Tel: 502.793.0010 Fax: 502.793.0040 Maryland Bethesda Tel: 301.897.5800 Fax: 301.897.8389 Massachusetts Waltham 781.890.0180 Fax: 781.890.6158 Minnesota Minneapolis Sales Offices with Design Resource Centers Tel: INTERNATIONAL Australia New South Wales Reptechnic Pty Ltd 612.9953.9844 Fax: 612.9953.9683 China Beijing LSI Logic International Services Inc Tel: 86.10.6804.2534 Fax: 86.10.6804.2521 France Paris LSI Logic S.A. Immeuble Europa 33.1.34.63.13.13 Fax: 33.1.34.63.13.19 Tel: Tel: Tel: Tel: 612.921.8300 Tel: 732.549.4500 New Jersey Edison Fax: 612.921.8399 Tel: Fax: 732.549.4802 Tel: |
Price & Availability of SYM53C140
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |