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| D a ta S he e t , D S 1 , N o v . 20 0 1 T-SMINTI 4 B 3 T Se c o n d G e n . Mo d u l a r I S D N N T (I n t e l l i g e n t ) PE F 82 90 2 V er s io n 1 . 1 Wi re d C om m un ic a t io ns Never stop thinking. Edition 2001-11-09 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. D a ta S he e t , D S 1 , N o v . 20 0 1 T-SMINTI 4 B 3 T Se c o n d G e n . Mo d u l a r I S D N N T (I n t e l l i g e n t ) PE F 82 90 2 V er s io n 1 . 1 Wi re d C om m un ic a t io ns Never stop thinking. PEF 82902 Revision History: Previous Version: Page 2001-11-09 Preliminary Data Sheet 06.01 Subjects (major changes since last revision) DS 1 Table 18 Additional C/I-command LTD Figure 41 Chapter 2.4.7.4 Chapter 3.2.3 Chapter 4.3 Chapter 4.9.4 Chapter 4.3 Chapter 4.3 Chapter 4.9.8 Chapter 4.9.4 Chapter 5.2 Chapter 5.4 The Framer / Deframer Loopback (DLB) is no more supported Reset value of MASKU is FFh (not 00h) Reset value of FW-Version is 3Eh Restriction of LOOP.LB1, LB2 and LBBD to Transparent state Input Leakage Current AIN, BIN: max. 30A Reduced power consumption For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com PEF 82902 Table of Contents 1 1.1 1.2 1.3 1.4 1.5 1.6 1.6.1 1.7 2 2.1 2.1.1 2.1.1.1 2.1.2 2.1.3 2.2 2.3 2.3.1 2.3.2 2.3.2.1 2.3.2.2 2.3.3 2.3.3.1 2.3.3.2 2.3.3.3 2.3.3.4 2.3.3.5 2.3.3.6 2.3.4 2.3.5 2.3.5.1 2.3.5.2 2.3.5.3 2.3.5.4 2.3.5.5 2.3.6 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.4.1 Data Sheet Page Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Not Supported are ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Specific Pins and Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microcontroller Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microcontroller Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Data Access (CDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Data Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MONITOR Channel Programming as a Master Device . . . . . . . . . . . MONITOR Channel Programming as a Slave Device . . . . . . . . . . . . Monitor Time-Out Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MONITOR Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C/I Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Examples for D-Channel Access Control . . . . . . . . . . . . TIC Bus Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop/Go Bit Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-Channel Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Machine of the D-Channel Arbiter . . . . . . . . . . . . . . . . . . . . . . Activation/Deactivation of IOM(R)-2 Interface . . . . . . . . . . . . . . . . . . . . . U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4B3T Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maintenance Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coding from Binary to Ternary Data . . . . . . . . . . . . . . . . . . . . . . . . . . . Decoding from Ternary to Binary Data . . . . . . . . . . . . . . . . . . . . . . . . . Monitoring of Code Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 16 19 21 23 23 27 27 28 30 40 41 41 45 47 47 48 48 49 51 51 52 53 54 55 57 59 59 63 63 64 65 2001-11-09 PEF 82902 Table of Contents 2.4.4.2 2.4.5 2.4.6 2.4.7 2.4.7.1 2.4.7.2 2.4.7.3 2.4.7.4 2.4.7.5 2.4.7.6 2.4.8 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.5.1 2.5.5.2 2.5.5.3 2.5.6 2.5.7 3 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.2 3.2.1 3.2.2 3.2.2.1 3.2.2.2 3.2.3 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 Data Sheet Page 65 66 66 67 67 68 71 72 74 75 77 79 79 81 82 82 82 85 87 91 94 95 Block Error Counter (RDS Error Counter) . . . . . . . . . . . . . . . . . . . . . Scrambler / Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command/Indication Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Machine for Activation and Deactivation . . . . . . . . . . . . . . . . . . . State Machine Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Awake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NT State Machine (IEC-T / NTC-T Compatible) . . . . . . . . . . . . . . . . Inputs to the U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Outputs of the U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NT-States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Transceiver Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line Coding, Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S/Q Channels, Multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transfer between IOM-2 and S0 . . . . . . . . . . . . . . . . . . . . . . . . . Loopback 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control of S-Transceiver / State Machine . . . . . . . . . . . . . . . . . . . . . . . C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Machine NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S-Transceiver Enable / Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Structure S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Layer 1 Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Generation of 4B3T Signal Elements . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Complete Activation Initiated by Exchange . . . . . . . . . . . . . . . . . . . . . . 99 Complete Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Complete Activation Initiated by NT . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Complete Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Layer 1 Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Analog Loop-Back S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Loopback No.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Complete Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Loopback No.2 - Single Channel Loopbacks . . . . . . . . . . . . . . . . . . 106 Local Loopbacks Featured By the LOOP Register . . . . . . . . . . . . . . . 106 External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Power Supply Blocking Recommendation . . . . . . . . . . . . . . . . . . . . . . 108 U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Oscillator Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 2001-11-09 PEF 82902 Table of Contents 4 4.1 4.2 4.3 4.3.1 4.3.2 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.5.7 4.5.8 4.5.9 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 4.6.6 4.7 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.7.6 4.7.7 4.7.8 4.7.9 4.7.10 4.7.11 Data Sheet Page 114 114 114 116 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset of U-Transceiver Functions During Deactivation or with C/I-Code RESET 122 Mode Register Evaluation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed C/I Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODEH - Mode Register IOM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CIR0 - Command/Indication Receive 0 . . . . . . . . . . . . . . . . . . . . . . . . CIX0 - Command/Indication Transmit 0 . . . . . . . . . . . . . . . . . . . . . . . . CIR1 - Command/Indication Receive 1 . . . . . . . . . . . . . . . . . . . . . . . . CIX1 - Command/Indication Transmit 1 . . . . . . . . . . . . . . . . . . . . . . . . Detailed S-Transceiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S_CONF0 - S-Transceiver Configuration Register 0 . . . . . . . . . . . . . . S_CONF2 - S-Transmitter Configuration Register 2 . . . . . . . . . . . . . . S_STA - S-Transceiver Status Register . . . . . . . . . . . . . . . . . . . . . . . S_CMD - S-Transceiver Command Register . . . . . . . . . . . . . . . . . . . . SQRR - S/Q-Channel Receive Register . . . . . . . . . . . . . . . . . . . . . . . SQXR- S/Q-Channel Transmit Register . . . . . . . . . . . . . . . . . . . . . . . ISTAS - Interrupt Status Register S-Transceiver . . . . . . . . . . . . . . . . . MASKS - Mask S-Transceiver Interrupt . . . . . . . . . . . . . . . . . . . . . . . . S_MODE - S-Transceiver Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt and General Configuration Registers . . . . . . . . . . . . . . . . . . . . ISTA - Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MASK - Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE1 - Mode1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE2 - Mode2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID - Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRES - Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed IOM(R)-2 Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CDAxy - Controller Data Access Register xy . . . . . . . . . . . . . . . . . . . . XXX_TSDPxy - Time Slot and Data Port Selection for CHxy . . . . . . . CDAx_CR - Control Register Controller Data Access CH1x . . . . . . . . S_CR - Control Register S-Transceiver Data . . . . . . . . . . . . . . . . . . . CI_CR - Control Register for CI1 Data . . . . . . . . . . . . . . . . . . . . . . . . MON_CR - Control Register Monitor Data . . . . . . . . . . . . . . . . . . . . . SDS1_CR - Control Register Serial Data Strobe 1 . . . . . . . . . . . . . . . SDS2_CR - Control Register Serial Data Strobe 2 . . . . . . . . . . . . . . . IOM_CR - Control Register IOM Data . . . . . . . . . . . . . . . . . . . . . . . . . MCDA - Monitoring CDA Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STI - Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 123 124 124 124 126 126 127 128 128 129 129 130 131 132 133 134 134 135 135 136 137 139 139 140 140 140 141 142 143 144 145 146 147 148 149 149 2001-11-09 PEF 82902 Table of Contents 4.7.12 4.7.13 4.8 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.8.6 4.9 4.9.1 4.9.2 4.9.3 4.9.4 4.9.5 4.9.6 4.9.7 4.9.8 5 5.1 5.2 5.3 5.4 5.5 5.6 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 6 7 7.1 7.1.1 7.1.2 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 Data Sheet Page 150 151 151 151 152 152 153 154 154 155 155 155 155 156 157 157 158 159 160 160 161 163 163 163 165 166 168 169 173 174 ASTI - Acknowledge Synchronous Transfer Interrupt . . . . . . . . . . . . . MSTI - Mask Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . Detailed MONITOR Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . MOR - MONITOR Receive Channel . . . . . . . . . . . . . . . . . . . . . . . . . . MOX - MONITOR Transmit Channel . . . . . . . . . . . . . . . . . . . . . . . . . . MOSR - MONITOR Interrupt Status Register . . . . . . . . . . . . . . . . . . . MOCR - MONITOR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . MSTA - MONITOR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . MCONF - MONITOR Configuration Register . . . . . . . . . . . . . . . . . . . . Detailed U-Transceiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPMODE - Operation Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . UCIR - C/I Code Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UCIW - C/I Code Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LOOP - Loopback Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RDS - Block Error Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . ISTAU - Interrupt Status Register U-Interface . . . . . . . . . . . . . . . . . . . MASKU - Mask Register U-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . FW_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial P Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel P Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage Detection Characteristics . . . . . . . . . . . . . . . . . . . . . . . Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Appendix: Differences between Q- and T-SMINTI . . . . . . . . . . . . . . . Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Pin ACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Interface Conformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Transceiver State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command/Indication Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 179 179 179 180 180 181 184 185 187 2001-11-09 PEF 82902 Table of Contents 7.3 8 Page External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Data Sheet 2001-11-09 PEF 82902 List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Data Sheet Page Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application Example T-SMINT(R)I: High Feature Intelligent NT. . . . . . . 13 Control via P Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Control via IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Serial Command Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Direct/Indirect Register Address Mode . . . . . . . . . . . . . . . . . . . . . . . . 22 Reset Generation of the T-SMINTI . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 IOM-2 Frame Structure of the T-SMINTI . . . . . . . . . . . . . . . . . . . . . 27 Architecture of the IOM-2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Data Access via CDAx0 and CDAx1 register pairs . . . . . . . . . . . . . . . 31 Examples for Data Access via CDAxy Registers. . . . . . . . . . . . . . . . . 32 Data Access when Looping TSa from DU to DD . . . . . . . . . . . . . . . . . 33 Data Access when Shifting TSa to TSb on DU (DD) . . . . . . . . . . . . . . 34 Example for Monitoring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Interrupt Structure of the Synchronous Data Transfer . . . . . . . . . . . . . 38 Examples for the Synchronous Transfer Interrupt Control with one STIxy enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Data Strobe Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MONITOR Channel Protocol (IOM(R)-2) . . . . . . . . . . . . . . . . . . . . . . . . 43 Monitor Channel, Transmission Abort requested by the Receiver. . . . 46 Monitor Channel, Transmission Abort requested by the Transmitter. . 46 Monitor Channel, Normal End of Transmission . . . . . . . . . . . . . . . . . . 46 MONITOR Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 CIC Interrupt Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 D-Channel Arbitration: C with HDLC and Direct Access to TIC Bus . 51 D-Channel Arbitration: C with HDLC and no Access to TIC Bus . . . . 52 Structure of Last Octet of Ch2 on DU . . . . . . . . . . . . . . . . . . . . . . . . . 53 Structure of Last Octet of Ch2 on DD . . . . . . . . . . . . . . . . . . . . . . . . . 54 State Machine of the D-Channel Arbiter (Simplified View). . . . . . . . . . 56 Deactivation of the IOM(R)-2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 State Diagram Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Awake Procedure initiated by the LT . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Awake Procedure initiated by the NT. . . . . . . . . . . . . . . . . . . . . . . . . . 69 NT State Machine (IEC-T/NTC-T Compatible). . . . . . . . . . . . . . . . . . . 71 Interrupt Structure U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 S/T -Interface Line Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . . 80 S-Transceiver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 State Machine NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2001-11-09 PEF 82902 List of Figures Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Figure 75 Figure 76 Figure 77 Figure 78 Figure 79 Page State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Interrupt Structure S-Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Activation Initiated by Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Activation Initiated by NT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Complete Deactivation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Test Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 External Loop at the S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Complete Loopback Options in NT-Mode . . . . . . . . . . . . . . . . . . . . . 106 Loopbacks Featured by Register LOOP . . . . . . . . . . . . . . . . . . . . . . 107 Power Supply Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 External Circuitry U-Transceiver with External Hybrid . . . . . . . . . . . . 109 External Circuitry S-Interface Transmitter . . . . . . . . . . . . . . . . . . . . . 112 External Circuitry S-Interface Receiver . . . . . . . . . . . . . . . . . . . . . . . 112 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 T-SMINTI Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . 115 Maximum Sinusoidal Ripple on Supply Voltage . . . . . . . . . . . . . . . 164 Input/Output Waveform for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . 165 IOM(R)-2 Interface - Bit Synchronization Timing . . . . . . . . . . . . . . . . . 166 IOM(R)-2 Interface - Frame Synchronization Timing . . . . . . . . . . . . . . 166 Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Microprocessor Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Multiplexed Address Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Microprocessor Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Reset Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Undervoltage Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 NTC-Q Compatible State Machine Q-SMINTI: 2B1Q . . . . . . . . . . . . 181 Simplified State Machine Q-SMINTI: 2B1Q . . . . . . . . . . . . . . . . . . . 182 IEC-T/NTC-T Compatible State Machine T-SMINTI: 4B3T. . . . . . . . 183 Interrupt Structure U-Transceiver Q-SMINTI: 2B1Q . . . . . . . . . . . . . 185 Interrupt Structure U-Transceiver T-SMINTI: 4B3T. . . . . . . . . . . . . . 186 External Circuitry Q- and T-SMINTI . . . . . . . . . . . . . . . . . . . . . . . . . 190 Data Sheet 2001-11-09 PEF 82902 List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 41 Page NT Products of the 2nd Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ACT States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interface Selection for the T-SMINTI. . . . . . . . . . . . . . . . . . . . . . . . . . 16 Header Byte Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bus Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MCLK Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Reset Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Examples for Synchronous Transfer Interrupts . . . . . . . . . . . . . . . . . . 37 Transmit Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Receive Direction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 T-SMINTI Configuration Settings in Intelligent NT Applications . . . . . 55 Frame Structure A for Downstream Transmission LT to NT . . . . . . . . 61 Frame Structure B for Upstream Transmission NT to LT. . . . . . . . . . . 62 MMS 43 Coding Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4B3T Decoding Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Active States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Differences to the former NT-SM of the IEC-T/NTC-T . . . . . . . . . . . . . 72 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 M Symbol Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Signal Output on Uk0 in State Test . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 C/I-Code Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 S/Q-Bit Position Identification and Multi-Frame Structure . . . . . . . . . . 81 4B3T Signal Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Generation of the 4B3T Signal Elements. . . . . . . . . . . . . . . . . . . . . . . 97 S/T-Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 U-Transformer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 S-Transformer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Crystal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Reset of U-Transceiver Functions During Deactivation or with C/I-Code RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Mode Register with Immediate Evaluation and Execution. . . . . . . . . 123 Maximum Input Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 S-Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 U-Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Reset Input Signal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Parameters of the UVD/POR Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 174 Design Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 ACT States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Data Sheet 2001-11-09 PEF 82902 Overview 1 Overview The PEB 82902 (T-SMINTaI) offers U-transceiver, S-transceiver and an IOMa-2 interface. A microcontroller interface provides access to both transceivers as well as the IOMa-2 interface. However, as opposed to its bigger brother T-SMINTaIX, the T-SMINTaI does not have an HDLC controller. Main target applications of the T-SMINTaI are intelligent NT applications where the HDLC controller(s) is (are) provided by the microcontroller. An example for such a microcontroller is the Infineon UTAH chip which features four flexible HDLC controllers. Table 1 on Page 1 summarizes the 2nd generation NT products. * Table 1 NT Products of the 2nd Generation PEF 80902 T-SMINT(R)O PEF 81902 T-SMINT(R)IX P-MQFP-64 P-TQFP-64 U+S+HDLC+ IOMa-2 PEF 82902 T-SMINT(R)I P-MQFP-64 P-TQFP-64 U+S+IOMa-2 Package Register access Access via MCLK, watchdog timer, SDS, BCL, Dchannel arbitration, IOMa-2 access and manipulation etc. provided HDLC controller NT1 mode available P-MQFP-44 no n.a no parallel (or SCI or IOMa-2) parallel (or SCI or IOMa-2) yes yes no yes (only) yes no no no Data Sheet 1 2001-11-09 PEF 82902 Overview 1.1 [1] [2] [3] References TS 102 080, Transmission and Multiplexing; ISDN basic rate access; Digital transmission system on metallic local lines, ETSI, November 1998 FTZ 1 TR 220 Technische Richtlinie, Spezifikation der ISDN Schnittstelle Uk0 Schicht 1, Deutsche Telecom AG, August 1991 TS 0284/96 Technische Spezifikation Intelligenter Netzabschlu (iNT) mit den Funktionen eines Terminaladapters TA 2a/b (ohne Internverkehr), Deutsche Telekom AG, Marz 2001 pr ETS 300 012 Draft, ISDN; Basic User Network Interface (UNI), ETSI, November 1996 T1.605-1991, ISDN-Basic Access Interface for S and T Reference Points (Layer 1 Specification), ANSI, 1991 I.430, ISDN User-Network Interfaces: Layer 1 Recommendations, ITU, November 1988 IEC-T, ISDN Echocancellation Circuit, PEB 20901 (IEC - TD) / PEB 20902 (IEC - TA), preliminary Target Specification 11.88, Siemens AG, 1988 SBCX, S/T Bus Interface Circuit Extended, PEB 2081 V3.4, User's Manual 11.96, Siemens AG, 1996 NTC-T, Network Termination Controller (4B3T), PEB 8090 V1.1, Data Sheet 06.98, Siemens AG, 1998 INTC-Q, Intelligent Network Termination Controller (2B1Q), PEB 8191 V1.1, Data Sheet 10.97, Siemens AG, 1997 Q-SMINTO, 2B1Q Second Gen. Modular ISDN NT (Ordinary), PEF 80912 Q-SMINTIX, 2B1Q Second Gen. Modular ISDN NT (Intelligent eXended), PEF 81912 Q-SMINTI, 2B1Q Second Gen. Modular ISDN NT (Intelligent), PEF 82912 V1.3, Data Sheets 03.01, Infineon AG, 2001 IOMa-2 Interface Reference Guide, Siemens AG, 03.91 SCOUT-S(X), Siemens Codec with S/T-Transceiver, PSB 2138x V1.1, Preliminary Data Sheet 08.98, Infineon Technologies AG, 1999 PITA, PCI Interface for Telephony/Data Applications V0.3, SICAN GmbH, September1997 Dual Channel SLICOFI-2, HV-SLIC; DUSLIC; PEB3265, 4265, 4266; Data Sheet DS2, Infineon Technologies, July 2000. [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] * Data Sheet 2 2001-11-09 T-SMINT(R)I 4B3T Second Gen. Modular ISDN NT (Intelligent) PEF 82902 Version 1.1 * 1.2 CMOS Features Features known from the PEB 8090 * U-transceiver and S-transceiver on one chip * U-interface (4B3T) conform to ETSI [1] and FTZ [2]: - Meets all transmission requirements on all ETSI and FTZ loops with margin * S/T-interface conform to ETSI [4], ANSI [5] and ITU [6] - Supports point-to-point and bus configurations - Meets and exceeds all transmission requirements * Access to IOMa-2 C/I and Monitor channels * Power-on reset and Undervoltage Detection with no external components * ESD robustness 2kV New Features P-MQFP-64-1,-2 * P-TQFP-64-1 * Conforms to 'Technische Spezifikation Intelligenter Netzabschlu (iNT) mit den Funktionen eines Terminaladapters TA 2a/b' of Deutsche Telekom AG [3] * Perfectly suited for high-end intelligent NTs that require multiple HDLC controllers * Pin compatible with Q-SMINTaI (2nd Generation) * Parallel or serial P-interface - Siemens/Intel non-multiplexed (direct or indirect addressing (SCOUT)) - Siemens/Intel multiplexed - Motorola - programmable MCLK (can be disabled) (SCOUT) Type PEF 82902 PEF 82902 Data Sheet 3 Package P-MQFP-64 P-TQFP-64 2001-11-09 PEF 82902 Overview * Enhanced IOMa-2 interface - Timeslot access and manipulation (SCOUT) - BCL output; programmable and flexible strobes SDS1/2, e.g. active during several timeslots. - Optional: All registers can be read and written to via new Monitor channel concept - External Awake (EAW) * Optional: Implementation of S-transceiver statemachine in software * Power Down and reset states (e.g. S-transceiver) for individual circuits * Automatic D-channel arbitration between S-bus and external HDLC controller * Priority setting (8/10) for off-chip HDLC controller * Pin Vref and the according external capacitor removed * Inputs accept 3.3V and 5V * I/O (open drain) accepts pull-up to 3.3V1) * Lowest power consumption due to - Low power CMOS technology (0.35) - Newly optimized low power libraries - High output swing on U- and S-line interface leads to minimized power consumption - Single 3.3 Volt power supply 1.3 Not Supported are ... * No integrated hybrid is provided by the T-SMINTaI. Therefore, an external hybrid is always required, which consists of only two additional resistors as compared to an integrated hybrid, but allows for more flexibility in board design. * On-chip HDLC controller * Auxiliary IOMa-2 interface * SRA (capacitive receiver coupling is not suited for S-feeding) * NT-Star with star point on the IOM(R)-2 bus (already not supported in NTC-T). * No access to S2-5 channels. Access only to S1 and Q channel as in Scout-S. No selection betweeen transparent and non-auto mode provided. 1) Pull-ups to 5V must be avoided. A so-called 'hot-electron-effect' would lead to long term degradation. Data Sheet 4 2001-11-09 PEF 82902 Overview 1.4 * Pin Configuration SR2 SR1 VDDa_SX VSSa_SX SX2 SX1 TP1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 /VDDDET TP2 VDDa_SR VSSa_SR A5 A6 A4 A3 A2 A1 A0 BCL DU DD 33 32 31 30 49 50 51 52 53 54 55 56 57 T-SMINT I PEF 82902 (R) 29 28 27 26 25 24 23 22 21 20 19 18 17 XOUT XIN BOUT VDDa_UX VSSa_UX AOUT 58 59 60 61 62 63 64 1 2 3 4 56 7 8 9 10 11 12 13 14 15 16 FSC DCL VSSD VDDD AD7 or SDX AD6 or SDR AD5 or SCLK AD4 AD3 AD2 AD1 AD0 /EAW MCLK /ACT pin_2.vsd Figure 1 Pin Configuration Data Sheet SDS1 ALE /WR or R/W /RD or /DS /CS VDDD VSSD /INT 5 VSSa_UR VDDa_UR AIN BIN /RST /RSTO SDS2 2001-11-09 PEF 82902 Overview 1.5 * Block Diagram XIN SR1 SR2 XOUT VDDDET RST RSTO Clock Generation POR/UVD AOUT BOUT SX1 SX2 S-Transceiver U-Tansceiver AIN BIN D-Channel Arbitration TP1 TP2 Factory Tests M O N C/I TIC C D A W D T LED ACT IOM-2 Interface P Interface (e.g. Multiplexed Mode) FSC DCL BCL DU DD SDS1 SDS2 AD0-AD7 ALE RD WR CS INT MCLK EAW block diagram.vsd Figure 2 Block Diagram Data Sheet 6 2001-11-09 PEF 82902 Overview 1.6 * Pin Definitions and Functions Pin Definitions and Functions Pin 2 1 62 63 51 52 46 45 29 30 13 14 32 31 Symbol VDDa_UR Table 2 Type - - - - - - - - - - - - O O Function Supply voltage for U-Receiver (3.3 V 5 %) Analog ground (0 V) U-Receiver Supply voltage for U-Transmitter (3.3 V 5 %) Analog ground (0 V) U-Transmitter Supply voltage for S-Receiver (3.3 V 5 %) Analog ground (0 V) S-Receiver Supply voltage for S-Transmitter (3.3 V 5 %) Analog ground (0 V) S-Transmitter Supply voltage digital circuits (3.3 V 5 %) Ground (0 V) digital circuits Supply voltage digital circuits (3.3 V 5 %) Ground (0 V) digital circuits Frame Sync: 8-kHz frame synchronization signal Data Clock: IOMa-2 interface clock signal (double clock): 1.536 MHz Bit Clock: The bit clock is identical to the IOMa-2 data rate (768 kHz) Data Downstream: Data on the IOMa-2 interface Data Upstream: Data on the IOMa-2 interface VSSa_UR VDDa_UX VSSa_UX VDDa_SR VSSa_SR VDDa_SX VSSa_SX VDDD VSSD VDDD VSSD FSC DCL 35 BCL O 33 34 DD DU I/O OD I/O OD Data Sheet 7 2001-11-09 PEF 82902 Overview Table 2 Pin 8 Pin Definitions and Functions (cont'd) Symbol SDS1 Type O Function Serial Data Strobe1: Programmable strobe signal for time slot and/or D-channel indication on IOMa-2 Serial Data Strobe2: Programmable strobe signal for time slot and/or D-channel indication on IOMa-2 Chip Select: A low level indicates a microcontroller access to the T-SMINTaI Serial Clock: Clock signal of the SCI interface if a serial interface is selected Multiplexed Bus Mode: Address/data bus Address/data line AD5 if the parallel interface is selected Non-Multiplexed Bus Mode: Data bus Data line D5 if the parallel interface is selected Serial Data Receive: Receive data line of the SCI interface if a serial interface is selected Multiplexed Bus Mode: Address/data bus Address/data line AD6 if the parallel interface is selected Non-Multiplexed Bus Mode: Data bus Data line D6 if the parallel interface is selected 7 SDS2 O 12 CS I 26 SCLK I 26 AD5 I/O 27 SDR I 27 AD6 I/O Data Sheet 8 2001-11-09 PEF 82902 Overview Table 2 Pin 28 Pin Definitions and Functions (cont'd) Symbol SDX Type OD/O Function Serial Data Transmit: Transmit data line of the SCI interface if a serial interface is selected Multiplexed Bus Mode: Address/data bus Address/data line AD7 if the parallel interface is selected Non-Multiplexed Bus Mode: Data bus Data line D7 if the parallel interface is selected Multiplexed Bus Mode: Address/data bus Transfers addresses from the microcontroller to the T-SMINTaI and data between the microcontroller and the T-SMINTaI. Non-Multiplexed Bus Mode: Data bus. Transfers data between the microcontroller and the T-SMINTaI (data lines D0-D4). Non-Multiplexed Bus Mode: Address bus transfers addresses from the microcontroller to the T-SMINTaI. For indirect address mode only A0 is valid. Multiplexed Bus Mode Not used in multiplexed bus mode. In this case A0-A6 should directly be connected to VDD. Read Indicates a read access to the registers (Intel bus mode). Data Strobe The rising edge marks the end of a valid read or write operation (Motorola bus mode). 28 AD7 I/O 21 22 23 24 25 AD0 AD1 AD2 AD3 AD4 I/O I/O I/O I/O I/O 36 37 38 39 40 53 54 11 A0 A1 A2 A3 A4 A5 A6 RD I I I I I I I I DS I Data Sheet 9 2001-11-09 PEF 82902 Overview Table 2 Pin 10 Pin Definitions and Functions (cont'd) Symbol WR Type I Function Write Indicates a write access to the registers (Intel bus mode). Read/Write A HIGH identifies a valid host access as a read operation and a LOW identifies a valid host access as a write operation (Motorola bus mode). Address Latch Enable An address on the external address/data bus (multiplexed bus type only) is latched with the falling edge of ALE. ALE also selects the microcontroller interface type (multiplexed or non multiplexed). Reset: Low active reset input. Schmitt-Trigger input with hysteresis of typical 360mV. Tie to '1' if not used. Reset Output: Low active reset output. Interrupt Request: INT becomes active if the T-SMINTaI requests an interrupt. Microcontroller Clock: Clock output for the microcontroller External Awake: A low level on EAW during power down activates the clock generation of the TSMINTaI, i.e. the IOMa-2 interface provides FSC, DCL and BCL for read and write access.1) R/W I 9 ALE I 5 RST I 6 15 RSTO INT OD OD 18 20 MCLK EAW O I 43 44 47 SX1 SX2 SR1 O O I S-Bus Transmitter Output (positive) S-Bus Transmitter Output (negative) S-Bus Receiver Input Data Sheet 10 2001-11-09 PEF 82902 Overview Table 2 Pin 48 60 59 Pin Definitions and Functions (cont'd) Symbol SR2 XIN XOUT Type I I O Function S-Bus Receiver Input Crystal 1: Connected to a 15.36 MHz crystal Crystal 2: Connected to a 15.36 MHz crystal Differential U-interface Output Differential U-interface Output Differential U-interface Input Differential U-interface Input VDD Detection: This pin selects if the VDD detection is active ('0') and reset pulses are generated on pin RSTO or whether it is deactivated ('1') and an external reset has to be applied on pin RST. Activation LED. Indicates the activation status of U- and Stransceiver. Can directly drive a LED (4mA). Test Pin 1. Used for factory device test. Tie to 'VSS' Test Pin 2. Used for factory device test. Tie to 'VSS' Tie to `1` res Reserved These pins are reserved for future use. Do not connect. 64 61 3 4 49 AOUT BOUT AIN BIN VDDDET O O I I I 17 ACT O 42 TP1 I 50 TP2 I 16, 19, 41, 55 56, 57, 58 1) This function of pin EAW is different to that defined in Ref. [13] Data Sheet 11 2001-11-09 PEF 82902 Overview I: Input O: Output (Push-Pull) OD: Output (Open Drain) 1.6.1 Specific Pins and Test Modes LED Pin ACT A LED can be connected to pin ACT to display four different states (off, slow flashing, fast flashing, on). It displays the activation status of the U- and S-transceiver according to Table 3. or it is programmable via two bits (LED1 and LED2 in register MODE2). Table 3 Pin ACT VDD ACT States LED OFF U_Deactivated 1 0 0 U_Activated x 0 1 1 S_Activated x x 0 1 2Hz (1 : 1)* fast flashing GND ON 1Hz (3 : 1)* slow flashing 0 Note: * denotes the duty cycle 'high' : 'low'. with: U_Deactivated: 'Deactivated State' as defined in Chapter 2.4.7.6. U_Activated: 'SBC Synchronizing', 'Wait for Info U4H', and `Transparent` as defined in Chapter 2.4.7.6. S-Activated: 'Activated State' as defined in Chapter 2.5.5.2. Note: Optionally, pin ACT can drive a second LED with inverse polarity (connect this additional LED to 3.3V only). Test Modes The test patterns on the S-interface (`2 kHz Single Pulses`, `96 kHz Continuous Pulses`) and on the U-interface (`Data Through`, `Send Single Pulses`,) are invoked via C/I codes (TM1, TM2, DT, SSP). Setting SRES.RES_U to `1` forces the U-transceiver into test mode `Quiet Mode` (QM), i.e. the U-transceiver is hardware reset. Data Sheet 12 2001-11-09 PEF 82902 Overview 1.7 * System Integration DC/DC Converter IDCC PEB2023 S/T - Interface S T-SMINTI PEF82902 U - Interface U POTS Interface P HV - SLIC SLICOFI - 2 HV - SLIC IOM-2 C 165 Core 4x HDLC IOM-2 UTAH USB/ V.24 USB / V.24 Interface HENTappl.vsd Figure 3 Application Example T-SMINT(R)I: High Feature Intelligent NT The U-transceiver, the S-transceiver and the IOMa-2 channels can be controlled and monitored via: a) the parallel or serial microprocessor interface - Access of on-chip registers via P interface Address/Data format - Activation/Deactivation control of U- and S-transceiver via P interface and C/I handler - T-SMINTaI is Monitor channel master - TIC bus is transparent on IOMa-2 interface and is used for D-channel arbitration between S-transceiver and off-chip HDLC controllers. Data Sheet 13 2001-11-09 PEF 82902 Overview * S C/I0 C/I1 U MON Mon C/I Register IOM -2 c - Interface IOM-2 Slave e.g. SLICOFI-2 c iommaster.vsd Figure 4 Control via P Interface Alternatively, the T-SMINTaI can be controlled via b) the IOMa-2 Interface - Access of on-chip registers via the Monitor channel with Header/Address/Data format (Device is Monitor slave) - Activation/Deactivation control of U- and S-transceiver via the C/I channels CI0 and CI1 - TIC bus is transparent on IOMa-2 interface and is used for D-channel arbitration between S-transceiver and off-chip HDLC controllers. Data Sheet 14 2001-11-09 PEF 82902 Overview * S C/I1 C/I0 U MON Register IOM -2 INT IOM-2 Master e.g. UTAH iomslave.vsd Figure 5 Control via IOMa-2 Interface Data Sheet 15 2001-11-09 PEF 82902 Functional Description 2 2.1 Functional Description Microcontroller Interfaces The T-SMINTaI supports either a serial or a parallel microcontroller interface. For applications where no controller is connected to the T-SMINTaI microcontroller interface, register programming is done via the IOMa-2 MONITOR channel from a master device. In such applications the T-SMINTaI operates in the IOMa-2 slave mode (refer to the corresponding chapter of the IOMa-2 MONITOR handler). The interface selections are all done by pinstrapping. The possible interface selections are listed in Table 4. The selection pins are evaluated when the reset input RST is released. For the pin levels stated in the tables the following is defined: 'High':dynamic pin value which must be 'High' when the pin level is evaluated VDD, VSS:static 'High' or 'Low' level (tied to VDD, VSS) * Table 4 PINS WR (R/W) RD (DS) Interface Selection for the T-SMINTaI Serial /Parallel Interface PINS CS ALE VDD Interface Type/Mode Motorola Siemens/Intel Non-Mux Siemens/Intel Mux Serial Control Interface(SCI) IOMa-2 MONITOR Channel (Slave Mode) 'High' 'High' VSS VSS Parallel Serial `High' 'High' VSS VSS edge VSS VSS Note: For a selected interface mode which does not require all pins (e.g. address pins) the unused pins must be tied to VDD. The microcontroller interface also consists of a microcontroller clock generation at pin MCLK, an interrupt request at pin INT, a reset input pin RST and a reset output pin RSTO. The interrupt request pin INT (open drain output) becomes active if the T-SMINTaI requests an interrupt. 2.1.1 Serial Control Interface (SCI) The serial control interface (SCI) is compatible to the SPI interface of Motorola and to the Siemens C510 family of microcontrollers. The SCI consists of 4 lines: SCLK, SDX, SDR and CS. Data is transferred via the lines SDR and SDX at the rate given by SCLK. The falling edge of CS indicates the beginning Data Sheet 16 2001-11-09 PEF 82902 Functional Description of a serial access to the registers. The T-SMINTaI latches incoming data at the rising edge of SCLK and shifts out at the falling edge of SCLK. Each access must be terminated by a rising edge of CS. Data is transferred in groups of 8 bits with the MSB first. Pad mode of SDX can be selected 'open drain' or 'push-pull' by programming MODE2.PPSDX. Figure 6 shows the timing of a one byte read/write access via the serial control interface. Data Sheet 17 2001-11-09 PEF 82902 Functional Description * Write Access CS SCLK Header Command/Address Data SDR 765432107654321076543210 0 write SDX Read Access CS SCLK Header Command/Address SDR 7654321076543210 1 read Data SDX 76543210 SCI_TIM.VSD Figure 6 Serial Control Interface Timing Data Sheet 18 2001-11-09 PEF 82902 Functional Description 2.1.1.1 Programming Sequences The basic structure of a read/write access to the T-SMINTaI registers via the serial control interface is shown in Figure 7. * write sequence: SDR 7 header write byte 2 byte 3 0 address (command) 07 write data 0 07 6 read sequence: SDR 7 header read byte 2 1 address (command) 07 byte 3 07 6 0 SDX read data Figure 7 Serial Command Structure A new programming sequence starts with the transfer of a header byte. The header byte specifies different programming sequences allowing a flexible and optimized access to the individual functional blocks of the T-SMINTaI. The possible sequences are listed in Table 5 and are described after that. * Table 5 Header Byte 40H 48H 43H 41H 49H Header Byte Code Sequence Adr-Data-Adr-Data Adr-Data-Data-Data Sequence Type non-interleaved interleaved Read-/Write-only non-interleaved interleaved Address Range 00H-7FH Access to Address Range 00H-7FH Header 40H: Non-interleaved A-D-A-D Sequences The non-interleaved A-D-A-D sequences give direct read/write access to the address range 00H-7FH and can have any length. In this mode SDX and SDR can be connected Data Sheet 19 2001-11-09 PEF 82902 Functional Description together allowing data transmission on one line. Example for a read/write access with header 40H: SDR SDX header wradr wrdata rdadr rddata rdadr rddata wradr wrdata Header 48H: Interleaved A-D-A-D Sequences The interleaved A-D-A-D sequences give direct read/write access to the address range 00H-7FH and can have any length. This mode allows a time optimized access to the registers by interleaving the data on SDX and SDR. Example for a read/write access with header 48H: SDR SDX header wradr wrdata rdadr rdadr rddata wradr rddata wrdata Header 43H: Read-/Write- only A-D-D-D Sequence Generally, it can be used for any register access to the address range 20H-7DH. The sequence can have any length and is terminated by the rising edge of CS. Example for a write access with header 43H: SDR SDX Example for a read access with header 43H: SDR SDX header rdadr rddata (rdadr) header wradr wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) Header 41H: Non-interleaved A-D-D-D Sequence This sequence (header 41H) allows in front of the A-D-D-D write access a noninterleaved A-D-A-D read access. Generally, it can be used for any register access to the address range 20H-7DH.The termination condition of the read access is the reception of the wradr. The sequence can have any length and is terminated by the rising edge of CS. Data Sheet 20 2001-11-09 PEF 82902 Functional Description Example for a read/write access with header 41H: SDR SDX header rdadr rddata rdadr rddata wradr wrdata (wradr) wrdata (wradr) wrdata (wradr) Header 49H: Interleaved A-D-D-D Sequence This sequence (header 49H) allows in front of the A-D-D-D write access an interleaved A-D-A-D read access. Generally, it can be used for any register access to the address range 20H-7DH.The termination condition of the read access is the reception of the wradr. The sequence can have any length and is terminated by the rising edge of CS. Example for a read/write access with header 49H: SDR SDX header rdadr rdadr rddata wradr rddata wrdata (wradr) wrdata (wradr) wrdata (wradr) 2.1.2 Parallel Microcontroller Interface The 8-bit parallel microcontroller interface with address decoding on chip allows an easy and fast microcontroller access. The parallel interface of the T-SMINTaI provides three types of P busses which are selected via pin ALE. The bus operation modes with corresponding control pins are listed in Table 6. * Table 6 Bus Operation Modes Pin ALE VDD VSS Edge Control Pins CS, R/W, DS CS, WR, RD CS, WR, RD, ALE Bus Mode (1) Motorola (2) Siemens/Intel non-multiplexed (3) Siemens/Intel multiplexed The occurrence of an edge on ALE, either positive or negative, at any time during the operation immediately selects the interface type (3). A return to one of the other interface types is possible only if a hardware reset is issued. Note: For a selected interface mode which does not require all pins (e.g. address pins) the unused pins must be tied to VDD. A read/write access to the T-SMINTaI registers can be done in multiplexed or nonmultiplexed mode. In non-multiplexed mode the register address must be applied to the address bus (A0A6) for the data access via the data bus (D0-D7). Data Sheet 21 2001-11-09 PEF 82902 Functional Description In multiplexed mode the address on the address bus (AD0-AD7) is latched in by ALE before a read/write access via the address/data bus is performed. The T-SMINTaI provides two different ways to address the register contents which can be selected with the AMOD bit in the MODE2 register. The address mode after reset is the indirect address mode (AMOD = '0'). Reprogramming into the direct address mode (AMOD = '1') has to take place in the indirect address mode. Figure 8 illustrates both register addressing modes. Direct address mode (AMOD = '1'): The register address to be read or written is directly set in the way described above. Indirect address mode (AMOD = '0'): * non-muxed: only the LSB of the address bus (A0) * muxed: only the LSB of the address-data bus (AD0) gets evaluated to address a virtual ADDRESS (0H) and a virtual DATA (1H) register. Every access to a target register consists of: * a write access (muxed or non-muxed) to ADDRESS to store the target registers address, as well as * a read access (muxed or non-muxed) from DATA to read from the target register or * a write access (muxed or non-muxed) to DATA to write to the target register * Direct Address Mode AMOD = 1 D7 - D0 A6 - A0 7Fh 7Eh 7Dh 7Ch Data A0 Indirect Address Mode AMOD = 0 (default) D7 - D0 Data 04h 03h 02h 01h 00h 1h 0h DATA ADDRESS regacces.vsd Figure 8 Direct/Indirect Register Address Mode Data Sheet 22 2001-11-09 PEF 82902 Functional Description 2.1.3 Microcontroller Clock Generation The microcontroller clock is derived from the unregulated 15.36 MHz clock from the oscillator and provided by the pin MCLK. Five clock rates are selectable by a programmable prescaler which is controlled by the bits MODE1.MCLK and MODE1.CDS corresponding to the following table. Table 7 MODE1. MCLK Bits 0 0 1 1 0 1 0 1 MCLK Frequencies MCLK frequency with MODE1.CDS = '0' 3.84 MHz 0.96 MHz 7.68 MHz disabled MCLK frequency with MODE1.CDS = '1' 7.68 MHz 1.92 MHz 15.36 MHz disabled The clock rate is changed after CS becomes inactive. 2.2 Reset Generation Figure 9 shows the organization of the reset generation of the T-SMINTaI. Data Sheet 23 2001-11-09 PEF 82902 Functional Description *. RSS1 C/I0 Code Change (Exchange Awake) 125s t 250s 0 1,x 1 0,0 RSS2,1 RSTO 1 RSS2,1 0,1= open Watchdog t = 125s Deactivation Delay Software Reset Register (SRES) Reset MODE1 Register 1 0 VDDDET RES_CI Reset Functional Block POR/UVD RES_HDLC RES_S 0 RES_U 1 VDDDET 1 Internal Reset of all Registers RST Pin RESETGEN.VSD Figure 9 Reset Generation of the T-SMINTaI1) Reset Source Selection The internal reset sources C/I code change and Watchdog timer can be output at the low active reset pin RSTO. These reset sources can be selected with the RSS2,1 bits in the MODE1 register according to Table 8. 1) The 'OR'-gates shall illustrate in a symbolic way, that 'source A active' or 'source B active' is forwarded. The real polarity of the different sources is not considered. Data Sheet 24 2001-11-09 PEF 82902 Functional Description The internal reset sources set the MODE1 register to its reset value. Table 8 RSS2 Bit 1 0 0 1 1 1) Reset Source Selection RSS1 Bit 0 0 1 0 1 x -C/I Code Change -Watchdog Timer -/RSTO disabled (= high impedance) -x x x POR/UVD1) and RST x POR/UVD can be enabled/disabled via pin VDDDET * * C/I Code Change (Exchange Awake) A change in the downstream C/I channel (C/I0) generates a reset pulse of 125 s t 250 s. * Watchdog Timer After the selection of the watchdog timer (RSS = '11') an internal timer is reset and started. During every time period of 128 ms the microcontroller has to program the WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog timer: WTC1 1. 2. 1 0 WTC2 0 1 Otherwise the timer expires and a WOV-interrupt (ISTA Register) together with a reset out pulse on pin RSTO of 125 s is generated. Deactivation of the watchdog timer is only possible with a hardware reset (including expiration of the watchdog timer). As in the SCOUT-S, the watchdog timer is clocked with the IOMa-2 clocks and works only if the internal IOMa-2 clocks are active. Hence, the power consumption is minimized in state power down. Software Reset Register (SRES) Several main functional blocks of the T-SMINTaI can be reset separately by software setting the corresponding bit in the SRES register. This is equivalent to a hardware reset of the corresponding functional block. The reset state is activated as long as the bit is set to '1'. Data Sheet 25 2001-11-09 PEF 82902 Functional Description External Reset Input At the RST input an external reset can be applied forcing the T-SMINTaI in the reset state. This external reset signal is additionally fed to the RSTO output. After release of an external reset, the C has to wait for min. tC before it starts read or write access to the T-SMINTaI (see Table 37). Reset Ouput If VDDDET is active, then the deactivation of a reset output on RSTO is delayed by tDEACT (see Table 38). Reset Generation The T-SMINTaI has an on-chip reset generator based on a Power-On Reset (POR) and Under Voltage Detection (UVD) circuit (see Table 38). The POR/UVD requires no external components. The POR/UVD circuit can be disabled via pin VDDDET. The requirements on VDD ramp-up during power-on reset are described in Chapter 5.6.5. Clocks and Data Lines During Reset During reset the data clock (DCL), the bit clock (BCL), the microcontroller clock1) (MCLK) and the frame synchronization (FSC) keep running. During reset DD and DU are high; with the exception of: * The output C/I code from the U-Transceiver on DD IOMa-2 channel 0 is 'DR' = 0000 (Value after reset of register UCIR = '00H') * The output C/I code from the S-Transceiver on DU IOMa-2 channel 1 is 'TIM' = 0000. 1) during a Power-On/UVD Reset, the microcontroller clock MCLK is not running, but starts running as soon as timer tDEAC is started. Data Sheet 26 2001-11-09 PEF 82902 Functional Description 2.3 IOM-2 Interface The T-SMINTaI supports the IOMa-2 interface in terminal mode (DCL=1.536 MHz) according to the IOMa-2 Reference Guide [12]. 2.3.1 IOMa-2 Functional Description The IOMa-2 interface consists of four lines: FSC, DCL, DD, DU and optionally BCL. The rising edge of FSC indicates the start of an IOMa-2 frame. The DCL and the BCL clock signals synchronize the data transfer on both data lines DU and DD. The DCL is twice the bit rate, the BCL rate is equal to the bit rate. The bits are shifted out with the rising edge of the first DCL clock cycle and sampled at the falling edge of the second clock cycle. With BCL the bits are shifted out with the rising edge and sampled with the falling edge of the single clock cycle. The IOMa-2 interface can be enabled/disabled with the DIS_IOM bit in the IOM_CR registerThe FSC signal is an 8 kHz frame sync signal. The number of PCM timeslots on the receive and transmit lines is determined by the frequency of the DCL clock (or BCL), with the 1.536 MHz (BCL=768 kHz) clock 3 channels consisting of 4 timeslots each are available. IOM(R)-2 Frame Structure of the T-SMINTaI The frame structure on the IOMa-2 data ports (DU,DD) of the T-SMINTaI with a DCL clock of 1.536 MHz (or BCL=768 kHz) and if TIC bus is not disabled (IOM_CR.TIC_DIS) is shown in Figure 10. * macro_19 Figure 10 IOM-2 Frame Structure of the T-SMINTaI Data Sheet 27 2001-11-09 PEF 82902 Functional Description The frame is composed of three channels: * Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR programming channel (MON0) and a command/indication channel (CI0) for control and programming of e.g. the U-transceiver. * Channel 1 contains two 64-kbit/s intercommunication channels (IC), a MONITOR programming channel (MON1) and a command/indication channel (CI1) for control and programming of e.g. the S-transceiver. * Channel 2 is used for D-channel access mechanism (TlC-bus, S/G bit). Additionally, channel 2 supports further IC and MON channels. 2.3.2 IOMa-2 Handler The IOMa-2 handler offers a great flexibility for handling the data transfer between the different functional units of the T-SMINTaI and voice/data devices connected to the IOMa-2 interface. Additionally it provides a microcontroller access to all time slots of the IOMa-2 interface via the four controller data access registers (CDA). The PCM data of the functional units * S-transceiver (S) and the * Controller data access (CDA) can be configured by programming the time slot and data port selection registers (TSDP). With the TSS bits (Time Slot Selection) the PCM data of the functional units can be assigned to each of the 12 PCM time slots of the IOMa-2 frame. With the DPS bit (Data Port Selection) the output of each functional unit is assigned to DU or DD respectively. The input is assigned vice versa. With the control registers (CR) the access to the data of the functional units can be controlled by setting the corresponding control bits (EN, SWAP). The IOMa-2 handler also provides access to the * * * * U and S transceiver MONITOR channel C/I channels (CI0,CI1) TIC bus (TIC) The access to these channels is controlled by the registers S_CR, CI_CR and MON_CR. The IOMa-2 interface with the two Serial Data Strobes (SDS1,2) is controlled by the control registers IOM_CR, SDS1_CR and SDS2_CR. The following Figure 11 shows the architecture of the IOMa-2 handler. Data Sheet 28 2001-11-09 PEF 82902 Functional Description BCL/SCLK SDS1 IOM-2 Handler SDS1/2_CR IOM_CR IOM-2 Interface (EN, OD) (EN, TLEN, TSS) TIC Bus Data SDS2 FSC DCL DU DD D/B1/B2 Data C/I0 Data Monitor Data Controller Data Access (CDA) Architecture of the IOMa-2 Handler CDA Data C/I0 Data C/I1 Data CDA Registers CDA10 CDA11 CDA20 CDA21 (TSDP, DPS, EN, SWAP, TBM, MCDA, STI) CDA_TSDPxy CDA_CRx MCDA STI MSTI ASTI Control Data Access Control Monitor Data TIC Bus Disable Control C/I1 Data Control Transceiver Data Access (TSS, DPS, EN) MON_CR IOM_CR CI_CR Transceiver Data (TR=U/S) S_TSDP_B1 S_TSDP_B2 S_CR TR_B1_X TR_B2_X TR_D_X TR_B1_R TR_B2_R TR_D_R TR represents the U and S transceiver MON Handler TIC C/I0 Data C/I1 21150_0 7 Microcontroller Interface Data Sheet * Figure 11 29 2001-11-09 PEF 82902 Functional Description 2.3.2.1 Controller Data Access (CDA) The four controller data access registers (CDA10, CDA11, CDA20, CDA21) provide microcontroller access to the 12 IOMa-2 time slots and more: * looping of up to four independent PCM channels from DU to DD or vice versa over the four CDA registers * shifting or switching of two independent PCM channels to another two independent PCM channels on both data ports (DU, DD). Between reading and writing the data can be manipulated (processed with an algorithm) by the microcontroller. If this is not the case a switching function is performed. * monitoring of up to four time slots on the IOMa-2 interface simultaneously * microcontroller read and write access to each PCM channel The access principle, which is identical for the two channel register pairs CDA10/11 and CDA20/21, is illustrated in Figure 12. The index variables x,y used in the following description can be 1 or 2 for x, and 0 or 1 for y. The prefix 'CDA_' from the register names has been omitted for simplification. To each of the four CDAxy data registers a TSDPxy register is assigned by which the time slot and the data port can be determined. With the TSS (Time Slot Selection) bits a time slot from 0...11 can be selected. With the DPS (Data Port Selection) bit the output of the CDAxy register can be assigned to DU or DD respectively. The time slot and data port for the output of CDAxy is always defined by its own TSDPxy register. The input of CDAxy depends on the SWAP bit in the control registers CRx. If the SWAP bit = '0' (swap is disabled) the time slot and data port for the input and output of the CDAxy register is defined by its own TSDPxy register. If the SWAP bit = '1' (swap is enabled) the input port and time slot of the CDAx0 is defined by the TSDP register of CDAx1 and the input port and time slot of CDAx1 is defined by the TSDP register of CDAx0. The input definition for time slot and data port CDAx0 are thus swapped to CDAx1 and for CDAx1 swapped to CDAx0. The output timeslots are not affected by SWAP. The input and output of every CDAxy register can be enabled or disabled by setting the corresponding EN (-able) bit in the control register CDAx_CR. If the input of a register is disabled the output value in the register is retained. Usually one input and one output of a functional unit (transceiver, CDA register) is programmed to a timeslot on IOMa-2 (e.g. for B-channel transmission in upstream direction the S-transceiver writes data onto IOMa-2 and the U-transceiver reads data from IOMa-2). For monitoring data in such cases a CDA register is programmed as described below under "Monitoring Data". Besides that none of the IOMa-2 timeslots must be assigned more than one input and output of any functional unit. Data Sheet 30 2001-11-09 PEF 82902 Functional Description *. TSa Control Register CDA_CRx 1 0 TSb DU 0 1 Time Slot Selection (TSS) Enable output (EN_O0) input (EN_I0) Input Swap (SWAP) input (EN_I1) Enable output (EN_O1) CDA_TSDPx0 Time Slot Selection (TSS) 1 1 1 1 CDAx0 CDAx1 1 1 Data Port Selection (DPS) 0 1 1 0 TSa x = 1 or 2; a,b = 0...11 TSb IOM_HAND.FM4 Figure 12 Data Access via CDAx0 and CDAx1 register pairs Looping and Shifting Data Figure 13 gives examples for typical configurations with the above explained control and configuration possibilities with the bits TSS, DPS, EN and SWAP in the registers TSDPxy or CDAx_CR: a) looping IOMa-2 time slot data from DU to DD or vice versa (SWAP = '0') b) shifting data from TSa to TSb and TSc to TSd in both transmission directions (SWAP = '1') c) switching data from TSa to TSb and looping from DU to DD or switching TSc to TSd and looping from DD to DU . TSa is programmed in TSDP10, TSb in TSDP11, TSc in TSDP20 and TSd in TSDP21. Data Sheet 31 2001-11-09 Data Port Selection (DPS) DD CDA_TSDPx1 PEF 82902 Functional Description * a) Looping Data TSa TSb TSc TSd DU CDA10 CDA11 CDA20 CDA21 .TSS: TSa TSb .DPS '0' '0' .SWAP '0' b) Shifting Data TSa TSb DD TSc '1' '0' TSc TSd TSd '1' DU CDA10 CDA11 CDA20 CDA21 DD .TSS: TSa TSb .DPS '0' '1' .SWAP '1' c) Switching Data TSa TSb TSc '0' '1' TSc TSd TSd '1' DU CDA10 CDA11 CDA20 CDA21 DD .TSS: TSa .DPS '0' .SWAP Figure 13 TSb '0' '1' TSc '1' '1' TSd '1' Examples for Data Access via CDAxy Registers a) Looping Data b) Shifting (Switching) Data c) Switching and Looping Data Data Sheet 32 2001-11-09 PEF 82902 Functional Description Figure 14 shows the timing of looping TSa from DU to DD via CDAxy register. TSa is read in the CDAxy register from DU and is written one frame later on DD. Figure 15 shows the timing of shifting data from TSa to TSb on DU(DD). In Figure 15a) shifting is done in one frame because TSa and TSb didn't succeed directly one another (a = 0...9 and b a+2). In Figure 15b) shifting is done from one frame to the following frame. This is the case when the time slots succeed one other (b = a+1) or b is smaller than a (b < a). At looping and shifting the data can be accessed by the controller between the synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). STI and STOV are explained in the section 'Synchronous Transfer'. If there is no controller intervention the looping and shifting is done autonomously. *. FSC DU TSa TSa CDAxy STI RD STOV ACK WR C *) DD TSa TSa *) if access by the C is required Figure 14 Data Access when Looping TSa from DU to DD Data Sheet 33 2001-11-09 PEF 82902 Functional Description * a) Shifting TSa TSb within one frame (a,b: 0...11 and b a+2) FSC DU (DD) TSa TSb TSa CDAxy STI RD WR STOV STI C *) b) Shifting TSa TSb in the next frame (a,b: 0...11 and (b = a+1 or b DU (DD) ACK TSa TSb TSa TSb CDAxy STI RD STOV WR C *) *) if access by the C is required ACK Figure 15 Data Access when Shifting TSa to TSb on DU (DD) Data Sheet 34 2001-11-09 PEF 82902 Functional Description Monitoring Data Figure 16 gives an example for monitoring of two IOMa-2 time slots each on DU or DD simultaneously. For monitoring on DU and/or DD the channel registers with even numbers (CDA10, CDA20) are assigned to time slots with even numbers TS(2n) and the channel registers with odd numbers (CDA11, CDA21) are assigned to time slots with odd numbers TS(2n+1). The user has to take care of this restriction by programming the appropriate time slots. This mode is only valid if two blocks (e.g. both transceivers) are programmed to these timeslots and communicating via IOMa-2. However, if only one block is programmed to this timeslot the timeslots for CDAx0 and CDAx1 can be programmed completely independently. *. a) Monitoring Data EN_O: '0' CDA_CR1. EN_I: '1' DPS: '0' TSS: TS(2n) '0' '1' '0' TS(2n+1) DU CDA10 CDA20 CDA11 CDA21 TSS: TS(2n) DPS: '1' CDA_CR2. EN_I: '1' EN_O: '0' TS(2n+1) '1' '1' '0' DD Figure 16 Example for Monitoring Data Monitoring TIC Bus Monitoring the TIC bus (TS11) is handled as a special case. The TIC bus can be monitored with the registers CDAx0 by setting the EN_TBM (Enable TIC Bus Monitoring) bit in the control registers CRx. The TSDPx0 must be set to 08h for monitoring from DU Data Sheet 35 2001-11-09 PEF 82902 Functional Description or 88h for monitoring from DD. By this it is possible to monitor the TIC bus (TS11) and the odd numbered D-channel (TS3) simultaneously on DU and DD. Synchronous Transfer While looping, shifting and switching the data can be accessed by the controller between the synchronous transfer interrupt (STI) and the synchronous transfer overflow interrupt (STOV). The microcontroller access to each of the CDAxy registers can be synchronized by means of four programmable synchronous transfer interrupts (STIxy)1) and synchronous transfer overflow interrupts (STOVxy)2) in the STI register. Depending on the DPS bit in the corresponding TSDPxy register the STIxy is generated two (for DPS='0') or one (for DPS='1') BCL clock after the selected time slot (CDA_TSDPxy.TSS). One BCL clock is equivalent to two DCL clocks. In the following description the index xy0 and xy1 are used to refer to two different interrupt pairs (STI/STOV) out of the four CDA interrupt pairs (STI10/STOV10, STI11/ STOV11, STI20/STOV20, STI21/STOV21). A STOVxy0 is related to its STIxy0 and is only generated if STIxy0 is enabled and not acknowledged. However, if STIxy0 is masked, the STOVxy0 is generated for any other STIxy1 which is enabled and not acknowledged. Table 9 gives some examples for that. It is assumed that a STOV interrupt is only generated because a STI interrupt was not acknowledged before. In example 1 only the STIxy0 is enabled and thus STIxy0 is only generated. If no STI is enabled, no interrupt will be generated even if STOV is enabled (example 2). In example 3 STIxy0 is enabled and generated and the corresponding STOVxy0 is disabled. STIxy1 is disabled but its STOVxy1 is enabled, and therefore STOVxy1 is generated due to STIxy0. In example 4 additionally the corresponding STOVxy0 is enabled, so STOVxy0 and STOVxy1 are both generated due to STIxy0. In example 5 additionally the STIxy1 is enabled with the result that STOVxy0 is only generated due to STIxy0 and STOVxy1 is only generated due to STIxy1. Compared to the previous example STOVxy0 is disabled in example 6, so STOVxy0 is not generated and STOVxy1 is only generated for STIxy1 but not for STIxy0. 1) In order to enable the STI interrupts the input of the corresponding CDA register has to be enabled. This is also valid if only a synchronous write access is wanted. The enabling of the output alone does not effect an STI interrupt. 2) In order to enable the STOV interrupts the output of the corresponding CDA register has to be enabled. This is also valid if only a synchronous read access is wanted. The enabling of the input alone does not effect an interrupt. Data Sheet 36 2001-11-09 PEF 82902 Functional Description * Table 9 Examples for Synchronous Transfer Interrupts Enabled Interrupts (Register MSTI) Generated Interrupts (Register STI) STI xy0 xy0 xy0 xy0 xy1 xy0 xy1 xy0 xy1 STOV xy1 xy0 ; xy1 xy0 xy1 xy1 xy0 ; xy2 xy1 ; xy2 Example 1 Example 2 Example 3 Example 4 Example 5 Example 6 Example 7 STI xy0 xy0 xy0 xy0 ; xy1 xy0 ; xy1 xy0 ; xy1 STOV xy0 xy1 xy0 ; xy1 xy0 ; xy1 xy1 xy0 ; xy1 ; xy2 Compared to example 5 in example 7 a third STOVxy2 is enabled and thus STOVxy2 is generated additionally for both STIxy0 and STIxy1. A STOV interrupt is not generated if all stimulating STI interrupts are acknowledged. A STIxy must be acknowledged by setting the ACKxy bit in the ASTI register two BCL clock (for DPS='0') or one BCL clocks (for DPS='1') before the time slot which is selected for the appropriate STIxy. The interrupt structure of the synchronous transfer is shown in Figure 17. Data Sheet 37 2001-11-09 PEF 82902 Functional Description *. INT U ST CIC 1 WOV S MOS 1 MASK Figure 17 U ST CIC 0 WOV S MOS 0 ISTA STOV21 STOV20 STOV11 STOV10 STI21 STI20 STI11 STI10 MSTI STOV21 STOV20 STOV11 STOV10 STI21 STI20 STI11 STI10 STI ACK21 ACK20 ACK11 ACK10 ASTI Interrupt Structure of the Synchronous Data Transfer Figure 18 shows some examples based on the timeslot structure. Figure a) shows at which point in time a STI and STOV interrupt is generated for a specific timeslot. Figure b) is identical to example 3 above, figure c) corresponds to example 5 and figure d) shows example 4. Data Sheet 38 2001-11-09 PEF 82902 Functional Description *. : STI interrupt generated : STOV interrupt generated for a not acknowledged STI interrupt a) Interrupts for data access to time slot 0 (B1 after reset), MSTI.STI10 and MSTI.STOV10 enabled xy: CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: 10 TS0 '0' '0' 11 TS1 '1' '1' TS2 TS3 21 TS5 '1' '1' TS4 TS5 20 TS11 '1' '1' TS6 TS7 TS8 TS9 TS10 TS11 TS0 TS11 TS0 TS1 b) Interrupts for data access to time slot 0 (B1 after reset), STOV interrupt used as flag for "last possible CDA access"; MSTI.STI10 and MSTI.STOV20 enabled xy: CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: 10 TS0 '0' '1' 11 TS1 '1' '1' TS2 TS3 21 TS5 '1' '1' TS4 TS5 20 TS11 '1' '0' TS6 TS7 TS8 TS9 TS10 TS11 TS0 TS11 TS0 TS1 c) Interrupts for data access to time slot 0 and 1 (B1 and B2 after reset), MSTI.STI10, MSTI.STOV10, MSTI.STI11 and MSTI.STOV11 enabled xy: CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: 10 TS0 '0' '0' 11 TS1 '0' '0' TS2 TS3 21 TS5 '1' '1' TS4 TS5 20 TS11 '1' '1' TS6 TS7 TS8 TS9 TS10 TS11 TS0 TS11 TS0 TS1 d) Interrupts for data access to time slot 0 (B1 after reset), STOV20 interrupt used as flag for "last possible CDA access", STOV10 interrupt used as flag for "CDA access failed"; MSTI.STI10, MSTI.STOV10 and MSTI.STOV20 enabled xy: CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: 10 TS0 '0' '0' 11 TS1 '1' '1' TS2 TS3 21 TS5 '1' '1' TS4 TS5 20 TS11 '1' '0' TS6 TS7 TS8 TS9 TS10 TS11 TS0 TS11 TS0 TS1 sti_stov.vsd Figure 18 * . Examples for the Synchronous Transfer Interrupt Control with one STIxy enabled Data Sheet 39 2001-11-09 PEF 82902 Functional Description 2.3.2.2 Serial Data Strobe Signal For time slot oriented standard devices at the IOMa-2 interface, the T-SMINTaI provides two independent data strobe signals SDS1 and SDS2. The two strobe signals can be generated with every 8-kHz-frame and are controlled by the registers SDS1/2_CR. By programming the TSS bits and three enable bits (ENS_TSS, ENS_TSS+1, ENS_TSS+3) a data strobe can be generated for the IOMa-2 time slots TS, TS+1 and TS+3 (bit7,6) and the combinations of them. The data strobes for TS and TS+1 are always 8 bits long (bit7 to bit0) whereas the data strobe for TS+3 is always 2 bits long (bit7, bit6). * FSC DD,DU B1 TS0 B2 TS1 MON0 TS2 MM RX D CI0 IC1 TS4 IC2 MON1 TS5 TS6 CI1 MM RX TS3 TS7 TS8 TS9 TS10 TS11 TS0 TS1 SDS1,2 (Example1) SDS1,2 (Example2) SDS1,2 (Example3) Example 1: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 = '0H' = '0' = '1' = '0' = '5H' = '1' = '1' = '0' = '0H' = '1' = '1' = '1' Example 2: Example 3: strobe.vsd Figure 19 Data Strobe Signal Generation Data Sheet 40 2001-11-09 PEF 82902 Functional Description Figure 19 shows three examples for the generation of a strobe signal. In example 1 the SDS is active during channel B2 on IOMa-2, whereas in the second example during IC2 and MON1. The third example shows a strobe signal for 2B+D channels which is used e.g. at an IDSL (144 kbit/s) transmission. 2.3.3 IOMa-2 Monitor Channel The IOMa-2 MONITOR channel is utilized for information exchange between the TSMINTaI and other devices in the MONITOR channel. The MONTIOR channel data can be controlled by the bits in the MONITOR control register (MON_CR). For the transmission of the MONITOR data one of the 3 IOMa-2 channels can be selected by setting the MONITOR channel selection bits (MCS) in the MONITOR control register (MON_CR). The DPS bit in the same register selects between an output on DU or DD respectively and with EN_MON the MONITOR data can be enabled/disabled. The default value is MONITOR channel 0 (MON0) enabled and transmission on DD. The MONITOR channel of the T-SMINTaI can be used in the following applications (refer also to and ): * As a master device the T-SMINTaI can program and control other devices (e.g. PSB 2161) attached to the IOMa-2, which therefore, do not need a microcontroller interface. * As a slave device the T-SMINTaI is programmed and controlled from a master device on IOMa-2 (e.g. UTAH). This is used in applications where no microcontroller is connected directly to the T-SMINTaI. The MONITOR channel operates according to the IOMa-2 Reference Guide [12]. Note: In contrast to the NTC-T, the T-SMINTaI does neither issue nor react on Monitor commands (MON0,1,2,8). Instead, the T-SMINTaI operated in IOMa-2 slave mode must be programmed via new MONITOR channel concept (see Chapter 2.3.3.4), which provides full register access. The Monitor time out procedure is available. Reporting of the T-SMINTaI is performed via interrupts. 2.3.3.1 Handshake Procedure The MONITOR channel operates on an asynchronous basis. While data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure using the MONITOR Channel Receive (MR) and MONITOR Channel Transmit (MX) bits. Data is placed onto the MONITOR channel and the MX bit is activated. This data will be transmitted once per 8-kHz frame until the transfer is acknowledged via the MR bit. Data Sheet 41 2001-11-09 PEF 82902 Functional Description The MONITOR channel protocol is described In the following section and Figure 22 shall illustrate this. The relevant control and status bits for transmission and reception are listed in Table 10 and Table 11. Table 10 Control/ Status Bit Control Status Transmit Direction Register MOCR MOSR MSTA Table 11 Control/ Status Bit Control Status Bit MXC MIE MDA MAB MAC Function MX Bit Control Transmit Interrupt (MDA, MAB, MER) Enable Data Acknowledged Data Abort Transmission Active Receive Direction Register MOCR MOSR Bit MRC MRE MDR MER Function MR Bit Control Receive Interrupt (MDR) Enable Data Received End of Reception Data Sheet 42 2001-11-09 PEF 82902 Functional Description * P Transmitter MON MX 1 1 0 0 1 0 0 0 1 0 0 0 1 1 1 1 Receiver MR 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 1 ITD10032 P MIE = 1 MOX = ADR MXC = 1 MAC = 1 MDA Int. MOX = DATA1 FF FF ADR ADR DATA1 DATA1 DATA1 DATA1 DATA2 DATA2 DATA2 DATA2 FF FF FF FF 125 s MDR Int. RD MOR (=ADR) MRC = 1 MDR Int. RD MOR (=DATA1) MDA Int. MOX = DATA2 MDR Int. RD MOR (=DATA2) MDA Int. MXC = 0 MER Int. MRC = 0 MAC = 0 Figure 20 MONITOR Channel Protocol (IOM(R)-2) Before starting a transmission, the microprocessor should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. This is indicated by a '0' in the MONITOR Channel Active MAC status bit. After having written the MONITOR Data Transmit (MOX) register, the microprocessor sets the MONITOR Transmit Control bit MXC to '1'. This enables the MX bit to go active (0), indicating the presence of valid MONITOR data (contents of MOX) in the corresponding frame. As a result, the receiving device stores the MONITOR byte in its MONITOR Receive MOR register and generates a MDR interrupt status. Alerted by the MDR interrupt, the microprocessor reads the MONITOR Receive (MOR) register. When it is ready to accept data (e.g. based on the value in MOR, which in a point-to-multipoint application might be the address of the destination device), it sets the MR control bit MRC to '1' to enable the receiver to store succeeding MONITOR channel bytes and acknowledge them according to the MONITOR channel protocol. In addition, Data Sheet 43 2001-11-09 PEF 82902 Functional Description it enables other MONITOR channel interrupts by setting MONITOR Interrupt Enable (MIE) to '1'. As a result, the first MONITOR byte is acknowledged by the receiving device setting the MR bit to '0'. This causes a MONITOR Data Acknowledge MDA interrupt status at the transmitter. A new MONITOR data byte can now be written by the microprocessor in MOX. The MX bit is still in the active (0) state. The transmitter indicates a new byte in the MONITOR channel by returning the MX bit active after sending it once in the inactive state. As a result, the receiver stores the MONITOR byte in MOR and generates a new MDR interrupt status. When the microprocessor has read the MOR register, the receiver acknowledges the data by returning the MR bit active after sending it once in the inactive state. This in turn causes the transmitter to generate a MDA interrupt status. This "MDA interrupt - write data - MDR interrupt - read data - MDA interrupt" handshake is repeated as long as the transmitter has data to send. Note that the MONITOR channel protocol imposes no maximum reaction times to the microprocessor. When the last byte has been acknowledged by the receiver (MDA interrupt status), the microprocessor sets the MONITOR Transmit Control bit MXC to '0'. This enforces an inactive ('1') state in the MX bit. Two frames of MX inactive signifies the end of a message. Thus, a MONITOR Channel End of Reception MER interrupt status is generated by the receiver when the MX bit is received in the inactive state in two consecutive frames. As a result, the microprocessor sets the MR control bit MRC to 0, which in turn enforces an inactive state in the MR bit. This marks the end of the transmission, making the MONITOR Channel Active MAC bit return to '0'. During a transmission process, it is possible for the receiver to ask a transmission to be aborted by sending an inactive MR bit value in two consecutive frames. This is effected by the microprocessor writing the MR control bit MRC to '0'. An aborted transmission is indicated by a MONITOR Channel Data Abort MAB interrupt status at the transmitter. The MONITOR transfer protocol rules are summarized in the following section * A pair of MX and MR in the inactive state for two or more consecutive frames indicates an idle state or an end of transmission. * A start of a transmission is initiated by the transmitter by setting the MXC bit to '1' enabling the internal MX control. The receiver acknowledges the received first byte by setting the MR control bit to '1' enabling the internal MR control. * The internal MX, MR control indicates or acknowledges a new byte in the MON slot by toggling MX, MR from the active to the inactive state for one frame. * Two frames with the MR-bit set to inactive indicate a receiver request for abort. * The transmitter can delay a transmission sequence by sending the same byte continuously. In that case the MX-bit remains active in the IOMa-2 frame following the first byte occurrence. Delaying a transmission sequence is only possible while the receiver MR-bit and the transmitter MX-bit are active. Data Sheet 44 2001-11-09 PEF 82902 Functional Description * Since a double last-look criterion is implemented the receiver is able to receive the MON slot data at least twice (in two consecutive frames), the receiver waits for the acknowledge of the reception of two identical bytes in two successive frames. * To control this handshake procedure a collision detection mechanism is implemented in the transmitter. This is done by making a collision check per bit on the transmitted MONITOR data and the MX bit. * Monitor data will be transmitted repeatedly until its reception is acknowledged or the transmission time-out timer expires. * Two frames with the MX bit in the inactive state indicates the end of a message (EOM). * Transmission and reception of monitor messages can be performed simultaneously. This feature is used by the device to send back the response before the transmission from the controller is completed (the device does not wait for EOM from controller). 2.3.3.2 Error Treatment In case the device does not detect identical monitor messages in two successive frames, transmission is not aborted. Instead the device will wait until two identical bytes are received in succession. A transmission is aborted by the device if * an error in the MR handshaking occurs * a collision on the IOMa-2 bus of the MONITOR data or MX bit occurs * the transmission time-out timer expires A reception is aborted by the device if * an error in the MX handshaking occurs or * an abort request from the opposite device occurs MX/MR Treatment in Error Case In the master mode the MX/MR bits are under control of the microcontroller through MXC or MRC, respectively. An abort is indicated by an MAB interrupt or MER interrupt, respectively. In the slave mode the MX/MR bits are under control of the device. An abort is always indicated by setting the MX/MR bit inactive for two or more IOMa-2 frames. The controller must react with EOM. Figure 21 shows an example for an abort requested by the receiver, Figure 22 shows an example for an abort requested by the transmitter and Figure 23 shows an example for a successful transmission. Data Sheet 45 2001-11-09 PEF 82902 Functional Description * IOM -2 Frame No. MX (DU) MR (DD) 1 0 1 0 1 2 3 4 5 6 EOM 7 Abort Request from Receiver mon_rec-abort.vsd Figure 21 * Monitor Channel, Transmission Abort requested by the Receiver IOM -2 Frame No. MR (DU) MX (DD) 1 0 1 0 1 2 3 4 5 6 EOM 7 Abort Request from Transmitter mon_tx-abort.vsd Figure 22 * Monitor Channel, Transmission Abort requested by the Transmitter IOM -2 Frame No. MR (DU) MX (DD) 1 0 1 0 1 2 3 4 5 6 7 EOM 8 mon_norm.vsd Figure 23 Data Sheet Monitor Channel, Normal End of Transmission 46 2001-11-09 PEF 82902 Functional Description 2.3.3.3 MONITOR Channel Programming as a Master Device The master mode is selected by default if one of the microcontroller interfaces is selected. The monitor data is written by the microcontroller in the MOX register and transmitted via IOMa-2 DD(DU) line to the programmed/controlled device e.g. ARCOFIBA PSB 2161. The transfer of the commands in the MON channel is regulated by the handshake protocol mechanism with MX, MR. 2.3.3.4 MONITOR Channel Programming as a Slave Device MONITOR slave mode can be selected by pinstrapping the microcontroller interface pins according to Table 4. All programming data required by the device is received in the MONITOR time slot on the IOMa-2 and is transferred to the MOR register. The transfer of the commands in the MON channel is regulated by the handshake protocol mechanism with MX, MR which is described in the previous Chapter 2.3.3.1. The first byte of the MONITOR message must contain in the higher nibble the MONITOR channel address code which is '1000' for the T-SMINTaI. The lower nibble distinguishes between a programming command and an identification command. Identification Command In order to be able to identify unambiguously different hardware designs of the TSMINTaI by software, the following identification command is used: DU 1st byte value DU 2nd byte value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The T-SMINTaI responds to this identification sequence by sending a identification sequence: DD 1st byte value DD 2nd byte value 1 0 0 0 0 0 0 0 0 0 DESIGN DESIGN: six bit code, specific for each device in order to identify differences in operation (see "ID - Identification Register" on Page 139). This identification sequence is usually done once, when the T-SMINTaI is connected for the first time. This function is used so that the software can distinguish between different possible hardware configurations. However this sequence is not compulsory. Programming Sequence The programming sequence is characterized by a '1' being sent in the lower nibble of the received address code. The data structure after this first byte is equivalent to the structure of the serial control interface described in chapter Chapter 2.1.1. Data Sheet 47 2001-11-09 PEF 82902 Functional Description * DU 1st byte value DU 2nd byte value DU 3rd byte value DU 4th byte value DU (nth + 3) byte value 1 R/W 0 0 0 0 0 0 1 Header Byte Command/ Register Address Data 1 Data n All registers can be read back when setting the R/W bit to '1'. The T-SMINTaI responds by sending his IOMa-2 specific address byte (81h) followed by the requested data. Note: Application Hint: It is not allowed to disable the MX- and MR-control in the programming device at the same time! First, the MX-control must be disabled, then the C has to wait for an End of Reception before the MR-control may be disabled. Otherwise, the TSMINTaI does not recognize an End of Reception. 2.3.3.5 Monitor Time-Out Procedure To prevent lock-up situations in a MONITOR transmission a time-out procedure can be enabled by setting the time-out bit (TOUT) in the MONITOR configuration register (MCONF). An internal timer is always started when the transmitter must wait for the reply of the addressed device or for transmit data from the microcontroller. After 40 IOMa-2 frames (5 ms) without reply the timer expires and the transmission will be aborted with an EOM (End of Message) command by setting the MX bit to '1' for two consecutive IOMa-2 frames. 2.3.3.6 MONITOR Interrupt Logic Figure 24 shows the interrupt structure of the MONITOR handler. The MONITOR Data Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt Enable (MRE) and MR bit Control (MRC). The MONITOR channel End of Reception MER, MONITOR channel Data Acknowledged MDA and MONITOR channel Data Abort MAB interrupt status bits have a common enable bit MONITOR Interrupt Enable MIE. MRE set to "0" prevents the occurrence of MDR status, including when the first byte of a packet is received. When MRE is set to "1" but MRC is set to "0", the MDR interrupt status is generated only for the first byte of a receive packet. When both MRE and MRC are set to "1", MDR is always generated and all received MONITOR bytes - marked by a 1-to-0 transition in MX bit - are stored. Additionally, a MRC set to "1" enables the control of the MR handshake bit according to the MONITOR channel protocol. Data Sheet 48 2001-11-09 PEF 82902 Functional Description * MASK U ST CIC 1 WOV S MOS 1 ISTA U ST CIC 0 WOV S MOS 0 MRE MIE MOCR MDR MER MDA MAB MOSR INT Figure 24 MONITOR Interrupt Structure 2.3.4 C/I Channel Handling The Command/Indication channel carries real-time status information between the TSMINTaI and another device connected to the IOMa-2. 1) C/I0 channel lies in IOMa-2 channel 0 and access may be arbitrated via the TIC bus access protocol. In this case the arbitration is done in IOMa-2 channel 2. The C/I0 channel is accessed via register CIR0 (received C/I0 data from DD) and register CIX0 (transmitted C/I0 data to DU). The C/I0 code is four bits long. In the receive direction, the code from layer-1 is continuously monitored, with an interrupt being generated any time a change occurs (ISTA.CIC). C/I0 only: a new code must be found in two consecutive IOMa-2 frames to be considered valid and to trigger a C/I code change interrupt status (double last look criterion). In the transmit direction, the code written in CIX0 is continuously transmitted in C/I0. 2) A second C/I channel (called C/I1) lies in IOMa-2 channel 1 and is used to convey real time status information of the on-chip S-transceiver or an external device. The C/I1 channel consists of four or six bits in each direction. The width can be changed from 4 bit to 6 bit by setting bit CIX1.CICW. Data Sheet 49 2001-11-09 PEF 82902 Functional Description In 4-bit mode 6-bits are written whereby the higher 2 bits must be set to "1" and 6-bits are read whereby only the 4 LSBs are used for comparison and interrupt generation (i.e. the higher two bits are ignored). The C/I1 channel is accessed via registers CIR1 and CIX1. The connection of CIR1 and CIX1 to DD and DU, respectively, can be selected by setting bit CI_CR.DPS_CI1. A change in the received C/I1 code is indicated by an interrupt status without double last look criterion. CIC Interrupt Logic Figure 25 shows the CIC interrupt structure. The two corresponding status bits CIC0 and CIC1 are read in CIR0 register. CIC1 can be individually disabled by clearing the enable bit CI1E in the CIX1 register. In this case the occurrence of a code change in CIR1 will not be displayed by CIC1 until the corresponding enable bit has been set to one. Bits CIC0 and CIC1 are cleared by a read of CIR0. An interrupt status is indicated every time a valid new code is loaded in CIR0 or CIR1. The CIR0 is buffered with a FIFO size of two. If a second code change occurs in the received C/I channel 0 before the first one has been read, immediately after reading of CIR0 a new interrupt will be generated and the new code will be stored in CIR0. If several consecutive codes are detected, only the first and the last code are obtained at the first and second register read, respectively. For CIR1 no FIFO is available. The actual code of the received C/I channel 1 is always stored in CIR1. * MASK U ST CIC 1 WOV S MOS 1 ISTA U ST CIC 0 WOV S MOS 0 CI1E CIX1 CIC0 CIC1 CIR0 INT Figure 25 CIC Interrupt Structure Data Sheet 50 2001-11-09 PEF 82902 Functional Description 2.3.5 D-Channel Access Control The upstream D-channel is arbitrated between the S-bus and external HDLC controllers via the TIC bus (S/G, BAC, TBA bits) according to the IOMa-2 Reference Guide1). Further to the implementation in the INTC-Q it is possible, to set the priority (8 or 10) of all HDLC-controllers connected to IOMa-2, which is particularly useful for use of the TSMINTaI together with the UTAH. 2.3.5.1 Application Examples for D-Channel Access Control Figure 26 and Figure 27 show different scenarios for the local D-channel arbitration between the S-bus and the microcontroller. * T-SMINTaI E-Bit D BAC S Arbitr. Prio S/G U D IOM-2 i/f P - i/f *C has access to BAC-Bit and S/G-bit on IOM-2. *Access to TBA generally not required if only one local D-channel source. BAC S/G HDLC HDLC HDLC HDLC C e.g. UTAH; MPC860 IOM-2 Figure 26 D-Channel Arbitration: C with HDLC and Direct Access to TIC Bus 1) The A/B-bit is not supported by the U-transceiver Data Sheet 51 2001-11-09 PEF 82902 Functional Description * T-SMINTaI E-Bit D S Arbitr. Prio BAC S/G U S/G BAC CIX0 CIR0 D C/I Channel Handler IOM-2 i/f P - i/f HDLC HDLC HDLC HDLC IOM-2 C e.g. MC68302 . *C has access to BAC, TBA-Bit and S/G-bit via TIC-Bus Handler *C must poll S/G bit until S/G=0, then transmit D-channel Figure 27 D-Channel Arbitration: C with HDLC and no Access to TIC Bus 2.3.5.2 TIC Bus Handling The TIC bus is implemented to organize the access to the C/I0-channel and to the Dchannel from up to 7 D-channels HDLC controllers. The arbitration mechanism must be activated by setting MODEH.DIM2-0=00x. The arbitration mechanism is implemented in the last octet in IOMa-2 channel 2 of the IOMa-2 interface (see Figure 28). An access request to the TIC bus may either be generated by software (C access to the C/I0-channel via CIX0 register) or by an external D-channel HDLC controller (transmission of an HDLC frame in the D-channel). A software access request to the bus is effected by setting the BAC bit in register CIX0 to '1' (resulting in BAC = '0' on IOMa-2). In the case of an access request by the T-SMINTaI, the Bus Accessed-bit BAC (bit 5 of last octet of CH2 on DU, see Figure 28) is checked for the status "bus free", which is indicated by a logical '1'. If the bus is free, the T-SMINTaI transmits its individual TIC bus address TAD programmed in the CIX0 register (CIX0.TBA2-0). While being transmitted the TIC bus address TAD is compared bit by bit with the value read back on DU. If a sent bit set to '1' is read back as '0' because of the access of an external device with a lower TAD, the T-SMINTaI withdraws immediately from the TIC bus, i.e. the remaining TAD bits are not transmitted. The TIC bus is occupied by the device which sends and reads back its address error-free. If more than one device attempt to seize the bus simultaneously, the one with the lowest address values wins. This one will set BAC=0 on TIC bus and starts D-channel transmission in the same frame. Data Sheet 52 2001-11-09 PEF 82902 Functional Description * MR MX MR MX IC2 MON1 CI1 TAD BAC DU B1 B2 MON0 D CI0 IC1 BAC 2 TAD 1 0 ITD02575.vsd TIC-BUS Address (TAD 2 - 0) Bus Accessed ("1" no TIC-BUS Access) Figure 28 Structure of Last Octet of Ch2 on DU When the TIC bus is seized by the T-SMINTaI, the bus is identified to other devices as occupied via the DU Ch2 Bus Accessed-bit state '0' until the access request is withdrawn. After a successful bus access, the T-SMINTaI is automatically set into a lower priority class, that is, a new bus access cannot be performed until the status "bus free" is indicated in two successive frames. If none of the devices connected to the IOMa-2 interface request access to the D and C/ I0 channels, the TIC bus address 7 will be present. The device with this address will therefore have access, by default, to the D and C/I0 channels. Note: Bit BAC (CIX0 register) should be reset by the C when access is no more requested, to grant other devices access to the D and C/I0 channels. 2.3.5.3 Stop/Go Bit Handling The availability of the DU D channel is indicated in bit 5 "Stop/Go" (S/G) of the last octet in DD channel 2 (Figure 29). The arbitration mechanism must be activated by setting MODEH.DIM2-0=0x1. S/G = 1 : stop S/G = 0 : go The Stop/Go bit is available to other layer-2 devices connected to the IOMa-2 interface to determine if they can access the D channel in upstream direction. Data Sheet 53 2001-11-09 PEF 82902 Functional Description * MR MX MR MX IC2 MON1 CI1 S/G A/B DD B1 B2 MON 0 D CI0 IC1 S/G A/B Stop/Go Available/Blocked ITD09693.vsd Figure 29 Structure of Last Octet of Ch2 on DD 2.3.5.4 D-Channel Arbitration In intelligent NT applications (selected via register S_MODE.MODE2-0) the T-SMINTaI has to share the upstream D-channel with one or more D-channel controllers on the IOMa-2 interface and with all connected TEs on the S interface. The S-transceiver incorporates an elaborate state machine for D-channel priority handling on IOMa-2 (Chapter 2.3.5.5). For the access to the D-channel a similar arbitration mechanism as on the S interface (writing D-bits, reading back E-bits) is performed for all D-channel sources on IOMa-2. Due to this an equal and fair access is guaranteed for all D-channel sources on both the S interface and the IOMa-2 interface. The access to the upstream D-channel is handled via the S/G bit for the HDLC controllers and via E-bit for all connected terminals on S (E-bits are inverted to block the terminals on S). Furthermore, if more than one HDLC source is requesting D-channel access on IOMa-2 the TIC bus mechanism is used (see Chapter 2.3.5.2). The arbiter permanently counts the "1s" in the upstream D-channel on IOMa-2. If the necessary number of "1s" is counted and an HDLC controller on IOMa-2 requests upstream D-channel access (BAC bit is set to 0), the arbiter allows this D-channel controller immediate access and blocks other TEs on S (E-bits are inverted). Similar as on the S-interface the priority for D-channel access on IOMa-2 can be configured to 8 or 10 (S_CMD.DPRIO). The configuration settings of the T-SMINTaI in intelligent NT applications are summarized in Table 12. Data Sheet 54 2001-11-09 PEF 82902 Functional Description * Table 12 T-SMINTaI Configuration Settings in Intelligent NT Applications Configuration Setting S-Transceiver Mode Register: S_MODE.MODE0 = 0 (NT state machine) or S_MODE.MODE0 = 1 (LT-S state machine) S_MODE.MODE1 = 1 S_MODE.MODE2 = 1 Functional Configuration Block Description Layer 1 Select Intelligent NT mode Layer 2 Enable S/G bit and TIC bus evaluation D-channel Mode Register: MODEH.DIM2-0 = 001 Note: For mode selection in the S_MODE register the MODE1/2 bits are used to select intelligent NT mode, MODE0 selects NT or LT-S state machine. With the configuration settings shown above the T-SMINTaI in intelligent NT applications provides for equal access to the D-channel for terminals connected to the S-interface and for D-channel sources on IOMa-2. 2.3.5.5 State Machine of the D-Channel Arbiter Figure 30 gives a simplified view of the state machine of the D-channel arbiter. CNT is the number of '1' on the IOMa-2 D-channel and BAC corresponds to the BAC-bit on IOMa-2. The number n depends on configuration settings (selected priority 8 or 10) and the condition of the previous transmission, i.e. if an abort was seen (n = 8 or 10, respectively) or if the last transmission was successful (n = 9 or 11, respectively). Data Sheet 55 2001-11-09 PEF 82902 Functional Description * RST=0, A/B=0, Mode=0xx IN BAC State S/G DCI OUT BAC = 1 & DCI = 0 (CNT 2 & D=0) & [BAC = 1 or (BAC = 0 & CNT < n)] READY S/G = 1 E = D 1)2) CNT 6 E (BAC=1 & DCI=0) BAC = d.c. DCI = 0 S ACCESS S/G = 1 E = D1) (BAC=0 or DCI=1) & CNT n BAC = d.c. DCI = d.c. LOCAL ACCESS Transmit / Stop Flag S/G = 0 E=D CNT = 6 BAC = 0 or DCI = 1 1) Setting DCI = 1 causes E = D 2) Setting A/B = 0 causes E = D D-Channel_Arbitration.vsd LOCAL ACCESS Wait for Start Flag S/G = 0 E=D Figure 30 State Machine of the D-Channel Arbiter (Simplified View)1) 1. Local D-Channel Controller Transmits Upstream In the initial state ('Ready' state) neither the local D-channel sources nor any of the terminals connected to the S-bus transmit in the D-channel. The T-SMINTaI S-transceiver thus receives BAC = "1" (IOMa-2 DU line) and transmits S/G = "1" (IOMa-2 DD line). The access will then be established according to the following procedure: * Local D-channel source verifies that BAC bit is set to ONE (currently no bus access). * Local D-channel source issues TIC bus address and verifies that no controller with higher priority requests transmission (TIC bus access must always be performed even if no other D-channel sources are connected to IOMa-2). * Local D-channel source issues BAC = "0" to block other sources on IOMa-2 and to announce D-channel access. * T-SMINTaI S-transceiver pulls S/G bit to ZERO ('Local Access' state) as soon as CNT n (see note) to allow sending D-channel data from the entitled source. 1) If the S-transceiver is reset by SRES.RES_S = '1' or disabled by S_CONF0.DIS_TR = '1', then the D-channel arbiter is in state Ready (S/G = '1'), too. The S/G evaluation of the HDLC has to be disabled in this case; otherwise, the HDLC is not able to send data. Data Sheet 56 2001-11-09 PEF 82902 Functional Description T-SMINTaI S-transceiver transmits inverted echo channel (E bits) on the S-bus to block all connected S-bus terminals (E = D). Local D-channel source commences with D data transmission on IOMa-2 as long as it receives S/G = "0". After D-channel data transmission is completed the controller sets the BAC bit to ONE. T-SMINTaI S-transceiver transmits non-inverted echo (E = D). T-SMINTaI S-transceiver pulls S/G bit to ONE ('Ready' state) to block the D-channel controller on IOMa-2. * * * * Note: If right after D-data transmission the D-channel arbiter goes to state 'Ready' and the local D-channel source wants to transmit again, then it may happen that the leading '0' of the start flag is written into the D-channel before the D-channel source recognizes that the S/G bit is pulled to '1' and stops transmission. In order to prevent unintended transitions to state 'S-Access', the additional condition CNT 2 is introduced. As soon as CNT n, the S/G bit is set to '0' and the D-channel source may start transmission again (if TIC bus is occupied). This allows an equal access for D-channel sources on IOMa-2 and on the S interface. 2. Terminal Transmits D-Channel Data Upstream The initial state is identical to that described in the last paragraph. When one of the connected S-bus terminals needs to transmit in the D-channel, access is established according to the following procedure: * S-transceiver recognizes that the D-channel on the S-bus is active via D = '0'. * S-transceiver transfers S-bus D-channel data transparently through to the upstream IOMa-2 bus. 2.3.6 Activation/Deactivation of IOM(R)-2 Interface The deactivation procedure of the IOMa-2 interface is shown in Figure 31. After detecting the code DI (Deactivation Indication) the T-SMINTaI responds by transmitting DC (Deactivation Confirmation) during subsequent frames and stops the timing signals after the fourth frame. The clocks stop at the end of the C/I-code in IOMa-2 channel 0. Data Sheet 57 2001-11-09 PEF 82902 Functional Description * a) FSC DI DIN DR DOUT DR DC DC DC DC DI DI DI DI DI IOM R -2 Interface deactivated Detail see Fig.b b) DCL IOM R -2 Interface deactivated DIN D C/ C/ C/ C/ ITD10292 Figure 31 Deactivation of the IOM(R)-2 Clocks Conditions for Power-Down If none of the following conditions is true, the IOMa-2 interface can be switched off, reducing power consumption to a minimum. * * * * * * * S-transceiver is not in state 'Deactivated' Signal INFO0 on the S-interface Uk0-transceiver is not in state 'Deactivated' Pin DU is low (either at the IOMa-2 interface or via IOM_CR.SPU) External pin EAW External Awake is low Bit MODE 1.CFS = '0' Stop on the correct place in the IOMa-2 frame. DCL must be low during power down (stop on falling edge of DCL) (see Figure 31). A deactivated IOMa-2 can be reactivated by one of the following methods: * Pulling pin DU line low: - directly at the IOMa-2 interface - via the P interface with "Software Power Up" (IOM_CR:SPU bit) * Pulling pin EAW `External Awake` low * Setting `Configuration Select` MODE1:CFS bit = '0' * Level detection at the S-interface Data Sheet 58 2001-11-09 PEF 82902 Functional Description * Activation from the U-interface 2.4 U-Transceiver The statemachine of the U-Transceiver is compatible to the NT state machine in the PEB 8090 documentation [9], but includes some minor changes for simplification and compliance to Ref. [1]. The U-transceiver is configured and controlled via the registers described in Chapter . The U-transceiver is always in IOMa-2 channel 0. 2.4.1 4B3T Frame Structure The 4B3T U-interface performs full duplex data transmission and reception at the Ureference point according to ETSI TS 102 080 and FTZ 1TR 220. It applies the 4B3T block code together with adaptive echo cancelling and equalization. Transmission performance shall be such, that it meets all ETSI and FTZ test loops with margin. The U-interface is designed for data transmission on twisted pair wires in local telephone loops, with basic access to ISDN and a user bit rate of 144 kbit/s. The following information is transmitted over the twisted pair: * Bidirectional: - B1, B2, D data channels - 120 kHz Symbol clock - 1 kHz Frame - Activation - 1 kbit/s Transparent Channel (M symbol), (not implemented) * From LT to NT side: - Power feeding - Deactivation - Remote control of test loops (M symbol) * From NT to LT side: - Indication of monitored code violations (M symbol) Performance Requirements according to FTZ 1 TR 220 (August 1991): On the U-interface, the following transmission ranges are achieved without additional signal regeneration on the loop (bit error rate 10-7): * with noise: 4.2 km on wires of 0.4 mm diameter and 8 km on 0.6 mm wires * without noise: 5 km on wires of 0.4 mm diameter and 10 km on 0.6 mm wires Note: Typical attenuation of FTZ wires of 0.4 mm diameter is about 7dB/km in contrast to ETSI wires of 0.4 mm with about 8dB/km. The transmission ranges can be doubled by inserting a repeater for signal regeneration. Data Sheet 59 2001-11-09 PEF 82902 Functional Description Performance requirements according to ETSI TS 102 080 are met, too. 1 ms frames are transmitted via the U-interface, each consisting of: * 108 symbols: 144 bit scrambled and coded B1 + B2 + D data * 11 symbols: Barker code for both symbol and frame synchronization (not scrambled) * 1 symbol: Ternary maintenance symbol (not scrambled) The 108 user data symbols are split into four equally structured groups. Each group (27 ternary symbols, resp. 36 bits) contains the user data of two IOM(R)-2 frames in the same order (8B + 8B + 2D + 8B + 8B + 2D). Different syncwords are used for each direction: * Downstream from LT to NT * Upstream from NT to LT +++---+--+- -+--+---+++ On the NT side, the transmitted Barker code begins 60 symbols after the received Barker code and vice versa. D1 ... D8 M +, - Ternary 2B + D data of IOM(R)-2 frames 1 ... 8 Maintenance symbol Syncword Data Sheet 60 2001-11-09 PEF 82902 Functional Description Table 13 1 D1 13 D1/2 25 D2 37 D3 49 D4 61 D5 73 D6 85 M 97 D7/8 109 D8 2 D1 14 D1/2 26 D2 38 D3 50 D4 62 D5 74 D6 86 D7 98 D8 110 + Frame Structure A for Downstream Transmission LT to NT 3 D1 15 D1/2 27 D2 39 D3 51 D4 63 D5 75 D6 87 D7 99 D8 111 + 4 D1 16 D2 28 D3 40 D3/4 52 D4 64 D5 76 D6 88 D7 100 D8 112 + 5 D1 17 D2 29 D3 41 D3/4 53 D4 65 D5 77 D6 89 D7 101 D8 113 - 6 D1 18 D2 30 D3 42 D3/4 54 D4 66 D5 78 D6 90 D7 102 D8 114 - 7 D1 19 D2 31 D3 43 D4 55 D5 67 D5/6 79 D6 91 D7 103 D8 115 - 8 D1 20 D2 32 D3 44 D4 56 D5 68 D5/6 80 D6 92 D7 104 D8 116 + 9 D1 21 D2 33 D3 45 D4 57 D5 69 D5/6 81 D6 93 D7 105 D8 117 - 10 D1 22 D2 34 D3 46 D4 58 D5 70 D6 82 D7 94 D7 106 D8 118 - 11 D1 23 D2 35 D3 47 D4 59 D5 71 D6 83 D7 95 D7/8 107 D8 119 + 12 D1 24 D2 36 D3 48 D4 60 D5 72 D6 84 D7 96 D7/8 108 D8 120 - Data Sheet 61 2001-11-09 PEF 82902 Functional Description * Table 14 1 U1 13 U1/2 25 M 37 U3 49 U4 61 U4 73 U5 85 U6 97 U7 109 U8 U1 ... U8 M +, 2 U1 14 U1/2 26 U2 38 U3 50 - 62 U4 74 U5 86 U6 98 U7 110 U8 Frame Structure B for Upstream Transmission NT to LT 3 U1 15 U1/2 27 U2 39 U3 51 + 63 U4 75 U5 87 U6 99 U7 111 U8 4 U1 16 U2 28 U2 40 U3 52 - 64 U4 76 U5 88 U6 100 U7 112 U8 5 U1 17 U2 29 U3 41 U3/4 53 - 65 U4 77 U5 89 U6 101 U7 113 U8 6 U1 18 U2 30 U3 42 U3/4 54 + 66 U4 78 U5 90 U6 102 U7 114 U8 7 U1 19 U2 31 U3 43 U3/4 55 - 67 U5 79 U5/6 91 U6 103 U7 115 U8 8 U1 20 U2 32 U3 44 U4 56 - 68 U5 80 U5/6 92 U6 104 U7 116 U8 9 U1 21 U2 33 U3 45 U4 57 - 69 U5 81 U5/6 93 U6 105 U7 117 U8 10 U1 22 U2 34 U3 46 U4 58 + 70 U5 82 U6 94 U7 106 U7/8 118 U8 11 U1 23 U2 35 U3 47 U4 59 + 71 U5 83 U6 95 U7 107 U7/8 119 U8 12 U1 24 U2 36 U3 48 U4 60 + 72 U5 84 U6 96 U7 108 U7/8 120 U8 Ternary 2B + D data of IOM(R)-2 frames 1... 8 Maintenance symbol Syncword Data Sheet 62 2001-11-09 PEF 82902 Functional Description 2.4.2 Maintenance Channel The 4B3T frame structure provides a 1 kbit/s M(aintenance)-channel for the transfer of remote loopback commands and error indications. Loopback Commands The LT station uses the M-channel to request remote loopbacks. Loopback commands are coded with a series of '0' and '+' symbols. * A continuous series of '+' requests for loopback 2 activation in the NT * A continuous series of '0' requests for deactivation of any loopback The NT station reacts as soon as the pattern has been detected in 8 consecutive symbols. Error Indications The NT U-transceiver reports line code violations via the M-channel to the exchange by setting one M-Bit to '+' polarity. Transparent Messages The exchange of Transparent Messages via the Transparent Channel is not supported by the T-SMINTaI. 2.4.3 Coding from Binary to Ternary Data Each 4 bit block of binary data is coded into 3 ternary symbols of MMS 43 block code according to Table 15. The number of the next column to be used, is given at the right hand side of each block. The left hand signal elements in the table (both ternary and binary) are transmitted first. * Table 15 t 0 0 0 0 1 1 1 0 1 1 0 0 1 0 0 1 0 1 1 1 0 MMS 43 Coding Table S1 t 1 1 0 0 1 0 1 0 - - + + 0 + - 0 + - 0 + - + + 0 0 - - + 1 1 1 1 1 1 2 S2 t 0 - - + + 0 + - 0 + - 0 + - + + 0 0 - - + 2 2 2 2 2 2 3 S3 t 0 - - + + 0 + - 0 + - 0 + - + + 0 0 - - + 3 3 3 3 3 3 4 S4 t 0 - - + + 0 - - 0 + - 0 + - + + 0 0 - - - 4 4 4 4 4 4 1 Data Sheet 63 2001-11-09 PEF 82902 Functional Description Table 15 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 0 0 0 MMS 43 Coding Table S1 1 1 0 0 0 1 0 1 0 0 0 + - + + + 0 + 0 + 0 + + + 0 + + + 0 0 + - 0 + + + 2 2 2 2 2 3 3 3 4 S2 0 0 + - + 0 0 - - 0 + 0 + + 0 - 0 + + 0 0 + - - 0 0 - 3 3 3 3 3 1 1 1 1 S3 0 0 + - + 0 0 - - 0 + 0 - - 0 - 0 + + 0 0 + - - 0 0 - 4 4 4 2 2 2 2 2 2 S4 - - 0 - + 0 0 - - - 0 - - - 0 - 0 + 0 - - + - - 0 0 - 2 2 2 3 3 3 3 3 3 2.4.4 Decoding from Ternary to Binary Data Decoding is done in the reverse manner of coding. The received blocks of 3 ternary symbols are converted into blocks of 4 bits. The decoding algorithm is given in Table 16. As in the encoding table, the left hand symbol of each block (both binary and ternary) is the first bit and the right hand is the last. If a ternary block "0 0 0" is received, it is decoded to binary "0 0 0 0". This pattern usually occurs only during deactivation. * Table 16 0 0 0, 0-+ +-0 0 0 +, -+0 0 + +, - + +, -0+ + 0 0, + - +, + + -, +0- + + +, Data Sheet 4B3T Decoding Table Ternary Block + 0 +, 0-0 0 0 0 --0 -00 --+ 0-- --- +-- -+- 64 Binary Block 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 2001-11-09 0 0 0 0 0 1 1 1 1 1 PEF 82902 Functional Description Table 16 0 + 0, 0+- + + 0, 00- 4B3T Decoding Table -0- 1 1 1 1 1 1 0 1 1 1 0 1 2.4.4.1 Monitoring of Code Violations The running digital sum monitor (RDSM) computes the running digital sum from the received ternary symbols by adding the polarity of the received user data (+ 1, 0, -1). At the end of each block, the running digital sum is supposed to reflect the number of the next column in Table 15. A code violation has occurred if the running digital sum is less than one or more than four at the end of a ternary block, or if the ternary block 0 0 0 (three user symbols with zero polarity) is found in the received data. If at the end of a ternary block no error was found, the running digital sum retains its current value. If the counter value is greater than 4, it is set to 4 at the beginning of the next ternary block, if its value is 0 or less, it is set to one. So after a code violation has been detected, the RDSM synchronizes itself within a period depending on the received data pattern. Note there are some transmission errors which do not cause a code violation. 2.4.4.2 Block Error Counter (RDS Error Counter) The T-SMINTaI provides a block error counter. This feature allows monitoring the transmission quality on the U-interface. On the NT side a block error is given, if a U-frame with at least one code violation has been detected (near-end block error). In the following frame the NT transmits a positive M-symbol upstream. On the LT side a block error is given, if a U-frame with at least one code violation has been detected (near-end block error) or a positive M-symbol has been received from the NT (far-end block error). The current status of the block error counter can be retrieved by the system interface. When the block error counter is read (register RDS), it is automatically reset. The counter is enabled in all states listed in Table 17 and reset in all other states. The counter is saturated at its maximum value (255). Table 17 Active States SBC Sychronizing Wait for INFO U4H Transparent Data Sheet 65 2001-11-09 PEF 82902 Functional Description Note that every frame with a detected code violation causes about 10 to 20 binary bit errors on average. So a bit error rate of 10-7 in both directions is equivalent to 2 detected frame errors within 1000 s in the LT (1 frame error detected in the NT and transmitted via M-symbol). 2.4.5 Scrambler Scrambler / Descrambler The binary transmit data from the IOM(R)-2 interface is scrambled with a polynomial of 23 bits, before it is sent to the 4B3T coder. The scrambler polynomial is:: z Descrambler The received data (after decoding from ternary to binary) is multiplied with a polynomial of 23 bits in order to recover the original data before it is forwarded to the IOM(R)-2 interface.The descrambler is self synchronized after 23 symbols. The descrambler polynomial is:: z - 23 - 23 +z - 18 +1 +z -5 +1 The scrambling / descrambling process is controlled fully by the T-SMINTaI. Hence, no influence can be taken by the user. 2.4.6 Command/Indication Codes Both commands and indications depend on the data direction. Table 18 presents all defined C/I codes. A new command or indication will be recognized as valid after it has been detected in two successive IOM(R)-2 frames (double last-look criterion). Note: Unconditional C/I-commands must be applied for at least 4 IOM(R)-2 frames for reliable recognition by the U-transceiver. Indications are strictly state orientated. Refer to the state diagrams in the following sections for commands and indications applicable in various states. Table 18 Code 0000 0001 0010 C/I Codes IN TIM - - OUT DR - - Data Sheet 66 2001-11-09 PEF 82902 Functional Description 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1) LTD - SSP DT - AR reserved1) - - AI RES - DI - RSY - - - AR - ARL - AI - AIL DC C/I code `1010` must not be input to the U-transceiver. * AI AIL AR ARL DT DC Activation Indication Activation Indication Loop 2 Activation Request Activation Request Local Loop Data Through Mode Deactivation Confirmation DI DR LTD RES RSY SSP TIM Deactivation Indication. Deactivation Request LT Disable Reset Resynchronization Indication Send-Single-Pulses Timing Request 2.4.7 2.4.7.1 State Machine for Activation and Deactivation State Machine Notation The following state diagram describes all the actions/reactions resulting from any command or detected signal and resulting from the various operating modes. The states with its inputs and outputs are interpreted as shown below: Data Sheet 67 2001-11-09 PEF 82902 Functional Description IN Transmitted U-Signal State Name C/I Channel Indication (DOUT) OUT SM_expl.emf Figure 32 State Diagram Example Each state has one or more transitions to other states. These transitions depend on certain conditions which are noted next to the transition lines. These conditions are the only possibility to leave a state. If more conditions have to be fulfilled together, they are put into parentheses with an AND operator (&). If more than one condition leads to the same transition, they are put into parentheses with an OR operator (|). The meaning of a condition may be inverted by the NOT operator (/). Only the described states and transitions exist. At some transitions, an internal timer is started. The start of a timer is indicated by TxS ('x' is the timer number). Transitions that are caused if a timer has expired are labelled by TxE. Some conditions lead to the same target state. To reduce the number of lines and the complexity of the figures, a state named "ANY STATE" acts on behalf of all state. The state machines are designed to cope with all ISDN devices with IOM(R)-2 standard interfaces. Undefined situations are excluded. In any case, the involved devices will enter defined conditions as soon as the line is deactivated. 2.4.7.2 Awake Protocol For the awake process two signals are defined' U1W' and 'U2W'. Depending on the call direction (up-, downstream) U1W and U2W are interpreted as awake or acknowledge signals (see figures below). Data Sheet 68 2001-11-09 PEF 82902 Functional Description * 12 ms 7 ms LT INFO U2W 2.133 ms INFO U2 (A) 13 ms NT INFO U1W 2.133 ms ITD06385.vsd INFO U1A Figure 33 Awake Procedure initiated by the LT * 6 ms 7 ms LT INFO U2W 2.133 ms INFO U2 (A) 13 ms NT INFO U1W 2.133 ms INFO U1A ITD06386.v sd Figure 34 Awake Procedure initiated by the NT Acting as Calling Station After sending the awake signal, the awaking U-transceiver waits for the acknowledge. After 12 ms, the awake signal is repeated, if no acknowledge has been recognized. If an acknowledge signal has been recognized, the U-transceiver waits for its possible repetition (in case of previous coincidence of two awake signals). If no repetition was detected, the U-transceiver starts transmitting U2 with a delay of 7 ms. If such a repetition is detected, the U-transceiver interprets it as an awake signal and behaves like a device awoken by the far end. Data Sheet 69 2001-11-09 PEF 82902 Functional Description Acknowledging a Wake-Up Call If a deactivated device detects an awake signal on U, an acknowledge signal is sent out. After that, the U-transceiver waits for a possible repetition of the awake signal (in case the acknowledge hasn't been recognized). If no repetition is found, the awoken U-transceiver starts sending U2 after 7 ms from detecting the awake signal. If a repeated awake signal is found, the procedure in the awoken U-transceiver starts again. Data Sheet 70 2001-11-09 PEF 82902 Functional Description 2.4.7.3 * NT State Machine (IEC-T / NTC-T Compatible) AWR U0 IOM Awaked DC AR T6S U1W Start Awaking Uk0 RSY T6S T6E U0 Awake Signal Sent RSY AWR T13S T13E U0 Ack. Sent / Received RSY AWT AWR (DI & T05E) T12S U1A Synchronizing RSY U2 T05S DT U1 SBC Synchronizing AR / ARL AI U0 LOF (U0 & T12E) T05S U0 Pend. Deactivation DR DI SP / U0 Test DR SSP or LTD ANY STATE RES DI U0 LOF U0 Reset DR T13S U1W Sending Awake-Ack. RSY T13S AWT T6S T05S T05S T05E U0 Deactivating DC AWR TIM AR U0 Deactivated DC U0, DA AWR DI U3 Wait for Info U4H AR / ARL U4H U0 U5 Transparent AI / AIL U0 LOF U0 Loss of Framing RSY NT_SM_4B3T_cust.emf Figure 35 NT State Machine (IEC-T/NTC-T Compatible) Note: The test modes `Data Through` (DT) and `Send Single Pulses` (SSP) are invoked via C/I codes 'DT' and 'SSP' according to Table 18. Setting SRES.RES_U to `1` forces the U-transceiver into test mode `Quiet Mode` (QM), i.e. the U-transceiver is hardware reset. Data Sheet 71 2001-11-09 PEF 82902 Functional Description * Table 19 1. Differences to the former NT-SM of the IEC-T/NTC-T Change Comment simplifies SM implementation No. State/ Signal State 'Deact. split into 3 states Request Rec.' - 'Pend. Deactivation 1' - 'Reset' State - 'Test' State State 'Loss of Framing' new inserted, results in different behavior in state 'Transparent', no return to normal transmission possible after detection of LOF new inserted renamed to state 'Deactivated' renamed to state 'Transparent' Name Duration 2. compliance to ETSI TS 102 080, corresponds to state NT1.10 3. 4. 5. C/I-code LTD State 'Power Down' State 'Data Transmission' Timer variables introduced for consistency reasons to 2B1Q 6. see Table 20 2.4.7.4 Inputs to the U-Transceiver C/I-Commands AI Activation Indication The downstream device issues this indication to announce that layer 1 is available. The U-transceiver in turn informs the LT side by transmitting U3. Activation Request The U-transceiver is requested to start the activation process (if not already done) by sending the wake-up signal U1W. Deactivation Indication This indication is used during a deactivation procedure to inform the Utransceiver that it may enter the 'Deactivated' (power-down) state. Data Through Test Mode This unconditional command is used for test purposes only and forces the Utransceiver into state 'Transparent'. AR DI DT Data Sheet 72 2001-11-09 PEF 82902 Functional Description LTD LT Disable This unconditional command forces the U-transceiver to state 'Test', where it transmits U0. No further action is initiated. Reset Unconditional command which resets the U-transceiver. Send Single Pulses Unconditional command which requests the transmission of single pulses on the U-interface. Timing The U-transceiver is requested to enter state 'IOM Awaked'. RES SSP TIM U-Interface Events U0 U0 detected U0 is recognized after 120 symbols (1ms) with zero level in a row. Detection may last up to 2 ms. U2 detected The U-transceiver detects U2 if continuous binary 0`s are found after descrambling and LOF = 0 for at least 8 subsequent U-frames. U2 is detected after 8 to 9 ms. U4H detected U4H is recognized, if the U-transceiver detects 16 subsequent binary 1's after descrambling. Awake signal (U2W) detected Awake signal (U1W) has been sent out Loss of Framing on U-interface Timer ended, the started timer has expired U2 U4H AWR AWT LOF TxE Timers The start of timers is indicated by TxS, the expiry by TxE. The following table shows which timers are used. * Table 20 Timer T05 T6 0.5 6 Timers Duration (ms) Function C/I code recognition Supervises U1W repetition State Pend. Deactivation, Deactivating Start Awaking Uk0 Data Sheet 73 2001-11-09 PEF 82902 Functional Description Table 20 Timer T12 12 Timers (cont'd) Duration (ms) Function Prevents the U-transceiver in state Synchronizing from immediate transition to state 'Pend. Deactivation' if U0 is detected Supervises U2W repetition State Synchronizing T13 13 Ack. sent / received Sending awake-ack. 2.4.7.5 Outputs of the U-Transceiver Below the signals and indications are summarized that are issued on IOM(R)-2 (C/I indications) and on the U-interface (predefined U-signals). C/I Indications AI Activation Indication The U-transceiver has established transparency of transmission. The downstream device is requested to establish layer-1 functionality. Activation Indication Loop-back The U-transceiver has established transparency of transmission. The downstream device is requested to establish a loopback #2. Activation Request The downstream device is requested to start the activation procedure. Activation Request Loop-back The U-transceiver has detected a loop-back 2 command in the M-channel and has established transparency of transmission in the direction IOM(R) to Uinterface. The downstream device is requested to start the activation procedure and to establish a loopback #2. Deactivation Confirmation Idle code on the IOM(R)-2 interface. Deactivation Request The U-transceiver has detected a deactivation request command from the LTside for a complete deactivation. The downstream device is requested to start the deactivation procedure. Resynchronizing Indication RSY informs the downstream device that the U-transceiver is not synchronous. AIL AR ARL DC DR RSY Data Sheet 74 2001-11-09 PEF 82902 Functional Description Signals on U-Interface The signals U0, U1W, U1A, U1, U3, U5 and SP are transmitted on the U-interface.They are defined in Table 25. Signals on IOM(R)-2 The Data (B+B+D) is set to all '1's in all states besides the states listed in Table 17. Dependence of Outputs The M-symbol output in states with valid M-symbol output its value is set according to Table 21 *: Table 21 RDS Error M Symbol Output not detected '0' detected '+' M Symbol Output * Table 22 Input Signal Output on Uk0 in State Test C/I-Code SSP applied SP all other except C/I-Code 'DI' U0 Signal Output on Uk0 * Table 23 C/I-Code Output SBC Synchronizing AR ARL Wait for Info U4H AR ARL Transparent AI AIL Loopback Command not received received 2.4.7.6 NT-States In this section each state is described with its function. Acknowledge Sent / Receive After having sent the awake signal, the U-transceiver has received the acknowledge wake tone. If being awoken the U-transceiver has sent the acknowledge. In both cases the U-transceiver waits for possible repetition or time-out. Data Sheet 75 2001-11-09 PEF 82902 Functional Description Awake Signal Sent The NT has sent out the awake signal U1W and waits now for a response. If the LT does not react in time timer T6 expires and the NT repeats its wake-up call. Deactivated Only in "Deactivated" state the device may enter the power-down mode. Deactivating State Deactivating assures that the C/I-channel code DC is issued four times before entering the 'Deactivated' state. IOM(R) Awaked The U-transceiver is deactivated, but may not enter the power-down mode. Loss of Framing This state is entered on loss of framing (LOF). No signal is transmitted on the U-interface. A receiver-reset is performed by. Note that there is no return to the 'Transparent' state that has been possible before in the former IEC-T based state machine. Pending Deactivation The U-transceiver has received U0. The U-transceiver remains at least 0.5ms in this state before it accepts DI. SBC Synchronizing The NT is now synchronized and indicates this by AR/ARL towards the downstream device. The NT waits for the acknowledge 'AI' from the downstream device. Sending Awake-Ack. On the receipt of the awake signal U2W the U-transceiver responds with the transmission of U1W. Start Awaking Uk0 On the receipt of AR in the C/I-channel the U-transceiver sends the awake signal U1W to start an activation. Data Sheet 76 2001-11-09 PEF 82902 Functional Description Synchronizing After the successful awake procedure the U-transceiver trains its receiver coefficients until it is able to detect the signals U2. Reset In state 'Reset' a software-reset is performed. Test State "Test" is entered when the unconditional commands C/I=SSP is applied. The test signal SSP is issued as long as pin SSP is active or C/I=SSP is applied. Transparent The transmission line is fully activated. User data is transparently exchanged by U4/U5. Transparent state is entered in the case of a loopback 2. The downstream device is informed by C/I code AI that the transparent state has been reached Note that in contrast to the former IEC-T state machine there is no resynchronization mechanism. Once loss of framing (LOF) has been detected a deactivation is initiated. Wait for Info U4H The NT is synchronized and waits now for the permission (U4H) to go to the 'Transparent' state. 2.4.8 U-Transceiver Interrupt Structure The U-Interrupt Status register (ISTAU) contains the interrupt sources of the UTransceiver (Figure 36). Each source can be masked by setting the corresponding bit of the U-Interrupt Mask register (MASKU) to '1'. Such masked interrupt status bits are not indicated when ISTAU is read and do not generate an interrupt request. The ISTAU register is cleared on read access. The interrupt sources of the ISTAU register (UCIR, RDS, 1ms) need not be evaluated. When at time t1 an interrupt source generates an interrupt, all further interrupts are collected. Reading the ISTAU register clears all interrupts set before t1, even if masked. All interrupts, which are flagged after t1 remain active. After the ISTAU read access, the next unmasked interrupt will generate the next interrupt at time t2. After t2 it is possible to reprogram the MASKU register, so that all interrupts, which arrived between t1 and t2 are accessible. Data Sheet 77 2001-11-09 PEF 82902 Functional Description *I UCIR 7 0 0 0 0 C/I C/I C/I 0 C/I ISTAU 7 0 CI RDS 0 0 0 0 0 1ms MASKU 1 CI RDS 1 1 1 1 1ms ISTA U S ... ... ... ... ... ... MASK intstruct_4b3t.emf INT Figure 36 Interrupt Structure U-Transceiver Data Sheet 78 2001-11-09 PEF 82902 Functional Description 2.5 S-Transceiver The S-Transceiver offers the NT and LT-S mode state machines described in the User's Manual V3.4 [8]. The S-transceiver lies in IOMa-2 channel 1 (default) and is configured and controlled via the registers described in Chapter 4.5. The state machine is set to NT mode (default) but can be set to LT-S mode via register programming. The TE mode (S-transceiver TE mode, U-transceiver disabled) is not supported. 2.5.1 Line Coding, Frame Structure Line Coding The following figure illustrates the line code. A binary ONE is represented by no line signal. Binary ZEROs are coded with alternating positive and negative pulses with two exceptions: For the required frame structure a code violation is indicated by two consecutive pulses of the same polarity. These two pulses can be adjacent or separated by binary ONEs. In bus configurations a binary ZERO always overwrites a binary ONE. * 011 code violation Figure 37 S/T -Interface Line Code Frame Structure Each S/T frame consists of 48 bits at a nominal bit rate of 192 kbit/s. For user data (B1+B2+D) the frame structure applies to a data rate of 144 kbit/s (see Figure 37). In the direction TE NT the frame is transmitted with a two bit offset. For details on the framing rules please refer to ITU I.430 section 6.3. The following figure illustrates the standard frame structure for both directions (NT TE and TE NT) with all framing and maintenance bits. Data Sheet 79 2001-11-09 PEF 82902 Functional Description * Figure 38 -F - L. -D -E - FA -N - B1 - B2 -A -S -M Frame Structure at Reference Points S and T (ITU I.430) Framing Bit D.C. Balancing Bit D-Channel Data Bit D-Channel Echo Bit Auxiliary Framing Bit B1-Channel Data Bit B2-Channel Data Bit Activation Bit S-Channel Data Bit Multiframing Bit F = (0b) identifies new frame (always positive pulse, always code violation) L. = (0b) number of binary ZEROs sent after the last L. bit was odd Signaling data specified by user E = D received E-bit is equal to transmitted D-bit See section 6.3 in ITU I.430 N = FA User data User data A = (0b) INFO 2 transmitted A = (1b) INFO 4 transmitted S1 channel data (see note below) M = (1b) Start of new multi-frame Note: The ITU I.430 standard specifies S1 - S5 for optional use. Data Sheet 80 2001-11-09 PEF 82902 Functional Description 2.5.2 S/Q Channels, Multiframing According to ITU recommendation I.430 a multi-frame provides extra layer-1 capacity in the TE-to-NT direction through the use of an extra channel between the TE and NT (Qchannel). The Q bits are defined to be the bits in the FA bit position. In the NT-to-TE direction the S-channel bits are used for information transmission. The S- and Q-channels are accessed via C by reading/writing the SQR or SQX bits in the S/Q channel registers (SQRR, SQXR). Table 24 shows the S and Q bit positions within the multi-frame. Table 24 S/Q-Bit Position Identification and Multi-Frame Structure NT-to-TE NT-to-TE FA Bit Position M Bit ONE ZERO ZERO ZERO ZERO ONE ZERO ZERO ZERO ZERO ONE ZERO ZERO ZERO ZERO ONE ZERO ZERO ZERO ZERO ONE ZERO ONE ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ONE ZERO NT-to-TE S Bit S11 S21 S31 S41 S51 S12 S22 S32 S42 S52 S13 S23 S33 S43 S53 S14 S24 S34 S44 S54 S11 S21 TE-to-NT FA Bit Position Q1 ZERO ZERO ZERO ZERO Q2 ZERO ZERO ZERO ZERO Q3 ZERO ZERO ZERO ZERO Q4 ZERO ZERO ZERO ZERO Q1 ZERO Frame Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 The S-transceiver starts multiframing if SQXR1.MFEN is set. After multi-frame synchronization has been established in the TE, the Q data will be inserted at the upstream (TE NT) FA bit position by the TE in each 5th S/T frame, the Data Sheet 81 2001-11-09 PEF 82902 Functional Description S data will be inserted at the downstream (NT TE) S bit position in each 5th S/T frame (see Table 24). Access to S2-S5-channel is not supported. Interrupt Handling for Multi-Framing To trigger the microcontroller for a multi-frame access an interrupt can be generated once per multi-frame (SQW) or if the received Q-channel have changed (SQC). In both cases the microcontroller has access to the multiframe within the duration of one multiframe (5 ms). The start of a multiframe can not be synchronized to an external signal. 2.5.3 Data Transfer between IOMa-2 and S0 In the state G3 (Activated) or if the internal layer-1 statemachine is disabled and XINF of register S_CMD is programmed to '011' the B1, B2 and D bits are transferred transparently from the S/T to the IOMa-2 interface and vice versa. In all other states '1's are transmitted to the IOMa-2 interface. Note: In intelligent NT or intelligent LT-S mode the D-channel access can be blocked by the IOMa-2 D-channel handler. 2.5.4 Loopback 2 C/I commands ARL and AIL close the analog loop as close to the S-interface as possible. ETSI refers to this loop under 'loopback 2'. ETSI requires, that B1, B2 and D channels have the same propagation delay when being looped back. The D-channel Echo bit is set to bin. 0 during an analog loopback (i.e. loopback 2). The loop is transparent. Note: After C/I-code AIL has been recognized by the S-transceiver, zeros are looped back in the B and D-channels (DU) for four frames. 2.5.5 Control of S-Transceiver / State Machine The S-transceiver activation/ deactivation can be controlled by an internal statemachine via the IOMa-2 C/I-channel or by software via the C interface directly. In the default state the internal layer-1 statemachine of the S-transceiver is used. By setting the L1SW bit in the S_CONF0 register the internal statemachine can be disabled and the layer-1 transmit commands, which are normally generated by the internal statemachine can be written directly into the S_CMD register or the received status read out from the S_STA register, respectively. The S-transceiver layer-1 control flow is shown in Figure 39. Data Sheet 82 2001-11-09 PEF 82902 Functional Description * Disable internal Statemachine (S_CONF.L1SW) C/I Command IOM-2 C/I Indication Layer-1 State Machine Transmit Command Register INFO Transmitter for Transmitter (S_CMD) Receive Status Register INFO Receiver of Receiver (S_STA) Layer-1 Control C-Interface macro_14 Figure 39 S-Transceiver Control The state diagram notation is given in Figure 40. The information contained in the state diagrams are: - - - - - - state name Signal received from the line interface (INFO) Signal transmitted to the line interface (INFO) C/I code received (commands) C/I code transmitted (indications) transition criteria The transition criteria are grouped into: - C/I commands - Signals received from the line interface (INFOs) - Reset Data Sheet 83 2001-11-09 PEF 82902 Functional Description * OUT IN IOM-2 Interface C/I code Ind. Cmd. S tate Unconditional Transition S/T Interface INFO ix ir macro_17.vsd Figure 40 State Diagram Notation As can be seen from the transition criteria, combinations of multiple conditions are possible as well. A "" stands for a logical AND combination. And a "+" indicates a logical OR combination. Test Signals * 2 kHz Single Pulses (TM1) One pulse with a width of one bit period per frame with alternating polarity. * 96 kHz Continuous Pulses (TM2) Continuous pulses with a pulse width of one bit period. Note: The test signals TM1 and TM2 are invoked via C/I codes `TM1` and `TM2` according to Chapter 2.5.5.1. External Layer-1 Statemachine Instead of using the integrated layer-1 statemachine it is also possible to implement the layer-1 statemachine completely in software. The internal layer-1 statemachine can be disabled by setting the L1SW bit in the S_CONF0 register to '1'. The transmitter is completely under control of the microcontroller via register S_CMD. The status of the receiver is stored in register S_STA and has to be evaluated by the microcontroller. This register is updated continuously. If not masked a RIC interrupt is generated by any change of the register contents. The interrupt is cleared after a read access to this register. Reset States After an active signal on the reset pin RST the S-transceiver state machine is in the reset state. Data Sheet 84 2001-11-09 PEF 82902 Functional Description C/I Codes in Reset State In the reset state the C/I code 0000 (TIM) is issued. This state is entered either after a hardware reset (RST) or with the C/I code RES. C/I Codes in Deactivated State If the S-transceiver is in state `Deactivated` and receives i0, the C/I code 0000 (TIM) is issued until expiration of the 8 ms timer. Otherwise, the C/I code 1111 (DI) is issued. 2.5.5.1 C/I Codes The table below presents all defined C/I0 codes. A command needs to be applied continuously until the desired action has been initiated. Indications are strictly state orientated. Refer to the state diagrams in the following sections for commands and indications applicable in various states. * LT-S Code 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Cmd DR RES TM1 TM2 - - - - AR - ARL - - - - DC Ind TIM - - - RSY - - - AR - - CVR AI - - DI NT Cmd DR RES TM1 TM2 RSY - - - AR - ARL - AI - AIL DC Ind TIM - - - RSY - - - AR - - CVR AI - - DI Data Sheet 85 2001-11-09 PEF 82902 Functional Description Receive Infos on S/T I0 I0 I3 I3 INFO 0 detected Level detected (signal different to I0) INFO 3 detected Any INFO other than INFO 3 Transmit Infos on S/T I0 I2 I4 It INFO 0 INFO 2 INFO 4 Send Single Pulses (TM1). Send Continuous Pulses (TM2). Data Sheet 86 2001-11-09 PEF 82902 Functional Description 2.5.5.2 * State Machine NT Mode RST TIM RES Reset i0 RES Any State * DC DI ARD1) DR ARD1) TIM DR DR TM1 TIM TM2 Test Mode i it DC * TM1 TM2 Any State G4 Pend. Deact. i0 i0 (i0*16ms)+32ms DR G4 Wait for DR i0 * DC DI TIM DR DC G1 Deactivated ARD1) i0 i0 (i0*8ms) AR DC DR G1 i0 Detected i0 * ARD1) AR ARD G2 Pend. Act i2 i3 i3 AID RSY ARD G2 Lost Framing S/T i2 RSY DR RSY RSY G3 Lost Framing U i2 * i3 i3*ARD AI i3*ARD1) i3*AID2) RSY AID2) ARD1) AID2) i3*AID2) ARD1) AI AID DR ARD DR DR G2 Wait for AID i2 i3 G3 Activated RSY i4 i3 1): 2): ARD = AR or ARL AID =AI or AIL statem_nt_s.vsd Figure 41 State Machine NT Mode Note: State 'Test Mode' can be entered from any state except from state 'Test Mode' itself, i.e. C/I-code 'TMi' must not be followed by C/I-code 'TMj' directly. Data Sheet 87 2001-11-09 PEF 82902 Functional Description G1 Deactivated The S-transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. Activation is possible from the S/T interface and from the IOMa-2 interface. G1 I0 Detected An INFO 0 is detected on the S/T-interface, translated to an "Activation Request" indication in the C/I channel. The S-transceiver is waiting for an AR command, which normally indicates that the transmission line upstream is synchronized. G2 Pending Activation As a result of the ARD command, an INFO 2 is sent on the S/T-interface. INFO 3 is not yet received. In case of ARL command, loop 2 is closed. G2 wait for AID INFO 3 was received, INFO 2 continues to be transmitted while the S-transceiver waits for a "switch-through" command AID from the device upstream. G3 Activated INFO 4 is sent on the S/T-interface as a result of the "switch through" command AID: the B and D-channels are transparent. On the command AIL, loop 2 is closed. G2 Lost Framing S/T This state is reached when the transceiver has lost synchronism in the state G3 activated. G3 Lost Framing U On receiving an RSY command which usually indicates that synchronization has been lost on the transmission line, the S-transceiver transmits INFO 2. G4 Pending Deactivation This state is triggered by a deactivation request DR, and is an unstable state. Indication DI (state "G4 wait for DR") is issued by the transceiver when: either INFO0 is received for a duration of 16 ms or an internal timer of 32 ms expires. Data Sheet 88 2001-11-09 PEF 82902 Functional Description G4 wait for DR Final state after a deactivation request. The S-transceiver remains in this state until DC is issued. Unconditional States Test Mode TM1 Send Single Pulses Test Mode TM2 Send Continuous Pulses C/I Commands * Command Deactivation Request Reset Abbr. DR RES Code 0000 0001 Remark Deactivation Request. Initiates a complete deactivation by transmitting INFO 0. Reset of state machine. Transmission of Info0. No reaction to incoming infos. RES is an unconditional command. Send Single Pulses. Send Continuous Pulses. Receiver is not synchronous Activation Request. This command is used to start an activation. Activation request loop. The transceiver is requested to operate an analog loop-back close to the S/T-interface. Activation Indication. Synchronous receiver, i.e. activation completed. Send Single Pulses Send Continuous Pulses Receiver not Synchronous Activation Request Activation Request Loop Activation Indication TM1 TM2 RSY AR ARL 0010 0011 0100 1000 1010 AI 1100 Data Sheet 89 2001-11-09 PEF 82902 Functional Description Command Activation Indication Loop Deactivation Confirmation Abbr. AIL DC Code 1110 1111 Remark Activation Indication Loop Deactivation Confirmation. Transfers the transceiver into a deactivated state in which it can be activated from a terminal (detection of INFO 0 enabled). Remark Interim indication during deactivation procedure. Receiver is not synchronous. INFO 0 received from terminal. Activation proceeds. Illegal code violation received. This function has to be enabled in S_CONF0.EN_ICV. Synchronous receiver, i.e. activation completed. Timer (32 ms) expired or INFO 0 received for a duration of 16 ms after deactivation request. Indication Timing Receiver not Synchronous Activation Request Illegal Code Ciolation Activation Indication Deactivation Indication Abbr. TIM RSY AR CVR AI DI Code 0000 0100 1000 1011 1100 1111 Data Sheet 90 2001-11-09 PEF 82902 Functional Description 2.5.5.3 * State Machine LT-S Mode RST TIM RES Reset i0 RES Any State * DC DI ARD1) DR ARD 1) TIM DR G4 Pend. Deact. i0 i0 (i0*16ms)+32ms DR DR TM1 TIM TM2 Test Mode i it DC * TM1 TM2 Any State G4 Wait for DR i0 * DC DI DC TIM G1 Deactivated i0 i0 (i0*8ms)+ARD1) DC AR ARD G2 Pend. Act. i2 i3 i3 DR DR DC RSY ARD G2 Lost Framing S/T i2 i3 DR i3 AI i3 DC ARD G3 Activated i4 i3 DR 1) : ARD = AR or ARL statem_lts_s.vsd Figure 42 State Machine LT-S Mode Note: State 'Test Mode' can be entered from any state except from state 'Test Mode' itself, i.e. C/I-code 'TMi' must not be followed by C/I-code 'TMj 'directly. Data Sheet 91 2001-11-09 PEF 82902 Functional Description G1 deactivated The S-transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. Activation is possible from the S/T interface and from the IOMa-2 interface. G2 pending activation As a result of an INFO 0 detected on the S/T line or an ARD command, the S-transceiver begins transmitting INFO 2 and waits for reception of INFO 3. The timer to supervise reception of INFO 3 is to be implemented in software. In case of an ARL command, loop 2 is closed. G3 activated Normal state where INFO 4 is transmitted to the S/T-interface. The transceiver remains in this state as long as neither a deactivation nor a test mode is requested, nor the receiver looses synchronism. When receiver synchronism is lost, INFO 2 is sent automatically. After reception of INFO 3, the transmitter keeps on sending INFO 4. G2 lost framing This state is reached when the S-transceiver has lost synchronism in the state G3 activated. G4 pending deactivation This state is triggered by a deactivation request DR. It is an unstable state: indication DI (state "G4 wait for DR.") is issued by the S-transceiver when: either INFO0 is received for a duration of 16 ms, or an internal timer of 32 ms expires. G4 wait for DR Final state after a deactivation request. The transceiver remains in this state until DC is issued. Unconditional States Test mode - TM1 Single alternating pulses are sent on the S/T-interface. Data Sheet 92 2001-11-09 PEF 82902 Functional Description Test mode - TM2 Continuous alternating pulses are sent on the S/T-interface. * Command Deactivation Request Abbr. DR Code 0000 Remark DR - Deactivation Request. Initiates a complete deactivation by transmitting INFO 0. Reset of state machine. Transmission of Info0. No reaction to incoming infos. RES is an unconditional command. Send Single Pulses. Send Continuous Pulses. Activation Request. This command is used to start an activation. Activation request loop. The transceiver is requested to operate an analog loop-back close to the S/T-interface. Deactivation Confirmation. Transfers the transceiver into a deactivated state in which it can be activated from a terminal (detection of INFO 0 enabled). Remark Interim indication during activation procedure in G1. Receiver is not synchronous INFO 0 received from terminal. Activation proceeds. Illegal code violation received. This function has to be enabled in S_CONF0.EN_ICV. Synchronous receiver, i.e. activation completed. Timer (32 ms) expired or INFO 0 received for a duration of 16 ms after deactivation request Reset RES 0001 Send Single Pulses Send Continuous Pulses Activation Request Activation Request Loop Deactivation Confirmation TM1 TM2 AR ARL 0010 0011 1000 1010 DC 1111 Indication Timing Receiver not Synchronous Activation Request Illegal Code Ciolation Activation Indication Deactivation Indication Abbr. TIM RSY AR CVR AI DI Code 0000 0100 1000 1011 1100 1111 Data Sheet 93 2001-11-09 PEF 82902 Functional Description 2.5.6 S-Transceiver Enable / Disable The layer-1 part of the S-transceiver can be enabled/disabled with the two bits S_CONF0.DIS_TR and S_CONF2.DIS_TX. If DIS_TX='1' the transmit buffers are disabled. The receiver will monitor for incoming data in this configuration. By default the transmitter is disabled (DIS_TX = '1'). If the transceiver is disabled (DIS_TR = '1', DIS_TX = don't care) all layer-1 functions are disabled including the level detection circuit of the receiver. In this case the power consumption of the S-transceiver is reduced to a minimum. Data Sheet 94 2001-11-09 PEF 82902 Functional Description 2.5.7 * Interrupt Structure S-Transceiver Level Detect S_STA 7 RINF 0 FECV 0 FSYN 0 0 LD SQRR 7 MSYN MFEN 0 0 SQR1 SQR2 SQR3 0 SQR4 SQXR 7 0 MFEN 0 0 SQX1 SQX2 SQX3 0 SQX4 7 ISTAS 0 0 0 0 LD RIC SQC 0 SQW MASKS 1 1 1 1 LD RIC SQC SQW S 7 ISTA MASK Reserved 0 INT interr.vsd Figure 43 Interrupt Structure S-Transceiver Data Sheet 95 2001-11-09 PEF 82902 Operational Description 3 3.1 3.1.1 Operational Description Layer 1 Activation/Deactivation Generation of 4B3T Signal Elements For control and monitoring purposes of the activation/deactivation progress the following signal elements are defined by TS 102 080 and FTZ 1 TR 220. Table 25 U0 4B3T Signal Elements No signal or deactivation signal that is used in both directions. Downstream, it requests the NT to deactivate. Upstream, the NT acknowledges by U0 that it is deactivated. U1W, U2W Awake or awake acknowledge signal used in the awake procedure of the U-interface. U2 The LT sends U2 to enable the own echo canceller to adapt the coefficients. By the Barker code the NT at the other end is enabled to synchronize. The detection of U2 is used by the NT as a criterion for synchronization. The M-channel on U may be used to transfer loop commands. While the NT-RP is synchronizing on the received signal, the LT-RP sends out U2A to enable its echo canceller to adapt the coefficients, but sending no Barker code it inhibits the NT to synchronize on the still asynchronous signal. Due to proceeding synchronization, the U-frame may jump from time to time. U2A can not be detected in the NT at the far end. U1A is similar to U1 but without framing information. While the NT synchronizes on the received signal, it sends out U1A to enable its echo canceller to adapt its coefficients, but sends no Barker code to prevent the LT from synchronizing on the still asynchronous signal. Due to proceeding synchronization, the U-frame may jump from time to time. U1A can not be detected by the far-end LT. When synchronized, the NT sends the Barker code and the LT may synchronize itself. U1 indicates additionally that a terminal equipment has not yet activated. Upon receiving U1 the LT indicates the synchronized state by C/I 'UAI' to layer-2. Usually during activation, no U1 signal is detected in the LT because the TE is activated first and U1 changes to U3 before being detected. The M-channel on U may be used to transfer code error indications and 1 kbit/s transparent data. Data Sheet 96 2001-11-09 U2A U1A U1 PEF 82902 Operational Description Table 25 U3 4B3T Signal Elements (cont'd) U3 indicates that the whole link to the TE is synchronous in both directions. On detecting U3 the LT requests the NT by U4H to establish a fully transparent connection. The M-channel on U may be used to transfer code error indications and 1 kbit/s transparent data. U4H U4H requires the NT to go to the 'Transparent' state. On detecting U4H the NT stops sending signal U3 and informs the S-transceiver or a layer-2 device via the system interface. The M-channel on U may be used to transfer loop commands and 1 kbit/s transparent data. U4 U5 U4 transports operational data on B and D channels. The M-channel on U may be used to transfer loop commands and 1 kbit/s transparent data. U5 transports operational data on B and D channels. The M-channel on U may be used to transfer code error indications and 1 kbit/s transparent data. The T-SMINTI sends periodically single pulses once per millisecond on the U-interface. The test mode can be used for pulse mask measurements. Loss of frame, generated by flywheel Generation of the 4B3T Signal Elements symbols (ternary) sync word (tern ary) M sym bol (tern ary) n/a binary data before scram bling n/a SP LOF Table 26 Upstream Downstream (NT to LT) (LT to NT) U1W U2W Resulting in a tone of: Frequency: 7.5 kHz Duration: 2.13 ms when sending the wakeup tone is finished, signal AWT is set and ternary "0" is sent scrambled binary data scrambled binary data scrambled binary data 16 times + n/a +++++ ++---- ---- U1A U1 U3 U2A U2 0 yes yes 0 yes yes 0 0 1 Data Sheet 97 2001-11-09 PEF 82902 Operational Description Table 26 Generation of the 4B3T Signal Elements (cont'd) U4H Duration: 1 ms (warranted by state machine) Binary data from the digital interface Ternary continuous "0" single pulses 0 yes yes 1 U5 U0 SP U4 U0 SP yes 0 yes 0 n/a BBD n/a n/a once "+", n/a 119 times "0" (repeatedl y) Table 27 S/T-Interface Signals Signals from TE to NT INFO 0 INFO 1 No signal. A continuous signal with the following pattern: Positive ZERO, negative ZERO, six ONEs. Signals from NT to TE INFO 0 No signal. INFO 2 Frame with all bits of B, D, and D-echo channels set to binary ZERO. Bit A set to binary ZERO. N and L bits set according to the normal coding rules. INFO 3 Synchronized frames with operational data on B and D-channels. INFO 4 Frames with operational data on B, D, and D-echo channels. Bit A set to binary ONE. Data Sheet 98 2001-11-09 PEF 82902 Operational Description 3.1.2 * Complete Activation Initiated by Exchange IOMa-2 TE S/T-Reference Point NT U-Reference Point LT IOMa-2 DC DI INFO 0 INFO 0 S0 DC DI C DC DI Uk0 U0 U0 DC DI AR RSY U2W U0 U1W U0 U1A U2 AR AR INFO 2 AR INFO 3 AI AI U3 U4H AI AI INFO 4 AI AR8/10 SBCX-X or IPAC-X DFE-T actbyLT_TSMINT.vsd AR AR U1 UAI UAI U5 U4 1 ms AI Figure 44 Activation Initiated by Exchange Note: The LT starts issuing signal U2 before the NT starts issuing U1A. This chronological order is not displayed for clarification. Data Sheet 99 2001-11-09 PEF 82902 Operational Description 3.1.3 * Complete Activation Initiated by TE IOMa-2 TE S/T-Reference Point NT U-Reference Point LT IOMa-2 DC DI TIM PU AR8/10 INFO 0 INFO 0 S0 DC DI DC DI Uk0 U0 U0 DC DI INFO 1 8ms TIM AR TIM AR U1W RSY U0 U2W U0 AR U1A U2 AR RSY AR INFO 2 INFO 0 INFO 3 AI AI AR U1 UAI U3 AI U4H U5 U4 UAI AI INFO 4 AI 1 ms AI SBCX-X or IPAC-X DFE-T actbyTE_TSMINT.vsd Figure 45 Activation Initiated by TE Note: The LT starts issuing signal U2 before the NT starts issuing U1A. This chronological order is not displayed for clarification. Data Sheet 100 2001-11-09 PEF 82902 Operational Description 3.1.4 * Complete Activation Initiated by NT IOMa-2 TE S/T-Reference Point NT U-Reference Point LT IOMa-2 DC DI INFO 0 INFO 0 S0 DC DI C DC DI Uk0 U0 U0 DC DI TIM AR U1W RSY U0 U2W U0 AR U1A U2 AR INFO 2 AR INFO 3 AI AR AI AR U1 UAI U3 AI U4H U5 U4 UAI AI INFO 4 AI 1 ms AI AR 8/10 SBCX-X or IPAC-X DFE-T actbyNT_TSMINT.vsd Figure 46 Activation Initiated by NT Note: The LT starts issuing signal U2 before the NT starts issuing U1A. This chronological order is not displayed for clarification. Data Sheet 101 2001-11-09 PEF 82902 Operational Description 3.1.5 * Complete Deactivation IOMa-2 TE S/T-Reference Point NT U-Reference Point LT IOMa-2 AI AR INFO 4 INFO 3 S0 AI AI AI AI Uk0 U4 U5 AR AI DR U0 DR RSY DR DI DC INFO 0 INFO 0 DI DC DI DC SBCX-X or IPAC-X DR TIM U0 DEAC DI DC DFE-T deac_TSMINT.vsd Figure 47 Complete Deactivation Data Sheet 102 2001-11-09 PEF 82902 Operational Description 3.1.6 * Loop 2 NT IOM -2 AI AR8/10 a TE S/T-Reference Point INFO 4 INFO 3 S0 AI AI AI AI Uk0 U-Reference Point U4 U5 LT IOMa-2 AR AI 2B+D U4 (M-Bit= 8x '+' ) AIL AIL 2B+D U4 (M-Bit= 8x '0' ) AI AI AR2 AR 2B+D SBCX-X or IPAC-X DFE-T act_loop2_TSMINT.vsd Figure 48 Loop 2 Note: Closing/resolving loop 2 may provoke the S-transceiver to resynchronize. In this case, the following C/I-codes are exchanged immediately on reception of AIL/AI, respectively: DU: 'RSY', DU: 'AI', DD: 'AIL'/'AI'. Data Sheet 103 2001-11-09 PEF 82902 Operational Description 3.2 Layer 1 Loopbacks Test loopbacks are specified by the national PTTs in order to facilitate the location of defect systems. Four different loopbacks are defined. The position of each loopback is illustrated in Figure 49. * U S-BUS Loop 2 S-Transceiver U IOM(R)-2 Loop 2 U-Transceiver IOM(R)-2 Loop 1 A U-Transceiver U-Transceiver Loop 1 U-Transceiver NT IOM(R)-2 Loop 2 Layer-1 Controller U-Transceiver IOM(R)-2 Repeater (optional) Exchange IOM-2 Loop 3 Layer-1 Controller U-Transceiver PBX or TE loop_2b1q.emf Figure 49 Test Loopbacks Loopbacks #1, #1A and #2 are controlled by the exchange. Loopback #3 is controlled locally on the remote side. All four loopback types are transparent. This means all bits that are looped back will also be passed onwards in the normal manner. Only the data looped back internally is processed; signals on the receive pins are ignored. The propagation delay of actually looped B and D channels data must be identical in all loopbacks. Besides the remote controlled loopback stimulation via the M channel, the T-SMINTaI features also direct loopback control via its register set. 3.2.1 Analog Loop-Back S-Transceiver The T-SMINTaI provides test and diagnostic functions for the S/T interface: The internal local loop (internal Loop A) is activated by a C/I command ARL or by setting the bit LP_A (Loop Analog) in the S_CMD register if the layer-1 statemachine is disabled. The transmit data of the transmitter is looped back internally to the receiver. The data of the IOMa-2 input B- and D-channels are looped back to the output B- and D-channels. Data Sheet 104 2001-11-09 PEF 82902 Operational Description The S/T interface level detector is enabled, i.e. if a level is detected this will be reported by the Resynchronization Indication (RSY) but the loop function is not affected. Depending on the DIS_TX bit in the S_CONF2 register the internal local loop can be transparent or non transparent to the S/T line. The external local loop (external Loop A) is activated in the same way as the internal local loop described above. Additionally the EXLP bit in the S_CONF0 register has to be programmed and the loop has to be closed externally as described in Figure 50. The S/T interface level detector is disabled. * SX1 100 SX2 SCOUT-S(X) SR1 100 SR2 Figure 50 External Loop at the S/T-Interface 3.2.2 Loopback No.2 For loopback #2 several alternatives exist. Both the type of loopback and the location may vary. The following loopback types belong to the loopback-#2 category: * * * * complete loopback (B1,B2,D), in the U-transceiver complete loopback (B1,B2,D), in a downstream device B1-channel loopback, always performed in the U-transceiver B2-channel loopback, always performed in the U-transceiver All loop variations performed by the U-transceiver are closed as near to the internal IOMa-2 interface as possible. Normally loopback #2 is controlled by the exchange. The maintenance channel is used for this purpose. Data Sheet 105 2001-11-09 PEF 82902 Operational Description 3.2.2.1 Complete Loopback When receiving the request for a complete loopback, the U transceiver passes it on to the downstream device, e.g. the S-bus transceiver. This is achieved by issuing the C/Icode AIL in the "Transparent" state or C/I = ARL in states different than "Transparent" * S-Transceiver 2B+D loop request U-Transceiver 2 B+D U loop command Controller loop command lp2bymon8.v sd Figure 51 Complete Loopback Options in NT-Mode The complete loopback is either opened under control of the exchange via the maintenance channel or locally controlled via the C. No reset is required for loopback #2. The line stays active and is ready for data transmission. 3.2.2.2 Loopback No.2 - Single Channel Loopbacks Single channel loopbacks are always performed directly in the U-Transceiver. No difference between the B1-channel and the B2-channel loopback control procedure exists. 3.2.3 Local Loopbacks Featured By the LOOP Register Besides the standardized remote loopbacks the U-transceiver features additional local loopbacks for enhanced test and debugging facilities. The local loopbacks that are featured by register LOOP are shown in Figure 52. They are closed in the U-transceiver itself and can be activated regardless of the current operational status. By the LOOP register it can be configured whether the loopback is closed only for the B1 and/or B2 or for 2B+D channels and whether the loopback is closed towards the internal IOMa-2 interface or towards the U-Interface. By default the loopbacks are set to transparent mode. In transparent mode the data is both passed on and looped back. In non-transparent mode the data is not forwarded but substituted by 1s (idle code). Data Sheet 106 2001-11-09 PEF 82902 Operational Description * LOOP.LB1=1 LOOP.LB2=1 LOOP.LBBD= 1 & LOOP.U/IOM= 1 LOOP.LB1=1 LOOP.LB2=1 LOOP.LBBD= 1 & LOOP.U/IOM= 0 Analog Part Line Interface Unit Digital Part DAC Echo Canceller ADC PDM Filter 2B1Q Scrambler UFraming Tx-FIFO + Timing Recovery A G C Rx-FIFO Equalizer 2B1Q DeScrambler U-DeFraming IOM-2 Interface Bandgap, Bias, Refer. U-Transceiver Activation/ Deactivation Controller loopreg.emf Figure 52 Loopbacks Featured by Register LOOP Data Sheet 107 2001-11-09 PEF 82902 Operational Description 3.3 3.3.1 * External Circuitry Power Supply Blocking Recommendation The following blocking circuitry is suggested. VDDa_UR VDDa_UX VDDa_SR VDDa_SX VDDD VDDD 100nF 1) 3.3V 100nF 1) 100nF 1) 100nF 1) 100nF 1) 100nF 1) 1F VSSD VSSD VSSa_SX VSSa_SR VSSa_UX VSSa_UR 1) GND These capacitors should be located as near to the pins as possible blocking_caps_Smint.vsd Figure 53 Power Supply Blocking 3.3.2 U-Transceiver The T-SMINTI is connected to the twisted pair via a transformer. Figure 54 shows the recommended external circuitry with external hybrid. The recommended protection circuitry is not displayed. Data Sheet 108 2001-11-09 PEF 82902 Operational Description * AOUT R3 RT BIN R4 RCOMP n C >1 Loop AIN R4 RCOMP R3 BOUT RT extcirc_U_Q2_exthybrid.emf Figure 54 External Circuitry U-Transceiver with External Hybrid U-Transformer Parameters The following table lists parameters of typical U-transformers. Table 28 U-Transformer Parameters Symbol Value n LH 1 : 1.6 7.5 120 30 0.9 1.8 mH H pF Unit U-Transformer Parameters U-Transformer ratio; Device side : Line side Main inductanc of windings on the line side Leakage inductance of windings on the line side LS Coupling capacitance between the windings on CK the device side and the windings on the line side DC resistance of the windings on device side DC resistance of the windings on line side RB RL Data Sheet 109 2001-11-09 PEF 82902 Operational Description Resistors of the External Hybrid R3, R4 and RT R3 = 1.75 k R4 = 1.0 k RT = 25 Resistors RCOMP / RT * Optional use of trafos with non negligible resistance RB, RL requires compensation resistors RCOMP depending on RB and RL: n2 x (2RCOMP + RB) + RL = 20 * Compliance with Return Loss Measurements: n2 x (2RCOMP + 2RT + Rout + RB) + RL = 150 RB, RL : see Table 28 ROUT : see Table 35 15nF Capacitor To achieve optimum performance the 15nF capacitor should be MKT. A Ceramic capacitor is not recommended. Tolerances * Rs: 1% * C = 15nF: 10-20% * LH = 7.5mH: 10% (2) (1) 3.3.3 S-Transceiver In order to comply to the physical requirements of ITU recommendation I.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (EMC), the S-transceiver needs some additional circuitry. Data Sheet 110 2001-11-09 PEF 82902 Operational Description S-Transformer Parameters The following Table 29 lists parameters of a typical S-transformer: Table 29 S-Transformer Parameters Symbol Value n LH 2:1 typ. 30 typ. <3 typ. <100 typ. 2.4 typ. 1.4 mH H pF Unit Transformer Parameters Transformer ratio; Device side : Line side Main inductance of windings on the line side Leakage inductance of windings on the line side LS Coupling capacitance between the windings on CK the device side and the windings on the line side DC resistance of the windings on device side DC resistance of the windings on line side Transmitter RB RL The transmitter requires external resistors Rstx = 47 in order to adjust the output voltage to the pulse mask (nominal 750 mV according to ITU I.430, to be tested with the test mode "TM1") on the one hand and in order to meet the output impedance of minimum 20 on the other hand (to be tested with the testmode 'Continuous Pulses') on the other hand. Note: The resistance of the S-transformer must be taken into account when dimensioning the external resistors Rstx. If the transmit path contains additional components (e.g. a choke), then the resistance of these additional components must be taken into account, too. Data Sheet 111 2001-11-09 PEF 82902 Operational Description * 47 SX1 20...40 VDD 2:1 GND SX2 47 DC Point extcirc_S.vsd Figure 55 Receiver External Circuitry S-Interface Transmitter The receiver of the S-transceiver is symmetrical. 10 k overall resistance are recommended in each receive path. It is preferable to split the resistance into two resistors for each line. This allows to place a high resistance between the transformer and the diode protection circuit (required to pass 96 kHz input impedance test of ITU I.430 [6] and ETS 300012-1). The remaining resistance (1.8 k) protects the Stransceiver itself from input current peaks. * 1k8 SR1 VDD 8k2 2:1 GND SR2 1k8 8k2 DC Point extcirc_S.vsd Figure 56 Data Sheet External Circuitry S-Interface Receiver 112 2001-11-09 PEF 82902 Operational Description 3.3.4 * Oscillator Circuitry Figure 57 illustrates the recommended oscillator circuit. CLD XOUT 15.36 MHz XIN CLD Figure 57 Table 30 Parameter Frequency Crystal Oscillator Crystal Parameters Symbol f CL R1 C0 Limit Values 15.36 +/-60 20 20 7 fundamental Unit MHz ppm pF pF Frequency calibration tolerance Load capacitance Max. resonance resistance Max. shunt capacitance Oscillator mode External Components and Parasitics The load capacitance CL is computed from the external capacitances CLD, the parasitic capacitances CPar (pin and PCB capacitances to ground and VDD) and the stray capacitance CIO between XIN and XOUT: ( C LD + C Par ) x ( C LD + C Par ) C L = ------------------------------------------------------------------------ + C IO ( C LD + C Par ) + ( C LD + C Par ) For a specific crystal the total load capacitance is predefined, so the equation must be solved for the external capacitances CLD, which is usually the only variable to be determined by the circuit designer. Typical values for the capacitances CLD connected to the crystal are 22 - 33 pF. 3.3.5 General - low power LEDs Data Sheet 113 2001-11-09 PEF 82902 Register Description 4 4.1 Register Description Address Space 7DH U-Transceiver 60H 5CH 40H 3CH Monitor Handler IOMa-2 Handler (CDA, TSDP, CR, STI) Interrupt, Global Registers S-Transceiver CI-Register MODEH-Register reserved 30H 2EH 22H 00H Figure 58 Address Space 4.2 Interrupts Special events in the T-SMINTaI are indicated by means of a single interrupt output, which requests the host to read status information from the T-SMINTaI or transfer data from/to the T-SMINTaI. Since only one INT request output is provided, the cause of an interrupt must be determined by the host reading the interrupt status registers of the T-SMINTaI. The structure of the interrupt status registers is shown in Figure 59. Data Sheet 114 2001-11-09 PEF 82902 Register Description MASKU 1 CI RDS 1 1 1 1 1ms MASK U ST CIC 1 WOV S MOS 1 ISTA U ST CIC 0 WOV S MOS 0 ISTAU 0 CI RDS 0 0 0 0 1ms MSTI STOV21 STOV20 STOV11 STOV10 STI21 STI20 STI11 STI10 STI STOV21 STOV20 STOV11 STOV10 STI21 STI20 STI11 STI10 MASKS LD RIC SQC SQW MRE MIE MOCR ASTI ACK21 ACK20 ACK11 ACK10 ISTAS LD RIC SQC SQW MDR MER MDA MAB MOSR CI1E CIX1 CIC0 CIC1 CIR0 INT Figure 59 T-SMINTaI Interrupt Status Registers After the T-SMINTaI has requested an interrupt by setting its INT pin to low, the host must read first the T-SMINTaI interrupt status register (ISTA) in the associated interrupt service routine. The INT pin of the T-SMINTaI remains active until all interrupt sources are cleared. Therefore, it is possible that the INT pin is still active when the interrupt service routine is finished. Each interrupt indication of the interrupt status registers can selectively be masked by setting the respective bit in the MASK register. For some interrupt controllers or hosts it might be necessary to generate a new edge on the interrupt line to recognize pending interrupts. This can be done by masking all interrupts at the end of the interrupt service routine (writing FFH into the MASK register) and writing back the old mask to the MASK register. Data Sheet 115 2001-11-09 PEF 82902 Register Description 4.3 Register Summary r(0) = reserved, implemented as zero CI Handler Name 7 6 5 4 3 2 1 0 ADDR R/W RES 00H -21H DIM2 DIM1 DIM0 22H 23H2DH CIC1 TBA1 S/G TBA0 CICW CICW BAS BAC CI1E CI1E 2EH 2EH 2FH 2FH R W R W F3H FEH FEH FEH R/W C0H reserved MODEH 1 1 0 r(0) 0 reserved CIR0 CIX0 CIR1 CIX1 CODR0 CODX0 CODR1 CODX1 CIC0 TBA2 Data Sheet 116 2001-11-09 PEF 82902 Register Description S-Transceiver Name S_ CONF0 7 DIS_ TR 6 BUS 5 EN_ ICV 4 0 3 L1SW 2 0 1 EXLP 0 0 ADDR R/W RES 30H 31H 0 0 0 32H 33H 34H 35H 35H 36H-37H RIC RIC SQC SQC MODE2-0 SQW SQW 38H 39H 3AH 3BH R 00H R/W 80H R 00H R/W 40H reserved S_ CONF2 S_STA S_CMD SQRR SQXR DIS_ TX RINF XINF MSYN MFEN 0 MFEN 0 0 0 0 0 0 0 ICV DPRIO 0 0 0 1 SQR1 SQX1 FSYN PD SQR2 SQX2 0 LP_A SQR3 SQX3 LD 0 SQR4 SQX4 R/W 08H R W 00H 00H reserved ISTAS MASKS S_ MODE 0 1 0 x 1 0 x 1 0 x 1 0 LD LD DCH_ INH R/W FFH R/W 02H reserved Data Sheet 117 2001-11-09 PEF 82902 Register Description Interrupt, General Configuration Name ISTA MASK MODE1 MODE2 ID SRES 7 U U 6 ST ST MCLK LED2 0 0 LED1 0 0 RES_ CI/TIC 0 5 CIC CIC CDS LEDC 4 0 1 WTC1 3 WOV WOV WTC2 0 2 S S CFS 0 1 MOS MOS RSS2 0 0 1 RSS1 ADDR R/W RES 3CH 3CH 3DH 3EH 3FH RES_ S RES_ U 3FH R W 00H FFH R/W 04H R/W 00H R W 20H 00H AMOD PPSDX DESIGN 0 0 Data Sheet 118 2001-11-09 PEF 82902 Register Description IOM Handler (Timeslot, Data Port Selection, CDA Data and CDA Control Register) Name CDA10 CDA11 CDA20 CDA21 CDA_ TSDP10 CDA_ TSDP11 CDA_ TSDP20 CDA_ TSDP21 DPS 0 7 6 5 4 3 2 1 0 ADDR R/W RES 40H 41H 42H 43H 44H 45H 46H 47H 48H4BH TSS 4CH R/W 84H R/W FFH R/W FFH R/W FFH R/W FFH R/W 00H R/W 01H R/W 80H R/W 81H Controller Data Access Register Controller Data Access Register Controller Data Access Register Controller Data Access Register 0 0 TSS DPS 0 0 0 TSS DPS 0 0 0 TSS DPS 0 0 0 TSS reserved S_ TSDP_ B1 S_ TSDP_ B2 CDA1_ CR CDA2_ CR DPS 0 0 0 DPS 0 0 0 TSS 4DH R/W 85H 0 0 EN_ TBM EN_ TBM EN_I1 EN_I0 EN_O1 EN_O0 SWAP 4EH 4FH R/W 00H R/W 00H 0 0 EN_I1 EN_I0 EN_O1 EN_O0 SWAP Data Sheet 119 2001-11-09 PEF 82902 Register Description IOM Handler (Control Registers, Synchronous Transfer Interrupt Control) Name 7 6 5 4 3 2 1 0 ADDR R/W RES 50H EN_ B2X 1 EN_ B1X 0 D_CS 51H 52H 53H 54H 55H DIS_ IOM 56H 57H 58H 58H 59H 5AH5BH R/W FFH R/W 04H R/W 40H R/W 00H R/W 00H R/W 08H R R FFH 00H 00H reserved S_CR 1 CI_CS EN_ D 0 EN_ B2R 0 EN_ B1R 0 CI_CR DPS_ CI1 DPS EN_ CI1 EN_ MON MON_ CR SDS1_ CR SDS2_ CR IOM_CR 0 0 0 0 MCS ENS_ TSS ENS_ TSS SPU ENS_ ENS_ TSS+1 TSS+3 ENS_ ENS_ TSS+1 TSS+3 0 0 0 TSS 0 TSS TIC_ DIS EN_ BCL 0 DIS_ OD MCDA STI MCDA21 STOV 21 0 STOV 20 0 MCDA20 STOV 11 0 STOV 10 0 MCDA11 STI 21 ACK 21 STI 21 STI 20 ACK 20 STI 20 MCDA10 STI 11 ACK 11 STI 11 STI 10 ACK 10 STI 10 ASTI W MSTI STOV 21 STOV 20 STOV 11 STOV 10 R/W FFH reserved Data Sheet 120 2001-11-09 PEF 82902 Register Description MONITOR Handler Name MOR MOX MOSR MOCR MSTA MCONF MDR MRE 0 0 MER MRC 0 0 7 6 5 4 3 2 1 0 ADDR R/W RES 5CH 5CH 0 0 0 0 0 0 TOUT TOUT 5DH 5EH 5FH 5FH R W R FFH FFH 00H MONITOR Receive Data MONITOR Transmit Data MDA MIE 0 0 MAB MXC 0 0 0 0 0 0 0 0 MAC 0 R/W 00H R W 00H 00H Data Sheet 121 2001-11-09 PEF 82902 Register Description U-Transceiver Name OPMODE 7 0 6 UCI 5 0 4 0 3 0 2 0 1 0 0 0 ADDR R/W RES 60H 61H6CH C/I code output C/I code input 6DH 6EH 6FH LBBD LB2 LB1 70H 71H 72H 73H79H 0 1 0 1 1 ms 1 ms 7AH 7BH 7CH 7DH R 3EH R 00H R 00H R*/W 08H R W 00H 01H R*/W 00H reserved UCIR UCIW 0 0 0 0 0 0 0 0 reserved LOOP 0 0 TRANS U/IOM 1 reserved RDS Block Error Counter Value reserved ISTAU MASKU 0 1 CI CI RDS RDS 0 1 0 1 R*/W FFH reserved FW_ VERSION FW Version Number Note: Registers, which are denoted as `reserved`, may not be accessed by the C, neither for read nor for write operations. 4.3.1 Reset of U-Transceiver Functions During Deactivation or with C/I-Code RESET The following U-transceiver register is reset upon transition to state 'Deactivating' or with software reset: Data Sheet 122 2001-11-09 PEF 82902 Register Description * Table 31 Register LOOP Reset of U-Transceiver Functions During Deactivation or with C/ICode RESET Affected Bits/ Comment only the bits LBBD, LB2 and LB1 are reset 4.3.2 * Mode Register Evaluation Timing Table 32 lists registers, which are evaluated and executed immediately. Table 32 Register OPMODE LOOP MASKU Mode Register with Immediate Evaluation and Execution Affected Bits UCI complete register complete register Comment Data Sheet 123 2001-11-09 PEF 82902 Register Description 4.4 4.4.1 MODEH Detailed C/I Registers MODEH - Mode Register IOM-2 read/write Address: 22H Value after reset: C0H 7 1 1 0 r(0) 0 DIM2 DIM1 0 DIM0 DIM2-0 Digital Interface Modes These bits define the characteristics of the IOM Data Ports (DU, DD). The DIM0 bit enables/disables the stop/go bit (S/G) evaluation. The DIM1 bit enables/disables the TIC bus access. The effect of the individual DIM bits is as follows: 0-0 = 0-1 = 00- = 01- = 1xx = Stop/go bit evaluation is disabled Stop/go bit evaluation is enabled TIC bus access is enabled TIC bus access is disabled Reserved 4.4.2 CIR0 CIR0 - Command/Indication Receive 0 read Address: 2EH Value after reset: F3H 7 CODR0 CIC0 CIC1 S/G 0 BAS Data Sheet 124 2001-11-09 PEF 82902 Register Description CODR0 C/I0 Code Receive Value of the received Command/Indication code. A C/I-code is loaded in CODR0 only after being the same in two consecutive IOM-frames and the previous code has been read from CIR0. CIC0 C/I0 Code Change 0= 1= No change in the received Command/Indication code has been recognized A change in the received Command/Indication code has been recognized. This bit is set only when a new code is detected in two consecutive IOM-frames. It is reset by a read of CIR0. CIC1 C/I1 Code Change 0= 1= No change in the received Command/Indication code has been recognized A change in the received Command/Indication code in IOM-channel 1 has been recognized. This bit is set when a new code is detected in one IOM-frame. It is reset by a read of CIR0. S/G Stop/Go Bit Monitoring Indicates the availability of the upstream D-channel; 0= 1= Go Stop BAS Bus Access Status Indicates the state of the TIC-bus: 0= 1= the T-SMINTaI itself occupies the D- and C/I-channel another device occupies the D- and C/I-channel Note: The CODR0 bits are updated every time a new C/I-code is detected in two consecutive IOM-frames. If several consecutive valid new codes are detected and CIR0 is not read, only the first and the last C/I code are made available in CIR0 at the first and second read of that register. Data Sheet 125 2001-11-09 PEF 82902 Register Description 4.4.3 CIX0 CIX0 - Command/Indication Transmit 0 write Address: 2EH Value after reset: FEH 7 CODX0 TBA2 TBA1 TBA0 0 BAC CODX0 C/I0-Code Transmit Code to be transmitted in the C/I-channel 0. The code is only transmitted if the TIC bus is occupied, otherwise "1s" are transmitted. TBA2-0 TIC Bus Address Defines the individual address for the T-SMINTaI on the IOM bus. This address is used to access the C/I- and D-channel on the IOM interface. Note: If only one device is liable to transmit in the C/I- and D-channels of the IOM it should always be given the address value `7'. BAC Bus Access Control Only valid if the TIC-bus feature is enabled (MODE:DIM2-0). 0= 1= inactive The T-SMINTaI will try to access the TIC-bus to occupy the C/Ichannel even if no D-channel frame has to be transmitted. It should be reset when the access has been completed to grant a similar access to other devices transmitting in that IOM-channel. Note: Access is always granted by default to the T-SMINTaI with TIC-Bus Address (TBA2-0, CIX0 register) `7', which has the lowest priority in a bus configuration. 4.4.4 CIR1 CIR1 - Command/Indication Receive 1 read Address: 2FH Value after reset: FEH Data Sheet 126 2001-11-09 PEF 82902 Register Description 7 CODR1 CICW 0 CI1E CODR1 CICW C/I1-Code Receive C/I-Channel Width Contains the read back value from CIX1 register (see below) 0= 1= 4 bit C/I1 channel width 6 bit C/I1 channel width CI1E C/I1-channel Interrupt Enable Contains the read back value from CIX1 register (see below) 0= 1= Interrupt generation ISTA.CIC of CIR0.CIC1is masked Interrupt generation ISTA.CIC of CIR0.CIC1 is enabled 4.4.5 CIX1 CIX1 - Command/Indication Transmit 1 write Address: 2FH Value after reset: FEH 7 CODX1 CICW 0 CI1E CODX1 C/I1-Code Transmit Bits 5-0 of C/I-channel 1 CICW C/I-Channel Width 0= 1= 4 bit C/I1 channel width 6 bit C/I1 channel width Data Sheet 127 2001-11-09 PEF 82902 Register Description The C/I1 handler always reads and writes 6-bit values but if 4-bit is selected, the higher two bits are ignored for interrupt generation. However, in write direction the full CODX1 code is transmitted, i.e. the host must write the higher two bits to "1". CI1E C/I1-channel Interrupt Enable 0= 1= Interrupt generation ISTA.CIC of CIR0.CIC1is masked Interrupt generation ISTA.CIC of CIR0.CIC1 is enabled 4.5 4.5.1 S_ CONF0 Detailed S-Transceiver Registers S_CONF0 - S-Transceiver Configuration Register 0 read/write Address: 30H Value after reset: 40H 7 DIS_TR BUS EN_ ICV 0 L1SW 0 EXLP 0 0 DIS_TR Disable Transceiver 0= 1= All S-transceiver functions are enabled. All S-transceiver functions are disabled and powered down (analog and digital parts). BUS Point-to-Point / Bus Selection 0= 1= Adaptive Timing (Point-to-Point, extended passive bus). Fixed Timing (Short passive bus), directly derived from transmit clock. EN_ICV Enable Far End Code Violation 0= 1= normal operation. ICV enabled. The receipt of at least one illegal code violation within one multi-frame according to ANSI T1.605 is indicated by the C/I indication `1011' (CVR) in two consecutive IOM frames. 128 2001-11-09 Data Sheet PEF 82902 Register Description L1SW Enable Layer 1 State Machine in Software 0= 1= Layer 1 state machine of the T-SMINTaI is used. Layer 1 state machine is disabled. The functionality must be realized in software. The commands are written to register S_CMD and the status read in the S_STA. EXLP External Loop In case the analog loopback is activated with C/I = ARL or with the LP_A bit in the S_CMD register the loop is a 0= 1= internal loop next to the line pins external loop which has to be closed between SR1/SR2 and SX1/ SX2 Note: For the external loop the transmitter must be enabled (S_CONF2:DIS_TX = 0). 4.5.2 S_ CONF2 S_CONF2 - S-Transmitter Configuration Register 2 read/write Address: 32H Value after reset: 80H 7 DIS_TX 0 0 0 0 0 0 0 0 DIS_TX Disable Line Driver 0= 1= Transmitter is enabled Transmitter is disabled 4.5.3 S_ STA S_STA - S-Transceiver Status Register read Address: 33H Value after reset: 00H Data Sheet 129 2001-11-09 PEF 82902 Register Description 7 RINF 0 ICV 0 FSYN 0 0 LD Important: This register is used only if the Layer 1 state machine of the device is disabled (S_CONF0:L1SW = 1) and implemented in software! With the layer 1 state machine enabled, the signals from this register are automatically evaluated. RINF Receiver INFO 00 = 01 = 10 = 11 = ICV Received INFO 0 (no signal) Received any signal except INFO 0 or INFO 3 reserved Received INFO 3 Illegal Code Violation 0= 1= No illegal code violation is detected. Illegal code violation (ANSI T1.605) in data stream is detected. FSYN Frame Synchronization State 0= 1= The S/T receiver is not synchronized. The S/T receiver has synchronized to the framing bit F. LD Level Detection 0= 1= No receive signal has been detected on the line. Any receive signal has been detected on the line. 4.5.4 S_ CMD S_CMD - S-Transceiver Command Register read/write Address: 34H Value after reset: 08H 7 XINF DPRIO 1 PD LP_A 0 0 Data Sheet 130 2001-11-09 PEF 82902 Register Description Important: This register - except bit DPRIO - is writable only if the Layer 1 state machine of the device is disabled (S_CONF0.L1SW = 1) and implemented in software! With the device layer 1 state machine enabled, the signals from this register are automatically generated. DPRIO can also be written in intelligent NT mode. XINF Transmit INFO 000 = 001 = 010 = 011 = 100 = 101 = 11x = DPRIO Transmit INFO 0 reserved Transmit INFO 2 Transmit INFO 4 Send continuous pulses at 192 kbit/s alternating or 96 kHz rectangular, respectively (TM2) Send single pulses at 4 kbit/s with alternating polarity corresponding to 2 kHz fundamental mode (TM1) reserved D-Channel Priority 0= 1= Priority class 1 for D channel access on IOM Priority class 2 for D channel access on IOM PD Power Down 0= 1= The transceiver is set to operational mode The transceiver is set to power down mode LP_A Loop Analog The setting of this bit corresponds to the C/I command ARL. 0= 1= Analog loop is open Analog loop is closed internally or externally according to the EXLP bit in the S_CONF0 register 4.5.5 SQRR SQRR - S/Q-Channel Receive Register read Address: 35H Value after reset: 00H Data Sheet 131 2001-11-09 PEF 82902 Register Description 7 MSYN MFEN 0 0 SQR1 SQR2 SQR3 0 SQR4 MSYN Multi-frame Synchronization State 0= 1= The S/T receiver has not synchronized to the received FA and M bits The S/T receiver has synchronized to the received FA and M bits MFEN Multiframe Enable Read-back of the MFEN bit of the SQXR register 0= 1= S/T multiframe is disabled S/T multiframe is enabled SQR1-4 Received S/Q Bits Received Q bits in frames 1, 6, 11 and 16 4.5.6 SQXR SQXR- S/Q-Channel Transmit Register write Address: 35H Value after reset: 00H 7 0 MFEN 0 0 SQX1 SQX2 SQX3 0 SQX4 MFEN Multiframe Enable Used to enable or disable the multiframe structure. 0= 1= S/T multiframe is disabled S/T multiframe is enabled SQX1-4 Transmitted S/Q Bits Transmitted S bits in frames 1, 6, 11 and 16 Data Sheet 132 2001-11-09 PEF 82902 Register Description 4.5.7 ISTAS ISTAS - Interrupt Status Register S-Transceiver read Address: 38H Value after reset: 00H 7 x x x x LD RIC SQC 0 SQW These bits are set if an interrupt status occurs and an interrupt signal is activated if the corresponding mask bit is set to "0". If the mask bit is set to "1" no interrupt is generated, however the interrupt status bit is set in ISTAS. RIC, SQC and SQW are cleared by reading the corresponding source register S_STA, SQRR or writing SQXR, respectively. x LD Reserved Level Detection 0= 1= inactive Any receive signal has been detected on the line. This bit is set to "1" (i.e. an interrupt is generated if not masked) as long as any receive signal is detected on the line. RIC Receiver INFO Change 0= 1= inactive RIC is activated if one of the S_STA bits RINF or ICV has changed. SQC S/Q-Channel Change 0= 1= inactive A change in the received 4-bit Q-channel has been detected. The new code can be read from the SQRx bits of registers SQRR within the next multiframe1). This bit is reset by a read access to the SQRR register. SQW S/Q-Channel Writable Data Sheet 133 2001-11-09 PEF 82902 Register Description 0= 1= inactive The S channel data for the next multiframe is writable. The register for the S bits to be transmitted has to be written within the next multiframe. This bit is reset by writing register SQXR. This timing signal is indicated with the start of every multiframe. Data which is written right after SQW-indication will be transmitted with the start of the following multiframe. Data which is written before SQW-indication is transmitted in the multiframe which is indicated by SQW. SQW and SQC could be generated at the same time. 1) Register SQRR stays valid as long as no code change has been received. 4.5.8 MASKS MASKS - Mask S-Transceiver Interrupt read/write Address: 39H Value after reset: FFH 7 1 1 1 1 LD RIC SQC 0 SQW Bit 3..0 Mask bits 0= 1= The transceiver interrupts LD, RIC, SQC and SQW are enabled The transceiver interrupts LD, RIC, SQC and SQW are masked 4.5.9 S_ MODE S_MODE - S-Transceiver Mode read/write Address: 3AH Value after reset: 02H 7 0 0 0 0 DCH_INH MODE 0 Data Sheet 134 2001-11-09 PEF 82902 Register Description DCH_ INH D-Channel Inhibit 0= 1= inactive The S-transceiver blocks the access to the D-channel on S by inverting the E-bits. MODE Mode Selection 000 = 001 = 010 = 011 = 110 111 100 101 reserved reserved NT (without D-channel handler) LT-S (without D-channel handler) Intelligent NT mode (with NT state machine and with D-channel handler) Intelligent NT mode (with LT-S state machine and with D-channel handler) reserved reserved 4.6 4.6.1 ISTA Interrupt and General Configuration Registers ISTA - Interrupt Status Register read Address: 3CH Value after reset: 00H 7 U ST CIC 0 WOV S MOS 0 0 U U-Transceiver Interrupt 0= 1= inactive An interrupt was generated by the U-transceiver. Read the ISTAU register. Data Sheet 135 2001-11-09 PEF 82902 Register Description ST Synchronous Transfer 0= 1= inactive This interrupt enables the microcontroller to lock on to the IOM(R)-2 timing, for synchronous transfers. CIC C/I Channel Change 0= 1= 0= inactive A change in C/I0 channel or C/I1 channel has been recognized. The actual value can be read from CIR0 or CIR1. inactive WOV Watchdog Timer Overflow 0= 1= inactive Signals the expiration of the watchdog timer, which means that the microcontroller has failed to set the watchdog timer control bits WTC1 and WTC2 (MODE1 register) in the correct manner. A reset out pulse on pin RSTO has been generated by the T-SMINTaI. S S-Transceiver Interrupt 0= 1= inactive An interrupt was generated by the S-transceiver. Read the ISTAS register. MOS MONITOR Status 0= 1= 0= inactive A change in the MONITOR Status Register (MOSR) has occurred. inactive Note: A read of the ISTA register clears only the WOV interrupt. The other interrupts are cleared by reading the corresponding status register. 4.6.2 MASK MASK - Mask Register write Address: 3CH Value after reset: FFH Data Sheet 136 2001-11-09 PEF 82902 Register Description 7 U ST CIC 1 WOV S MOS 0 1 Bit 7..0 Mask bits 0= 1= Interrupt is not masked Interrupt is masked Each interrupt source in the ISTA register can be selectively masked by setting the corresponding bit in MASK to `1'. Masked interrupt status bits are not indicated when ISTA is read. Instead, they remain internally stored and pending, until the mask bit is reset to `0'. Note: In the event of a C/I channel change, CIC is set in ISTA even if the corresponding mask bit in MASK is active, but no interrupt is generated. 4.6.3 MODE1 MODE1 - Mode1 Register read/write Address: 3DH Value after reset: 04H 7 MCLK CDS WTC1 WTC2 CFS RSS2 0 RSS1 MCLK Master Clock Frequency The Master Clock Frequency bits control the microcontroller clock output depending on MODE1.CDS = '0' or '1' (Table Table 2.1.3). MODE1.CDS = '0' 00 = 01 = 10 = 11 = 3.84 MHz 0.96 MHz 7.68 MHz disabled MODE1.CDS = '1' 7.68 MHz 1.92 MHz 15.36 MHz disabled Data Sheet 137 2001-11-09 PEF 82902 Register Description CDS Clock Divider Selection 0= 1= The 15.36 MHz oscillator clock divided by two is input to the MCLK prescaler The 15.36 MHz oscillator clock is input to the MCLK prescaler. WTC1, 2 Watchdog Timer Control 1, 2 After the watchdog timer mode has been selected (RSS = `11') the watchdog timer is started. During every time period of 128 ms the microcontroller has to program the WTC1 and WTC2 bit in the following sequence (Chapter 2.2): 10 01 first step second step to reset and restart the watchdog timer. If not, the timer expires and a WOV-interrupt (ISTA Register) together with a reset out pulse on pin RSTO is generated. The watchdog timer runs only when the internal IOM(R)-2 clocks are active, i.e. the watchdog timer is dead when bit CFS = 1 and the U and Stransceivers are in state power down. CFS Configuration Select 0= The IOM(R)-2 interface clock and frame signals are always active, "Deactivated State" of the U-transceiver and the S-transceiver included. The IOM(R)-2 interface clocks and frame signals are inactive in the "Deactivated State" of the U-transceiver and the S-transceiver. 1= RSS2, RSS1 Reset Source Selection 2,1 The T-SMINTaI reset sources can be selected according to the table below. C/I Code Change 00 = 01 = 10 = 11 = x --Watchdog Timer --x POR/UVD and RST x x x RSTO disabled (high impedance) Data Sheet 138 2001-11-09 PEF 82902 Register Description 4.6.4 MODE2 MODE2 - Mode2 Register read/write Address: 3EH Value after reset: 00H 7 LED2 LED1 LEDC 0 0 0 AMOD 0 PPSDX LED2,1 LED Control on pin ACT 00 = 01 = 10 = 11 = High flashing at 2 Hz (1 : 1)* flashing at 1 Hz (3 : 1)* Low LEDC LED Control Enable 0= 1= LED is controlled by the state machines as defined in Table 3. LED is controlled via bits LED2,1. AMOD Address Mode Selects between direct and indirect register access of the parallel microcontroller interface. 0= 1= Indirect address mode is selected. The address line A0 is used to select between address (A0 = `0') and data (A0 = `1') register Direct address mode is selected. The address is applied to the address bus (A0-A6) PPSDX Push/Pull Output for SDX 0= 1= The SDX pin has open drain characteristic The SDX pin has push/pull characteristic 4.6.5 ID ID - Identification Register read Address: 3FH Value after reset: 20H Data Sheet 139 2001-11-09 PEF 82902 Register Description 7 0 0 DESIGN 0 DESIGN Design Number The design number (DESIGN) allows to identify different hardware designs1) of the T-SMINTaI by software. 100000: Version 1.1 1) Distinction of different firmware versions is also possible by readingregister (7D)H in the address space of the U-transceiver (see Chapter 4.9.8). 4.6.6 SRES SRES - Software Reset Register write Address: 3FH Value after reset: 00H 7 0 0 RES_ CI/TIC 0 0 0 RES_S 0 RES_U RES_xx Reset_xx 0= 1= Deactivates the reset of the functional block xx Activates the reset of the functional block xx. The reset state is activated as long as the bit is set to `1' 4.7 4.7.1 Detailed IOM(R)-2 Handler Registers CDAxy - Controller Data Access Register xy These registers are used for microcontroller access to the IOM(R)-2 timeslots as well as for timeslot manipulations. (e.g. loops, shifts, ... see also "Controller Data Access (CDA)" on Page 30). Data Sheet 140 2001-11-09 PEF 82902 Register Description CDAxy 7 Controller Data Access Register Data register CDAxy which can be accessed by the controller. Register CDA10 CDA11 CDA20 CDA21 Value after Reset FFH FFH FFH FFH Register Address 40H 41H 42H 43H read/write Address: 40-43H 0 4.7.2 XXX_TSDPxy - Time Slot and Data Port Selection for CHxy read/write Address: 44-4DH 0 0 0 0 TSS XXX_TSDPxy 7 DPS Register CDA_TSDP10 CDA_TSDP11 CDA_TSDP20 CDA_TSDP21 S_TSDP_B1 S_TSDP_B2 Value after Reset 00H (= output on B1-DD) 01H (= output on B2-DD) 80H (= output on B1-DU) 81H (= output on B2-DU) reserved 84H (= output on TS4-DU) 85H (= output on TS5-DU) Register Address 44H 45H 46H 47H 48-4BH 4CH 4DH This register determines the time slots and the data ports on the IOM(R)-2 Interface for the data channels xy of the functional units XXX (Controller Data Access (CDA) and Stransceiver (S)). Note: The U-transceiver is always in IOM-2 channel 0. Data Sheet 141 2001-11-09 PEF 82902 Register Description DPS Data Port Selection 0= 1= The data channel xy of the functional unit XXX is output on DD. The data channel xy of the functional unit XXX is input from DU. The data channel xy of the functional unit XXX is output on DU. The data channel xy of the functional unit XXX is input from DD. Note: For the CDA (controller data access) data the input is determined by the CDAx_CR.SWAP bit. If SWAP = `0' the input for the CDAxy data is vice versa to the output setting for CDAxy. If the SWAP = `1' the input from CDAx0 is vice versa to the output setting of CDAx1 and the input from CDAx1 is vice versa to the output setting of CDAx0. TSS Timeslot Selection Selects one of the 12 timeslots from 0...11 on the IOM(R)-2 interface for the data channels. 4.7.3 CDAx_CR 7 0 CDAx_CR - Control Register Controller Data Access CH1x read/write Address: 4E-4FH 0 0 EN_TBM EN_I1 EN_I0 EN_O1 EN_O0 SWAP Register CDA1_CR CDA2_CR Value after Reset 00H 00H Register Address 4EH 4FH EN_TBM Enable TIC Bus Monitoring 0= 1= The TIC bus monitoring is disabled The TIC bus monitoring with the CDAx0 register is enabled. The TSDPx0 register must be set to 08H for monitoring from DU, or 88H for monitoring from DD. EN_I1, EN_I0 Data Sheet Enable Input CDAx1, CDAx0 142 2001-11-09 PEF 82902 Register Description 0= 1= EN_O1, EN_O0 The input of the CDAx1, CDAx0 register is disabled The input of the CDAx1, CDAx0 register is enabled Enable Output CDAx1, CDAx0 0= 1= The output of the CDAx1, CDAx0 register is disabled The output of the CDAx1, CDAx0 register is enabled SWAP Swap Inputs 0= The time slot and data port for the input of the CDAxy register is defined by its own TSDPxy register. The data port for the CDAxy input is vice versa to the output setting for CDAxy. The input (time slot and data port) of the CDAx0 is defined by the TSDP register of CDAx1 and the input of CDAx1 is defined by the TSDP register of CDAx0. The data port for the CDAx0 input is vice versa to the output setting for CDAx1. The data port for the CDAx1 input is vice versa to the output setting for CDAx0. The input definition for time slot and data port CDAx0 are thus swapped to CDAx1 and for CDAx1 to CDAx0. The outputs are not affected by the SWAP bit. 1= 4.7.4 S_CR S_CR - Control Register S-Transceiver Data read/write Address: 51H Value after reset: FFH 7 1 CI_CS EN_D EN_B2R EN_B1R EN_B2X EN_B1X 0 D_CS CI_CS C/I Channel Selection This bit is used to select the IOM channel to which the S-transceiver C/Ichannel is related to. 0= 1= C/I-channel in IOM-channel 0 C/I-channel in IOM-channel 1 Data Sheet 143 2001-11-09 PEF 82902 Register Description EN_D Enable Transceiver D-Channel Data 0= 1= The corresponding data path to the transceiver is disabled The corresponding data path to the transceiver is enabled. EN_B2R Enable Transceiver B2 Receive Data (transmitter receives from IOM) 0= 1= The corresponding data path to the transceiver is disabled The corresponding data path to the transceiver is enabled. EN_B1R Enable Transceiver B1 Receive Data (transmitter receives from IOM) 0= 1= The corresponding data path to the transceiver is disabled The corresponding data path to the transceiver is enabled. EN_B2X Enable Transceiver B2 Transmit Data (transmitter transmits to IOM) 0= 1= The corresponding data path to the transceiver is disabled The corresponding data path to the transceiver is enabled. EN_B1X Enable Transceiver B1 Transmit Data (transmitter transmits to IOM) 0= 1= The corresponding data path to the transceiver is disabled The corresponding data path to the transceiver is enabled. These bits are used to individually enable/disable the D-channel and the receive/transmit paths for the B-channels for the S-transceiver. D_CS D Channel Selection This bit is used to select the IOM channel to which the S-transceiver Dchannel is related to. 0= 1= D-channel in IOM-channel 0 D-channel in IOM-channel 1 4.7.5 CI_CR CI_CR - Control Register for CI1 Data read/write Address: 52H Value after reset: 04H Data Sheet 144 2001-11-09 PEF 82902 Register Description 7 DPS_CI1 EN_CI1 0 0 0 1 0 0 DPS_CI1 Data Port Selection CI1 Handler 0= 1= EN_CI1 The CI1 data is output on DD and input from DU The CI1 data is output on DU and input from DD Enable CI1 Handler 0= 1= CI1 data access is disabled CI1 data access is enabled Note: The timeslot for the C/I1 handler cannot be programmed but is fixed to IOM channel 1. 4.7.6 MON_CR MON_CR - Control Register Monitor Data read/write Address: 53H Value after reset: 40H 7 DPS EN_MON 0 0 0 0 MCS 0 DPS Data Port Selection 0= 1= The Monitor data is output on DD and input from DU The Monitor data is output on DU and input from DD EN_MON Enable Output 0= 1= MCS The Monitor data input and output is disabled The Monitor data input and output is enabled MONITOR Channel Selection 00 = The MONITOR data is output on MON0 Data Sheet 145 2001-11-09 PEF 82902 Register Description 01 = The MONITOR data is output on MON1 10 = The MONITOR data is output on MON2 11 = Not defined 4.7.7 SDS1_CR SDS1_CR - Control Register Serial Data Strobe 1 read/write Address: 54H Value after reset: 00H 7 ENS_ TSS ENS_ TSS+1 ENS_ TSS+3 0 TSS 0 This register is used to select position and length of the strobe signal 1. The length can be any combination of two 8-bit timeslot (ENS_TSS, ENS_TSS+1) and one 2-bit timeslot (ENS_TSS+3). ENS_ TSS Enable Serial Data Strobe of timeslot TSS 0= 1= ENS_ TSS+1 The serial data strobe signal SDS1 is inactive during TSS The serial data strobe signal SDS1 is active during TSS Enable Serial Data Strobe of timeslot TSS+1 0= 1= The serial data strobe signal SDS1 is inactive during TSS+1 The serial data strobe signal SDS1 is active during TSS+1 ENS_ TSS+3 Enable Serial Data Strobe of timeslot TSS+3 (D-Channel) 0= 1= The serial data strobe signal SDS1 is inactive during the D-channel (bit7, 6) of TSS+3 The serial data strobe signal SDS1 is active during the D-channel (bit7, 6) of TSS+3 Data Sheet 146 2001-11-09 PEF 82902 Register Description TSS Timeslot Selection Selects one of 12 timeslots on the IOM(R)-2 interface (with respect to FSC) during which SDS1 is active high. The data strobe signal allows standard data devices to access a programmable channel. 4.7.8 SDS2_CR SDS2_CR - Control Register Serial Data Strobe 2 read/write Address: 55H Value after reset: 00H 7 ENS_ TSS ENS_ TSS+1 ENS_ TSS+3 0 TSS 0 This register is used to select position and length of the strobe signal 2. The length can be any combination of two 8-bit timeslot (ENS_TSS, ENS_TSS+1) and one 2-bit timeslot (ENS_TSS+3). ENS_ TSS Enable Serial Data Strobe of timeslot TSS 0= 1= ENS_ TSS+1 The serial data strobe signal SDS2 is inactive during TSS The serial data strobe signal SDS2 is active during TSS Enable Serial Data Strobe of timeslot TSS+1 0= 1= The serial data strobe signal SDS2 is inactive during TSS+1 The serial data strobe signal SDS2 is active during TSS+1 ENS_ TSS+3 Enable Serial Data Strobe of timeslot TSS+3 (D-Channel) 0= 1= The serial data strobe signal SDS2 is inactive during the D-channel (bit7, 6) of TSS+3 The serial data strobe signal SDS2 is active during the D-channel (bit7, 6) of TSS+3 Data Sheet 147 2001-11-09 PEF 82902 Register Description TSS Timeslot Selection Selects one of 12 timeslots on the IOM(R)-2 interface (with respect to FSC) during which SDS2 is active high. The data strobe signal allows standard data devices to access a programmable channel. 4.7.9 IOM_CR IOM_CR - Control Register IOM Data read/write Address: 56H Value after reset: 08H 7 SPU 0 0 TIC_DIS EN_BCL 0 0 DIS_OD DIS_IOM SPU Software Power UP 0= 1= The DU line is normally used for transmitting data. Setting this bit to `1' will pull the DU line to low. This will enforce the T-SMINTaI and other connected layer 1 devices to deliver IOMclocking. TIC_DIS TIC Bus Disable 0= 1= The last octet of the last IOM time slot (TS 11) is used as TIC bus. The TIC bus is disabled. The last octet of the last IOM time slot (TS 11) can be used like any other time slot. This means that the timeslots TIC, A/B, S/G and BAC are not available any more. EN_BCL Enable Bit Clock BCL 0= 1= The BCL clock is disabled (output is high impedant) The BCL clock is enabled DIS_OD Disable Open Drain 0= 1= IOM outputs are open drain driver IOM outputs are push pull driver Data Sheet 148 2001-11-09 PEF 82902 Register Description DIS_IOM Disable IOM DIS_IOM should be set to `1' if external devices connected to the IOM interface should be "disconnected" e.g. for power saving purposes. However, the T-SMINTaI internal operation is independent of the DIS_IOM bit. 0= 1= The IOM interface is enabled The IOM interface is disabled (FSC, DCL, clock outputs have high impedance; DU, DD data line inputs are switched off and outputs are high impedant) 4.7.10 MCDA MCDA - Monitoring CDA Bits read Address: 57H Value after reset: FFH 7 MCDA21 Bit7 Bit6 MCDA20 Bit7 Bit6 MCDA11 Bit7 Bit6 0 MCDA10 Bit7 Bit6 MCDAxy Monitoring CDAxy Bits Bit 7 and Bit 6 of the CDAxy registers are mapped into the MCDA register. This can be used for monitoring the D-channel bits on DU and DD and the "Echo bits" on the TIC bus with the same register. 4.7.11 STI STI - Synchronous Transfer Interrupt read Address: 58H Value after reset: 00H 7 STOV21 STOV20 STOV11 STOV10 STI21 STI20 STI11 0 STI10 Data Sheet 149 2001-11-09 PEF 82902 Register Description For all interrupts in the STI register the following logical states are applied 0= 1= STOVxy Interrupt has not occurred Interrupt has occurred Synchronous Transfer Overflow Interrupt Enabled STOV interrupts for a certain STIxy interrupt are generated when the STIxy has not been acknowledged in time via the ACKxy bit in the ASTI register. This must be one (for DPS = `0') or zero (for DPS = `1') BCL clock cycles before the time slot which is selected for the STOV. STIxy Synchronous Transfer Interrupt Depending on the DPS bit in the corresponding TSDPxy register the Synchronous Transfer Interrupt STIxy is generated two (for DPS = `0') or one (for DPS = `1') BCL clock cycles after the selected time slot (TSDPxy.TSS). Note: ST0Vxy and ACKxy are useful for synchronizing microcontroller accesses and receive/transmit operations. One BCL clock is equivalent to two DCL clocks. 4.7.12 ASTI ASTI - Acknowledge Synchronous Transfer Interrupt write Address: 58H Value after reset: 00H 7 0 0 0 0 ACK21 ACK20 ACK11 0 ACK10 ACKxy Acknowledge Synchronous Transfer Interrupt After a STIxy interrupt the microcontroller has to acknowledge the interrupt by setting the corresponding ACKxy bit. 0= 1= No activity is initiated Sets the acknowledge bit ACKxy for a STIxy interrupt Data Sheet 150 2001-11-09 PEF 82902 Register Description 4.7.13 MSTI MSTI - Mask Synchronous Transfer Interrupt read/write Address: 59H Value after reset: FFH 7 STOV21 STOV20 STOV11 STOV10 STI21 STI20 STI11 0 STI10 For the MSTI register the following logical states are applied: 0= 1= STOVxy Interrupt is not masked Interrupt is masked Mask Synchronous Transfer Overflow xy Mask bits for the corresponding STOVxy interrupt bits. STIxy Synchronous Transfer Interrupt xy Mask bits for the corresponding STIxy interrupt bits. 4.8 4.8.1 MOR Detailed MONITOR Handler Registers MOR - MONITOR Receive Channel read Address: 5CH Value after reset: FFH 7 0 Contains the MONITOR data received in the IOM(R)-2 MONITOR channel according to the MONITOR channel protocol. The MONITOR channel (0,1,2) can be selected by setting the monitor channel select bit MON_CR.MCS. Data Sheet 151 2001-11-09 PEF 82902 Register Description 4.8.2 MOX MOX - MONITOR Transmit Channel write Address: 5CH Value after reset: FFH 7 0 Contains the MONITOR data to be transmitted in IOM(R)-2 MONITOR channel according to the MONITOR channel protocol. The MONITOR channel (0,1,2) can be selected by setting the monitor channel select bit MON_CR.MCS 4.8.3 MOSR MOSR - MONITOR Interrupt Status Register read Address: 5DH Value after reset: 00H 7 MDR MER MDA MAB 0 0 0 0 0 MDR MONITOR channel Data Received 0= 1= inactive MONITOR channel Data Received MER MONITOR channel End of Reception 0= 1= inactive MONITOR channel End of Reception MDA MONITOR channel Data Acknowledged The remote end has acknowledged the MONITOR byte being transmitted. 0= 1= inactive MONITOR channel Data Acknowledged MAB Data Sheet MONITOR channel Data Abort 152 2001-11-09 PEF 82902 Register Description 0= 1= inactive MONITOR channel Data Abort 4.8.4 MOCR MOCR - MONITOR Control Register read/write Address: 5EH Value after reset: 00H 7 MRE MRC MIE MXC 0 0 0 0 0 MRE MONITOR Receive Interrupt Enable 0= 1= MONITOR interrupt status MDR generation is masked. MONITOR interrupt status MDR generation is enabled. MRC MR Bit Control Determines the value of the MR bit: 0= 1= MR is always `1'. In addition, the MDR interrupt is blocked, except for the first byte of a packet (if MRE = 1). MR is internally controlled by the T-SMINTaI according to MONITOR channel protocol. In addition, the MDR interrupt is enabled for all received bytes according to the MONITOR channel protocol (if MRE = 1). MIE MONITOR Interrupt Enable 0= 1= MONITOR interrupt status MER, MDA, MAB generation is masked MONITOR interrupt status MER, MDA, MAB generation is enabled MXC MX Bit Control Determines the value of the MX bit: 0= 1= The MX bit is always `1'. The MX bit is internally controlled by the T-SMINTaI according to MONITOR channel protocol. Data Sheet 153 2001-11-09 PEF 82902 Register Description 4.8.5 MSTA MSTA - MONITOR Status Register read Address: 5FH Value after reset: 00H 7 0 0 0 0 0 MAC 0 0 TOUT MAC MONITOR Transmit Channel Active 0= 1= No data transmission in the MONITOR channel The data transmission in the MONITOR channel is in progress. TOUT Time-Out Read-back value of the TOUT bit 0= 1= The monitor time-out function is disabled The monitor time-out function is enabled 4.8.6 MCONF MCONF - MONITOR Configuration Register write Address: 5FH Value after reset: 00H 7 0 0 0 0 0 0 0 0 TOUT TOUT Time-Out 0= 1= The monitor time-out function is disabled The monitor time-out function is enabled Data Sheet 154 2001-11-09 PEF 82902 Register Description 4.9 4.9.1 Detailed U-Transceiver Registers OPMODE - Operation Mode Register The Operation Mode register determines the operating mode of the U-transceiver. OPMODE Reset value: 00H 7 0 6 UCI 5 0 4 0 3 0 2 0 1 0 0 0 read*)/write Address: 60H UCI Enable/Disable P-control of C/I codes 0= 1= P control disabled - C/I codes are exchanged via IOM(R)-2 Read access to register UCIR by the P is still possible P control enabled - C/I codes are exchanged via UCIR and UCIW registers In this case, the according C/I-channel on IOM(R)-2 is idle `1111` 4.9.2 UCIR - C/I Code Read Register Via the U-transceiver C/I code Read register a microcontroller can access the C/I code that is output from the state machine. UCIR Reset value: 00H 7 0 6 0 5 0 4 0 3 2 1 0 read Address: 6DH C/I code output 4.9.3 UCIW - C/I Code Write Register The U-transceiver C/I code Write register allows a microcontroller to control the state of the U-transceiver. To enable this function bit UCI in register OPMODE must be set to '1' before. Data Sheet 155 2001-11-09 PEF 82902 Register Description UCIW Reset value: 01H 7 0 6 0 5 0 4 0 3 2 1 0 write Address: 6EH C/I code input 4.9.4 LOOP - Loopback Register The Loop register controls local digital loopbacks of the U-transceiver. LOOP Reset value: 08H 7 0 6 0 5 TRAN S 4 U/IOM 3 1 2 LBBD 1 LB2 0 LB1 read*)/write Address: 70H TRANS Transparent/ Non-Transparent Loopback In transparent mode data is both passed on and looped back, whereas in non-transparent mode data is not forwarded but substituted by 1s (idle code) and just looped back 0= 1= transparent mode non-transparent mode '1's are sent on the IOM(R)-2 interface in the corresponding time-slot U/IOM(R) Close LBBD, LB2, LB1 towards U or towards IOM(R) Switch that selects whether loopback LB1, LB2 or LBBD is closed towards U or towards IOM(R)-2 the setting affects all test loops, LBBD, LB2 and LB1 an individual selection for LBBD, LB2, LB1 is not possible 0= 1= LB1, LB2, LBBD loops are closed towards IOM(R) LB1, LB2, LBBD loops are closed towards U Data Sheet 156 2001-11-09 PEF 82902 Register Description LBBD Close complete loop (B1, B2, D) near the system interface - the direction towards which the loop is closed is determined by bit U/IOM(R) - the state machine has to be in state 'Transparent' first (e.g. by C/I = DT) before data is output on the U-interface 0= 1= complete loopback open complete loopback closed LB2 Close loop B2 near the system interface - the direction towards which the loop is closed is determined by bit U/IOM(R) - the state machine has to be in state 'Transparent' first (e.g. by C/I = DT) before data is output on the U-interface 0= 1= loopback B2 open loopback B2 closed LB1 Close loop B1 near the system interface - the direction towards which the loop is closed is determined by bit U/IOM(R) - the state machine has to be in state 'Transparent' first (e.g. by C/I = DT) before data is output on the U-interface 0= 1= loopback B1 open loopback B1 closed 4.9.5 RDS - Block Error Counter Register see Chapter 2.4.4.2. RDS Reset value: 00H 7 6 5 4 3 2 1 0 read Address: 72H Block Error Counter Value 4.9.6 ISTAU - Interrupt Status Register U-Interface The Interrupt Status register U-interface generates an interrupt for the unmasked interrupt flags. Refer to Chapter 2.4.8 for details on masking and clearing of interrupt flags. Data Sheet 157 2001-11-09 PEF 82902 Register Description ISTAU Reset value: 00H 7 0 6 CI 5 RDS 4 0 3 0 2 0 1 0 0 1 ms read Address: 7AH CI C/I code indication the CI interrupt is generated independently on OPMODE.UCI 0= 1= inactive CI code change has occurred RDS Code violation occurred 0= 1= inactive code violation has occurred 1 ms Start of a new frame on the U-interface useful for synchronization of register accesses by an external C 0= 1= inactive signals the start of a new frame on the U-interface 4.9.7 MASKU - Mask Register U-Interface The Interrupt Mask register U-Interface selectively masks each interrupt source in the ISTAU register by setting the corresponding bit to '1'. MASKU Reset Value: FFH 7 1 6 CI 5 RDS 4 1 3 1 2 1 1 1 0 1 ms read*)/write Address: 7BH Data Sheet 158 2001-11-09 PEF 82902 Register Description Bit 0..7 Mask bits 0= 1= interrupt active interrupt masked 4.9.8 FW_VERSION FW_VERSION Register contains the Firmware Version number FW_VERSION Reset value: 3EH 7 6 5 4 3 2 1 0 read Address: 7DH Firmware Version Number Data Sheet 159 2001-11-09 PEF 82902 Electrical Characteristics 5 5.1 * Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values -40 to 85 - 65 to 150 4.2 -0.3 to VDD + 3.3 (max. < 5.5) Unit C C V V Parameter Ambient temperature under bias TA TSTG Storage temperature Maximum Voltage on VDD VDD Maximum Voltage on any pin with respect to VS ground ESD integrity (according EIA/JESD22-A114B (HBM)): 2 kV Note: Stress above those listed here may cause permanent damage to the device. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. Line Overload Protection The T-SMINTaI is compliant to ESD tests according to ANSI / EOS / ESD-S 5.1-1993 (CDM), EIA/JESD22-A114B (HBM) and to Latch-up tests according to JEDEC EIA / JESD78. From these tests the following max. input currents are derived (Table 33): * Table 33 Test ESD Latch-up DC Maximum Input Currents Pulse Width 100 ns 5 ms -Current 1.3 A +/-200 mA 10 mA Remarks 3 repetitions 2 repetitions, respectively Data Sheet 160 2001-11-09 PEF 82902 Electrical Characteristics 5.2 * DC Characteristics VDD/VDDA = 3.3 V +/- 5% ; VSS/VSSA = 0 V; TA = -40 to 85 C Digital Pins All All except DD/DU ACT,LP2I MCLK DD/DU ACT,LP2I MCLK All Analog Pins AIN, BIN Input leakage current ILI 30 A 0 V VIN VD D Parameter Input low voltage Input high voltage Output low voltage Output high voltage Output low voltage Output high voltage (DD/DU push-pull) Input leakage current Symbol Limit Values min. VIL VIH VOL1 VOH1 VOL2 VOH2 ILI 2.4 10 10 2.4 0.45 -0.3 2.0 max. 0.8 5.25 0.45 Unit V V V V V V A A Test Condition IOL1 = 3.0 mA IOH1 = 3.0 mA IOL2 = 4.0 mA IOH2 = 4.0 mA 0 V VIN VDD 0 V VIN VDD Output leakage current ILO Table 34 Pin SX1,2 S-Transceiver Characteristics Symbol Limit Values min. typ. 2.2 max. 2.31 V VX 2.03 Unit Test Condition RL = 50 Parameter Absolute value of output pulse amplitude (VSX2 - VSX1) S-Transmitter output impedance SX1,2 ZX ZR 10 0 10 100 34 k k see 1) see 2)3) VDD = 3.3 V VDD = 0 V SR1,2 S-Receiver input impedance 1) Requirement ITU-T I.430, chapter 8.5.1.1a): 'At all times except when transmitting a binary zero, the output impedance , in the frequency range of 2kHz to 1 MHz, shall exceed the impedance indicated by the template in Figure 11. The requirement is applicable with an applied sinusoidal voltage of 100 mV (r.m.s value)' Data Sheet 161 2001-11-09 PEF 82902 Electrical Characteristics 2) Requirement ITU-T I.430, chapter 8.5.1.1b): 'When transmitting a binary zero, the output impedance shall be > 20 .': Must be met by external circuitry. Requirement ITU-T I.430, chapter 8.5.1.1b), Note: 'The output impedance limit shall apply for a nominal load impedance (resistive) of 50 . The output impedance for each nominal load shall be defined by determining the peak pulse amplitude for loads equal to the nominal value +/- 10%. The peak amplitude shall be defined as the the amplitude at the midpoint of a pulse. The limitation applies for pulses of both polarities.' 3) Table 35 U-Transceiver Characteristics Limit Values min. typ. max. dB 50 55 23 %3) mV peak k Unit Receive Path Signal / (noise + total harmonic distortion)1) 652) DC-level at AD-output Threshold of level detect (measured between AIN and BIN with respect to zero signal) Input impedance AIN/BIN Transmit Path Signal / (noise + total harmonic distortion)4) 70 Common mode DC-level Offset between AOUT and BOUT Absolute peak voltage for a single +3 or -3 pulse measured between AOUT and BOUT5) Output impedance AOUT/BOUT: Power-up Power-down 1) 2) 3) 4) 45 10 80 dB 1.65 2.5 1.69 35 2.58 V mV V 1.61 2.42 0.8 3 1.5 6 Test conditions: 1.4 Vpp differential sine wave as input on AIN/BIN with long range (low, critical range). Versions PEF 8x913 with enhanced performance of the U-interface are tested with tightened limit values The percentage of the "1 "-values in the PDM-signal. Interpretation and test conditions: The sum of noise and total harmonic distortion, weighted with a low pass filter 0 to 80 kHz, is at least 70 dB below the signal for an evenly distributed but otherwise random sequence of +3, +1, -1, -3. The signal amplitude measured over a period of 1 min. varies less than 1%. 5) Data Sheet 162 2001-11-09 PEF 82902 Electrical Characteristics 5.3 * Capacitances TA = 25 C, 3.3 V 5 % VSSA = 0 V, VSSD = 0 V, fc = 1 MHz, unmeasured pins grounded. Table 36 Parameter Digital pads: Input Capacitance I/O Capacitance Analog pads: Load Capacitance Pin Capacitances Symbol Limit Values Unit min. CIN CI/O CL max. 7 7 3 pF pF pF pin AIN, BIN Remarks 5.4 * Power Consumption Power Consumption VDD=3.3 V, VSS=0 V, Inputs at VSS/VDD, no LED connected, 50% bin. zeros, no output loads except SX1,2 (50 1)) Parameter Operational U and S enabled, IOMa-2 off Limit Values min. typ. 185 165 Power Down 1) Unit Test Condition max. mW mW mW U: ETSI loop 1 (0 m) U: ETSI Loop 2.(typical line) 15 50 (2 x TR) on the S-bus. 5.5 Supply Voltages VDDD = + Vdd 5% VDDA = + Vdd 5% The maximum sinusoidal ripple on VDD is specified in the following figure: Data Sheet 163 2001-11-09 PEF 82902 Electrical Characteristics * mV (peak) 200 100 Supply Voltage Ripple 10 60 80 100 Frequency / kHz ITD04269.vsd Frequency Ripple Figure 60 Maximum Sinusoidal Ripple on Supply Voltage Data Sheet 164 2001-11-09 PEF 82902 Electrical Characteristics 5.6 AC Characteristics TA = -40 to 85 C, VDD = 3.3 V 5% Inputs are driven to 2.4 V for a logical "1" and to 0.4 V for a logical "0". Timing measurements are made at 2.0 V for a logical "1" and 0.8 V for a logical "0". The AC testing input/output waveforms are shown in Figure 61. * 2.4 2.0 2.0 Test Points 0.8 0.45 0.8 Device Under Test CLoad=50 pF ITS00621.vsd Figure 61 Input/Output Waveform for AC Tests Parameter All Output Pins Fall time Rise time Symbol Limit values Min Max 30 30 Unit ns ns Data Sheet 165 2001-11-09 PEF 82902 Electrical Characteristics 5.6.1 * IOM(R)-2 Interface DCL t4 DU/DD (Input) t6 DU/DD (Output) t8 DU/DD (Output) bit n t18 SDS1,2 IOM-Timing.vsd t5 Data valid t7 first bit last bit bit n+1 Figure 62 * IOM(R)-2 Interface - Bit Synchronization Timing t9 FSC t10 DCL t2 t1 BCL t11 t14 t13 t12 t3 Figure 63 Data Sheet IOM(R)-2 Interface - Frame Synchronization Timing 166 2001-11-09 PEF 82902 Electrical Characteristics * Parameter IOM(R)-2 Interface DCL period DCL high DCL low Input data setup Input data hold Symbol Limit values Min t1 t2 t3 t4 t5 565 200 200 20 20 100 Typ 651 310 310 Max 735 420 420 Unit ns ns ns ns ns ns Output data from high impedance to t6 active (FSC high or other than first timeslot) Output data from active to high impedance Output data delay from clock FSC high t7 t8 t9 50% of FSC cycle time 65 565 565 1130 65 130 651 651 1302 130 100 80 ns ns ns FSC advance to DCL BCL high BCL low BCL period FSC advance to BCL DCL, FSC rise/fall t10 t11 t12 t13 t14 t15 195 735 735 1470 195 30 200 150 120 ns ns ns ns ns ns ns ns ns Data out fall (CL = 50 pF, R = 2 k to t16 VDD, open drain) Data out rise/fall (CL = 50 pF, tristate) Strobe Signal Delay t17 t18 Note: At the start and end of a reset period, a frame jump may occur. This results in a DCL, BCL and FSC high time of min. 130 ns after this specific event. Data Sheet 167 2001-11-09 PEF 82902 Electrical Characteristics 5.6.2 * Serial P Interface t1 t4 CS t11 t2 t3 t5 SCLK t6 SDR t8 SDX t10 SCI_timing.vsd t7 t9 Figure 64 * Serial Control Interface Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 10 Limit values Min 200 80 80 20 10 15 15 60 40 60 Max ns ns ns ns ns ns ns ns ns ns ns Unit Parameter SCI Interface SCLK cycle time SCLK high time SCLK low time CS setup time CS hold time SDR setup time SDR hold time SDX data out delay CS high to SDX tristate SCLK to SDX active CS high to SCLK Data Sheet 168 2001-11-09 PEF 82902 Electrical Characteristics 5.6.3 Parallel P Interface Siemens/Intel Bus Mode * tRR RD x CS tRD AD0 - AD7 tDF tDH tRI Data Itt00712.vsd Figure 65 * Microprocessor Read Cycle tWW tWI WR x CS tDW AD0 - AD7 tWD Data Itt00713.vsd Figure 66 * Microprocessor Write Cycle tAA ALE WR x CS or RD x CS tALS tLA tAD tAL AD0 - AD7 Address Itt00714.vsd Figure 67 Multiplexed Address Timing Data Sheet 169 2001-11-09 PEF 82902 Electrical Characteristics * WR x CS or RD x CS tAS A0 - A6 tAH Address Itt009661.vsd Figure 68 Non-Multiplexed Address Timing Motorola Bus Mode * R/W tDSD CS x DS tRD D0 - D7 tRR tRWD tRI tDF tDH Data Itt00716.vsd Figure 69 * Microprocessor Read Timing R/W tDSD CS x DS tDW D0 - D7 tWW tRWD tWI tWD Data Itt09679.vsd Figure 70 Microprocessor Write Cycle Data Sheet 170 2001-11-09 PEF 82902 Electrical Characteristics * CS x DS tAS A0 - A6 tAH Address Itt09662.vsd Figure 71 Non-Multiplexed Address Timing Microprocessor Interface Timing * Parameter ALE pulse width Address setup time to ALE Address hold time from ALE Address latch setup time to WR, RD Address setup time Address hold time ALE guard time DS delay after R/W setup RD pulse width Data output delay from RD Data hold from RD Data float from RD RD control interval1) W pulse width Data setup time to W x CS Data hold time W x CS W control interval R/W hold from CS x DS inactive Symbol tAA tAL tLA tALS tAS tAH tAD tDSD tRR tRD tDH tDF tRI tWW tDW tWD tWI tRWD Limit Values min. 20 10 10 10 10 10 10 10 80 80 0 25 70 60 10 10 70 10 max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data Sheet 171 2001-11-09 PEF 82902 Electrical Characteristics 1) control interval: tRI' is minimal 70ns for all registers except ISTAU, FEBE and NEBE. However, the time between two consecutive read accesses to one of the registers ISTAU, FEBE or NEBE, respectively, must be longer than 330ns. This does not limit tRI of read sequences, which involve intermediate read access to other registers, as for instance: ISTAU -(tRI)- ISTA -(tRI)- ISTAH -(tRI)- ISTAU. Data Sheet 172 2001-11-09 PEF 82902 Electrical Characteristics 5.6.4 Table 37 Parameter Reset Reset Input Signal Characteristics Symbol tRST Limit Values min. typ. max. ms Power On the 4 ms are assumed to be long enough for the oscillator to run correctly After Power On 4 Unit Test Conditions Length of active low state 2x DCL clock cycles + 400 ns Delay time for C tC access after RST rising edge * 500 ns tC RST tRST ITD09823.vsd Figure 72 Reset Input Signal Data Sheet 173 2001-11-09 PEF 82902 Electrical Characteristics 5.6.5 * Undervoltage Detection Characteristics VDD VDET VHYS VDDmin t RSTO tACT tACT tDEACT tDEACT t VDDDET.VSD Figure 73 Table 38 Undervoltage Control Timing Parameters of the UVD/POR Circuit VDD= 3.3 V 5 %; VSS= 0 V; TA = -40 to 85 C Parameter Detection Threshold1) Hysteresis Max. rising/falling VDD edge for activation/ deactivation of UVD Max. rising VDD for power-on2) Min. operating voltage VDDmin 1.5 Symbol min. VDET VHys dVDD/dt 2.7 30 Limit Values typ. 2.8 max. 2.92 90 0.1 V mV V/s VDD = 3.3 V 5 % Unit Test Condition 0.1 V/ ms V Data Sheet 174 2001-11-09 PEF 82902 Electrical Characteristics VDD= 3.3 V 5 %; VSS= 0 V; TA = -40 to 85 C Parameter Delay for activation of RSTO Delay for deactivation of RSTO 1) Symbol min. tACT tDEACT Limit Values typ. max. 10 64 Unit Test Condition s ms The Detection Threshold VDET is far below the specified supply voltage range of analog and digital parts of the (R) T-SMINT . Therefore, the board designer must take into account that a range of voltages is existing, where (R) neither performance and functionality of the T-SMINT are guaranteed, nor a reset is generated. If the integrated Power-On Reset of the T-SMINTI is selected (VDDDET = '0') and the supply voltage VDD is ramped up from 0V to 3.3V +/- 5%, then the T-SMINTI is kept in reset during V DDmin < VDD < VDET + VHys. VDD must be ramped up so slowly that the T-SMINTI leaves the reset state after the oscillator circuit has already finished start-up. The start-up time of the oscillator circuit is typically in the range between 3ms and 12ms. 2) Data Sheet 175 2001-11-09 PEF 82902 Package Outlines 6 * Package Outlines Plastic Package, P-MQFP-64 (Metric Quad Flat Package) Data Sheet 176 2001-11-09 PEF 82902 Package Outlines * Plastic Package, P-TQFP-64 (Thin Quad Flat Package) Data Sheet 177 2001-11-09 PEF 82902 Appendix: Differences between Q- and T-SMINTI 7 Appendix: Differences between Q- and T-SMINTaI Especially the pin compatibility between Q- and T-SMINTaI allows for one single PCB design for both series with only some mounting differences. The C software can distinguish between the Q- and T-series by reading the hardware Design Number via the IOMa-2 (MONITOR channel identification command) or the C interface (register ID.DESIGN), respectively (see Table 39). Table 39 Design Number Design Number Q-SMINTaI: 2B1Q Version Version 1.3: '000 001' T-SMINTaI: 4B3T Version 1.1: '100 000' The Q- and T-SMINTaI have been designed to be as compatible as possible. However, some differences between them are unavoidable due to the different line codes 2B1Q and 4B3T used for data transmission on the Uk0 line. The following chapter summarizes the main differences between the Q- and T-SMINTaI. Data Sheet 178 2001-11-09 PEF 82902 Appendix: Differences between Q- and T-SMINTI 7.1 7.1.1 * Pinning Pin Definitions and Functions Pin Definitions and Functions Pin T/MQFP-64 16 55 41 Q-SMINTaI: 2B1Q Metallic Termination Input (MTI) Power Status (primary) (PS1) Power Status (secondary) (PS2) T-SMINTaI: 4B3T Tie to `1` Tie to `1` Tie to `1` Table 40 7.1.2 LED Pin ACT The 4 LED states (off, fast flashing, slow flashing, on), which can be displayed with pin ACT, are slightly different for Q- and T-SMINTaI (see Table 41). This adoption guarantees full compliance of T-SMINTaI to the new iNT specification TS 0284/96. Table 41 LED States Q-SMINTaI: 2B1Q off fast flashing slow flashing on VDD 8Hz (1 : 1)* 1Hz (1 : 1)* GND ACT States Pin ACT T-SMINTaI: 4B3T VDD 2Hz (1 : 1)* 1Hz (3 : 1)* GND Note: * denotes the duty cycle 'high' : 'low'. Data Sheet 179 2001-11-09 PEF 82902 Appendix: Differences between Q- and T-SMINTI 7.2 7.2.1 * U-Transceiver U-Interface Conformity Related Documents to the U-Interface Q-SMINTaI: 2B1Q T-SMINTaI: 4B3T conform to annex B conform to annex A compliant to 10 ms interruptions Table 42 ETSI: TS 102 080 ANSI: T1.601-1998 (Revision of ANSI T1.6011992) CNET: ST/LAA/ELR/DNP/ 822 RC7355E FTZ-Richtlinie 1 TR 220 conform not required MLT input and decode logic conform conform not required not required not required conform conform not required FTZ TS 0284/96 'Intelligenter Netzabschluss (iNT)' Marz 2001 Data Sheet 180 2001-11-09 PEF 82902 Appendix: Differences between Q- and T-SMINTI 7.2.2 * U-Transceiver State Machines T14S SN0 . T14E T14S TL Pending Timing DC T14S DI . SN0 Deactivated DC TIM DI AR or TL Any State SSP or C/I= 'SSP' SP Test DR . . SN0 IOM Awaked PU AR or TL SN0 Reset Any State Pin-RST or C/I= 'RES' DR ARL . DI DI & NT-AUTO T1S, T11S TN DC . Alerting PU T12S T1S T11S . TN Alerting 1 DR T11E T12S T1S, T11S T11E T12S SN1 . EC-Training AL DC LSEC or T12E LSUE or T1E . SN1 EC-Training DC SN0 SN1 DI . EC-Training 1 DR LSEC or T12E act=0 SN3 Wait for SF AL DC BBD1 & SFD EQ-Training DC T20S .. BBD0 & FD SN3T act=0 Analog Loop Back AR LSUE or T1E SN2 . T20E & BBD0 & SFD LOF Wait for SF DC DI dea=0 LSUE uoa=0 dea=0 LSUE uoa=0 dea=0 LSUE SN3/SN3T act=1/0 Pend.Deact. S/T DR LSUE 1) 3) dea=0 LOF SN3/SN3T act=0 Synchronized 1 1) DC uoa=1 LOF SN3/SN3T 1) act=0 Synchronized 2 2) AR/ARL Al LOF SN3/SN3T 1) act=1 Wait for Act El1 2) AR/ARL act=1 act=0 Any State DT or C/I='DT' LOF El1 act=1 SN3T Transparent 2) AI/AIL act=1 & Al uoa=0 dea=0 LSUE Yes . SN0 Pend Receive Res. T13S EI1 LSU or ( /LOF & T13E ) SN3/SN3T 1) act=0 Error S/T act=0 2) AR/ARL LOF dea=0 uoa=0 LSUE uoa=1 ? No dea=1 LOF SN3/SN3T act=1/0 3) Pend.Deact. U DC LSU 1) T7E & DI . SN0 Receive Reset DR T7S T7S TL Figure 74 NTC-Q Compatible State Machine Q-SMINTaI: 2B1Q Data Sheet 181 2001-11-09 PEF 82902 Appendix: Differences between Q- and T-SMINTI * T14S SN0 . T14E T14S TL Pending Timing DC T14S DI . SN0 Deactivated DC TIM DI AR or TL Any State SSP or C/I= 'SSP' SP Test DR . TIM . SN0 IOM Awaked PU AR or TL SN0 Reset Any State Pin-RST or C/I= 'RES' DR ARL . DI T1S, T11S TN Alerting PU T11E . T1S T11S . TN Alerting 1 DR T11E T1S, T11S T12S SN1 . EC-Training AL DR LSEC or T12E LSUE or T1E . SN1 EC-Training PU SN0 EQ-Training PU T12S DI or TIM . SN1 EC-Training 1 DR T12S LSEC or T12E act=0 SN3 Wait for SF AL DR BBD1 & SFD .. SN3T act=0 Analog Loop Back AR LSUE or T1E . SN2 Wait for SF PU T20E & BBD0 & SFD T20S BBD0 & FD LOF SN3/SN3T 1) act=1/0 3) Pend.Deact. S/T DR LSUE dea=0 LOF DI or TIM dea=0 LSUE uoa=0 dea=0 LSUE uoa=0 dea=0 LSUE SN3/SN3T 1) act=0 Synchronized 1 PU uoa=1 LOF SN3/SN3T act=0 Synchronized 2 2) AR/ARL Al 1) LOF SN3/SN3T 1) act=1 Wait for Act 2) El1 AR/ARL act=1 act=0 Any State DT or C/I='DT' LOF El1 act=1 SN3T Transparent 2) AI/AIL act=1 & Al uoa=0 dea=0 LSUE Yes . SN0 Pend Receive Res. T13S DR LSU or ( /LOF & T13E ) T7E & TIM T7E & DI SN3/SN3T 1) act=0 Error S/T act=0 2) AR/ARL LOF dea=0 uoa=0 LSUE uoa=1 ? No SN3/SN3T act=1/0 3) LOF Pend.Deact. U DR LSU 1) dea=1 . SN0 Receive Reset DR T7S T7S TL Figure 75 Data Sheet Simplified State Machine Q-SMINTaI: 2B1Q 182 2001-11-09 PEF 82902 Appendix: Differences between Q- and T-SMINTI * AWR U0 IOM Awaked DC AR T6S U1W Start Awaking Uk0 RSY T6S T6E U0 Awake Signal Sent RSY AWR T13S T13E U0 Ack. Sent / Received RSY (DI & T05E) T12S U1A Synchronizing RSY U2 (U0 & T12E) T05S U0 Pend. Deactivation DR T05S DT U1 SBC Synchronizing AR / ARL AI U0 LOF DI SP / U0 Test DR SSP or LTD ANY STATE RES DI U0 LOF U0 Reset DR AWT AWR T13S U1W Sending Awake-Ack. RSY T13S AWT T6S T05S T05S T05E U0 Deactivating DC AWR TIM AR U0 Deactivated DC U0, DA AWR DI U3 Wait for Info U4H AR / ARL U4H U0 U5 Transparent AI / AIL U0 LOF U0 Loss of Framing RSY NT_SM_4B3T_cust.emf Figure 76 IEC-T/NTC-T Compatible State Machine T-SMINTaI: 4B3T Both the Q- and the T-SMINTaI U-transceiver can be controlled via state machines, which are compatible to those defined for the old NT generation INTC-Q and NTC-T. Additionally, the Q-SMINTaI possesses a newly defined, so called `simplified` state machine. This simplified state machine can be used optionally instead of the INTC-Q compatible state machine and eases the U-transceiver control by software. Such a simplified state machine is not available for the T-SMINTaI. Data Sheet 183 2001-11-09 PEF 82902 Appendix: Differences between Q- and T-SMINTI 7.2.3 Table 43 Code Command/Indication Codes C/I Codes Q-SMINTaI: 2B1Q IN OUT DR - - - EI1 - - PU AR - ARL - AI - AIL DC T-SMINTaI: 4B3T IN TIM - - LTD - SSP DT - AR - - - AI RES - DI OUT DR - - - RSY - - - AR - ARL - AI - AIL DC 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 TIM RES - - EI1 SSP DT - AR - ARL - AI - - DI Data Sheet 184 2001-11-09 PEF 82902 Appendix: Differences between Q- and T-SMINTI 7.2.4 * Interrupt Structure M56R 7 0 MS2 MS1 NEBE M61 M52 M51 0 FEBE + OPMODE.MLT CRC, TLL, no Filtering MFILT + M4R 7 AIB UOA M46 M45 M44 SCO DEA 0 ACT MFILT M4RMASK 7 UCIR CRC, TLL, no Filtering C/I C/I C/I 0 C/I EOCR 15 MFILT 11 a1 a2 TLL, CHG, no Filtering ISTAU 7 MLT CI FEBE/ NEBE M56 M4 EOC 6ms 0 12ms MASKU MLT CI FEBE/ NEBE M56 M4 EOC 6ms 12ms 7 0 i8 ISTA U Reserved MASK interr_U_Q2.vsd 0 INT Figure 77 Interrupt Structure U-Transceiver Q-SMINTaI: 2B1Q Data Sheet 185 2001-11-09 PEF 82902 Appendix: Differences between Q- and T-SMINTI * UCIR 7 0 0 0 0 C/I C/I C/I 0 C/I ISTAU 7 0 CI RDS 0 0 0 0 0 1ms MASKU 1 CI RDS 1 1 1 1 1ms ISTA U S ... ... ... ... ... ... MASK intstruct_4b3t.emf INT Figure 78 Interrupt Structure U-Transceiver T-SMINTaI: 4B3T Data Sheet 186 2001-11-09 PEF 82902 Appendix: Differences between Q- and T-SMINTI 7.2.5 Register Summary U-Transceiver U-Interface Registers Q-SMINTaI: 2B1Q Name OPMODE 7 0 6 UCI 5 FEBE 4 MLT 3 0 2 CI_ SEL 1 0 0 0 ADDR R/W RES 60H 61H 62H a2 i6 a2 i6 a3 i7 a3 i7 d/m i8 d/m i8 63H 64H 65H 66H 67H 68H 69H 6AH FEBE FEBE 6BH 6CH 6DH 6EH 40 KHz 6FH LB1 70H 71H 72H 73H79H W R 0F FFH 01H 00H R*/W 00H R*/W A8H R BEH R*/W 14H R*/W 14H MFILT M56 FILTER M4 FILTER reserved EOC FILTER EOCR 0 i1 0 i2 0 i2 0 i3 0 i3 0 i4 0 i4 a1 i5 a1 i5 EOCW 0 i1 M4RMASK M4WMASK M4R M4W M56R M56W UCIR UCIW TEST 0 1 0 0 0 M4 Read Mask Bits M4 Write Mask Bits verified M4 bit data of last received superframe M4 bit data to be send with next superframe MS2 1 0 0 0 MS1 1 0 0 0 NEBE 1 0 0 0 CCRC M61 M61 M52 M52 M51 M51 R*/W BEH R W R W 1FH FFH 00H 01H C/I code output C/I code input +-1 Tones LBBD 0 R*/W 00H R*/W 08H R R 00H 00H LOOP FEBE NEBE 0 DLB TRANS U/IOMa 1 LB2 FEBE Counter Value NEBE Counter Value reserved Data Sheet 187 2001-11-09 PEF 82902 Appendix: Differences between Q- and T-SMINTI Name ISTAU 7 MLT 6 CI 5 FEBE/ NEBE FEBE/ NEBE 4 M56 3 M4 2 EOC 1 6ms 0 12ms ADDR R/W RES 7AH 7BH 7CH 7DH 7EH7FH R 6xH R 00H MASKU MLT CI M56 M4 EOC 6ms 12ms R*/W FFH reserved FW_ VERSION FW Version Number reserved Data Sheet 188 2001-11-09 PEF 82902 Appendix: Differences between Q- and T-SMINTI U-Interface Registers T-SMINTaI: 4B3T Name OPMODE 7 0 6 UCI 5 0 4 0 3 0 2 0 1 0 0 0 ADDR R/W RES 60H 61H6CH C/I code output C/I code input 6DH 6EH 6FH LBBD LB2 LB1 70H 71H 72H 73H79H 0 1 0 1 1 ms 1 ms 7AH 7BH 7CH 7DH 7EH7FH R 3xH R 00H R 00H R*/W 08H R W 00H 01H R*/W 00H reserved UCIR UCIW 0 0 0 0 0 0 0 0 reserved LOOP 0 0 TRANSU/IOMa 1 reserved RDS Block Error Counter Value reserved ISTAU MASKU 0 1 CI CI RDS RDS 0 1 0 1 R*/W FFH reserved FW_ VERSION FW Version Number reserved Data Sheet 189 2001-11-09 PEF 82902 Appendix: Differences between Q- and T-SMINTI 7.3 External Circuitry The external circuitry of the Q- and T-SMINTaI is equivalent; however, some external components of the U-transceiver hybrid must be dimensioned different for 2B1Q and 4B3T. All information on the external circuitry is preliminary and may be changed in future documents. * AOUT R3 RT BIN R4 RCOMP n C >1 RPTC Loop AIN R4 RCOMP RPTC R3 BOUT RT extcirc_U_Q2_exthybrid.emf Figure 79 External Circuitry Q- and T-SMINTaI Note: the necessary protection circuitry is not displayed in Figure 79. Table 44 Component Transformer: Ratio Main Inductivity Resistance Resistance Resistance Capacitor C RPTC and RComp Data Sheet Dimensions of External Components Q-SMINTaI: 2B1Q 1:2 14.5 mH 1.3 k 1.0 k 9.5 27 nF 2RPTC + 8RComp = 40 190 T-SMINTaI: 4B3T 1:1.6 7.5 mH 1.75 k 1.0 k 25 15 nF n2 x (2RCOMP + RB) + RL = 20 2001-11-09 PEF 82902 Index 8 A Index L Frame Structure 27 Functional Description 27 Absolute Maximum Ratings 160 Address Space 114 B Block Diagram 6 Block Error Counter 65 Layer 1 Activation / Deactivation 96 Loopbacks 104 LED Pins 12 Line Overload Protection 160 C C/I Channel Detailed Registers 124 Functional Description 49 C/I Codes S-Transceiver 85 U-Transceiver 66 Controller Data Access (CDA) 30 M Maintenance Channel 63 Microcontroller Clock Generation 23 Microcontroller Interfaces Interface Selection 16 Parallel Microcontroller Interface 21 Serial Control Interface (SCI) 16 Monitor Channel Detailed Registers 151 Error Treatment 45 Functional Description 41 Handshake Procedure 41 Interrupt Logic 48 Time-Out Procedure 48 D DC Characteristics 161 D-Channel Access Control Functional Description 51 State Machine 55 Differences between Q- and T-SMINT 178 O Oscillator Circuitry 113 E External Circuitry S-Transceiver 110 P Package Outlines 176 Parallel Microcontroller Interface AC-Characteristics 169 Functional Description 21 Pin Configuration 5 Pin Definitions and Functions 7 Power Consumption 163 Power Supply Blocking 108 Power-On Reset 26, 174 F Features 3 I Identification via Monitor Channel 47 via Register Access 139 Interrupts 114 IOM(R)-2 Interface AC Characteristics 166 Activation/Deactivation 57 Detailed Registers 140 R Register Summary 116 Reset Generation 23 191 2001-11-09 Data Sheet PEF 82902 Index Input Signal Characteristics 173 Power-On Reset 26, 174 Under Voltage Detection 26, 174 S S/Q Channels 81 Scrambler / Descrambler 66 Serial Control Interface (SCI) AC-Characteristics 168 Functional Description 16 Serial Data Strobe Signal 40 Stop/Go Bit Handling 53 S-Transceiver Detailed Registers 128 Functional Description 79 State Machine, LT-S 91 State Machine, NT 87 Supply Voltages 163 Synchronous Transfer 36 System Integration 13 T Test Modes 12 TIC Bus Handling 52 U U-Interface Hybrid 108 Under Voltage Detection 26, 174 U-Transceiver 4B3T Frame Structure 59 Detailed Registers 155 Functional Description 59 State Machine NT 67 W Watchdog Timer 25 Data Sheet 192 2001-11-09 Infineon goes for Business Excellence "Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction." Dr. Ulrich Schumacher http://www.infineon.com Published by Infineon Technologies AG |
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