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| MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Doc. No. 100723A June 21, 2000 Ordering Information Marketing Name Device Set Order No. Part No. MFC2000 xxx-xxx-xxx xxxxx Package Part No. Package Revision History Revision A A Date 04/07/00 06/21/00 Comments Initial, internal, preliminary release of document. Second internal, preliminary release with revisions tracked. (c) 2000, Conexant Systems, Inc. All Rights Reserved. Information in this document is provided in connection with Conexant Systems, Inc. ("Conexant") products. These materials are provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no responsibility for errors or omissions in these materials. Conexant may make changes to specifications and product descriptions at any time, without notice. Conexant makes no commitment to update the information contained herein. Conexant shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Conexant's Terms and Conditions of Sale for such products, Conexant assumes no liability whatsoever. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF CONEXANT PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Conexant further does not warrant the accuracy or completeness of the information, text, graphics or other items contained within these materials. Conexant shall not be liable for any special, indirect, incidental, or consequential damages, including without limitation, lost revenues or lost profits, which may result from the use of these materials. Conexant products are not intended for use in medical, life saving or life sustaining applications. Conexant customers using or selling Conexant products for use in such applications do so at their own risk and agree to fully indemnify Conexant for any damages resulting from such improper use or sale. The following are trademarks of Conexant Systems, Inc.: Conexant, the Conexant C symbol, "What's Next in Communications Technologies", and SmartDAA. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners. Reader Response: Conexant strives to produce quality documentation and welcomes your feedback. Please send comments and suggestions to conexant.tech.pubs@conexant.com. For technical questions, contact your local Conexant sales office or field applications engineer. ii Conexant 100723A Contents 1. INTRODUCTION .............................................................................................................................................. 1-1 1.1 SCOPE ...................................................................................................................................................... 1-1 1.2 SYSTEM OVERVIEW ................................................................................................................................ 1-1 1.3 REFERENCE DOCUMENTATION............................................................................................................ 1-5 2. MFC2000 SUMMARY ...................................................................................................................................... 2-1 2.1 MFC2000 DEVICE FAMILY....................................................................................................................... 2-1 2.2 MFC2000 SYSTEM BLOCK DIAGRAM .................................................................................................... 2-1 3. HARDWARE INTERFACE............................................................................................................................... 3-1 3.1 PIN DESCRIPTION ................................................................................................................................... 3-1 3.2 MAXIMUM RATINGS................................................................................................................................. 3-7 3.3 ELECTRICAL CHARACTERISTICS.......................................................................................................... 3-8 3.4 PIN LAYOUT............................................................................................................................................ 3-10 4. CPU AND BUS INTERFACE ........................................................................................................................... 4-1 4.1 MEMORY MAP AND CHIP SELECT DESCRIPTION ............................................................................... 4-1 4.2 CACHE MEMORY CONTROLLER.......................................................................................................... 4-19 4.3 SIU.......... ............................................................................................................................................... 4-24 4.4 INTERRUPT CONTROLLER................................................................................................................... 4-46 4.5 DRAM CONTROLLER (INCLUDING BATTERY DRAM) ........................................................................ 4-54 4.6 FLASH MEMORY CONTROLLER........................................................................................................... 4-72 4.7 DMA CONTROLLER ............................................................................................................................... 4-76 5. RESET LOGIC/BATTERY BACKUP/WATCH DOG TIMER........................................................................... 5-1 5.1 RESET LOGIC/BATTERY BACKUP ......................................................................................................... 5-1 5.2 WATCHDOG TIMER ............................................................................................................................... 5-11 6. FAX TIMING CONTROL INTERFACE ............................................................................................................ 6-1 6.1 PLL.............. ............................................................................................................................................ 6-1 6.2 FAX TIMING LOGIC .................................................................................................................................. 6-2 6.3 MFC2000 TIMING CHAIN ......................................................................................................................... 6-3 6.4 SCAN CONTROL TIMING......................................................................................................................... 6-4 6.5 FAX TIMING REGISTERS......................................................................................................................... 6-5 7. VIDEO/SCANNER CONTROLLER ................................................................................................................. 7-1 7.1 SCANNER CONTROLLER........................................................................................................................ 7-2 7.2 SERIAL PROGRAMMING INTERFACE.................................................................................................. 7-41 7.3 VIDEO CONTROLLER ............................................................................................................................ 7-50 8. ADC................................................................................................................................................................. 8-1 8.1 PADC AND SCAN ANALOG FRONT END ............................................................................................... 8-1 8.2 TADC......................... ........................................................................................................................... 8-5 100723A Conexant iii 9. BI-LEVEL RESOLUTION CONVERSION ....................................................................................................... 9-1 9.1 FUNCTIONAL DESCRIPTION .................................................................................................................. 9-1 9.2 REGISTER DESCRIPTION ....................................................................................................................... 9-6 9.3 RESOLUTION CONVERSION PROGRAMMING EXAMPLES............................................................... 9-15 10. EXTERNAL PRINT ASIC INTERFACE ......................................................................................................... 10-1 10.1 INTERFACE BETWEEN THE MFC2000 AND EXTERNAL PRINT ASIC .......................................... 10-1 11. BIT ROTATION LOGIC.................................................................................................................................. 11-1 11.1 11.2 11.3 11.4 FUNCTIONAL DESCRIPTION ............................................................................................................ 11-1 BLOCK DIAGRAM............................................................................................................................... 11-3 REGISTER DESCRIPTION................................................................................................................. 11-6 FIRMWARE OPERATION................................................................................................................. 11-10 12. PRINTER AND SCANNER STEPPER MOTOR INTERFACE ...................................................................... 12-1 12.1 12.2 VERTICAL PRINT STEPPER MOTOR INTERFACE ......................................................................... 12-1 SCANNER STEPPER MOTOR INTERFACE ..................................................................................... 12-5 13. GENERAL PURPOSE INPUTS/OUTPUTS (GPIO) ...................................................................................... 13-1 13.1 13.2 13.3 GPIO SIGNALS ................................................................................................................................... 13-1 GPO/GPI SIGNALS............................................................................................................................. 13-5 GPIO CONTROL AND DATA REGISTERS........................................................................................ 13-6 14. COMPRESSOR AND DECOMPRESSOR..................................................................................................... 14-1 14.1 14.2 FUNCTIONAL DESCRIPTION ............................................................................................................ 14-1 REGISTER DESCRIPTION................................................................................................................. 14-2 15. SYNCHRONOUS/ASYNCHRONOUS SERIAL INTERFACE (SASIF) ......................................................... 15-1 15.1 15.2 15.3 15.4 FUNCTIONAL DESCRIPTION ............................................................................................................ 15-1 REGISTER DESCRIPTION................................................................................................................. 15-3 SASIF TIMING................................................................................................................................... 15-12 FIRMWARE OPERATION................................................................................................................. 15-16 16. USB INTERFACE .......................................................................................................................................... 16-1 16.1 16.2 16.3 FUNCTION DESCRIPTION ................................................................................................................ 16-1 REGISTER DESCRIPTION................................................................................................................. 16-1 FIRMWARE OPERATION................................................................................................................. 16-23 17. BI-DIRECTIONAL PARALLEL PERIPHERAL INTERFACE........................................................................ 17-1 17.1 17.2 17.3 17.4 17.5 17.6 OPERATIONAL MODES..................................................................................................................... 17-1 ADDITIONAL FEATURES................................................................................................................... 17-2 FUNCTIONAL DESCRIPTION ............................................................................................................ 17-3 REGISTER DESCRIPTION................................................................................................................. 17-4 TIMING .............................................................................................................................................. 17-16 FIRMWARE OPERATION................................................................................................................. 17-22 iv Conexant 100723A 18. REAL-TIME CLOCK ...................................................................................................................................... 18-1 18.1 18.2 18.3 DESCRIPTION .................................................................................................................................... 18-1 REAL-TIME CLOCK (RTC) REGISTERS ........................................................................................... 18-2 RTC OPERATIONS............................................................................................................................. 18-3 19. SYNCHRONOUS SERIAL INTERFACE (SSIF)............................................................................................ 19-1 19.1 19.2 19.3 INTRODUCTION AND FEATURES .................................................................................................... 19-1 REGISTER DESCRIPTION................................................................................................................. 19-2 SSIF TIMING ....................................................................................................................................... 19-7 20. PROGRAMMABLE TONE GENERATORS .................................................................................................. 20-1 20.1 20.2 20.3 INTRODUCTION ................................................................................................................................. 20-1 BELL/RINGER GENERATOR ............................................................................................................. 20-1 TONE GENERATOR........................................................................................................................... 20-6 21. PWM LOGIC .................................................................................................................................................. 21-1 21.1 21.2 FUNCTIONAL DESCRIPTION ............................................................................................................ 21-1 REGISTER DESCRIPTION................................................................................................................. 21-2 22. CALLING PARTY CONTROL (CPC) ............................................................................................................ 22-1 22.1 REGISTERS DESCRIPTION .............................................................................................................. 22-5 23. SSD_P80 ........................................................................................................................................................ 23-1 23.1 23.2 23.3 FUNCTION DESCRIPTION ................................................................................................................ 23-1 REGISTER DESCRIPTION................................................................................................................. 23-3 FIRMWARE OPERATION................................................................................................................... 23-6 24. COUNTACH IMAGING DSP BUS SUBSYSTEM ......................................................................................... 24-1 24.1 24.2 24.3 24.4 24.5 24.6 24.7 24.8 COUNTACH IMAGING DSP SUBSYSTEM........................................................................................ 24-3 COUNTACH IMAGING DSP BUS UNIT ............................................................................................. 24-4 ARM BUS INTERFACE....................................................................................................................... 24-8 COUNTACH IMAGING DSP SUBSYSTEM INTERFACE ................................................................ 24-11 COUNTACH DMA CONTROLLER.................................................................................................... 24-12 VIDEO/SCANNER INTERFACE ....................................................................................................... 24-22 (S)DRAM CONTROLLER ((S)DRAMC) ............................................................................................ 24-23 REGISTER DESCRIPTION............................................................................................................... 24-28 25. CONFIGURATION ......................................................................................................................................... 25-1 25.1 25.2 HARDWARE VERSION ...................................................................................................................... 25-1 PRODUCT CODE ............................................................................................................................... 25-1 100723A Conexant v Figures Figure 1-1. MFP System Diagram Using MFC2000 .............................................................................................................. 1-1 Figure 1-2: MFC2000 Function Diagram ............................................................................................................................... 1-4 Figure 2-1. MFC2000 Organization ....................................................................................................................................... 2-2 Figure 3-1. MFC2000 BGA Bottom View ............................................................................................................................. 3-10 Figure 4-1. MFC2000 Memory Map....................................................................................................................................... 4-6 Figure 4-2. MFC2000 Internal Memory Map.......................................................................................................................... 4-7 Figure 4-3. MFC2000 Cache Organization .......................................................................................................................... 4-19 Figure 4-4. 2-Way Interleave ROM Connection................................................................................................................... 4-26 Figure 4-5. Zero Wait State, Single Access, Normal Read, Normal Write ........................................................................... 4-36 Figure 4-6. One Wait State, Single Access, One Read, One Write ..................................................................................... 4-37 Figure 4-7. Two Wait States, Single Access, Read On Delayed (CS1n), Write Early Off (CS2n)........................................ 4-38 Figure 4-8. Zero Wait State, Burst Access, Normal Read, Normal Write............................................................................. 4-39 Figure 4-9. Fast Page Mode ROM Access1,0,0 Read Access Followed by 1,1,1,1, Write Access.................................. 4-40 Figure 4-10. System Bus TimingRead/Write with Wait States ......................................................................................... 4-41 Figure 4-11. System Bus TimingZero-Wait-State Read/Write.......................................................................................... 4-42 Figure 4-12. System Bus Timing2-Way Interleave Read Timing (S = 1).......................................................................... 4-43 Figure 4-13. System Bus Timing2-Way Interleave Write Timing (S = 0 or 1)................................................................... 4-44 Figure 4-14. External Interrupt Request Timing................................................................................................................... 4-54 Figure 4-15. DRAM Bank/Address Map............................................................................................................................... 4-56 Figure 4-16. Simplified DRAM Controller Block Diagram .................................................................................................... 4-59 Figure 4-17. DRAM Interface Example ................................................................................................................................ 4-60 Figure 4-18. 8-bit Memory Data Bus.................................................................................................................................... 4-65 Figure 4-19. 16-bit Memory Data Bus.................................................................................................................................. 4-65 Figure 4-20. CASn Non-Interleaved 8-bit DRAM Read........................................................................................................ 4-66 Figure 4-21. 2-Way Interleaved Memory with Halfword Bursts of Data ............................................................................... 4-66 Figure 4-22. 2-Way Interleaved DRAM Read (3 words) ...................................................................................................... 4-67 Figure 4-23. 2-Way Interleaved DRAM Write ...................................................................................................................... 4-67 Figure 4-24. Refresh Cycle.................................................................................................................................................. 4-68 Figure 4-25. DRAM TimingRead, Write and Wait States for Non-interleave Mode .......................................................... 4-68 Figure 4-26. DRAM Timing for 2-way Interleave Write ........................................................................................................ 4-69 Figure 4-27. DRAM TimingRead for 2-way interleave mode............................................................................................ 4-69 Figure 4-28. DRAM Refresh Timing .................................................................................................................................... 4-70 Figure 4-29. DRAM Battery Refresh Timing ........................................................................................................................ 4-70 Figure 4-30. Flash Control Block Diagram........................................................................................................................... 4-73 Figure 4-31. NAND-Type Flash Memory Access with Two Wait States .............................................................................. 4-75 Figure 4-32: External DMA Read Timing (Single Access, One Wait State) ......................................................................... 4-80 Figure 4-33. External DMA Write Timing (Single Access, One Wait State) ......................................................................... 4-81 Figure 4-34. USB Logical Channels Block Diagram ............................................................................................................ 4-82 Figure 5-1. Power Reset Block Diagram................................................................................................................................ 5-2 vi Conexant 100723A Figure 5-2. Power-down Select Logic .................................................................................................................................... 5-3 Figure 5-3. Power Reset Timing Diagram.............................................................................................................................. 5-5 Figure 5-4. +5v Prime Power Signal and VGG ...................................................................................................................... 5-6 Figure 5-5. Internal Power Detection ................................................................................................................................... 5-10 Figure 5-6. Figure Caption Required ................................................................................................................................... 5-10 Figure 5-7. Voltage Divider Circuit....................................................................................................................................... 5-11 Figure 5-8. Watchdog Timer Block Diagram........................................................................................................................ 5-12 Figure 5-9. Watchdog Time-Out Timing Diagram ................................................................................................................ 5-13 Figure 6-1. Fax Timing Control Logic Block Diagram ............................................................................................................ 6-2 Figure 6-2. MFC2000 Timing Chain ...................................................................................................................................... 6-3 Figure 6-3. Scan Control Timing............................................................................................................................................ 6-4 Figure 7-1. Video/Scanner Controller Block Diagram ............................................................................................................ 7-1 Figure 7-2. Untitled Timing Diagram .................................................................................................................................... 7-19 Figure 7-3. Untitled Timing Diagram .................................................................................................................................... 7-20 Figure 7-4. Untitled Timing Diagram .................................................................................................................................... 7-20 Figure 7-5. Untitled Timing Diagram .................................................................................................................................... 7-21 Figure 7-6. Untitled Timing Diagram .................................................................................................................................... 7-22 Figure 7-7. Untitled Timing Diagram .................................................................................................................................... 7-23 Figure 7-8. Untitled Timing Diagram .................................................................................................................................... 7-23 Figure 7-9. Untitled Timing Diagram .................................................................................................................................... 7-24 Figure 7-10. Untitled Timing Diagram .................................................................................................................................. 7-24 Figure 7-11. Untitled Timing Diagram .................................................................................................................................. 7-24 Figure 7-12. Untitled Timing Diagram .................................................................................................................................. 7-25 Figure 7-13. Untitled Timing Diagram .................................................................................................................................. 7-25 Figure 7-14. Untitled Timing Diagram .................................................................................................................................. 7-26 Figure 7-15. Untitled Timing Diagram .................................................................................................................................. 7-28 Figure 7-16. Untitled Timing Diagram .................................................................................................................................. 7-30 Figure 7-17. Untitled Timing Diagram .................................................................................................................................. 7-32 Figure 7-18. Untitled Timing Diagram .................................................................................................................................. 7-34 Figure 7-19. Untitled Timing Diagram .................................................................................................................................. 7-36 Figure 7-20. Untitled Timing Diagram .................................................................................................................................. 7-38 Figure 7-21. External circuit required for SONY-ILX516K interface .................................................................................... 7-40 Figure 7-22. LED timing for SONY-ILX516K....................................................................................................................... 7-40 Figure 7-23. Serial Programming Interface, Physical Connection ....................................................................................... 7-41 Figure 7-24. Bus Protocol .................................................................................................................................................... 7-42 Figure 7-25. Serial Programming Interface, Timing Diagram............................................................................................... 7-42 Figure 7-26. Stretching the Low Period of the Clock ........................................................................................................... 7-44 Figure 7-27. Firmware OperationTransmission................................................................................................................ 7-48 Figure 7-28. Firmware OperationReception ..................................................................................................................... 7-49 Figure 7-29. Connection to External Video Capture Device ................................................................................................ 7-51 Figure 7-30. Untitled Timing Diagram .................................................................................................................................. 7-54 100723A Conexant vii Figure 7-31. DMA Operation................................................................................................................................................ 7-55 Figure 8-1. Untitled Figure ..................................................................................................................................................... 8-1 Figure 9-1: Bi-level Resolution Conversion Block Diagram ................................................................................................... 9-2 Figure 9-2. The Physical Nozzle Diagram for Typical Inkjet Heads ....................................................................................... 9-5 Figure 9-3. Untitled Figure ..................................................................................................................................................... 9-5 Figure 9-4: Resolution Conversion Programming................................................................................................................ 9-15 Figure 10-1. Print ASIC Interface......................................................................................................................................... 10-2 Figure 11-1. Nozzle Diagram of a Typical Programmable Inkjet Head ................................................................................ 11-1 Figure 11-2. Examples of Nozzle Head Configurations ....................................................................................................... 11-2 Figure 11-3. Nozzle Configuration by Bit Rotation Block (Regardless of Physical Nozzle Configuration) ........................... 11-2 Figure 11-4. MFC2000 Bit Rotation Block Diagram............................................................................................................. 11-3 Figure 11-5. Fetcher DMA Channel Fetch Order................................................................................................................. 11-4 Figure 11-6. CPU Background Print Data Preparation ...................................................................................................... 11-12 Figure 11-7. MFC2000 Little-Endian Format ..................................................................................................................... 11-13 Figure 12-1. Vertical Printer Motor Control Block Diagram .................................................................................................. 12-1 Figure 12-2. Stepping Timing .............................................................................................................................................. 12-2 Figure 12-3. Scan Motor Control Diagram ........................................................................................................................... 12-5 Figure 12-4. Stepping Timing .............................................................................................................................................. 12-7 Figure 12-5: Current Control Diagram ................................................................................................................................. 12-9 Figure 14-1. Data Flow for Compression/Decompression ................................................................................................... 14-1 Figure 14-2. Compressor/Decompressor FIFO Structure .................................................................................................... 14-2 Figure 15-1. SASIF Block Diagram...................................................................................................................................... 15-2 Figure 15-2. SASSCLK Timing Diagram............................................................................................................................ 15-12 Figure 15-3. Synchronous Mode Timing............................................................................................................................ 15-13 Figure 15-4. Asynchronous Transmitter Timing................................................................................................................. 15-14 Figure 17-1. Parallel Port Interface Controller Block Diagram ............................................................................................. 17-3 Figure 17-2. Compatibility Mode Timing Diagram.............................................................................................................. 17-16 Figure 17-3. Nibble Mode Data Transfer Cycle ................................................................................................................. 17-17 Figure 17-4. BYTE Mode Data Transfer Cycle .................................................................................................................. 17-18 Figure 17-5. ECP Mode Timing Diagram........................................................................................................................... 17-19 Figure 17-6. Reverse ECP Transfer Timing....................................................................................................................... 17-20 Figure 17-7. Error Cycle Timing Diagram .......................................................................................................................... 17-21 Figure 18-1. RTC Block Diagram......................................................................................................................................... 18-1 Figure 19-1. SSIF Block Diagram ........................................................................................................................................ 19-1 Figure 19-2. SSCLK1 Diagram ............................................................................................................................................ 19-3 Figure 19-3. SSCLK2 Diagram ............................................................................................................................................ 19-6 Figure 19-4. Timing Diagram ............................................................................................................................................... 19-8 Figure 20-1. Bell/Ringer Timing ........................................................................................................................................... 20-1 Figure 20-2. Bell/Ringer Block Diagram .............................................................................................................................. 20-2 Figure 20-3. Bell/Ringer Generator Waveform .................................................................................................................... 20-3 Figure 20-4. Tone Generator Frequency Change................................................................................................................ 20-6 viii Conexant 100723A Figure 22-1: CPC Signal...................................................................................................................................................... 22-1 Figure 22-2. CPC Operation Flowchart ............................................................................................................................... 22-2 Figure 22-3: CPC Operation (with CPCThreshold = 4)........................................................................................................ 22-3 Figure 22-4: CPC Block Diagram ........................................................................................................................................ 22-4 Figure 23-1. System Configuration One .............................................................................................................................. 23-1 Figure 23-2. System Configuration Two .............................................................................................................................. 23-2 Figure 23-3. System Configuration Three............................................................................................................................ 23-2 Figure 24-1. The ARM Bus System Block Diagram............................................................................................................. 24-2 Figure 24-2. SDRAM Setup and Hold Timing .................................................................................................................... 24-29 Figure 24-3. SDRAM Read or Write Timing....................................................................................................................... 24-30 Figure 24-4. SDRAM Mode Timing.................................................................................................................................... 24-30 Figure 24-5. SDRAM Refresh Timing ................................................................................................................................ 24-30 Figure 24-6. FPDRAM Timing (Read or Write) .................................................................................................................. 24-31 Figure 24-7. FPDRAM Timing (Refresh)............................................................................................................................ 24-33 100723A Conexant ix Tables Table 1-1. Reference Documentation.................................................................................................................................... 1-5 Table 2-1. MFC2000 Device Family ...................................................................................................................................... 2-1 Table 3-1. Pin Description (1 of 6) ......................................................................................................................................... 3-1 Table 3-2. Maximum Ratings................................................................................................................................................. 3-7 Table 3-3. Digital Input Characteristics .................................................................................................................................. 3-8 Table 3-4. Output Characteristics .......................................................................................................................................... 3-8 Table 3-5. Power Supply Requirements ................................................................................................................................ 3-9 Table 3-6. Battery Power Supply Current Requirements....................................................................................................... 3-9 Table 4-1. Fixed-Location and Size Chip Selects .................................................................................................................. 4-4 Table 4-2. Operation Register Map (1 of 9) ........................................................................................................................... 4-8 Table 4-3. Setup Registers (1 of 2)...................................................................................................................................... 4-17 Table 4-4. Cache Tag Data Format (for Test Mode Read/Write Operation) ........................................................................ 4-20 Table 4-5. Access Modes for Reading ROM ....................................................................................................................... 4-27 Table 4-6. Read Operation (Internal Peripheral Gets Data From Memory) ......................................................................... 4-29 Table 4-7. Write Operation (Internal Peripheral Puts Data Into Memory) ............................................................................ 4-29 Table 4-8. Read/Write with Wait States Timing Parameters................................................................................................ 4-45 Table 4-9. MFC2000 Interrupt and Reset Signals ............................................................................................................... 4-46 Table 4-10. Programmable Resolution of Timer1 and Timer2 ............................................................................................. 4-53 Table 4-11. DRAM Wait State Configurations ..................................................................................................................... 4-55 Table 4-12. Address MultiplexingPart 1 ........................................................................................................................... 4-57 Table 4-13. Address MultiplexingPart 2 ........................................................................................................................... 4-57 Table 4-14. DRAM Row/Column Configuration ................................................................................................................... 4-58 Table 4-15. DRAM Timing Parameters................................................................................................................................ 4-71 Table 4-16. Feature Matrix .................................................................................................................................................. 4-77 Table 4-17. DMA Channel Functions and Characteristics ................................................................................................... 4-78 Table 4-18 DMA Channel 3 Control Bit Sssignment............................................................................................................ 4-79 Table 6-1. Operation Mode Frequencies ............................................................................................................................... 6-1 Table 7-1. Register setup for Rohm-IA3008-ZE22............................................................................................................. 7-27 Table 7-2. Register setup for Dyna-DL507-07UAH............................................................................................................ 7-29 Table 7-3. Register setup for Mitsubishi-GT3R216.............................................................................................................. 7-31 Table 7-4. Register Setup for Toshiba-CIPS218MC300 ..................................................................................................... 7-33 Table 7-5. Register Setup for NEC - PD3724 ................................................................................................................... 7-35 Table 7-6. Register setup for NEC - PD3794.................................................................................................................... 7-37 Table 7-7. Register Setup for SONY - ILX516K.................................................................................................................. 7-39 Table 8-1. Untitled Table ....................................................................................................................................................... 8-2 Table 8-2. Untitled Table ....................................................................................................................................................... 8-2 Table 8-3. Offset Adjustment on DAC ................................................................................................................................... 8-2 Table 8-4. Programmable Gain Amplifier (PGA).................................................................................................................... 8-3 Table 8-5. Pipelined ADC (PADC)......................................................................................................................................... 8-4 x Conexant 100723A Table 8-6. PADC Timing Diagram ......................................................................................................................................... 8-4 Table 8-7. TADC Block Diagram ........................................................................................................................................... 8-5 Table 9-1. Untitled Table ....................................................................................................................................................... 9-2 Table 9-2: Procedure to determine Pixels to remove........................................................................................................... 9-17 Table 9-3: Resolution Conversion Examples....................................................................................................................... 9-17 Table 12-1. Full Step/Single Phase Excitation..................................................................................................................... 12-3 Table 12-2. Full Step/Two Phase Excitation ........................................................................................................................ 12-3 Table 12-3. Half-Step Excitation .......................................................................................................................................... 12-3 Table 12-4. Full Step/Single Phase Excitation..................................................................................................................... 12-7 Table 12-5. Full Step/Two Phase Excitation ........................................................................................................................ 12-7 Table 12-6. Half-Step Excitation .......................................................................................................................................... 12-8 Table 18-1. RTC Crystal Specifications for 32.768 kHz....................................................................................................... 18-4 Table 20-1. Bell/Ringer Setting............................................................................................................................................ 20-2 Table 23-1. SSD Registers .................................................................................................................................................. 23-4 Table 23-2. P80 CORE Registers........................................................................................................................................ 23-5 Table 24-1. Needs a title.................................................................................................................................................... 24-11 Table 24-2. DMA Channels: Functionality and Priorities ................................................................................................... 24-12 Table 24-3. DMA Parameters Scratch Pad Addresses...................................................................................................... 24-13 Table 24-4: Supported FPDRAM Chip Characteristics...................................................................................................... 24-23 Table 24-5: Supported SDRAM Chip Characteristics ........................................................................................................ 24-23 Table 24-6. Untitled table................................................................................................................................................... 24-25 Table 24-7. Untitled table................................................................................................................................................... 24-26 Table 24-8. Untitled table................................................................................................................................................... 24-26 Table 24-9. SDRAM Setup and Hold Timing ..................................................................................................................... 24-29 Table 24-10. Timing Parameters for 16-bit SDRAM Read and Write ................................................................................ 24-31 Table 24-11. Timing Parameters for 8-bit SDRAM Read and Write .................................................................................. 24-31 Table 24-12. 60ns Timing .................................................................................................................................................. 24-32 Table 24-13. 50ns Timing .................................................................................................................................................. 24-32 Table 24-14. FPDRAM Timing (Refresh)........................................................................................................................... 24-33 100723A Conexant xi This page is intentionally blank xii Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 1. Introduction 1.1 Scope This document defines and describes all hardware functions of the MFC2000 chip. The MFC2000 design is based on the MFC1000 design with many minor modifications/enhancements. It has several new key functions to accomplish the following: * * * * Support a full color MFP Enhance connectivity to the PC Provide an internal Fax Modem Connect to external Conexant video chips 1.2 System Overview The Conexant Multi-Functional Peripheral Controller 2000 (MFC2000) device set hardware, core code, application code, and evaluation system comprise a full color Multi-Functional Peripheral (MFP) system-needing only a power supply, scanner, printer mechanism, and paper path components to complete the machine. The standard device set hardware includes Conexant's MFC2000 chip, Conexant's SmartDAA or IA chip, and a Printer Interface chip. Optionally, a Conexant video chip with VIP interface can be used to support the video capture function. If V.17 or V.34 faxing without voice is required, the internal V.17/V.34 Fax Modem in the MFC2000 chip is used and the MFC2000 is connected to the external Conexant SmartDAA or IA chip. If the voice/speech function is required, the external Voice Fax Modem device from Conexant will be needed. Any other external interface device can be supported by using the external ARM for CPU and DMA accesses or by using the internal serial interface. An MFP system-level block diagram using the MFC 2000 is illustrated in Figure 1-1. Operator Panel module Prime power/ Battery power hybrid and power down circuit VDD Battery Serial Interface (sync.) SPI and VIP Interface MFC2000 (Conexant) Conexant Proprietary Interface Video Chip (Conexant) NTSC /PAL Video Camera PC USB Interface or P1284 Interface Color Scanner module Scanner Interface SmartDAA (Conexant) Telephone Line (Color Faxing) Program ROM/Flash Memory Video/Scan SDRAM/DRAM External ARM Bus Data DRAM/SRAM/Flash Memory Printer IF (Conexant) Color Inkjet Printer Figure 1-1. MFP System Diagram Using MFC2000 100723A Conexant 1-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 1.2.1 Integrated Full Color MFP Controller (MFC2000) The MFC2000 provides the majority of the electronics necessary to build a color scan and color inkjet printer based MFP whose electronics are integrated into a one-chip solution including one CPU (ARM7TDMI) and two DSPs (Countach Imaging DSP subsystem and P80 core). Full printer and copier functionality is provided by the following: * * * * * * * * * 1284 parallel port interface USB serial port interface Color scanner interface/controller Countach Imaging DSP subsystem for video/scan/compression process Flash memory controller SDRAM/DRAM controllers Resolution conversion logic Inkjet data formatter External inkjet printing In addition, the MFC2000 performs facsimile control/monitoring, compression/decompression, and 33.6 Kbps Fax Modem functions (P80 core). The MFC2000 interfaces with major MFP machine components like external modems, SmartDAA, external Fax IA, motors, sensors, external video chip, and operator control panel. The ARM7TDMI-embedded processor provides an external 48-MB direct memory access capability. An integrated 12-bit Pipeline ADC (PADC) and countach subsystem (DSP subsystem, combined with an advanced Conexant proprietary color image processing algorithm, provides state of the art image processing performance on any type of images, including text/half-tone and color images. The full color MFP Engine provides the hardware and software necessary to develop a full-color Multifunctional Peripheral including an architecture for color printing, color faxing, color scanning, video capturing, and color copying. It also supports many of these operations concurrently. 1.2.1.1 Printing The MFC2000 Controller supports color inkjet printing. Print speed throughput capabilities are inversely proportional to resolution and also depend on the external printer interface. For host printing, the host sends the image data with the print resolution; the MFC2000 performs no resolution conversion. If host printing and faxing need to be performed for the same image, the printing image data must be sent to the MFP. The MFC2000 converts the printing image data to the faxing image data locally and then faxes it out. An external printer interface chip is designed to support inkjet print mechanism/head subsystems. Different external printer interface chips can be designed and used to support other inkjet mechanisms and heads according to customer requirements. 1.2.1.2 Faxing Both host-based color faxing and standalone color faxing are supported in addition to monochrome faxing. Hostbased faxing can take place by using a Class One connection via the USB serial port or the P1284 parallel port. For host faxing, the host sends the image data with the fax resolution; the MFC2000 performs no resolution conversion. For standalone faxing, the resolution conversion is supported by the MFC2000. The standalone color scan-to-fax function is supported using the advanced Conexant proprietary color image processing technology: * * * * * * * 1-2 Shading correction Gamma correction Pixel-based dark-level correction Color/monochrome image processing Color conversion JPEG Multi-level resolution conversion. Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 1.2.1.3 Scanning For the color scan-to-PC function, up to 8 bits of scan data per pixel can be sent to the host. JPEG compression can be used to reduce the PC upload speed. 1.2.1.4 Copying The MFC2000 and associated firmware supports several modes of copying including standard, fine, superfine, and photo. Multiple copies of a single image can be made with a single pass. The standalone color/monochrome copy function is supported by using MFC2000's Inkjet print formatter, the external printer interface, and the advanced Conexant proprietary color image processing system. 1.2.2 MFC2000 Evaluation System The Conexant MFC2000 Evaluation System provides demonstration, prototype development, and evaluation capabilities to full color MFP developers using the MFC2000 Engine device set. The MFC2000 Evaluation system provides flexibility for visibility and access, i.e., plug-on board for the modem, sockets for programmable parts, and connectors for an emulator (refer to Figure 1-2). Jumper options and test points are provided throughout the MFC2000 evaluation Main Board. The MFC2000 Evaluation System is the most convenient environment for the developer needing to experiment with the several interfaces encountered in the full color MFP, for example, color printer functions. 1.2.3 * * * * * * * * * * * New Function Highlights PLL Clock Generation for several different clocks needed for ARM CPU, Countach Imaging DSP, Fax Modem core, and USB Interface 4 KB 2-way Set Associative Instruction Cache USB Interface (including USB Transceiver) to PC Video/ Color Scan Controller (up to 600 dpi) (including programmable ADC sampling rate) Countach Imaging DSP Subsystem for pixel-based dark level correction, shading correction, gamma correction, video/color scan image processing, color science and JPEG Countach Bus System which includes Countach Subsystem Interface, ARM Bus Interface, Video/Scan Interface, Countach Bus Unit, Countach DMA Controller, and SDRAM Controller. SmartDAA/IA Interface P80 Core + ARM IPB interface logic (V.34 Fax Modem core) Two Sync. Serial Interfaces Color Scan IA which includes Color Scan analog Front End, 12-bit PADC, Power-down Voltage Detection Circuit, and TADC reference voltage. SPI and VIP interface to the external Conexant video chip 100723A Conexant 1-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description MFC2000 32 ARM7TDMI DMA Controller Cache Controller and Memory (4KB) 30 MHz, 37.5 MHz, or 40 MHz PLL 100 MHz or 85.7 MHz 32 SIU All logic blocks on the internal system bus from MFC1000 External ARM Bus 16 28.224 MHz 48 MHz for USB 28.224 MHz for Modem Internal Peripheral Bus 16 P80 Core External System Memory Countach Bus System Countach Subsystem (for Video/Scan Image Processing) ARM IPB IF Mono and Color CIS/ CCD Control Video/Scan Controller Smart DAA IF Scanner In Analog Frontend 12-bit PADC Countach Subsystem IF Video Countach A R M /Scan Bus Unit Bus IF IF CDMAC SDRAMC P1284 IF USB IF 2 DMA channels for the ARM Bus System NTSC/ PAL Signal External Conexant Video Chip SPI VIP 16 or 8 External Local (S)DRAM Figure 1-2: MFC2000 Function Diagram 1-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 1.3 Reference Documentation Table 1-1. Reference Documentation Document MFC2000 Data Sheet MFC2000 Firmware Architecture MFC2000 Hardware Description (this document) MFC2000 Programmer's Reference Manual Number 100505 100972 100723 100971 100723A Conexant 1-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description This page is intentionally blank 1-6 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 2. MFC2000 Summary 2.1 MFC2000 Device Family The MFC2000 contains an internal 32-bit RISC Processor with 64-MB address space, the Countach Imaging DSP (Conexant's DSP) subsystem including embedded data and program memory, and dedicated circuitry optimized for color scanning, color faxing, color copying, color printing, and multifunctional control and monitoring. The device family with relevant features is described in Table 2-1. Table 2-1. MFC2000 Device Family Device No. CX0720X-11 CX0720X-12 CX0720X -13 CX0720X -14 CX0720X-15 Product Code BFH BDH BBH B9H B8H Data Modem Function Yes Yes No No No Voice Codec/Speaker Phone Functions Yes No Yes No No Smart DAA Support Yes Yes Yes Yes No 2.2 MFC2000 System Block Diagram The MFC2000 contains the ARM7TDMI RISC Processor (described separately in ARM7TDMI Manuals), Countach Imaging DSP, Modem DSP, and specialized hardware needed for the Multifunctional machine control and scanner and fax signal processing. The Countach Imaging DSP subsystem is on a separate data bus. Therefore, the ARM system data bus can operate in parallel with the Countach Imaging DSP subsystem data bus for most operations except the interaction time between two buses. The two-bus architecture is very important to provide enough bandwidth for full color MFP products. Figure 2-1 shows the MFP2000's two-bus architecture. The ARM Bus System (ABS) has two mastersARM CPU and DMA Controller. They provide accesses to all specialized hardware functions including the Countach Imaging DSP subsystem as a peripheral on the ARM Bus System. ABS has several sections. The System Interface Unit (SIU) is the control center. The ARM CPU and Cache Controller are on the Internal System Bus (ISB). The Cache Memory is on the Internal Cache Bus (ICB). The DMA Controller is on the DMA Bus (DAB). All internal peripherals are on the Internal Peripheral Bus (IPB). The SmartDAA/IA Interface and P80 core are on the IPB of the ARM Bus System. The ARM7TDMI runs at a clock rate 40 MHz, 37.5 MHz, or 30 MHz. All external peripherals are on the ARM External Bus (AEB). There is a separate bus system for the Countach Imaging DSP subsystem called Countach Bus System (CBS). There are three sections, the Video/Scan Interface, the ARM Bus Interface, and the countach subsystem interface. The external SDRAM/DRAM is on the Countach External Bus (CEB). 100723A Conexant 2-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description PLL Clock Generator Timing Control Prime/Battery Power and Reset Control 16-bit DAB CPU Core (ARM7TDMI) 32-bit ISB Cache Memory Controller 32-bit ISB ICB 1Kx32bit (2Kx16bit) Cache Memory 16-bit and/or 8-bit AEB ROM/Flash DMA Controller IRQ/CPU Access Bus IF (including DRAM/ Flash Controller) 16-bit IPB SRAM/Flash CPU Interrupt Access Controller DRAM/Flash Motor Drivers Scan/Print IRQ/ Motor CPU Controller Access DMA/ Bit Rotation CPU Access Sync/ IRQ/ Async CPU Serial Port Access Inkjet DMA/ Engine (including CPU Access Inkjet Print ASIC) Bi-level DMA/ Resolution CPU Access Conversion Sync Serial Panel IF CPU Access DMA/ IRQ/ CPU Access P1284 or USB Host IF IRQ/ Fax CPU Modem Access (Optional) Serial Operator Panel IF Host CPU Access IRQ/ Watchdog CPU Timer Access GPIOs CPU and Access PWM Channels Video/Color Scan IA RTC CPU Access Color Scanner Conexant Video Chip Video/Scan Controller NTSC /PAL Video ARM Bus Interface Countach Subsystem Interface Video/Scan Interface Countach Subsystem Countach Bus Unit Countach DMA Controller DRAM/ SDRAM Controller 16-bit and/or 8-bit CEB DRAM/ SDRAM Figure 2-1. MFC2000 Organization 2-2 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 3. Hardware Interface 3.1 Pin Description Table 3-1. Pin Description (1 of 6) Pin Name PRTIRQn AUXCLK A[11:0]/A[23:12] U14 K20 A20,B20,B19,B 18,B17,C20,C1 9,C18,C17,D20, D19,D18 C16 A19 Pin No. I/O I O I/O Input Type HU5VT 5VT Output Type 2XT3V 3XT5VT Pin Description (Hysteresis, Pull up) Interrupt from the external printing ASIC (active low) Auxiliary clock output for using as the master clock for external devices Address bus (12-bit), A[23:12] and A[11:0] are muxed out through same pins. ALE AE[2]/GPO[14]/SSTXD2/ ROM_CONFIG[0] O I/O D5VT 2XT5VT 2XT5VT Address Latch output signal for latching A[23:12] externally (Pull down) Address bit for external ROM mux in the ROM interleave access mode or GPO[14] or TX data output for SSIF2 (ROM_CONFIG[0] input during the reset period) (Pull down) Address bit for external ROM mux in the ROM interleave access mode or GPO[15] or Status input for SSIF2 (ROM_CONFIG[1] input during the reset period) (Pull down) Address bit for external ROM mux in the ROM interleave access mode or GPO[16] (CLK_CONFIG[0] input during the reset period) (Pull down) Address bit for external ROM mux in the ROM interleave access mode or GPO[17] (CLK_CONFIG[1] input during the reset period) Data bus (16-bit) AO[2]/GPO[15]/SSSTAT2/RO M_CONFIG[1] A18 I/O D5VT 2XT5VT AE[3]/GPO[16]/ CLK_CONFIG[0] AO[3]/GPO[17]/ CLK_CONFIG[1] D[15:0] A17 I/O D5VT 2XT5VT D16 I/O D5VT 2XT5VT A12,B12,C12,A 13,B13,C13,D1 3,A14,B14,C14, A15,B15,C15,D 15,A16,B16 D12 B9 I/O 5VT 2XT5VT RDn WREn/DOEEn O O - 3XT5VT 4XT5VT Read strobe (active low) Write strobe for the lower byte (active low) or DRAM output enables selects used for noninterleave mode and interleave modes. DOEEn is used for reading the even address bank (active low). Write strobe for the higher byte (active low) or DRAM output enables selects used for noninterleave mode and interleave modes. DOEOn is used for reading the odd address bank (active low). ROM chip select (active low) I/O chip select (active low). SRAM chip select (active low) (VRTC powered) DRAM row Address select for bank 0 and 1(active low) (VDRAM powered) DRAM column odd address selects used for noninterleave mode and interleave mode. (VDRAM powered) WROn/DOEOn C9 O - 4XT5VT ROMCSn CS[1]n CS[0]n RASn[1:0] CASOn[1:0] D10 A9 G18 F19,F18 E17,F20 O O O O O 3V - 2XT5VT 2XT5VT 2XT3V 2XT3V 2XT3V 100723A Conexant 3-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Table 3-1. Pin Description (2 of 6) Pin Name CASEn[1:0] Pin No. E20,E19 I/O O Input Type Output Type 2XT3V Pin Description DRAM column even address selects used for noninterleave mode and interleave mode. (VDRAM powered) DRAM write. (VDRAM powered) External DMA acknowledge output (channel 2). (Hysteresis) External DMA request input (channel 2). Flash memory chip select 0 or PWM channel 1 output Flash memory chip select 1 or PWM channel 2 output signal. (Hysteresis, Pull up) MFC2000 Reset input/output Crystal oscillator input pin for RTC. (VRTC powered) Crystal oscillator output pin for RTC. (VRTC powered) (Hysteresis) Indicate the loss of prime power (result in SYSIRQ). (VRTC powered) Write Protect during loss of VDD power. Note: The functional logic is powered by RTC battery power, but the output drive is powered by DRAM battery power. (VRTC powered) (Hysteresis) Battery power reset input. (VRTC powered) (Hysteresis) External power-down detector select input (active low)(VRTC powered) Scanner shift gate control 0 Scanner clock. Scanner LED control 0 Scanner LED control 1 or Scanner shift gate control 1 Scanner LED control 2 or Scanner shift gate control 2 TX data for SSIF1 (Hysteresis, Pull up) RX data for SSIF1 (Hysteresis) Clock input or output for SSIF1 (Hysteresis) GPIO[0] or flash write enable signal for NAND-type flash memory or scanner clamp control output (Hysteresis) GPIO[1] or flash read enable signal for NAND-type flash memory. (Hysteresis) GPIO[2] or DMA channel 1 request input or clock input/output for SSIF2. (Hysteresis) GPIO[3] or DMA channel 1 acknowledge or RX data for SSIF2 (Hysteresis) GPIO[4] or I/O chip select [2] (active low) (Hysteresis) GPIO[5]or I/O chip select [3] (active low) or PWM channel 3 output DWRn DMAACK2 DMAREQ2 FCS0n/PWM[1] FCS1n/PWM[2] RESETn XIN XOUT PWRDWNn WPROTn D17 K19 F4 D9 A8 K18 G20 H20 H18 H19 O O I O O I/O I O I O H5VT HU5VT OSC H3V - 2XT3V 1XT5VT 2XT5VT 2XT5VT 2XT5VT OSC 1XT3V BATRSTn EXT_PWRDWN_SELn SC_START[0] SC_CLK1/SC_CLK2A SC_LEDCTRL[0] SC_LEDCTRL[1]/ SC_START[1] SC_LEDCTRL[2]/ SC_START[2] SSTXD1 SSRXD1 SSCLK1 GPIO[0]/FWRn/CLAMP G17 G19 V8 U9 U7 Y8 W8 J19 H17 J20 J4 I I O O O O O O I I/O I/O H3V H3V HU5VT H5VT H5VT 1XT3V 1XT3V 1XT3V 1XT3V 1XT3V 2XT3V 2XT5VT 2XT5VT GPIO[1]/FRDn GPIO[2]/DMAREQ1/ SSCLK2 GPIO[3]/DMAACK1/ SSRXD2 GPIO[4]/CS[2]n GPIO[5]/CS[3]n/PWM[3] M3 V1 U4 U3 U2 I/O I/O I/O I/O I/O H5VT H5VT H5VT H5VT H5VT 2XT5VT 2XT5VT 2XT5VT 2XT5VT 2XT5VT 3-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 3-1. Pin Description (3 of 6) Pin Name GPIO[6]/CS[4]n/ EADC_D[3] GPIO[7]/CS[5]n/ GPIO[8]/IRQ[11]/ SSSTAT1/SC_CLK1/2B GPIO[9]/IRQ[13]/ EADC_D[2] GPIO[10]/RING_DETECT/PW M[4] GPIO[11]/CPCIN/PWM[0]/ALT TONE GPIO[12]/SASCLK/ SMPWRCTRL GPIO[13]/SASTXD/ PMPWRCTRL GPIO[14]/SASRXD/ RINGER GPIO[15]/IRQ[16]/ SC_CLK1/2C GPIO[16]/M_TXSIN GPIO[17]/M_CLKIN GPIO[18]/M_RXOUT GPIO[19]/M_SCK/MIRQn GPIO[20]/M_STROBE/ MCSn GPIO[21]/M_CNTRL_SIN GPIO[22]/EADC_Sample SM[3:0]/ GPO[7:4] PM[0]/SPI_SID/ EADC_D[0]/GPO[0] PM[1]/SPI_SIC/ EADC_D[1]/GPO[1] PM[2]/SMI0/GPO[2] PM[3]/SMI1/GPO[3] TONE PIODIR STROBEn AUTOFDn SLCTINn INITn BUSY ACKn U8 W9 Y9 Y12 V9 C1 A2 G3 G2 G1 A1 D3 I/O I/O O O I/O O I I I I O O 5VT 5VT H5VT H5VT H5VT H5VT H5VT 1XT5VT 1XT5VT 1XT3V 2XT3V 1XT5VT 2XT3V 2XT3V 2XT3V Print motor control [0] output or GPO[0] output or data output for SPI or external ADC data [0] input Print motor control [1] output or GPO[1] output or clock output for SPI or external ADC data [1] input Print motor control [2] output or GPO[2] output or scan motor current control 0. Print motor control [3] output or GPO[3] output or scan motor current control 1. (Hysteresis) Tone output signal. PIOD[7:0] is output when PIODIR is high and PIOD[7:0] is input when PIODIR is low. (Hysteresis) Input from PC (active low) (Hysteresis) Input from PC (active low) (Hysteresis) Input from PC (active low) (Hysteresis) Input from PC (active low) PIO Returned status to PC PIO Returned status to PC (active low) U1 T4 T3 T2 T1 R4 R3 R2 R1 P4 P3 P2 P1 N4 N3 N2 N1 V7,W7,Y7,U6 Pin No. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O Input Type H5VT H5VT H5VT H5VT H5VT H5VT H5VT H5VT H5VT H5VT H5VT H5VT H5VT H5VT H5VT H5VT H5VT Output Type 2XT5VT 2XT5VT 2XT5VT 2XT5VT 2XT5VT 2XT5VT 2XT5VT 2XT5VT 2XT5VT 2XT5VT 2XT5VT 2XT5VT 2XT5VT 2XT5VT 2XT5VT 2XT5VT 2XT5VT 1XT3V Pin Description (Hysteresis) GPIO[6] or I/O chip select [4] (active low) or external ADC data [3] input (Hysteresis) GPIO[7] or I/O chip select [5] (active low). (Hysteresis) GPIO[8] or external interrupt [11] or status input for SSIF1 or scan clock output (Hysteresis) GPIO[9] or external interrupt [13] or external ADC data [2] input (Hysteresis) GPIO[10] or ring detection input or PWM channel 4 output (Hysteresis) GPIO[11] or calling party control input or ALTTONE output (Hysteresis) GPIO[12] or clock input/output for SASIF or Scan Motor Power Control output (Hysteresis) GPIO[13] or TX data output for SASIF or Print Motor Power Control output (Hysteresis) GPIO[14] or RX data input for SASIF or ringer output (Hysteresis) GPIO[15] or external interrupt [16] or scan clock output (Hysteresis) GPIO[16] or internal modem (Hysteresis) GPIO[17] or internal modem (Hysteresis) GPIO[18] or internal modem (Hysteresis) GPIO[19] or internal modem or external modem interrupt input (Hysteresis) GPIO[20] or internal modem or external modem chip select (Hysteresis) GPIO[21] or internal modem (Hysteresis) GPIO[22] or external ADC sample signal output Scan motor control [3:0] pins or GPO[7:4] pins. 100723A Conexant 3-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Table 3-1. Pin Description (4 of 6) Pin Name SLCTOUT PE FAULTn PIOD[7:0] C3 B2 B1 D2,D1,C2,H4,H 3,H2,H1,G4 J2 Y3 Y2 Y1 W4 Y5 V5 U5 V12 Y4 W5 V6,W6,Y6 W3 W2 Pin No. I/O O O O I/O Input Type H5VT Output Type 2XT3V 2XT3V 2XT3V 2XT5VT Pin Description PIO Returned status to PC PIO Returned status to PC PIO Returned status to PC (active low) (Hysteresis) Driven by PC or MFC2000 and used to send data or address depending on which mode is used (Hysteresis) For test only, It must be `low' for the normal operation Positive reference voltage for the scan PADC Negative reference voltage for the scan PADC Voltage input for power-down detection circuit 1 Voltage input for power-down detection circuit 2 Scan PADC analog ground Scan PADC analog Power Scan PADC digital ground Analog telephone line monitoring output from SSD Scan PADC internal ground Analog scan input signal Analog sensor inputs for TADC HD5VT HU5VT (Hysteresis, Pull down) Test clock input for JTAG. It is positive edge-triggered. (Hysteresis, Pull up) Test mode select input for JTAG. Selects the next state in the TAP state machine. (Hysteresis, Pull down) Suggestion by Lauterbach for JTAG: connect this signal to RESETn in normal mode and disconnect in debug mode. (Hysteresis, Pull up) Test data input for JTAG. Serial data input to the JTAG shift register. Test data output for JTAG. Serial data output from the JTAG shift register. (Hysteresis, Pull down) For test only, It must be `low' for the normal operation. (Hysteresis, Pull down) For the scan test only, It must be `low' for normal operations. P80 DSP test and DFT scan mode select, This pin is only used for the test mode. Crystal input pin for PLL Crystal output pin for PLL +3.3V digital power for PLL +3.3V digital ground for PLL 5VT 2XT5VT Countach (S)DRAM data bus (16 bits) TESTER_MODE ADCREFp ADCREFn POWER1 POWER2 ADGA ADVA ADGD SDAA_SPKR ADCV SCIN SENIN[2:0] TCK TMS I I I I I O I I I I HD5VT - TRSTn W1 I HD5VT - TDI TDO TEST SCANMOD P80_SEL PLLREF_XIN PLLREF_XOUT PLLVDD PLLVSS SDDATA[15:0] V4 V3 V2 J1 J3 Y15 W15 U15 U16 N20,P17,P18,P 19,P20,R17,R1 8,R19,R20,T17, T18,T19,T20,U1 7,U18,U19 I O I I I I O I/O HU5VT HD5VT HD5VT H3V OSC - 1XT5VT OSC 3-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 3-1. Pin Description (5 of 6) Pin Name SDADDR[12:0] Pin No. V20,W20,Y20, W19,Y19,W18, Y18,W17,Y17,V 16,W16,Y16,V1 5 U20 V19 V18 V17 M19 B8 C8 E1 E2 E4 E3 W12 I/O O Input Type Output Type 2XT3V Pin Description Countach (S)DRAM address bus (13 pins) SDCASn SDRASn SDWRn SDCSn SDCLK100MHz USB_Dp USB_Dn SDAA_PWRCLK SDAA_PWRCLKn SDAA_DIBp SDAA_DIBn EV_VD[0]/EADC_D[4]/ MREQn O O O O O I/O I/O I/O I/O I/O I/O I/O 5VT 2XT3V 2XT3V 2XT3V 2XT3V 2XT5VT Countach (S)DRAM column address strobe (active low) Countach (S)DRAM row address strobe (active low) Countach (S)DRAM write strobe (active low) Countach (S)DRAM chip select Countach (S)DRAM clock Positive data input/output pin for USB Negative data input/output pin for USB Positive power/clock output from SSD Negative power/clock output from SSD Positive data input/output pin for SDAA Negative data input/output pin for SDAA 3V 2XT3V External video data [0] input for VIP or external ADC data [4] input or Memory Request (active low)-indicates that the following cycle is a memory access. External video data [1] input for VIP or external ADC data [5] input External video data [2] input for VIP or external ADC data [6] input or Op Code fetch (active low)LOW indicates that the processor is fetching an instruction from memory. External video data [3] input for VIP or external ADC data [7] input External video data [4] input for VIP or external ADC data [8] input or Memory access size MAS[1:0]: 00 - byte, 01 - halfword, 10 - word, 11 Reserved during the normal operation External video data [5] input for VIP or external ADC data [9] input or Memory access size MAS[1:0]: 00 - byte, 01 - halfword, 10 - word, 11 Reserved during the normal operation External video data [6] input for VIP or external ADC data [10] input External video data [7] input for VIP or external ADC data [11] input or aborted bus cycle-the address selected is outside of CS's address ranges. (Hysteresis) External video clock input (Pull down) The bus access is a read operation when W_Rn is LOW and write when W_Rn is HIGH. (Pull up) SIU Transaction Acknowledge. The D[15:0] data will be transferred during this MCLK cycle. EV_VD[1]/EADC_D[5] EV_VD[2]/EADC_D[6]/ OPCn U12 Y13 I/O I/O 3V 3V 2XT3V 2XT3V EV_VD[3]/EADC_D[7] EV_VD[4]/EADC_D[8]/ MAS[0] W13 U13 I/O I/O 3V 3V 2XT3V 2XT3V EV_VD[5]/EADC_D[9]/ MAS[1] Y14 I/O 3V 2XT3V EV_VD[6]/EADC_D[10] EV_VD[7]/EADC_D11]/ ABORT W14 V14 I/O I/O 3V 3V 2XT3V 2XT3V EV_CLK W_Rn V13 N19 I O H3V D5VT 2XT5VT XAKn N18 O U5VT 2XT5VT 100723A Conexant 3-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Table 3-1. Pin Description (6 of 6) Pin Name DMACYC/ CLK_CONFIG[2] Pin No. M18 I/O I/O Input Type U5VT Output Type 2XT5VT Pin Description (Pull up) DMA Cycle-the DMA logic has control of the external bus. (CLK_CONFIG[2] input during the reset period) (Pull up) Wait (active low)-reflects the wait states being used by the ARM processor. (Pull up) Cache hit-the ARM is retrieving data from the cache memory (JTAG_MODE_SEL during the reset period, "1" - ARM JTAG selected (Pull down) Sequential Address Access. (Used with nMREQ to indicate memory access type. Only required if using co-processor cycles) Internal test pin. Leave it open. Internal test pin. Leave it open. Internal test pin. Leave it open. Digital ground (16 pins) WAITn CACHEHIT/ JTAG_MODE_SEL SEQ J17 J18 O I/O U5VT U5VT 2XT5VT 2XT5VT N17 O D5VT 2XT5VT SSD_DIBRX TX_DATA SDAA_GPIO_INT VSS F3 F2 F1 L1,L2,L3,L4,U1 0,V10,W10,Y10, L17,L18,L19,L2 0,A11,B11,C11, D11 A10,B10,C10,K 1,K2,K3,K4,U11 ,V11,W11,Y11, K17,M20 M1 M2 M17 D14 D5 M4 E18 F17 A3,B3,A4,B4,C4 ,D4,A5,B5,C5,A 6,B6,C6,D6,A7, B7,C7,D7,D8 O O O - VDD - +3.3V digital power (13 pins) P80VSS P80VDD VGG1 VGG2 VGG3 VGG4 VDRAM VRTC (NC) - Digital ground for P80 DSP +3.3V digital power for P80 DSP +5V Power for the +5V tolerant pads +5V Power for the +5V tolerant pads +5V Power for the +5V tolerant pads +5V Power for the +5V tolerant pads Battery Power for DRAM refresh. Battery Power for RTC 18 RESERVED pins 3-6 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 3.2 Maximum Ratings Table 3-2. Maximum Ratings Parameter VDD Digital Power Battery Power VGG Digital Power Digital GND Digital Input (3V) Digital Input (5VT) Operating Temperature Range (Commercial) Storage Temperature Range Voltage Applied to Outputs in High Z State (3V) Voltage Applied to Outputs in High Z State (5VT) Static Discharge Voltage ( 25 C) Latch-up Current ( 25 C) o o Symbol VDD VRTC VDRAM VGG GND VI VI T Tstg VHz VHz ESD Itrig Limits -0.5 to +4.6 -0.5 to +4.6 -0.5 to +4.6 -0.5 to +6.0 -0.5 to +0.5 -0.5 to +4.6 -0.5 to +6.0 0 to 70 -40 to 80 -0.5 to 4.6 -0.5 to 6.0 +2500 +400 Unit V V V V V V V o C C o V V V mA 100723A Conexant 3-7 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 3.3 Electrical Characteristics Table 3-3. Digital Input Characteristics Symbol Description (V min.) VIL (V max.) 0.8 0.8 0.3*VDD 0.3*VDD (V min.) 2.0 2.0 0.7*VDD 0.7*VDD VIH (V max.) VDD VDD VDD VDD Hysteresis (V min.) --.5 .5 Pullup/Pulldown Resistance (K ohms) -50-200 --- 3V U3V H3V HD3V 3V CMOS input 3V CMOS input w/pullup 3V CMOS input w/hysteresis 3V CMOS input w/hysteresis and pull down 3V CMOS input w/hysteresis and pullup 5V tolerant CMOS input w/hysteresis 5V tolerant CMOS input w/pullup 5V tolerant CMOS input w/pulldown 5V tolerant CMOS input w/hysteresis and pullup 5V tolerant CMOS input w/hysteresis and pulldown 5V tolerant CMOS input 3V CMOS input 0 0 0 0 HU3V H5VT U5VT D5VT HU5VT 0 0 0 0 0 0.3*VDD 0.3*VDD 0.3*VDD 0.3*VDD 0.3*VDD 0.7*VDD 0.7*VDD 0.7*VDD 0.7*VDD 0.7*VDD VDD 5.25 5.25 5.25 5.25 .5 .3 --.3 50-200 -50-200 50-200 50-200 HD5VT 0 0.3*VDD 0.7*VDD 5.25 .3 50-200 5VT OSC** 0 0 0.8 0.3*VDD 2.0 0.7*VDD 5.25 VDD --- --- ** These parameters can only be tested under low speed XIN clock. Table 3-4. Output Characteristics Output Type Description VOL (V max) IOL (mA) VOH (V min) IOH (mA) CL (pF) 1X3V 1X5VT 1XT5VT 2X3V 2XT3V 2X5VT 2XT5VT 3XT3V 3XT5VT 4XT5VT 1X CMOS Output, 3V 1X CMOS Output, 5V tolerant 1X CMOS Output, tristatable, 5V tolerant 2X CMOS Output, 3V 2X CMOS output, tristatable, 3V 2X CMOS output, 5V tolerant 2X CMOS output, tristatable, 5V tolerant 3X CMOS output, 3V 3X CMOS output, tristatable, 5V tolerant 4X CMOS output, tristatable, 5V tolerant 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 -2.0 -2.0 -2.0 -4.0 -4.0 -4.0 -4.0 -8.0 -8.0 -12.0 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.0 2.0 2.0 4.0 4.0 4.0 4.0 8.0 8.0 12.0 3-8 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 3-5. Power Supply Requirements Symbol Description Operating Voltage Min. (V) Max. (V) Current* Typ. @ 25 C(mA) Max.@ 0C (mA) VGG VDD GND IDD VBAT VDRAM Digital Power for 5VT Digital Power Digital GND Total Digital Current Battery Power Battery Power 4.75 3.0 0 5.25 3.6 0 (TBD) (TBD) 2.7 2.7 3.6 3.6 Note: * Maximum power supply current is measured at 3.6V. Table 3-6. Battery Power Supply Current Requirements Operating Voltage (V) VBAT Typ.@25C (a) Max.@70C (a) Typ.@25C (a) VDRAM Max.@70C (a) 2.7 3.0 3.3 3.6 4 tbd 6 tbd tbd tbd tbd tbd 100 tbd tbd tbd tbd tbd tbd tbd Note: Battery power supply current is measured when a 32KHz crystal is used. The DRAM battery currents that are listed are somewhat dependent on the type of DRAM used. This particular configuration had 1 interleaved DRAM bank in backup mode. 100723A Conexant 3-9 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 3.4 Pin Layout A 1 2 3 4 5 6 7 8 9 B C D E F G H J K L M N P R T U V W Y 10 11 12 13 14 15 16 17 18 19 20 MFC2000 Chip Bottom View Figure 3-1. MFC2000 BGA Bottom View 3-10 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 4. CPU and Bus Interface 4.1 4.1.1 Memory Map and Chip Select Description Memory Map The ARM7TDMI Core is capable of directly accessing 4 GB of memory (A31-A0). The MFC2000 is designed to directly access 64-MB of memory composed of internal and external memory spaces by means of the 26-bit system address bus (A25-A0). The MFC2000 internally decodes address range 00000000H-03FFFFFFH (64 M). Address range 01000000H-01FFFFFFH (16 M) is arranged for the internal registers/memory and external Countach Imaging DSP Subsystem memory. Address range 00000000H-00FFFFFFH (16 M) and Address range 02000000H-03FFFFFFH (32 M) are arranged for the external device/memory use on the ARM Bus. Only 24 address lines (A23-A0) are brought out of the MFC2000 chip, and the lower half and the higher half are multiplexed through the same 12 pins. The 16 MB address range (maximum) can be decoded externally, if necessary. Figure 4-1 and Figure 4-2 show the MFC2000 memory map with memory type designations and locations and provides memory segmentation into select signal ranges. 4.1.1.1 Internal Memory Space The MFC2000 internal memory occupies 128 kB of the address range from 01FE0000h through 01FFFFFh). Internal memory space includes the following: Cache memory space (64 kB) (Reserved space) (32 kB) Internal register space (4 kB) Internal RAM space (28 kB) The cache memory space includes the following: 1. The cache memory (4096 bytes) 2. The Tag memory (4096 bytes) 3. (Reserved) (56 kB) (01FE0000h-01FE0FFFh) (01FE1000h-01FE1FFFh) (01FE2000h-01FEFFFFh) (01FE0000h-01FEFFFFh) (01FF0000h-01FF7FFFh) (01FF8000h-01FF8FFFh) (01FF9000h-01FFFFFFh) The internal register address range consists of 3 sections: 1. The first (lowest) section (01FF8000h to 01FF87FFh, 2 kB), is reserved for operational registers, i.e., those that are modified during normal operation, but which are not intended to require firmware initialization after reset. 2. The second section (01FF8800h to 01FF8DFFh, 1.5 kB) contains the setup registers, i.e., those that are generally written only once for system initialization after reset. 3. The third section (01FF8E00h to 01FF8FFFh, 512 bytes) is reserved for testing purposes. Note: All internal register accesses are two CPUCLK-cycle operations. 100723A Conexant 4-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description The internal RAM space includes the following: 1. Bit rotation RAM area Bit rotation RAM: 512 halfwords (1 kB) (Reserved) (3072 bytes) (01FF9000h-01FF93FFh) (01FF9400h-01FF9FFFh) 2. Countach Subsystem memory area Countach Scratch Pad (512 bytes) (256 halfwords)(01FFA000h-01FFA1FFh) Countach Data DMA Channel 0 (1 halfword) (01FFA200h-01FFA201h) Countach Data DMA Channel 1 (1 halfword) (01FFA202h-01FFA203h) Countach Data DMA Channel 2 (1 halfword) (01FFA204h-01FFA205h) Countach Data DMA Channel 3 (1 halfword) (01FFA206h-01FFA207h) Reserved (344 bytes) (01FFA208h-01FFA35Fh) Countach Program DMA Address (5 bytes) (01FFA360h-01FFA364h) Reserved (155 bytes) (01FFA365h-01FFA3FFh) VSI Buffer (256 bytes) (2x64 halfwords) (01FFA400h-01FFA4FFh) (Reserved) (23296 bytes) (01FFA500h-01FFFFFFh) 4.1.1.2 External Countach Imaging DSP Subsystem Memory Space The external memory space (8 MB) is allocated to the external DRAM/SDRAM on the Countach Imaging DSP Bus Subsystem. Countach Imaging DSP Subsystem SDRAM/DRAM (8 M) (01000000h-017FFFFFh) 4-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 4.1.1.3 External Memory Space The external memory space (up to 48 M) consists of ROM, DRAM/ARAM, Flash memory, SRAM, modem, and variable-use spaces with assigned chip selects. Most external chip selects have programmable address ranges, start locations, wait states, and read and write strobe timing. SRAM and DRAM/ARAM chip select controls are battery-backed up. Refer to Figure 4-1 for the MFC2000 memory map and to Figure 4-2 for the internal memory map. External memory spaces include the following: ROMCSn, ROM (4 M) CS5n, general (4 M) FCS0n, NOR type Flash memory (2 M) FCS1n, NOR type Flash memory (2 M) Address location for generating FWRn and FRDn for the NAND type Flash memory (Reserved) MCSn, modem (128 K) P80_CSn SDAA_CSn CS4n, optional general (128 K) CS3n, optional general (128 K) CS2n, optional general (512 K) CS1n, general (1 M) CS0n, SRAM or general (2 M) SDRAM (For internal and Countach Imaging DSP Subsystem) (16 M) RAS0n, DRAM or ARAM (16 M) RAS1n, DRAM or ARAM (16 M) (00000000h-003FFFFFh) (00400000h-007FFFFFh) (00800000h-009FFFFFh) (00A00000h-00BFFFFFh) (00C00000h-00C0003Fh) (00C00002h-00C1FFFFh) (00C20000h-00C2FFFFh) (00C30000h - 00C37FFFh) (00C38000h - 00C3FFFFh) (00C40000h-00C5FFFFh) (00C60000h-00C7FFFFh) (00C80000h-00CFFFFFh) (00D00000h-00DFFFFFh) (00E00000h-00FFFFFFh) (01000000h-01FFFFFFh) (02000000h-02FFFFFFh) (03000000h-03FFFFFFh) 100723A Conexant 4-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Table 4-1. Fixed-Location and Size Chip Selects Chip Select ROMCSn FCS1n/FCS0n CS0n CS1n (Optional) Optional MCSn (Optional) CS2n CS3n (Optional) CS4n (OptionaL0 CS5n ROM NAND- or NOR-type Flash Memory SRAM, or other General Use External Fax Modem (optional) I/O Devices, or other General Use General Use 4 MB ROM, SRAM, or other Device DRAM/ARAM chip selects can also be programmed to 1 of 4 sizes (from 512 k to 16 M). ROM Chip Select (ROMCSn) ROMCSn selects external ROM located in 4-MB address space 00000000h-003FFFFFh, and is active for read and write accesses. The ROMCtrl register can be used to select 0 to 7 (default) wait states, and 0 or 1 (default) read and write strobe on delays. For customers that choose to use NOR-type flash memory in the ROM address area, the write operation is also allowed in the ROM address area. Chip Select 5 (CS5n) CS5n is an active Read/Write select signal for the 4 MB address range (00400000h to 007FFFFFh) directly below the ROMCSn address range. The CS5Ctrl register can be used to select 0 to 7 (default) wait states, and 0 or 1 (default) read and write strobe on delays. GPIO[7] (default) can be configured as CS5n using the GPIO[7]/CS5n bit of the GPIOConfig register. SRAM Chip Select 0 (CS0n) CS0n is designed for use in selecting external SRAM, but can also be used for other purposes. It has 2 MB address range (00E00000h to 00FFFFFFh). The CS0n can also be programmed for 0 (default) to 7 wait states, 0 (default) or 1 read and write strobe on delays, and normal (default) or early write strobe off times using the CS0Ctrl register. DRAM Chip Select (RASn[1:0], CASOn[1:0] and CASEn[1:0]) DRAM address space can be selected in 2 separate memory blocks (Bank 0: RASn[0] and Bank 1: RASn[1]). Separate control bits are provided in the Backup Configuration register to enable and disable each of the memory banks (Default: Bank0 is enabled and 8-bit DRAM is selected). Non-interleaved DRAM accesses and 2-way interleaved DRAM accesses are supported. CASOn[1:0] and CASEn[1:0] are used differently for different access modes. RASn is asserted before CASn for normal read and write operations. Also, RAS can be kept active and CASn is toggled to do burst mode operations. CASn-Before-RASn refresh mode is the only refresh mode for MFC2K (For more DRAM information, see the DRAM Controller section.) The address ranges of the two memory banks (RAS0n and RAS1n) are continuous around the midpoint of the DRAM memory bank. The RASn[1] starting address is 03000000h and grows larger based on the size of the memory. The end of the RASn[0] bank ends at 03000000h and grows smaller from that point. Each bank has separate configuration controls. The memory range is programmed through the address multiplexer selections for bank 0 and bank 1 in the DRAMCtrl register. 4-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Flash Memory Chip Selects (FCS1n and FCS2n) FCS0n and FCS1n are multiplexed with PWM[1] and PWM[2] and output through FCS0n/PWM[1] and FCS1n/PWM[2] pins. After reset, the Flash disable bit (bit 0) of the FlashCtrl register is 0 and the FCS0n/PWM[1] and FCS1n/PWM[2] pins are used as FCS0n and FCS1n. FCS0n and FCS1n can access either NOR-type (default) or NAND-type flash memory, selectable with the NANDFlashEnb bit (bit 6) of the FlashCtrl register. When enabled for NOR-type flash memory (default), FCS1n can be activated by accessing the 2-MB (00A00000h-00BFFFFFh) flash memory address area. FCS0n can be activated by accessing the 2-MB (00800000h - 009FFFFFh) flash memory address area. Firmware controls the flash memory access block size. If enabled for NAND-type flash memory, FCS0n and FCS1n revert to the GPO function and output bit 9 and bit 8 values of the FlashCtrl register . 0 to 7 (default) wait states and normal (default) or early off of the write strobe can be chosen using the FlashCtrl register described in the SIU section. Modem Chip Select (MCSn) The 128 kB address space from 00C20000h to 00C2FFFFh is reserved for the external modem and selected with MCSn. It is muxed with the M_STROBE signal of the modem IA on the pin. M_STROBE is usually used to interface the embedded DSP to the external modem IA if the embedded V.34 modem DSP is used. MCSn can be selected and muxed out for the external modem if the embedded modem DSP is not used. MCSn can be programmed for 0 to 7 (default) wait states, 0 (default) or 1 read and write strobe on delays, and normal (default) or early write strobe off times using the MCSCtrl register. P80 Chip Select (P80_CSn) Address space form 00C3000 to 00C7FFF has been reserved for the P80 functions. Smart Data Access Arraignment (SDAA_CSn) Address space form 00C3800 to 00CFFFF has been reserved for the SDAA functions. 4.1.1.4 External I/O Chip Selects Chip Select [2] (CS2n) The 512 kB address space from 00C80000h to 00CFFFFFh is selected using the external I/O chip selects CS2n. GPIO[4] (default) can be configured as CS2n using the GPIO[4]/CS2n bit of the GPIOConfig register. CS2n can be programmed for 0 (default) to 7 wait states, 0 (default) to 3 read and write strobe delays, and normal (default) or early write strobe off times using the CS2Ctrl register. Chip Select [4:3] (CS4n-CS3n)(optional) The 256 kB address space from 00C40000h to 00C7FFFFh can optionally be selected using the two external I/O chip selects CS4n and CS3n. These chip selects are configured identically to CS2n. GPIO[6] (default) can be configured as CS4n using the GPIO[6]/CS4n bit of the GPIOConfig register. Likewise, GPIO[5] (default) can be configured as CS3n by using the GPIO[5]/CS3n bit in the GPIOconfig1 register. The top 128 kB (00C40000h to 00C5FFFFh) are addressed by CS4n. CS4n is active for read-access only (internally gated with the read strobe) when the CS4nReadOnly bit (bit 8) of the SIUConfig register is 1. CS4n is active for both read and write access when the CS4nReadOnly bit (bit 8) of the SIUConfig register is 0. The next 128 kB (00C60000h to 00C7FFFFh) is addressed by CS3n. CS3n is active for write-access only (internally gated with the write even strobe) when the CS3nWriteOnly bit (bit 7) of the SIUConfig register is 1. If the external I/O device using CS3n is a 16-bit device, 16-bit access must be done. No high-byte or low-byte access can be done. CS3n is active for both read and write access when the CS3nWriteOnly bit (bit 7) of the SIUConfig register is 0. Chip Select 1 (CS1n) The next address range below those of CS4n-CS2n is the 1-MB range (00D00000h to 00DFFFFFh) selected by CS1n. CS1n can be programmed for 0 (default) to 7 wait states, 0 (default) to 3 read and write strobe delays, and normal (default) or early write strobe off times using the CS1Ctrl register. 100723A Conexant 4-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 00000000 romcsn 003FFFFF csn[5] 007FFFFF fcs0n 009FFFFF fcs1n 00BFFFFF NAND Flash Registers 00C0003F (reserved) 00C1FFFF 00C3FFFF 00C5FFFF 00C7FFFF 00CFFFFF 00DFFFFF 00FFFFFF 017FFFFF (reserved) 01FDFFFF 01FFFFFF 01FFFFFF RASn[0] RASn[0] mcsn csn[4] csn[3] csn[2] csn[1] (reserved) 01FDFFFF cachecs 01FEFFFF (reserved) csn[0] 01FF7FFF SDRAM ics iiocs 01FF8FFF imemcs 02FFFFFF RASn[1] 03FFFFFF Figure 4-1. MFC2000 Memory Map 4-6 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 (reserved) (reserved) 01FF7FFF 01FDFFFF cache memory 01FF87FF iiocs 01FF8DFF Tag memory 01FF8FFF 01FE0FFF cachecs C (reserved) (reserved) 01FE1FFF iiocs Bit Rotation Buffer 01FF8FFF 01FF93FF 01FFA000 Countach ScratchPad 01FFA3FF VSI Buffer imemcs 01FFA4FF 01FFFFFF RASn[0] Figure 4-2. MFC2000 Internal Memory Map 100723A Conexant 4-7 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 4.1.2 Register Map Table 4-2. Operation Register Map (1 of 9) Operation registers are located from 01FF8000H to 01FF87FFH. Address Register Name Block Name R, DR (Dummy Read), W, DW (Dummy Write) 01FF8000-01 01FF8002-03 01FF8004-05 01FF8006-07 01FF8008-09 01FF800A-1F 01FF8020-21 01FF8022-23 01FF8024-25 01FF8026-27 01FF8028-29 01FF802A-2B 01FF802C-2D 01FF802E-2F 01FF8030-31 01FF8032-3F 01FF8040 01FF8042 01FF8044 01FF8046 01FF8048-4B 01FF804C-4D 01FF804E-4F 01FF8050-51 01FF8052-53 01FF8054-55 01FF8056-57 01FF8058-59 01FF805A-5B 01FF805C-5D 01FF805E-5F 01FF8060-61 01FF8062-63 01FF8064-67 01FF8069-6B 01FF806C-6D 01FF806E-6F 01FF8070-71 TADCCtrl TADCInsData TADCCh0Data TADCCh1Data TADCCh2Data (Not Used) IRQFIQEvent1 IRQFIQEvent2 IRQEnable1 IRQEnable2 FIQEnable1 FIQEnable2 EIRQConfigClr IRQTimer1 IRQTimer2 (Not Used) WatchdogEnRetrigger WatchdogInterval HWVersion ProductCode (Not Used) SSCurTimer1 SSCurTimer2 SStepCtrl SStepTimer SSDelayTimer SMPattern/GPO VPStepCtrl VPStepTimer VPMPattern/GPO (Not Used) RotCtrl RotPackeddata (Not Used) TotalBinDatCntr FirstBlkDatCnt LastBlkDatCnt BiRCInFIFO0 TADC TADC TADC TADC TADC Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Watchdog Timer Watchdog Timer Watchdog Timer Watchdog Timer Scan/Print Motor Controller Scan/Print Motor Controller Scan/Print Motor Controller Scan/Print Motor Controller Scan/Print Motor Controller Scan/Print Motor Controller Scan/Print Motor Controller Scan/Print Motor Controller Scan/Print Motor Controller Bit Rotation Block Bit Rotation Block Bi-level Resolution Conversion Bi-level Resolution Conversion Bi-level Resolution Conversion Bi-level Resolution Conversion R/W R R R R R R(Bit[6:2], Bit[0]) R/W(Bit[1]) R/W R/W R/W R/W R/W R/W R/W W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W 4-8 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 4-2. Operation Register Map (2 of 9) Address Register Name Block Name R, DR (Dummy Read), W, DW (Dummy Write) 01FF8072-73 01FF8074-75 01FF8076-77 01FF8078-79 01FF807A-7B 01FF807C-7D 01FF807E-7F 01FF8080-81 01FF8082-83 01FF8084-85 01FF8086-87 01FF8088-89 01FF808A-8B 01FF808C-8D 01FF808E-8F 01FF8090-1 01FF8092-3 01FF8094-5 01FF8096-7 01FF8098-9 01FF809A-F 01FF80A0-1 01FF80A2-7 01FF80A8-9 01FF80AA-B 01FF80AC-F 01FF80B0-1 01FF80B2-3 01FF80B4-5 01FF80B6-7 01FF80B8-9 01FF80BA-B 01FF80BC-D 01FF80BE-F 01FF80C0-C1 01FF80C2-C3 01FF80C4-C5 01FF80C6-C7 BiRCInFIFO1 BiRCInFIFO2 BiRCInFIFO3 BiRCInHold BiRCInFIFOCtrl BiResConRatio BiResConCtrl BiRCOutFIFO0 BiRCOutFIFO1 BiRCOutFIFO2 BiRCOutFIFO3 BiRCOutHold BiRCOutFIFOCtrl SinglingMask HSZeroNo Sec_Min Hour_Day Month_Year RTCCtrl BackupConfig (Not Used) LockEnb (Not Used) CPCThreshold CPCStatCtrl (Not Used) ToneGenF1 ALTToneGen BellCtrl BellPeriod BellPhase ToneGenF2 ToneGenSwitch ToneGenTotal PWMCh0Ctrl PWMCh1Ctrl PWMCh2Ctrl PWMCh3Ctrl Bi-level Resolution Conversion Bi-level Resolution Conversion Bi-level Resolution Conversion Bi-level Resolution Conversion Bi-level Resolution Conversion Bi-level Resolution Conversion Bi-level Resolution Conversion Bi-level Resolution Conversion Bi-level Resolution Conversion Bi-level Resolution Conversion Bi-level Resolution Conversion Bi-level Resolution Conversion Bi-level Resolution Conversion Bi-level Resolution Conversion Bi-level Resolution Conversion Battery RTC Battery RTC Battery RTC Battery RTC Battery RTC Prime Power Reset Logic CPC Logic CPC Logic ToneGen Block ToneGen Block Bell Ringer Bell Ringer Bell Ringer ToneGen Block ToneGen Block ToneGen Block PWM Logic PWM Logic PWM Logic PWM Logic R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R(bit[7]), R/DW(bit[5:0]) R(bit[15]), R/DW(bit[13:8]) R(bit[7]), R/DW(bit[4:0]) R(bit[15]), R/DW(bit[12:8]) R(bit[7]), R/DW(bit[3:0]) R(bit[15]), R/DW(bit[12:8]) DR/DW R/W DW R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 100723A Conexant 4-9 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Table 4-2. Operation Register Map (3 of 9) Address Register Name Block Name R, DR (Dummy Read), W, DW (Dummy Write) 01FF80C8-C9 01FF80CA-CF 01FF80D0-DF 01FF80E0-EF 01FF80F0-1 01FF80F2-3 01FF80F4-5 01FF80F6-7 01FF80F8-9 01FF80FA-FF 01FF8100 01FF8102 01FF8104 01FF8106-07 01FF8108-09 01FF810A-0B 01FF810C-0D 01FF810E-0F 01FF8110-11 01FF8112-13 01FF8114-15 01FF8116-17 01FF8118-19 01FF811A-1B 01FF811C-1D 01FF811E-1F 01FF8120-4F 01FF8150-51 01FF8152-53 01FF8154-55 01FF8156-57 01FF8158-59 01FF815A-5B 01FF815C-5D PWMCh4Ctrl (Not Used) (Not Used) (Reserved) SASCmd SASData SASDiv (Not Used) SASIRQSTS (Not Used) SSCmd SSData SSDiv (Not Used) SSCmd2 SSData2 SSDiv2 (Not Used) T4DataFIFO0 T4DataFIFO1 T4DataFIFO2 T4DataFIFO3 T4DataHold T4DataFIFOCtrl T4DataPort T4DataPortTfr (Not Used) T4RefDataFIFO0 T4RefDataFIFO1 T4RefDataFIFO2 T4RefDataFIFO3 T4RefDataHold T4RefDataFIFOCtrl T4RefDataPort PWM Logic SASIF SASIF SASIF SASIF SSIF SSIF SSIF SSIF2 SSIF2 SSIF2 T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 4-10 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 4-2. Operation Register Map (4 of 9) Address Register Name Block Name R, DR (Dummy Read), W, DW (Dummy Write) 01FF815E-5F 01FF8160-61 01FF8162-63 01FF8164-65 01FF8166-67 01FF8168-69 01FF816A-6B 01FF816C-6D 01FF816E-6F 01FF8170-71 01FF8172-73 01FF8174-75 01FF8176-77 01FF8178-79 01FF817A-7B 01FF817C-7F 01FF8180-81 01FF8182-83 01FF8184-85 01FF8186-87 01FF8188-89 01FF818A-8B 01FF818C-8D 01FF818E-8F 01FF8190-91 01FF8192-93 01FF8194-95 01FF8196-97 01FF8198-99 01FF819A-9B 01FF819C-9D 01FF819E-9F 01FF81A0-A1 01FF81A2-A3 01FF81A4-A5 01FF81A6-A7 01FF81A8-A9 01FF81AA-AB 01FF81AC-AD 01FF81AE-AF T4RefDataPortTfr T4CurDataFIFO0 T4CurDataFIFO1 T4CurDataFIFO2 T4CurDataFIFO3 T4CurDataHold T4CurDataFIFOCtrl T4CurDataPort T4CurDataPortTfr T4Config T4Control T4 Status T4IntMask T4Bytes T4FIFOBitRem (Not Used) (Not Used) DMA1Config DMA1CntLo DMA1CntHi DMA2CntLo DMA2CntHi DMA2BufCntLo DMA2BufCntHi DMA3CntLo DMA3CntHi DMA4CntLo DMA4CntHi DMA5CntLo DMA5CntHi DMA6CntLo DMA6CntHi DMA7CntLo DMA7CntHi DMA8CntLo DMA8CntHi DMA9CntLo DMA9CntHi DMA10CntLo DMA10CntHi T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block T4/T6 Block DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 100723A Conexant 4-11 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Table 4-2. Operation Register Map (5 of 9) Address Register Name Block Name R, DR (Dummy Read), W, DW (Dummy Write) 01FF81B0-B1 01FF81B2-B3 01FF81B4-B5 01FF81B6-B7 01FF81B8-B9 01FF81BA-BB 01FF81BC-BD 01FF81BE-BF 01FF81C0-C1 01FF81C2-C3 01FF81C4-C5 01FF81C6-C7 01FF81C8-C9 01FF81CA-CB 01FF81CC-CD 01FF81CE-CF 01FF81D0-D1 01FF81D2-D3 01FF81D4-D5 01FF81D6-D7 01FF81D8-D9 01FF81DA-DB 01FF81DC-DD 01FF81DE-DF 01FF81E0-E1 01FF81E2-E3 01FF81E4-E5 01FF81E6-E7 01FF81E8-E9 01FF81EA-EB 01FF81EC-FF 01FF8200-01 01FF8202-03 01FF8204-05 01FF8206-07 01FF8208-09 01FF820A-0B 01FF820C-0D 01FF820E-0F 01FF8210-11 DMA0Config DMA2Config DMA2BlkSize DMA2BufBlkSize (Not Used) DMA5BlkSize DMA6/10Throttle DMA9BlkSize DMA10BlkSize DMAIncConfig DMACntEnbConfig DMAEndian DMAUSB0CntLo DMAUSB0CntHi DMAUSB0BlkSiz DMAUSB1CntLo DMAUSB1CntHi DMAUSB1BlkSiz DMAUSB2CntLo DMAUSB2CntHi DMAUSB2BlkSiz DMAUSB3CntLo DMAUSB3CntHi DMAUSB3BlkSiz DMA11CntLo DMA11CntHi DMA11BlkSiz DMA12CntLo DMA12CntHi DMA12BlkSiz (Not Used) PIOCtrl PIOIF PIOData PIOAckPW PIORevDataSTS PIODataBusSTS PIOHostTimeOut PIOIRQSTS PIOIRQMask DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller PIO PIO PIO PIO PIO PIO PIO PIO PIO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 4-12 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 4-2. Operation Register Map (6 of 9) Address Register Name Block Name R, DR (Dummy Read), W, DW (Dummy Write) 01FF8212-13 01FF8214-1F 01FF8220-21 01FF8222-23 01FF8224-25 01FF8226-27 01FF8228-29 01FF822A-2B 01FF822C-2F 01FF8230-31 01FF8232-33 01FF8234-35 01FF8236-37 01FF8238-39 01FF823A-3B 01FF823C-4F 01FF8250-5B 01FF825C-5D 01FF825E-5F 01FF8260-61 01FF8262-63 01FF8264-65 01FF8266-67 01FF8268-69 01FF826A-6B 01FF826C-6D 01FF826E-6F 01FF8270-71 01FF8272-73 01FF8274-75 01FF8276-77 01FF8278-7F 01FF8280-81 01FF8282-83 01FF8284-85 01FF8286-87 01FF8288-89 01FF828A-A7 01FF82A8-A9 01FF82AA-AB PIOFIFOIF (Not Used) PIOOutFIFO0 PIOOutFIFO1 PIOOutFIFO2 PIOOutFIFO3 PIOOutHold PIOOutFIFOCtrl (Not Used) PIOInFIFO0 PIOInFIFO1 PIOInFIFO2 PIOInFIFO3 PIOInHold PIOInFIFOCtrl (Not Used) (Not Used) VSHiAddr1 VSLoAddr1 VSHiAddr2 VSLoAddr2 VSHiAddrStep VSLoAddrStep VSMode ABc2aBlkSiz ABa2cHiAddr ABa2cLoAddr ABc2aHiAddr ABc2aLoAddr ABa2cThrottle ABc2aThrottle (Not Used) DRAMConfig ABIIrqStat ABIIrqEnable ABICountachCtrl VSIMode (Not Used) DefRdHiAddr DefRdLoAddr PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO Countach Bus System - CDMAC Countach Bus System - CDMAC Countach Bus System - CDMAC Countach Bus System - CDMAC Countach Bus System - CDMAC Countach Bus System - CDMAC Countach Bus System - CDMAC Countach Bus System - CDMAC Countach Bus System - CDMAC Countach Bus System - CDMAC Countach Bus System - CDMAC Countach Bus System - CDMAC Countach Bus System - CDMAC Countach Bus System - CDMAC Countach Bus System - SDRAMC Countach Bus System - ABI Countach Bus System - ABI Countach Bus System - ABI Countach Bus System - VSI Countach Bus System - CBU Countach Bus System - CBU R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 100723A Conexant 4-13 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Table 4-2. Operation Register Map (7 of 9) Address Register Name Block Name R, DR (Dummy Read), W, DW (Dummy Write) 01FF82AC-AD 01FF82AE-AF 01FF82B0-B1 01FF82B2-B3 01FF82B4-FF 01FF8300-01 01FF8302-03 01FF8304-05 01FF8306-07 01FF8308-09 01FF830A-0B 01FF830C-0D 01FF830E-0F 01FF8310-11 01FF8312-13 01FF8314-15 01FF8316-17 01FF8318-FF 01FF8400-FF 01FF8500-3F 01FF8540-41 01FF8542-43 01FF8544-45 01FF8546-47 01FF8548-49 01FF854A-4B 01FF854C-4D 01FF854E-7F 01FF8580-81 01FF8582-83 01FF8584-85 01FF8586-87 01FF8588-89 01FF858A-8B 01FF858C-8D 01FF858E-8F 01FF8590-9F 01FF85A0-A1 01FF85A2-A3 01FF85A4-A5 01FF85A6-A7 01FF85A8-A9 DefWrHiAddr DefWrLoAddr DefRdData DefWrData (Not Used) ABIA2Cbuff1 ABIA2Cbuff2 ABIA2Cbuff3 ABIA2Cbuff4 ABIC2Abuff1 ABIC2Abuff2 ABIC2Abuff3 ABIC2Abuff4 CSIDMABuff1 CSIDMABuff2 CSIDMABuff3 CSIDMABuff4 (Not Used) (Not Used) (Not Used) ScanCtrl ScanCtrlStat VSCIRQStatus VSCCtrl VidCaptureCtrl SPI_Ctrl SPI_Stat (Not Used) USBEP1FIFO1 USBEP1FIFO2 USBEP1FIFO3 USBEP1FIFO4 USBEP1Hold USBEP1Ctrl USBEP1Data USBEP1Tran (Not Used) USBEP2FIFO1 USBEP2FIFO2 USBEP2FIFO3 USBEP2FIFO4 USBEP2Hold Countach Bus System - CBU Countach Bus System - CBU Countach Bus System - CBU Countach Bus System - CBU Countach Bus System - ABI Countach Bus System - ABI Countach Bus System - ABI Countach Bus System - ABI Countach Bus System - ABI Countach Bus System - ABI Countach Bus System - ABI Countach Bus System - ABI Countach Bus System - CSI Countach Bus System - CSI Countach Bus System - CSI Countach Bus System - CSI Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R only R/W R/W R/W (Bit[8] - R only) R/W (Bit[8] - R only) R only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 4-14 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 4-2. Operation Register Map (8 of 9) Address Register Name Block Name R, DR (Dummy Read), W, DW (Dummy Write) 01FF85AA-AB 01FF85AC-AD 01FF85AE-AF 01FF85B0-B1 01FF85B2-B3 01FF85B4-B5 01FF85B6-B7 01FF85B8-B9 01FF85BA-BB 01FF85BC-BD 01FF85BE-BF 01FF85C0-C1 01FF85C2-C3 01FF85C4-C5 01FF85C6-C7 01FF85C8-C9 01FF85CA-CB 01FF85CC-CD 01FF85CE-CF 01FF85D0-D1 01FF85D2-D3 01FF85D4-D5 01FF85D6-D7 01FF85D8-D9 01FF85DA-DB 01FF85DC-DD 01FF85DE-DF 01FF85E0-E1 01FF85E2-E3 01FF85E4-E5 01FF85E6-E7 01FF85E8-E9 01FF85EA-EB 01FF85EC-ED 01FF85EE-EF 01FF85F0-F1 01FF85F2-F3 01FF85F4-F5 01FF85F6-F7 01FF85F8-FF 01FF85EC-FF USBEP2Ctrl USBEP2Data USBEP2Tran USBEP3FIFO1 USBEP3FIFO2 USBEP3FIFO3 USBEP3FIFO4 USBEP3Hold USBEP3Ctrl USBEP3Data USBEP3Tran USBEP4FIFO1 USBEP4FIFO2 USBEP4FIFO3 USBEP4FIFO4 USBEP4Hold USBEP4Ctrl USBEP4Data USBEP4Tran USBEP0Buf12 USBEP0Buf34 USBEP0Buf56 USBEP0Buf78 USBVenBuf12 USBVenBuf34 USBVenBuf56 USBVenBuf78 USBVenStDat12 USBVenStDat34 USBVenStDat56 USBVenStDat78 USBDesAdr USBIRQ USBSoftReset USBStall USBPOSTDat1/2 USBPOSTDat3/4 USBPOSTDat5/6 USBPOSTDat7/8 (Not Used) (Not Used) USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface USB Interface R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W R R R R 100723A Conexant 4-15 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Table 4-2. Operation Register Map (9 of 9) Address Register Name Block Name R, DR (Dummy Read), W, DW (Dummy Write) 01FF8600-01 01FF8602-03 01FF8604-05 01FF8606-07 01FF8608-09 01FF860A-0B 01FF860C-0D 01FF860E-0F 01FF8610-11 01FF8612-13 01FF8614-15 01FF8616-17 01FF8618-19 01FF861A-1B 01FF861C-1D 01FF861E-1F 01FF8620-7FF SASTxFIFOHW0 SASTxFIFOHW1 SASTxFIFOHW2 SASTxFIFOHW3 SASTxFIFOHW4 SASTxFIFOHW5 SASTxFIFOHW6 SASTxFIFOHW7 SASRxFIFOHW0 SASRxFIFOHW1 SASRxFIFOHW2 SASRxFIFOHW3 SASRxFIFOHW4 SASRxFIFOHW5 SASRxFIFOHW6 SASRxFIFOHW7 (Not Used) SASIF SASIF SASIF SASIF SASIF SASIF SASIF SASIF SASIF SASIF SASIF SASIF SASIF SASIF SASIF SASIF R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 4-16 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 4-3. Setup Registers (1 of 2) Setup Registers are located from 01FF8800H to 01FF8DFFH. Address Register Name Block Name R, DR (Dummy Read), W, DW (Dummy Write) 01FF8800-01 01FF8802-03 01FF8804-05 01FF8806-07 01FF8808-09 01FF880A-0B 01FF880C-0D 01FF880E-0F 01FF8820-21 01FF8822-2F 01FF8830-31 01FF8832-33 01FF8834-35 01FF8836-4F 01FF8850-51 01FF8852-53 01FF8854-5F 01FF8860-6F 01FF8870-71 01FF8872-73 01FF8874-75 01FF8876-8F 01FF8880-1 01FF8882-3 01FF8884-5 01FF8886-7 01FF8888-8F 01FF8890-91 01FF8892-93 01FF8894-95 01FF8896-97 01FF8898-99 01FF889A-9B 01FF889C-9D 01FF889E-9F 01FF88A0-A1 01FF88A2-A3 01FF88A4-A5 SIUConfig ROMCtrl CS0/CS5Ctrl CS1/2Ctrl MCSCtrl FlashCtrl RotPackCtrl CS3/4Ctrl DRAMCtrl (Not Used) GPIOConfig GPIOData GPIODir (Not Used) SstepClk VPStepClk (Not Used) (Not Used) RotNN BRBWarp RotLineLength (Not Used) 125Sprescaler ICLKPeriod MSINTPeriod INTClear (Not Used) ScanCycle ScanConfig ScanDotCtrl ScanLength ScanStartDelay StartEdges StartConfig Clk2aEdges Clk2bEdges Clk2cEdges ADCSampleCfg SIU SIU SIU SIU SIU SIU SIU SIU DRAM/Flash Memory Controller GPIO Block GPIO Block GPIO Block Scan/Print Motor Control Scan/Print Motor Control Bit Rotation Block Bit Rotation Block Bit Rotation Block Fax Timing Block Fax Timing Block Fax Timing Block Fax Timing Block Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 100723A Conexant 4-17 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Table 4-3. Setup Registers (2 of 2) Address Register Name Block Name R, DR (Dummy Read), W, DW (Dummy Write) 01FF88A6-A7 01FF88A8-A9 01FF88AA-AB 01FF88AC-AD 01FF88AE-AF 01FF88B0-B1 01FF88B2-B3 01FF88B4-B5 01FF88B6-B7 01FF88B8-B9 01FF88BA-BB 01FF88BC-BD 01FF88BE-BF 01FF88C0-C1 01FF88C2-C3 01FF88C4-C5 01FF88C6-C7 01FF88C8-C9 01FF88CA-CB 01FF88CC-CD 01FF88CE-CF 01FF88D0-DF 01FF88E0-FF 01FF88900-FFF ClampCtrl ClampDelay ClampEdges LED0Edges LED1Edges LED2Edges LED0PWM LED1PWM LED2PWM LEDConfig ScanIAConfig ScanCtrlDelay ADCConfig SPIConfig SPIData (Not Used) VidLineCfg VidLLStat VidOddFLStat VidEvenFLStat (Not Used) (Not Used) Reserved (Not Used) Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller Video/Scan Controller R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (Bit[15:8] - R only) R/W R only R only R only 4-18 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 4.2 4.2.1 Cache Memory Controller Functional Description Cache Summary 4.2.1.1 * * * * * * * * 4 kB instruction cache RAM with expansion capability Physical address cache access and cache tags Two Way Set Associative with LRU algorithm 16 bytes cache line size with 128 cache lines in each way Supports both ARM and thumb mode instructions Cache memory can be enabled or disabled Provides lock function and flush function Interfaces between ARM7TDMI and SIU (System Interface Unit) Cache Overview 4.2.1.2 The Cache Controller is an instruction only cache; a level 1 cache for ARM7TDMI. The cache, when enabled, will support zero wait state sequential instruction access from ARM provided the instruction is in the cache and valid (Cache hit). If an instruction is not found in the cache memory (Cache miss), the Cache Controller will activate the LRU (Least Recently Used) replacement algorithm. In this case, the ARM will incur a number of wait states depending on the memory speed. The 4 kB Cache Memory is divided into two Ways, which means 2 kB per Way. Each Way is further divided into 128 Cache Lines with 16 bytes of instructions in each Line. If a Cache miss is detected and Cache Line fill is required, the Cache Controller will replace the least recently used (LRU) Cache line, the Cache Line fill operation is done in burst (sequential), minimizing the overhead. The ability for the software to lock the entire Cache or individual line and to flush the entire Cache Memory contents are provided. In addition, the Cache Memory and Cache Tags can be placed in Test Mode for power-up verification and system diagnoses. The entire Cache Memory and Cache Controller can also be disabled allowing the ARM to bypass the Cache Controller unit. Way Way 1 0 16 bytes 1 bit 1 bit 1 bit 21 bits 32 bits 32 bits 32 bits 32 bits vL 128 Sets a[31 : 11] Cache Tag (128 Sets) W3 W2 Cache ( 2K W1 RAM Bytes ) W0 LRU Figure 4-3. MFC2000 Cache Organization 100723A Conexant 4-19 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Table 4-4. Cache Tag Data Format (for Test Mode Read/Write Operation) Cache Tag Data Format Bits 31 30:23 22 21 20:0 Description LRU bit, accessible only through Way 0 Tag Read Unused Bits Lock Valid A[31:11] 4.2.1.3 Cache RAM The Cache RAM consists of four 512 X 16 Asynchronous Static RAM modules, and they are organized into two 512 words (32 bit/word) to support two way set associative. The memory map for direct accesses while in Test Mode or Lock Mode is as follows: WAY 0: $01FE0000-$01FE07FF WAY 1: $01FE0800-$01FE0FFF 4.2.1.4 Cache Tags The Cache Tags are defined as follows: Valid (1 bit): A 1 in this bit indicates that the Tags and data at the addressed Cache Line are both valid. Neither Tags nor data have meaning if this bit is 0. Upon power up, the tag memories will undergo an automatic flush operation that requires 128 clocks. During the flush operation, the cache is disabled. A 1 in this bit indicates that the Tags and data at the addressed Cache Line are both valid and locked and should not be replaced when a Cache miss is detected. Indicates that the Tags and data at the addressed Cache line (if not locked) at Way 0 can be replaced if this bit is 0. If this bit is a 1, the Cache Line and Tags in Way 1 should be chosen for replacement. Lock (1 bit): LRU (1 bit): Unused (8 bits): Unused bits are undefined. A[31:11]: Address Tag bits which together with Cache address (A[10:4]), uniquely identify a Cache Line in the entire 32-bit physical address space. The Cache Tags are memory mapped to the following address space (not fully utilized) when in the Test Mode or Lock Mode : WAY 0: $01FE1000-$01FE17FF WAY 1: $01FE1800-$01FE1FFF It should be noted that bits 2-3 of the addresses are not decoded during the Tag entry accesses, i.e., $sa+00, $sa+04, $sa+08, and $sa+0C all access the same Tag entry. 4.2.1.5 Accessing the Cache To access the Cache during an instruction fetch, the Cache Controller performs the normal cache operation. If accesses are performed during Test mode or Lock mode, the Tag RAM and Cache RAM are treated as regular memories. If the Cache is enabled, regardless of cache hit or miss, the Cache Controller asserts one wait state for every non-sequential cycle to start the instruction fetch cycle. 4-20 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 If the access results in a hit, the wait state is de-asserted and a 32-bit Cache data is output to the ARM. Subsequent Sequential (S-cycles) access(es) require zero wait state if they are found in the same Cache Line. If the access crosses Cache Line boundary, the Cache Controller will add one wait state for the first S cycle that crosses the boundary, and then add additional wait states if it results in a cache miss. If the access misses the Cache, the Cache Controller extends the wait states until the corresponding cache data or cache line is received from external memory through SIU. The number of wait states inserted is affected by the status of the lock bit for the corresponding Cache Line. If the Line is not locked, then the Cache Line fill operation will be performed and the required wait state will depend on the speed and the data width of the external devices. If the Cache Line is locked, the Cache Controller will re-generate the ARM cycle and forward the cycle to SIU. The required wait states in this case will be much less than that of Cache Line fill, but still a few cycles more than a simple pass-through operation when the Cache is disabled. This is due to the time required for the tag comparison. It should be noted that, in the case of Cache Line fill, the requested data is not transferred to the ARM until the Cache Line fill operation is completed. 4.2.1.6 Definition of a Cache Hit There are two requirements for a Cache hit. First the ARM A[31:11] must match the Cache Address Tags accessed by A[10 :4] in an instruction fetch cycle. Second, the addressed Cache Line must be Valid. 4.2.1.7 LRU Algorithm The LRU (Least Recently Used) algorithm is applied when a Cache miss is detected. This algorithm first looks for a non-valid Line in the Set for a replacement. The order that is used for this checking is Way 0 first, then Way 1. If both lines associated with the Set are valid, then the Lock bit check is followed. If both are not locked, then the LRU bit (one bit only) associated with the Set is tested. If it is a zero, the Cache Line in Way 0 is replaced; otherwise, Way 1. If both are locked, no replacement can be performed and the Cache Controller will convert the cycle from instruction fetch to data fetch and forward the cycle to SIU for the requested instruction. If only one of the two lines is locked, the unlocked line will be chosen for the replacement. 4.2.1.8 SIU interface The ARM to SIU interface behaves differently depending on whether the Cache is enabled or not. If the Cache is disabled, the only affect that the Cache Controller adds to the ARM/SIU interface is a small propagation delay for those signals that pass through the Cache Controller (refer to the block diagram for the pass-through signals). On the other hand, if the Cache is enabled, the Cache controller will response to an instruction cycle by either providing data to the ARM in a cache hit, or, converting the instruction cycle to a series of burst data cycle(s) and forwarding them to SIU in a cache miss. 100723A Conexant 4-21 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 4.2.2 Register Description Bit 7 N/A Bit 6 Flush Cache Bit 5 Global Lock Bit 4 Lock Mode Bit 3 Test Mode Bit 2 Cache Enable Bit 1 N/A Bit 0 N/A Default Rst Value 00h Name/Address Cache Control Register $01FF8800 This register resides in the SIU block. The SIU, upon detecting the set condition for a given bit(s) in this register, asserts the corresponding control signal(s) to the Cache controller. Bit 7 Bit 6 Reserved Flush Cache Read/writable bit. Writing a 1 to this bit flushes all Valid bits, LRU bits, and Lock bits in the Cache Tag to zero. It requires 128 cycles to flush the entire Tag memory area. This bit will be automatically reset upon completion of the flush operation. Flush does not reset Global Lock or Cache Enable condition if present. Read Writable bit. Writing a 1 to this bit locks the entire Cache memory; a 0 unlocks the Cache. This bit provides a quick way to lock the entire cache memory. Read/writable bit. Writing a 1 to this bit and a 0 to the Cache Enable bit places the Cache in the Lock Mode. The Cache stays in Lock Mode until a 0 is written to this bit. Read/writable bit. Writing a 1 to this bit and a 0 to the Cache Enable bit sets the Cache into test mode. In test mode, the Cache RAMs and Tags can be accessed in the same manner as regular memory. Certain Tag bits are readable only. The Cache stays in Test Mode until a 0 is written to this bit. Read/writable bit. Writing a 1 enables the Cache and the Cache stays enabled until a 0 is written or a reset is received. Power-up resets to 0 and disables the Cache. Bit 5 Global Lock Bit 4 Lock Mode Bit 3 Test Mode Bit 2 Cache Enable Bit 1 Bit 0 Reserved Reserved 4-22 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 4.2.3 4.2.3.1 Firmware Operation Enabling the Cache The Cache Enable bit in the SIU Cache Control register determines if the Cache is enabled or not. In power-up reset state, the Cache is disabled. If disabled, all CPU accesses go directly to the SIU and the Cache Controller passes through all signals from ARM to SIU. After the power-up reset, all Cache Tag entries are flushed after 128 clocks. If the Cache is enabled after power-up, the Cache Controller starts to update the Cache memory and Cache tag after the flush operation is completed. 4.2.3.2 Locking the Cache The system can lock the entire cache memory by setting GLOBAL LOCK bit to 1 in Cache Control register. The Cache remains locked until the bit is reset. Setting and resetting the Global _Lock bit has no effect on the individual lock bit set during the Lock mode, the individual lock bit can be cleared by setting Flush_Cache bit to 1. The system can also lock an individual Cache Line by placing the Cache in the Lock Mode. Once in the Lock mode, the system can access the Cache RAM and Tag RAM as if they were regular memory. A write to the Tag entry sets both the Lock bit and Valid bit for the corresponding Tag. The software is responsible for properly mapping the instructions from ROM (`where to be cached in') into Cache RAM and Tag RAM (`where to be locked down') based on the modular of 2048 bytes. In other words, the A10-A2 of address lines used for the ROM code and Cache/Tag RAM's entry must be identical, and the A31-A11used for the ROM code becomes the data entry for the corresponding Tag entry. Caching is disabled during lock mode; the system must exit the lock mode before enabling the Cache. Once a Cache line is locked, LRU replacement policy prevents the replacement of the locked Cache Line. If both Cache Lines in a Set (two Ways) are locked, the LRU algorithm is not able to replace either Line; thus, no Cache Line fill is performed; instead, a data fetch N (non-sequential) cycle is generated by the Cache Controller and sent to the SIU. A minimum of 5 wait states is expected. 4.2.3.3 Flushing the Cache The system can clear the Cache by activating the Flush input. This signal is generated by the SIU when the Flush bit in the Cache Control register is set by the system. Upon receiving the Flush input, the Cache Controller starts the flush operation. The operation takes 128 clocks to resets all the Tag Valid bits, LRU bit, and Lock bit. During the operation the cache, if enabled, is temporarily disabled until the flush is completed. The Flush bit is cleared automatically at the end of the flush operation. 4.2.3.4 Testing the Cache and Tag Memories The system can access the Cache memory and Tag RAM as regular memory does when in Test mode. Test mode is entered after setting the Test bit in the Cache Control register. In Test mode, the Tag RAM and Cache RAM behave like an ordinary memory for read/write cycles. This test feature is not only required for the power-up self test, but also is important for diagnostics when a system problem develops. The contents of the TAG and Cache RAM are essential to the investigation of the problem. Note: The Valid bit, Lock bit, and LRU bit can only be read, not written, and LRU is only available through Way 0 access. Note: It is important to flush the Cache upon completion of the Test Mode. 100723A Conexant 4-23 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 4.3 4.3.1 SIU Functional Description The System Integration Unit (SIU) is responsible for interfacing between the ARM7TDMI core, the Cache Memory Controller, the Internal Peripheral Bus (IPB), and the External Bus (EB). The ARM7TDMI core and the Cache Memory Controller are on the Internal System Bus (ISB). The ISB data bus is 32-bits wide and the IPB and EB data buses are 16-bits wide. The SIU generates the external chip selects along with chip selects to all the internal peripherals. It provides the following functions: 1. Interfaces between the Internal Peripheral Bus (IPB), the Internal System Bus (ISB) and the External Bus (EB). The SIU allows bus master devices on the IPB and ISB. 2. Control the chip selects to devices on the IPB, the ISB, and the EB. 3. Address multiplexing for DRAM access. 4. ROM interleave control (including wait state control for the interleave mode): no interleave and 2-way interleave with external Q-switch. 5. Fast page mode ROM operation. 6. Even though ARM7TDMI is fixed to the little endian in this MFC2000 chip, the SIU can support the little endian or big endian for the DMA operation. 7. Support Arm and Thumb mode operations. 4.3.1.1 IPB Bus The IPB Bus supports both 8-bit and 16-bit peripherals. The ARM or an internal bus master such as DMA can access a device residing on the IPB bus. The SIU provides the chip selects to each of the internal peripheral devices. The chip selects are driven in the second clock cycle of an IPB bus cycle. The peripheral device needs to decode only the address lines required to access the specific registers within the block. Transactions on the IPB bus only occur when a device on the IPB bus is being accessed. All accesses on the IPB bus require two peripheral bus clock cycles (2 SIUCLK's). During the first cycle, the address is decoded and determined if an access to an internal peripheral is occurring. During the second cycle the peripheral chip select is asserted, and the access occurs. During Write operations to peripherals, signals BS[1:0] are used to signal which bytes are valid on the data bus. 8-bit peripherals can ignored these signals. 16-bit peripherals MUST use these signals to allow each 8-bit half of the peripheral registers to be written independently. This is due to the fact that the ARM compiler may generate two byte transactions when accessing a 16-bite register on the IPB instead of a single halfword transaction. During Read operations, the peripherals must fill the 16-bit IPB data bus. If the peripheral is less than 16-bit wide, it should fill the empty bits with 0. IPB, ISB and External Bus 4-24 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 ISB Bus The ISB Bus is used for connecting ARM and Cache Controller to the highest performance. The 32-bit ISB bus directly interfaces with the ARM core 32-bit data bus. The cache memory controller resides on this bus. All control signals to and from the ARM, and its address bus go through the cache memory controller regardless of the cache enable bit. The cache controller control register resides in the SIU. When the ARM is fetching instructions, and it is a cache hit situation, the ARM gets the instructions from the cache. The SIU lets the other bus masters have the bus. When the ARM is fetching instructions, and it is a cache miss situation, the SIU must perform a burst read of eight halfwords (4 words) to fill up the cache line if the cache line is not locked. If the cache line is locked, then the SIU reads in two halfwords (one word) of instruction. When the ARM is fetching data, data is passed directly from the SIU to the ARM. EB Bus The EB Bus is used for connecting external memories and devices. The width of the selected slave device is programmable in the chip select configuration register. The external A[23:12] and A[11:0] addresses are multiplexed through A[11:0] pins. The ALE signal is provided to latch A[23:12] addresses externally. External Chip Selects The SIU provides programmable external chip selects. Each chip select is programmable through the chip select configuration register. * * * * * * Each chip select can be configured to be: enabled or disabled (default = enabled). programmable from 0 up to 7 wait states. programmable read/write delay-on (write strobe activated one or two SIUCLK cycles later). programmable write early-off (read or write strobe deactivated one SIUCLK cycle earlier). programmable to allow for 8 or 16 bit devices. The SIU will automatically perform the necessary transaction to access any size data as long as the source of the transaction is internal. Note: The RD/WR-delay-on and WR-early-off settings should be disabled for zero wait state access. For other wait state settings (> 1wait state), the delay-on and early-off will shorten the width of read/write strobe. Firmware has the responsibility to set RD/WR-delay-on and WRearly-off bits correctly. Otherwise, read or write strobes may disappear. For example, if 1 wait state and 1 RD/WR-delay-on are set for a chip select, the read strobe is not suppressed when firmware tries to do a read operation. If 2 wait states, 1 WR-early-off and 1 RD/WR-delay-on are set for a chip select, the write strobe is not suppressed when firmware try to do a write operation. ROM Interface The SIU supports non-interleave, 2-way interleave and fast page mode access to ROM, depending on the ROM Access Configuration pins (AE[2]/ROM_CFG[0] and AO[2]/ROM_CFG[1] pins). Following are the four configurations supported by the SIU. ROM Access Configuration[1:0] 00 01 10 11 ROM Mode 8-bit non-interleave 16-bit non-interleave 16-bit 2-way interleave 16-bit fast page mode 100723A Conexant 4-25 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description The MFC2000 assigns 4 multi-function pins (AE[2], AO[2], AE[3], and AO[3]) to facilitate the interleave access. SIU generates 4 signals on these 4 pins to control ROMs for the following types of interleave accesses. * In 2-way interleave mode, MFC2000 pins AE[2] ,AO[2], AE[3], and AO[3] are connected to pin A[1:0] of the even and odd external ROMs. MFC2000 pins A[1:0] are used to enable the ROM's data busses. ROMCSn RDn A[25] A[4] AE[3] AE[2] A23 CS OE A[25] A[4] AO[3] AO[2] A23 CS OE EVEN A2 A1 A0 D DD A2 A1 A0 ODD D A[0] EN Q-SW A[1] EN Q-SW D Figure 4-4. 2-Way Interleave ROM Connection * * * * The ROMCSn can be programmed to have up to 7 wait states for the initial access, and up to 1 wait state for the sub-sequential access. The write access to the ROM chip select area (ROMCSn) is allowed. It is customer's choice to use it or not. To use NOR-type flash memory in the ROM chip select area, WREn and WROn are designed to be used as the write strobes for the different banks in the interleave mode (not for the higher and lower bytes). Therefore, the 16-bit wide flash memory should be used in order to avoid the extra glue logic. For non-interleave mode flash memory in the ROM chip select area, the WROn is used to access the higher byte of the 16-bit data bus and the WREn is used to access the lower byte of the 16-bit data bus. Assume that W wait states are needed for the initial access to ROM and S wait states (S = 0 or 1) for the subsequential access according to the CPU clock frequency and the ROM speed. For a burst of 8 half-words interleave access, the wait state of each half-word access, assuming the starting address's A[3:1]=000. We can have the following table show all different access modes for reading from ROM. 4-26 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 4-5. Access Modes for Reading ROM ROM Access Mode Data Type Cache Memory Wait States Notes 8-bit noninterleave instruction Cache enabled and Cache miss w,w,w,w,w,w,w,w w,w,w,w,w,w,w,w (16 sequential accesses) w,w,w,w,w,w,w,w (8 sequential accesses) w w w w w, s, w-s-1, s, w-s-1, s, w-s-1, s (8 sequential accesses) This is cache burst access. Save the address decoding cycle for all accesses except the first access. 16-bit noninterleave 8-bit noninterleave 16-bit noninterleave 8-bit noninterleave 16-bit noninterleave 16-bit 2-way interleave instruction instruction instruction data data instruction Cache enabled and Cache miss Cache disabled Cache disabled Not applied Not applied Cache enabled and Cache miss This is cache burst access. Save the address decoding cycle for all accesses except the first access. If the sequential access occurs, save the address decoding cycle for all accesses except the first access. If the sequential access occurs, save the address decoding cycle for all accesses except the first access. If the sequential access occurs, save the address decoding cycle for all accesses except the first access. If the sequential access occurs, save the address decoding cycle for all accesses except the first access. This is cache burst access. 0 or 1 wait state is programmable and depends on the CPU clock frequency and the ROM speed. If `w-s-1' is less than 1, it will be forced to 1. 16-bit 2-way interleave instruction Cache disabled w, s, w-s-1, s, w-s-1, s, w-s-1, s (one interleave access sequence) The actual sequential access length is dynamic. 0 or 1 wait state is programmable and depends on the CPU clock frequency and the ROM speed. If the starting address of the sequential access is not lined up with the octal address boundary of the interleave access, the partial interleave access sequence should be done. Then, restart the interleave access sequence at the octal address boundary of the interleave access. Even if the stopping address of the sequential access is not lined up with the octal address boundary of the interleave access, the access sequence must be stopped immediately at anywhere. If `ws-1' is less than s, it will be forced to s. 0 or 1 wait state is programmable and depends on the CPU clock frequency and the ROM speed. If the starting address of the sequential access is not lined up with the octal address boundary of the interleave access, the partial interleave access sequence should be done. Then, restart the interleave access sequence at the octal address boundary of the interleave access. Even if the stopping address of the sequential access is not lined up with the address boundary of the interleave access, the access sequence must be stopped immediately at anywhere. If `ws-1' is less than s, it will be forced to s. 16-bit 2-way interleave data Cache enabled and Cache miss w, s, w-s-1, s, w-s-1, s, w-s-1, s (one interleave access sequence) The actual sequential access length is dynamic. 100723A Conexant 4-27 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description If the ROM write access (Flash memory in the ROM address range) is performed in the interleave access mode, the SIU still generates those signals to control ROMs and external multiplexes to perform the interleave access. But, all the access (no matter if it is the sequential access or not) have W wait states. External DRAM Interface When the decoded address from any bus master matches external DRAM address, the SIU will issue a DRAM request to the DRAM controller and start the transaction . First, it routes the DRAM row address to the address bus. After receiving the column enable signal from the DRAM controller, the SIU multiplexes the DRAM column address to the same address bus according to the size of the DRAM . The SIU will perform the next transaction after receiving the DRAM ready back from the DRAM controller signaling the DRAM transaction is complete. The SIU also looks at the burst request signals from the bus master who owns the bus to generate the BURST signal to the DRAM Controller indicating a burst access. Bus Arbitration The bus arbitrator block arbitrates control of the internal and external busses between the ARM7TDMI core and any bus master devices (such as DMA) residing on the IPB or ISB. The ARM core is the default bus master and has control of the bus whenever no other bus master requests it . In arbitrating control of the bus, the arbitrator gives highest priority to the DMA Controller and then, the ARM core. In burst mode access (both DMA and CPU), the bus is not arbitrated within the burst access. In order to prevent a bus master from hogging the bus. The maximum burst length allowed is eight halfword access. The DMA of internal peripherals only bursts a maximum of five halfwords. A bus master requests the bus by asserting request. The arbitrator grants the bus to the requesting bus master by asserting grant. The requesting bus master must continue to assert request for as long a bus ownership is required and release the bus by de-asserting request. The arbitrator always inserts a single dead cycle before granting the bus to another bus master. Little Endian and Big Endian The little endian and big endian control is only for internal DMA (The DMA request is from an internal peripheral). When a DMA access requires different endian format. the corresponding bit of the DMAEndian register needs to be set. The SIU will transform the endian format; from little endian DMA address and data into big endian format or from big endian DMA address and data into little endian format. The even and odd write signals (WREn, WROn) also change accordingly. The following tables show the final addresses and data at the ASIC pins, and the resulting DMA read or write data. Internal DMA data size is always 16 bits (a halfword). 4-28 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 4-6. Read Operation (Internal Peripheral Gets Data From Memory) BIG ENDIAN DMA SIZE MEM SIZE DMA_AD DMA DATA (output) Half Word Half Word Half Word Half Word Byte Byte Half Word Half Word 0000 0010 0000 0010 Byte 2, Byte 3 Byte 0, Byte 1 Byte 2, Byte 3 Byte 0, Byte 1 0011,0010 0001,0000 0010 0000 LITTLE ENDIAN MEM ADDR MEM DATA (input) Byte 3, Byte 2 Byte 1, Byte 0 Byte 3, Byte 2 Byte 1, Byte 0 Table 4-7. Write Operation (Internal Peripheral Puts Data Into Memory) LITTLE ENDIAN DMA SIZE MEM SIZE DMA_AD DMA DATA (input) Half Word Half Word Half Word Half Word Byte Byte Half Word Half Word 0000 0010 0000 0010 B1,B0 B3,B2 B1,B0 B3,B2 0011,0010 0001,0000 0010 0000 MEM ADDR BIG ENDIAN MEM DATA (output) B0,B1 B2,B3 B0,B1 B2,B3 0 0 0 0 0 0 0 0 WRON WREN 100723A Conexant 4-29 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 4.3.2 Register Description SIU Control Address Bit 15 Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 CS4n Read Only Default Rst. Value xxxxxxx0b Read Value 00h SIU Configuration (Not Used) (SIUConfig) 01FF8801 Address Bit 7 Bit 6 Flush Cache Bit 5 Bit 4 Bit 3 Bit 2 Cache Enable Bit 1 Disable Force External Bit 0 Disable Abort Default Rst. Value 00h Read Value 00h SIU Configuration CS3n Write Only (SIUConfig) 01FF8800 Global Lock Cache Lock Cache Test Mode Mode Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 CS4n Read only CS3n Write only Flush: Write only bit. Writing a 1 makes CS4n a read only CS. Default is 0. Writing a 1 makes CS3n a write only CS. Default is 0. Writing a 1 generates a pulse which flushes all Valid bits, LRU bits and Lock bits in the Cache Tag. Default is 0 Global_Lock: Read/writable bit Writing a 1 locks the whole Cache. The Cache stays in Lock Mode until a 0 is written. Default is 0. Cache_Lock: Read/writable bit Writing a 1 places the Cache in the Lock Mode and the Cache stays in Lock Mode until a 0 is written. Each cache line is locked individually . Default is 0 Cache_Test: Read/writable bit Writing a 1 sets the Cache into Test Mode and the Cache RAM and Tags can be accesses as regular memory. Note that certain Tag bit only readable . The Cache stays in Test Mode until a 0 is written to this bit. Default is 0. Bit 3 Bit 2 Cache_Enable: Read/writable bit Writing a 1 enables the Cache and the Cache stays enabled until a 0 is written or a reset is received. Power-up resets to 0, so the Cache is disabled. Force_external This signal will disable the forcing of all accesses to be visible on the external bus regardless of destination. If this signal is enabled, only external transactions will be visible on the external bus. 1 is disabled, 0 is enabled. Default is 0. This signal disables abort generation for internal and external access. If this signal is a 1, all transactions to internal and external address space will be allowed to occur regardless of if an valid internal or external peripheral exists. If this signal is 0, then accesses must be to valid peripheral locations or an abort signal will be generated. Default is 0. Bit 1 Bit 0 Disable_abort: 4-30 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 External Chip Select Control Registers Associated with each external chip select pin is a register to control automatic functions that will be executed when a location within the chip select range is accessed. All bits default to 0 unless otherwise specified. Several control functions are common between the various chip select register. A chip select is enable when the enable bit is set to 1. Wait states defines the number of wait states that are added to the associated bus cycle, in increments of SIUCLK cycle. A bus cycle is 1 SIUCLK. Size is the width of the external devices peripherals using the chip select. The allowable widths are 8 and 16 bits. Size are coded : 0=byte, 1 = half-word. If the size of the data is larger than the size of the peripheral, the SIU will automatically perform multiples accesses to complete the transaction. Default to 0. Where applicable, Strobe Delay On = 1 delays the activation of RDn or WRn by 1 clk. Write Early Off deactivates the WRn strobe by 1 clk earlier. Address ROMCS Control (ROMCtrl) 01FF8803 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Rst. Value xxh Read Value 00h Address ROMCS Control (ROMCtrl) 01FF8802 Bit 7 Bit 6 Bit 5 Mode[0] (read only) Bit 4 Bit 3 Bit 2 Wait[1] Bit 1 Wait[0] Bit 0 Enable Default Rst. Value 1??11111b Read Value 1??11111b Read/Write Mode[1] Strobe (read only) Delay On Subsequent Wait[2] Wait Bit 7 Bits 6-5 Read/Write strobe Delay On (default = 1) Mode[1:0] ROM interface mode (read only). These 2 bits are read in directly from 2 pins (the AE[2]/ROM_CFG[0] pin and the AO[2]/ROM_CFG[1] pin during reset). 00: 8-bit Non Interleave 01: 16-bit Non interleave 10: 16-bit 2way interleave 11: 16-bit fast page mode Bit 4 Bits 3-1 Bit 0 ROMCSn Enable. Note: Subsequent access wait states in interleave mode (default = 1) Wait states or initial access wait states in interleave mode (default = 7) (default = 1) These controls are also applicable to the optional CS5n. 100723A Conexant 4-31 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address CS5 Control (CS5Ctrl) 01FF8805 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Wait[2] Bit 10 Wait[1] Bit 9 Wait[0] Bit 8 Enable Default Rst. Value xxh Read Value 00h Write Strobe Read/Write Read/Write Size Early Off Strobe Strobe Delay Delay On[1] On[0] Address CS0 Control (CS0Ctrl) 01FF8804 Bit 7 Bit 6 Bit 5 Bit 4 Size Bit 3 Wait[2] Bit 2 Wait[1] Bit 1 Wait[0] 0 Bit 0 Default Rst. Value 00x00000b Read Value 00h Write Strobe Read/Write (Not Used) Early Off Strobe Delay On Bit 7,15 Bit 5 Bit 4,12 Write Strobe Early Off (default =0) (default = 0) (Not used) (default = 0 . Byte ) Mode = 0: 8-bit access 1: 16-bit access Bit 6,14-13 Read/Write Strobe Delay On Size Bit 3-1, 11-9 Wait states Bit 8 CS5n Enable Note: (default =0) The enable control for CS0 is set by the Battery Control Logic. Address CS2 Control (CS2Ctrl) 01FF8807 Bit 15 Write Strobe Early Off Bit 14 Read/Write Strobe Delay On[1] Bit 13 Bit 12 Bit 11 Wait[2] Bit 10 Wait[1] Bit 9 Wait[0] Bit 8 Enable Default Rst. Value 01h Read Value 01h Read/Write Size Strobe Delay On[0] Address CS1 Control (CS1Ctrl) 01FF8806 Bit 7 Write Strobe Early Off Bit 6 Read/Write Strobe Delay On[1] Bit 5 Bit 4 Bit 3 Wait[2] Bit 2 Wait[1] Bit 1 Wait[0] Bit 0 Enable Default Rst. Value 01h Read Value 01h Read/Write Size Strobe Delay On[0] Bit 15 Bit 12 Write Early Off strobe Size (default =0 ) (default = 00) (default = 0. Byte ) 0: 8-bit access 1: 16-bit access (default =0) (default = 1) . (default =0) (default = 00) Bit[14:13] Read/Write strobe Delay On Bit[11:9] Bit 8 Bit 7 Bit[6:5] Wait states CS2n Enable Write Early Off strobe Read/Write strobe Delay On 4-32 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Bit 4 Size (default = 0. Byte) 0: 8-bit access 1: 16-bit access (default =0) (default = 1) Bit 14 Read/Write Strobe Delay On[1] Bit 13 Bit 12 Bit 11 Wait[2] Bit 10 Wait[1] Bit 9 Wait[0] Bit 8 Enable Default Rst. Value 01h Read Value 01h Bit 3 Wait[2] Bit 2 Wait[1] Bit 1 Wait[0] Bit 0 Enable Default Rst. Value 01h Read Value 01h Bit[3:1] Bit 0 Address Wait states CS1n Enable Bit 15 Write Strobe Early Off CS4 Control (CS4Ctrl) 01FF880F Read/Write Size Strobe Delay On[0] Address CS3 Control (CS3Ctrl) 01FF880E Bit 7 Write Strobe Early Off Bit 6 Read/Write Strobe Delay On[1] Bit 5 Bit 4 Read/Write Size Strobe Delay On[0] Bit 15 Bit 12 Write Early Off strobe Size (default =0 ) (default = 00) (default = 0. Byte) 0: 8-bit access 1: 16-bit access (default =0) (default = 1) (default =0) (default = 00) (default = 0. Byte) 0: 8-bit access 1: 16-bit access (default =0) (default = 1) Bit[14:13] Read/Write strobe Delay On Bit[11:9] Bit 8 Bit 7 Bit[6:5] Bit 4 Wait states CS4n Enable Write Early Off strobe Read/Write strobe Delay On Size Bit[3:1] Bit 0 Wait states CS3n Enable Address Modem CS Control (MCSCtrl) 01FF8809 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 Modem Interrupt Select Default Rst. Value xxxxxxx0b Read Value 00h Address Modem CS Control (MCSCtrl) 01FF8808 Bit 7 Bit 6 Bit 5 Bit 4 Size Bit 3 Wait[2] Bit 2 Wait[1] Bit 1 Wait[0] Bit 0 Enable Default Rst. Value 00x00001b Read Value 01h Write Strobe Read/Write (Not Used) Strobe Early Off Delay On Bit 7 Bit 7 Bit 6 Bit 5 100723A Select P80 or external MIRQn interrupt ( default =0, select P80 ) Write Early Off strobe Read/Write strobe Delay On (default =0 ) (default = 00) (Not Used) Conexant 4-33 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Bit 4 Size (default = 0 . Byte) 0: 8-bit access 1: 16-bit access Bit 3,2&1 Wait states (default =0) Bit 0 MCSn Enable. (default = 1) Address: Flash Memory Control (FlashCtrl) Bit 15 (Not Used) Bit 14 Bit 13 Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 Bit 9 Bit 8 Default: Rst. Value x8h Read Value 08h (Not Used) (Not Used) FCS1n value FCS0n value FCS1n disable for NAND for NAND type type 01FF880B Address: Flash Memory Control (FlashCtrl) Bit 7 Bit 6 Bit 5 Bit 4 Size Bit 3 Wait[2] Bit 2 Wait[1] Bit 1 Wait[0] Bit 0 FCS0n disable Default: Rst. Value 00x00000b Read Value 00h Write Strobe FCSn (Not Used) Early Off NAND-type 01FF880A Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 4 Output value of FCS1n when NAND-type memory is used. Not applicable for NOR-type memory. Output value of FCS0n when NAND-type memory is used. Not applicable for NOR-type memory. 1= Disable FCS1n Write Early Off strobe Size (default = 0: Enable) When this bit is set to 1, pin PWM2/FCS1n is used as PWM2. (default =0) (default = 0 . Byte) 0: 8-bit access 1: 16-bit access (default =0) (default = 0: Enable) When this bit is set to 1, pin PWM0/FCS0n is used as PWM0. NAND-type memory is used when this bit is set to 1. (default =0 . NOR type). Bit[3:1] Bit 0 Wait states 1= Disable FCS0n 4-34 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address RotPacked Data register Access Control (RotPackCtrl) 01FF880D Address RotPacked Data register Access Control (RotPackCtrl) 01FF880C Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) Rst. Value xxh Read Value 00h Bit 7 Write Strobe Early Off Bit 6 Read/Write Strobe Delay On[1] Bit 5 Bit 4 Bit 3 Wait[2] Bit 2 Wait[1] Bit 1 Wait[0] Bit 0 Enable Default Rst. Value 01h Read Value 01h Read/Write Size Strobe Delay On[0] Bit 7 Bit[6:5] Bit 4 Write Early Off strobe (default =0 ) Read/Write strobe Delay On (default = 00) Size (default = 0. Byte) 0: 8-bit access 1: 16-bit access Bit[3:1] Bit 0 Wait states (default =0) RotPackedData register access enable. (default = 1) Note: This register is used to set up the access timing for the DMA read from RotPackedData register to the external PIF device. It provides the control of wait states and RDn width when accessing the RotPackedData. 100723A Conexant 4-35 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 4.3.3 Timing SIUCLK (internal clock) ARM_A[31:0] A B C Internal internal D ALE EXT_AD[11:0] C A[23:12] A[11:0] A[11:0]+2 B[23:12] B[11:0] B[11:0]+1 B[11:0]+2 B[11:0]+3 C[23:12] C[11:0] D[23:12] D[11:0] "+1 CSn RDn WRn Read Data Write Data Byte0 B1 B2 B3 Figure 4-5. Zero Wait State, Single Access, Normal Read, Normal Write 4-36 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 SIUCLK (internal clock) ARM_A[31:0] A Internal B C ALE EXT_AD[11:0] A[23:12] A[11:0] A[11:0]+2 B[23:12] B[11:0] B[11:0]+1 B[11:0]+2 B[11:0]+3 C[23:12] CSn RDn WRn Read Data Write Data Byte0 Byte1 Byte2 Byte3 Figure 4-6. One Wait State, Single Access, One Read, One Write 100723A Conexant 4-37 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description SIUCLK (internal clock) ARM_A[31:0] A B C ALE EXT_AD[11:0] A[23:12] A[11:0] A[11:0]+2 B[23:12] B[11:0] B[11:0]+2 C[23:12] C[11:0] CS1n CS2n RDn WRn Read Data Write Data Byte0 Byte1 Figure 4-7. Two Wait States, Single Access, Read On Delayed (CS1n), Write Early Off (CS2n) 4-38 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 SIUCLK (internal clock) ARM_A[31:0] A1 A2 A3 A4 A5 A6 A7 A8 ALE EXT_AD[11:0] A1[23:12] A1[11:0] A2[11:0] A3[11:0] A4[11:0] A5[11:0] A6[23:12] A6[11:0] A7[11:0] A8[11:0] CSn RDn WRn Read Data Write Data OCTAL BOUNDARY Figure 4-8. Zero Wait State, Burst Access, Normal Read, Normal Write 100723A Conexant 4-39 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description SIUCLK (internal clock) ARM_A[31:0] A A+2 A+4 C B B+2 B+4 B+6 ALE EXT_AD[11:0] A[23:12] A[11:0] A[11:0]+2 A[11:0]+4 B[23:12] B[11:0] B[11:0]+2 B[11:0]+4 B[11:0]+6 ROMCSn RDn WREn/WROn Figure 4-9. Fast Page Mode ROM Access1,0,0 Read Access Followed by 1,1,1,1, Write Access 4-40 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Detail External Bus Timing 3 wait states SIUCLK (internal clock) A[11:0] t AD upper address lower address tAAD tAAH ALE t ALD Ext. CS's (romcsn, gpio21(mcsn),gpio74(cs5,2n), cs1n,cs0n) RDn t CSD t RD t RD WREn, WROn t WD t WD t WD t WD GPIO[5] (CS3n), GPIO[6] (CS4n) t CGD D[15:0] (read) t DIS t DIH D[15:0] (write) t DOD t DOH Figure 4-10. System Bus TimingRead/Write with Wait States 100723A Conexant 4-41 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description zero wait state SIUCLK (internal clock) A[11:0] upper address t AD lower address tAS tAH Ext. CS's t CSD RDn t R0D t R0D WREn, WROn t W0D t W0D GPIO[5] (CS3n), GPIO[6] (CS4n) t CG0D D[15:0] (read) tDI0S t DI0H tDH D[15:0] (write) t DO0D t DO0H Figure 4-11. System Bus TimingZero-Wait-State Read/Write 4-42 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 4 wait states (w=4) s= 1 2 wait states s= 1 SIUCLK (internal clock) A[11:0] t AD ROMCS, CS5n tCSD AE[2] t iAD AE[3] t iAD AO[2] t iAD AO[3] t iAD RDn t RD D[15:0] (read) t DIS t DIH Figure 4-12. System Bus Timing2-Way Interleave Read Timing (S = 1) 100723A Conexant 4-43 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 3 wait states (w=3) 3 wait states 3 wait states 3 wait states SIUCLK (internal clock) A[11:0] t AD ROMCS, CS5n t CSD AE[2] AE[3] t iAD AO[2] t iAD AO[3] t iAD WREn, WROn t WD t WD D[15:0] (write) t DOS t DOH Figure 4-13. System Bus Timing2-Way Interleave Write Timing (S = 0 or 1) 4-44 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 4-8. Read/Write with Wait States Timing Parameters Parameter Address delay time Chip select delay time Read delay time for the normal case and delay-on) Write delay time (the normal case, delay-on, and early-off) CS[4:3] delay time (gated with read or write strobe) Data input setup time Data input hold time Data output delay time Data output hold time Read delay time (for zero wait state) Write delay time (for zero wait state) CS[4:3] delay time (gated with read or write strobe for zero wait state) Data input setup time (for zero wait state) Data input hold time (for zero wait state) Data output delay time (for zero wait state) Data output hold time (for zero wait state) 2-way interleave address delay time ALE address setup time ALE address hold time ALE delay time Address setup time (read and write) Address hold time (read and write) Data hold time (write) tAD tCSD tRD tWD tCGD tDIS tDIH tDOD tDOH tR0D tW0D tCG0D tDI0S tDI0H tDO0D tDO0H tIAD tAAD tAAH tIald tIAS tIAH tIDH Symbol 5 5 5 8 0 5 5 5 8 0 10 2 3 2 2 Min. Max. 20 20 18 12 18 21 21 11 11 20 21 21 11 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 ns ns ns ns Units Note: SIUCLK is the internal system interface clock. These values are for SIUCLK = 30 MHz. When S=0 in the 2-way interleave read operation, tIAD parameter is still same. 4.3.4 Firmware Operation Caution Only word or half-word accesses that happen on their respective boundaries are valid. If the access is to a non-boundary address, the SIU ignores the last 2 LSBs (word access) or 1 LSB (half word access) and reset the address to the appropriate boundaries. For 16-bit register, writing a byte to the even address (register address) will update the lower 8-bits of the register. Writing a byte to the odd address (register address + 1) will update the upper 8 bits of the register. BS[1:0] indicate which byte is written. Writing a halfword to either the even or odd address will update all 16-bits. 100723A Conexant 4-45 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 4.4 4.4.1 Interrupt Controller Function Description Table 4-9. MFC2000 Interrupt and Reset Signals Description Modem Interrupt Countach Bus System Interrupt (irqcbs) Print subsystem Interrupt Scan Step Interrupt (irqsstep) Vertical Print Step Interrupt (irqvpstep) SASIF Interrupt (irqsasif) DMA ch.2 Interrupt (irqdma2) Bi-level Resolution Conversion Interrupt (irqbrc) DMA ch.10 Interrupt (irqdma10) Reset VSC IF Interrupt (irqvsc) Timer Interrupt 1 (irqtimer1) External Interrupt 1 PIO Interrupt (irqpio) External Interrupt 2 T.4/T.6 Interrupt (irqt4) SOPIF Interrupt (irqsopif) System Interrupt (irqsys) Software Interrupt (irqsw) SSIF Interrupt (irqssif) DMA ch.5 Interrupt (irqdma5) SmartDAA IF Interrupt (irqsdaa) Timer Interrupt 2 (irqtimer2) USB Interrupt (irqusb) BATRSTn RESETn IRQ11 IRQ13 IRQ16 PRTIRQn External Source MIRQn Internal Source P80 Core Countach Imaging DSP Bus System Motor Control Block Motor Control Block SASIF Block DMA Control Block Bi-level Resolution Conversion Block DMA Control Block Watchdog Timer & power-down lockout VSC IF Block Interrupt Controller PIO Block T.4/T.6 Block SOPIF Block Power Down Block Interrupt Controller SSIF DMA Controller SmartDAA IF Interrupt Controller USB Block IRQ Number IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 N/A IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 IRQ21 IRQ22 4-46 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 This section describes the three methods of interrupting the CPU program flow, which are: * * * Reset Interrupts for the normal functions (IRQs) Interrupt for the development system (through the IRQ16 pin)/Power Down (through the Power Down block) The reset signal is controlled by the Prime Power Reset block. IRQs and SYSIRQn are managed by the Interrupt Controller and are sent to the ARM as either an IRQ or a FIQ if enabled. Table 4-9 summarizes the interrupts and their sources. 4.4.1.1 Reset An active level on the CPU Reset input halts program execution and resets the CPU's internal registers. When the CPU's Reset input is released, the CPU begins program execution at the address located in the reset vector. This signal can be activated externally by putting low levels on the BATRSTn or RESETn pins, or internally by the Watchdog Timer or the Battery Power Control logic Lockout circuitry. (For more information, see Section 5-1.) 4.4.1.2 System Interrupt The system interrupt can be activated externally by the programmable interrupt IRQ16 or by the power down signal from the Power Down Block. This interrupt is treated the same as other interrupts in the interrupt controller. Firmware has the responsibility to make it the highest priority and to use it as the NMI function which is provided by many other CPUs. The input from the Power Down Block is detected and OR'ed with the programmable external IRQ16 pin. This combined signal is then synchronized to the rising edge of SIUCLK, and then clocked to the falling edge of SIUCLK before an interrupt will be operated in the interrupt controller. For normal system operation, the system interrupt represents a loss of system power, indicated by Power Down signal going low. The system interrupt control firmware performs the necessary power-down maintenance operations, and then writes to the Lockout Enable register (LockEnn) to protect the battery backed-up registers during loss of power. (Note that activating lockout also generates a reset). 4.4.1.3 Interrupts for Normal Functions The level-mode interrupt is provided for internal and external interrupts. All internal interrupts are high-level interrupts. The external Modem interrupt is a low-level interrupt. All other external interrupts are programmable to be either high/low/level/edge interrupts. There are only two kinds of registers needed for the interrupt controller; one is the interrupt enable register and another is the interrupt event register. The interrupt controller DOES NOT prioritize the multiple sources of interrupts and DOES NOT generate the interrupt addresses. It only provides interrupt masking for all of interrupts including the system interrupt (i.e., enable/disable control), and generates the interrupt request for the CPU. When the bit corresponding to an interrupt in the interrupt enable register is set, it enables the interrupt request to cause an interrupt. When the bit is cleared, it masks the interrupt. When the event corresponding to an interrupt bit in the interrupt event register occurs, this bit needs to be set on the rising edge of SIUCLK whether it is enabled or not. On the falling edge of SIUCLK, the interrupt controller generates the interrupt (IRQn and FIQn) to CPU. This interrupt controller has two identical sets of interrupt logic and registers for IRQn and FIQn. Firmware needs to decide which interrupts trigger IRQn and which interrupts trigger FIQn. In the interrupt subroutine, the CPU needs to clear the interrupt event from the interrupt source. Then, this bit will be reset at the following rising edge of SIUCLK. For the software interrupt, the interrupt source is the interrupt bit in the interrupt event register itself. Therefore, the CPU needs to write a 1 to generate the software interrupt and write a 0 to clear the software interrupt. The source of the IRQ is required to latch the interrupt signal and hold the signal active until the CPU processes the IRQ. The CPU firmware clears the source of the IRQ before exiting the IRQ's service routine. If any IRQ's are pending when new IRQ's are enabled by either setting the interrupt enable registers or the Interrupt Disable bit in the CPU Processor Status register, the enabled IRQ causes an almost immediate CPU interrupt [the CPU only acknowledges interrupts during the op code fetch of an instruction]. 100723A Conexant 4-47 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description External Interrupts The optional IRQ13 and IRQ11 external interrupt requests share pins with GPIO9 and GPIO8, respectively, and these interrupts are enabled by setting the corresponding bits in the IRQ ENABLE registers to 1. These interrupt enable bits must be set to 0 when using GPIO[9:8] as GPIO to prevent these pins from causing interrupts. If an external interrupt source is connected to GPIO8 and/or GPIO9, the corresponding GPIO direction control register must remain set to 0 (GPI) [default] to avoid bi-directional conflicts with the GPIO output. Dedicated external interrupt pins are provided for an active low modem interrupt (MIRQn). All other external interrupts (IRQ2, IRQ11, IRQ13, and IRQ16) are programmable to be either active low or high, edge or level triggered. All external interrupts are resynchronized in the ASIC. Internal Interrupts Internal interrupts are provided for the Countach Imaging DSP Bus System (irqcbs), the T.4/T.6 logic (irqt4), the vertical printer stepper motor (irqvpstep), the scan stepper motor (irqsstep), the parallel IO block (irqpio), USB interface (irqusb), the 50ms timer1 and timer2 (irqtimer1, irqtimer2), DMA Channel 2 (irqdma2), Bi-level Resolution Conversion (irqbrc), DMA Channel 10 (irqdma10), Scanner IF (irqvsc), SOPIF (irqsopif ), SASIF (irqsasif), software interrupt (irqsw), SSIF (irqssif), DMA Channel 5 interrupt (irqdma5), and the SDAA Interface interrupt (irqsdaa). 4-48 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 4.4.2 4.4.2.1 Address: Register Description IRQ/FIQ Event1 Register Bit 15 IRQ15 irqsopif Event Status Bit 14 IRQ14 irqt4 Event Status Bit 13 IRQ13 irqext2 Event Status Bit 12 IRQ12 irqpio Event Status Bit 11 IRQ11 irqext1 Event Status Bit 10 IRQ10 irqtimer1 Event Status Bit 9 IRQ9 irqvsc Event Status Bit 8 IRQ8 irqdma10 Event Status Default: Rst Value 00h Read Value 00h Bit 7 IRQ7 irqbrc Event Status Bit 6 IRQ6 irqdma2 Event Status Bit 5 IRQ5 irqsasif Event Status Bit 4 IRQ4 irqvpstep Event Status Bit 3 IRQ3 irqsstep Event Status Bit 2 IRQ2 irqprt Event Status Bit 1 IRQ1 irqcbs Event Status Bit 0 IRQ0 MIRQ Event Status Default: Rst Value 00h Read Value 00h IRQFIQEvent1 0x01FF8021 Address: IRQFIQEvent1 0x01FF8020 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Internal interrupt from SOPIF block. Read only. Internal interrupt from T4/T6 block. Read only. External interrupt 2. Programmable. Read only. Internal PIO interrupt from PIO block. Read only. External interrupt 1. Programmable. Read only. Internal timer 1 interrupt up to 50 ms. Read only. Internal video scan controller interrupt from VSC IF block. Read only. Internal DMA channel 10 interrupt from DMA controller block. Read only. Internal bi-level resolution conversion interrupt from BLRC block. Read only. Internal DMA channel 2 interrupt from DMA controller block. Read only. Internal SASIF interrupt from SASIF block. Read only. Internal vertical print step interrupt from motor control block. Read only. Internal scan step interrupt from motor control block. Read only. External print subsystem interrupt. Programmable. Read only. Internal Countach bus system interrupt from Countach Bus System. Read only. External modem interrupt (active low) or the internal P80 core interrupt. Read only. 100723A Conexant 4-49 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 4.4.2.2 Address: IRQ/FIQ Event2 Register Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst Value xxh Read Value 00h Default: Rst Value x0000000b Read Value 00h IRQFIQEvent2 0x01FF8023 Address: IRQFIQEvent2 Bit 7 (Not Used) Bit 6 IRQ22 irqusb Event Status Bit 5 IRQ21 irqtimer2 Event Status Bit 4 IRQ20 irqsdaa Event Status Bit 3 IRQ19 irqdma5 Event Status Bit 2 IRQ18 irqssif Event Status Bit 1 IRQ17 irqsw Event Status Bit 0 IRQ16 irqsys Event Status 0x01FF8022 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Internal USB interrupt from USB block. Read only. Internal timer 2 interrupt up to 50 ms. Read only. Internal SmartDAA interface interrupt from SmartDAA IF block. Read only. Internal DMA channel 5 interrupt from DMA controller block. Read only. Internal SSIF from SSIF block. Read only. Internal Software interrupt. When CPU writes a 1, the software interrupt is issued. When CPU writes a 0, the software interrupt is cleared. R/W. Internal system interrupt from programmable external interrupt 16 or power down circuit Read only. Bit 0 4.4.2.3 Address: IRQ Enable1 Register Bit 15 Enable IRQ15 irqsopif Bit 7 Enable IRQ7 irqbrc Bit 14 Enable IRQ14 irqt4 Bit 13 Enable IRQ13 irqext2 Bit 5 Enable IRQ5 irqsasif Bit 12 Enable IRQ12 irqpio Bit 4 Enable IRQ4 irqvpstep Bit 11 Enable IRQ11 irqext1 Bit 3 Enable IRQ3 irqsstep Bit 10 Enable IRQ10 irqtimer1 Bit 2 Enable IRQ2 irqprt Bit 9 Enable IRQ9 irqvsc Bit 1 Enable IRQ1 irqcbs Bit 8 Enable IRQ8 irqdma10 Bit 0 Enable IRQ0 MIRQ Default: Rst Value 00h Read Value 00h Default: Rst Value 00h Read Value 00h IRQEnable1 0x01FF8025 Address: IRQEnable1 Bit 6 Enable IRQ6 irqdma2 0x01FF8024 Bit 15 - 0: When 1 will enable the corresponding interrupt and when 0 will mask that interrupt out. R/W. 4-50 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 4.4.2.4 Address: IRQ Enable2 Register Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst Value xxh Read Value 00h Default: Rst Value x0000000b Read Value 00h IRQEnable2 0x01FF8027 Address: IRQEnable2 Bit 7 (Not Used) Bit 6 Enable IRQ22 irqusb Bit 5 Enable IRQ21 irqtimer2 Bit 4 Enable IRQ20 irqsdaa Bit 3 Enable IRQ19 irqdma5 Bit 2 Enable IRQ18 irqssif Bit 1 Enable IRQ17 irqsw Bit 0 Enable IRQ16 irqsys 0x01FF8026 Bit 3 - 0: When 1 will enable the corresponding interrupt and when 0 will mask that interrupt out. R/W. 4.4.2.5 Address: FIQEnable1 FIQ Enable1 Register Bit 15 Enable IRQ15 irqsopif Bit 7 Enable IRQ7 irqbrc Bit 14 Enable IRQ14 irqt4 Bit 6 Enable IRQ6 irqdma2 Bit 13 Enable IRQ13 irqext2 Bit 5 Enable IRQ5 irqsasif Bit 12 Enable IRQ12 irqpio Bit 4 Enable IRQ4 irqvpstep Bit 11 Enable IRQ11 irqext1 Bit 3 Enable IRQ3 irqsstep Bit 10 Enable IRQ10 irqtimer1 Bit 2 Enable IRQ2 irqprt Bit 9 Enable IRQ9 irqvsc Bit 1 Enable IRQ1 irqcss Bit 8 Enable IRQ8 irqdma10 Default: Rst Value 00h Read Value 00h Default: Rst Value 00h Read Value 00h 0x01FF8029 Address: FIQEnable1 Bit 0 Enable IRQ0 MIRQ 0x01FF8028 Bit 15 - 0: When 1 will enable the corresponding interrupt and when 0 will mask that interrupt out. R/W. 4.4.2.6 Address: FIQEnable2 FIQ Enable2 Register Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst Value xxh Read Value 00h Default: Rst Value x0000000b Read Value 00h 0x01FF802B Address: FIQEnable2 Bit 7 (Not Used) Bit 6 Enable IRQ22 irqusb Bit 5 Enable IRQ21 irqtimer2 Bit 4 Enable IRQ20 irqsdaa Bit 3 Enable IRQ19 irqdma5 Bit 2 Enable IRQ18 irqssif Bit 1 Enable IRQ17 irqsw Bit 0 Enable IRQ16 irqsys 0x01FF802A Bit 3 - 0: When 1 will enable the corresponding interrupt and when 0 will mask that interrupt out. R/W. 100723A Conexant 4-51 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 4.4.2.7 Address: EIRQConfig External Interrupt Configuration Register Bit 7 irq16edge Bit 6 irq13edge Bit 5 irq11edge Bit 4 irq2edge Bit 3 irq16actlo Bit 2 irq13actlo Bit 1 irq11actlo Bit 0 irq2actlo Default Rst Value 00h Read Value 00h 0x01FF802C Bit 7 - 4: Bit 3 - 0: Write a 1 will configure the corresponding external interrupt to be edge triggered and write a 0 will configure it to be level triggered. Write a 1 will configure the corresponding external interrupt to be active low and write a 0 will configure it to be active high. 4.4.2.8 Address: EIRQClear External Interrupt Clear Register Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 irq21clr Bit 4 irq10clr Bit 3 eirq16clr Bit 2 eirq13clr Bit 1 eirq11clr Bit 0 eirq2clr Default: Rst Value xx000000b Read Value 00h 0x01FF802D Bit 3 - 0: Firmware uses these bits to clear the corresponding edge triggered external interrupt which is latched in the interrupt controller. After writing a 1 to clear the interrupts, the bits reset themselves to 0. Firmware uses these bits to clear the corresponding internal timer interrupts. After writing a 1 to clear the interrupts, the bits reset themselves to 0. Bit 5 - 4: 4.4.2.9 Address: Timer1 Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst Value 00h Read Value 00h Default: Rst Value 00h Read Value 00h Timer1 Timer 1 Value MSB 0x01FF802F Address: Timer1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer 1 Value LSB 0x01FF802E Bit 15 - 0: This is the timer value for the timer1 interrupt. This value will be loaded in a counter when the timer interrupt bit is enabled. The value loaded in this register is dependent on the SIUCLK frequency. This interrupt period can be programmed up to 50 ms with a programmable resolution. To write a new timer value into the register, the enable bit in the IRQ/FIQ Enable register must be disabled first; the new timer value is then written into the register and the enable bit is set to load the new timer value into the counter. 4-52 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 4.4.2.10 Timer2 Register Address: Timer2 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst Value 00h Read Value 00h Timer 2 Value MSB 0x01FF8031 Address: Timer1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst Value 00h Read Value 00h Timer 2 Value LSB 0x01FF8030 Bit 15 - 0: This is the timer value for the timer2 interrupt. This value will be loaded in a counter when the timer interrupt bit is enable. The value loaded in this register is dependent on the SIUCLK frequency. This interrupt period can be programmed up to 50 ms with a programmable resolution (see Table 4-10). To write new timer value into the register, the enable bit in the IRQ/FIQ Enable register has to be disabled first; the new timer value is then written into the register and the enable bit is then set to load the new timer value into the counter. TMRCLK = (SIUCLK/B)/8 = ICLK/8 (value of B is programmable) The resolution of the timer1 and timer2 is dependent on SIUCLK and can be calculated as follows: Table 4-10. Programmable Resolution of Timer1 and Timer2 SIUCLK (MHz) 30 30 37.5 40 3 4 4 4 B 10 7.5 9.375 10 ICLK (MHz) TMRCLK (MHz) 1.25 0.9375 1.171875 1.25 TMRCLK (uSec) 0.8 1.067 0.833 0.8 100723A Conexant 4-53 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 4.4.3 Timing SIUCLK (internal) MIRQn PRTIRQn(IRQ2) or GPIO[8](IRQ11) or GPIO[9](IRQ13) or IRQ16(SYSIRQ) Figure 4-14. External Interrupt Request Timing The MFP2000 chip resynchronizes MIRQn, PRTIRQn, GPIO[8], GPIO[9], and IRQ16 signals internally. There are no setup time and hold time requirements for MIRQn, PRTIRQn, GPIO[8], GPIO[9], MIRQn, and IRQ16 signals with respect to SYSCLK. The four Note: external interrupts PRTIRQn, GPIO[8], GPIO[9], and IRQ16 can also be programmed as edge triggered interrupts. In this case, the interrupt signals are implemented as clock into flip-flops with D-input either tied to high or low; again there is no setup and hold time requirements either. 4.5 4.5.1 DRAM Controller (Including Battery DRAM) Functional Description The DRAM Controller interfaces to external memory devices and to the internal ARM7 SIU block. The DRAM memory space can be divided into two banks of memory which can be independently configured. The system clock rate that is supported can be up to 40MHz and can support the DRAM characteristics that are listed in the following tables Addressing Size: Organization: Access Speed: 512K, 1M, 4M, 16M 4 bits, 8 bits, or 16 bits 50, 60, 70, 80 ns The maximum memory size that is supported for two memory banks is 32M. The DRAM Chip sizes that are supported go up to 16M, but are limited to the row/column configurations that can be accommodated from the address multiplexing table (Table 4-12) and the DRAM row/column configuration Table 4-14). The number of DRAM access and refresh cycle wait states can be programmed from the DRAMCtrl register. Specifically, options to control the RAS precharge width, RAS low time, and CAS low time are provided. The drive capability of the DRAM control signals can support a maximum of 50pF of loading capacitance. Several types of external DRAM configurations can be supported: non-interleaved (8-bit or 16-bit data bus) and 2way interleaved (16-bit data bus) (See Table 4-11). Memory bank 0 can be configured independently from memory bank 1. 4-54 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 If a burst of data is sent to the DRAM, the DRAM Controller will run in page mode once the initial access is completed. The maximum burst length is limited to 8 halfwords (i.e., the maximum burst length coincides with the CACHE line length) and is controlled by a burst signal that is generated from the SIU. If a burst of data is being sent to the DRAM, but an octal address boundary occurs, the burst signal will turn off causing a RASn precharge. It is impossible to go across a page boundary without precharging the RASn signal. Note: If a 16-bit wide memory structure is implemented, bursts of data must be 16-bit halfword bursts. 8-bit byte bursts are only allowed for an 8-bit wide memory structure. Table 4-11. DRAM Wait State Configurations Non-Interleaved Modes (8 or 16 bit interfaces) 1 Cycle CASn 30 MHz -50, -60 2 Cycle CASn 30 MHz 37.5 MHz and 40 MHz 37.5 MHz -50, -60, -70, -80 -50, -60 -70 3 wait state, PG = 2 wait state (read) 2 wait state, PG = 1 wait state (write) 5 wait state, PG = 2 wait state (read) 4 wait state, PG = 1 wait state (write) 5 wait state, PG = 2 wait state (read) 4 wait state, PG = 1 wait state (write) Interleaved Mode (16-bit interface) 30 MHz -50, -60, -70, -80 3 wait state, PG = 0,1,0 wait state (read)-Even starting address, non octal boundary 4 wait state, PG=1,0,1 wait state (read)- Odd starting address, non octal boundary 2 wait state, PG = 1 wait state (write) 37.5 MHz and 40 MHz 37.5 MHz -50, -60 -70 5 wait state, PG = 0,1,0 wait state (read) 4 wait state, PG = 1 wait state (write) 5 wait state, PG = 0,1,0 wait state (read) 4 wait state, PG = 1 wait state (write) 3 wait state, PG = 1 wait state Note: PG = page mode 4.5.1.1 Memory Bank Structure DRAM address space can be selected in 2 separate memory blocks (Bank 0: RASn[0] and CASOn[0] (8-bit) or CASOn[1:0] (16-bit) or CASOn[1:0] and CASEn[1:0] (interleaved), Bank 1: RASn[1] and CASOn[0] (8-bit) or CASOn[1:0] (16-bit) or CASOn[1:0] and CASEn[1:0] (interleaved). Separate control bits are provided in the Backup Configuration register to enable and disable (default) each of the memory banks. Each bank has separate configuration controls and the address ranges of the two memory banks is continuous around the midpoint of the DRAM memory bank. The RASn[1] starting address is 03000000h and grows larger based on the size of the memory. The end of the RASn[0] bank ends at 03000000h and grows smaller from that point. The memory range is programmed through the address multiplexer selections for bank 0 and bank 1 in the DRAMCtrl register. 100723A Conexant 4-55 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 4.5.1.2 Non-Interleaved DRAM Accesses Non-interleaved DRAM accesses are available for 8-bit or 16-bit data bus. Byte access is available for both 8-bit and 16-bit data bus and 16-bit halfword access is available for 16-bit data bus. DRAM early-write mode, normal read mode and page mode are supported. Read-modify-write is not supported. Note: 16-bit DRAMs must have upper and lower CAS's in order to work with the DRAM controller. 8-bit bursts of data will not work with a 16-bit wide memory structure. 02000000h 02800000h RASn[0] Bank 0 03000000h RASn[1] 03400000h Bank 1 04000000h NOTE: In this example, Bank 0 is 8M and Bank 1 is 4M. Figure 4-15. DRAM Bank/Address Map 4.5.1.3 2-way Interleaved DRAM Accesses The two-way interleaved DRAM interface can support up to four 16-bit wide devices a maximum of 8M deep. Bank 0 is selected with RASn[0] and bank 1 is selected with RASn[1]. CASEn[1:0], CASOn[1:0], DWRn, DOEOn, DOEEn, ADDR, and DATA are common between the two banks. 2-way interleaving is limited to a 16-bit wide databus. 8-bit or 16-bit wide devices can be used. The ARM CPU can write 32-bit words, 16-bit halfwords or bytes to the memory banks. The addressing to the interleaved DRAMs starts with address bit 2. Bits 1 and 0 are used internally to generate the proper CASOn[1:0] and CASEn[1:0] signals. When the memory structure is configured for two-way interleaving, byte bursts are not allowed. Only bursts of 32-bit words or 16-bit halfwords are allowed. The maximum burst length is eight 16-bit halfwords. The burst length is controlled by the DRAMBURST signal that is sent from the SIU. The external memory structure can use the output enables directly to the memory device or for increased speed can use external bus transceivers. Bus contention must be considered when the output enables are tied directly to a DRAM memory. 4-56 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 4-12. Address MultiplexingPart 1 Address Multiplexing Register Physical Address A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] ROW A[22] A[21] A[20] A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] A[9] COL. A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] ROW A[23] A[22] A[21] A[20] A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] COL. A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] ROW A[24] A[23] A[22] A[21] A[20] A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] COL. A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] ROW A[25] A[24] A[23] A[22] A[21] A[20] A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] COL. A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] Select Option 000 Select Option 001 Select Option 010 Select Option 011 Table 4-13. Address MultiplexingPart 2 Address Multiplexing Register Physical Address A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] ROW A[24] A[23] A[22] A[21] A[20] A[19] A[18] A[17] A[16] A[15] A[14] A[13] COL. A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] ROW A[23] A[22] A[21] A[20] A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] COL. A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] ROW A[24] A[23] A[22] A[21] A[20] A[19] A[18] A[17] A[16] A[15] A[14] A[13] COL. A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] ROW A[22] A[21] A[20] A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] COL. A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] Select Option 100 Select Option 101 Select Option 110 Select Option 111 100723A Conexant 4-57 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Table 4-14. DRAM Row/Column Configuration Memory Size Address Multiplex Setting 8-bit 256K x 8 256K x 16 DRAMs 000 000 --512K x 8 1M x 8 1M x 16 DRAMs 000 001 001 --4M x 8 4M x 16 DRAMs 010 001 --16M x 8 011 --16-bit 000 000 --000 001 001 --010 111 --110 --2-wy intrl. 000 000 --000 001 001 --100 101 ------Supported Supported Not Supported Supported Supported Supported Not Supported Supported Supported Not Supported Supported Not Supported 9 9 10 10 10 10 12 11 12 13 12 13 Supported/Not Supported Row/Column Configuration Row 9 9 8 9 10 10 8 11 10 9 12 11 Column 4.5.1.4 Refresh Operation DRAM Refresh is performed automatically using the CAS-before-RAS method. Three different refresh speeds are supported: slow, normal and fast. These speeds are selected by bits in the backup configuration register. The refresh time is based on the crystal oscillator frequency and the refresh rate that is selected. During prime power when it is time to refresh the DRAM, a CAS-before-RAS refresh cycle will be inserted. If the DRAM is being accessed when a DRAM refresh is requested, the refresh cycle is not inserted until the access is complete. The maximum burst length that the DRAM Controller will see is 8 halfwords (i.e., the maximum burst length coincides with the CACHE line size). The maximum burst length is controlled by the SIU with the DRAMBURST signal that is sent to the DRAM Controller. 4-58 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 4.5.1.5 Power Down Mode When the ASIC is powered down, the DRAMs cannot be accessed. Only DRAM refresh will continue on battery power (VDRAM). Refresh timing is generated from a one shot and an internal gate delay circuit during battery powered operation. To ensure a smooth transition from VDD refresh to battery powered refresh, a control signal from the power reset block allows the DRAM controller to switch from VDD refresh to battery refresh when power is down. When the prime power is reapplied, the refresh logic switches back to VDD refresh. The refresh speed selected using the BackupConfig register remains in force during the battery backed up mode. The DRAM Backup time duration is defined by the two DRAM Backup time bits in the BackupConfig register. No backup, 1-2 days, 2-3 days, and infinite are the backup options. Note: The AMFPC ASIC uses a 3V process; therefore, if the DRAM memory structure is to be backed up, for the lowest power consumption 3 DRAMs should be used. Also, any external circuitry must also be battery powered. The output pads of the AMFPC are only 5V tolerant during high Z. The simplified block diagram for the DRAM controller is illustrated in Figure 4-16. EXTERNAL ADDRESS DATABUS SIU DRAM CONTROLLER DOEOn SIUCLK DRAMREQ DRAMRDY DRAM CNTL. DRAM CONTROL REGISTER DRAM STATE M STHI E D R A M A C A TN E MACHINE BANK 0 BANK 1 BATTERY BACKED UP LOGIC BATTERY BACKUP REGISTER RASn[1:0] CASOn[1:0] CASEn[1:0] DWRn DOEEn DRAM ADDR REFRESH SPEED SIU CNTL ONESHOT SWITCH MUX RTC Battery OSCCLK, CO_1DAY DRAM Battery Figure 4-16. Simplified DRAM Controller Block Diagram 100723A Conexant 4-59 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description addr[u:0] data[7:0] RASn[1] DRAM CASOn[0] DWRn DOEOn (Wron) WEn OEn Bank 1 (8-bit Non-interleaved) DOEOn (WRon) data[15:0] QSwitch addr[11:0] ASIC RASn[0] CASOn[0] CASOn[1] OEn DWRn DOEen (WRen) WEn DRAM Bank 0 (Interleaved) data[15:0] QSwitch addr[11:0] RASn[0] CASEn[0] CASEn[1] DRAM OEn DWRn WEn Figure 4-17. DRAM Interface Example Figure 4-17 gives an example of how each bank of DRAMs might be setup for non-battery back-up DRAM system. In this example, Bank 0 is setup for an 8-bit non-interleaved memory bank and Bank 1 is setup with a 16bit 2-way interleaved DRAM bank. Note: 1. DWRn is a battery backed-up signal and is `high' during the battery back-up mode. All inputs of the prime powered logic will have `no power' or `low' during the battery back-up mode. Therefore, all external logic, which uses DWRn, should be battery backed-up logic and should be gated with WRPROTn to ensure that outputs are `low' when the prime power is off for the battery back-up DRAM operation. 2. DWRn, CASO[1:0]n and CASE[1:0]n are shared by both DRAM banks (RAS[0]n and RAS[1]n). If you only want to back up one bank by battery power, all shared signals should be separated by the external logic and should follow the rule in note 2. 4-60 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 4.5.2 Register Description Bit 15 Bit 14 Bit 13 Bit 12 Bank 1 Increase RAS Cycle Time Bit 11 Bank 1 2-cycle RAS Precharge Bit 10 Bank 1 1-cycle RAH Bit 9 Bit 8 Default Rst. Value x0000000b Read Value 00h Address DRAM Control Register (DRAMCtrl1) $01FF8821 Bank 1 Address Multiplexing Bank 1 Non-interleaved Speed Control 00 = Fast Mode 01 = Normal Mode 10 = Slow Mode 11 = N/A Bit 1 Bit 0 Bank 0 Non-interleaved Speed Control 00 = Fast Mode 01 = Normal Mode 10 = Slow Mode 11 = N/A Address DRAM Control Register (DRAMCtrl1) $01FF8820 Bit 7 Bit 6 Bit 5 Bit 4 Bank 0 Increase RAS Cycle Time Bit 3 Bank 0 2-cycle RAS Precharge Bit 2 Bank 0 1-cycle RAH Default Rst. Value x0000000b Read Value 00h Bank 0 Address Multiplexing Register Description: The DRAM Control register is used to program the two DRAM banks for the type of operation that is desired. Bits 15-13: Bank 1 Address Multiplexing This register controls the addressing multiplexing for Bank 1 Bit 12: Bank 1 Increase RAS Cycle Time This register will add one cycle after the refresh cycle prior to RAS precharge to meet TRC (RASn cycle time). This is needed in order to use 70 ns DRAMs while running at 39MHz. Bank 1 2-cycle RAS Precharge This register will increase the RASn[1] Precharge time from 1 to 2 clock cycles. Bit 10: Bank 1 1-cycle RAH This register will increase the RASn[1] address hold time. When this bit is set, the address will be multiplexed 1 clock cycle after the falling edge of RAS[1]n. The default setting will multiplex the row/column address 1/2 clock cycle after the falling edge of RAS[1]n. Bit 9-8: Bank 1 Speed Control These registers will control the speed of the DRAM interface for bank 1 when in the non-interleaved mode. This register controls the width of the CASn signal. These bits are ignored in interleaved mode. Bit 9 0 0 1 1 Bit 8 0 1 0 1 Non-Interleaved Operation: CASn is 1/2 clock cycle wide. CASn is 1 clock cycle wide. CASn is 2 clock cycles wide for Read and 1 clock cycle wide for write. N/A Bit 11: Bits 7-5: Bank 0 Addressing Multiplexing: This register controls the addressing multiplexing for Bank 0 (Table 4-12). 100723A Conexant 4-61 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Bit 4: Bank 0 Increase RAS Cycle Time This register will add one cycle after the refresh cycle prior to RAS precharge to meet TRC (RASn cycle time). This is needed in order to use 70 ns DRAMs while running at 39MHz. Bank 0 2-cycle RAS Precharge This register will increase the RASn[0] Precharge time from 1 to 2 clock cycles. Bit 3: Bit 2: Bank 0 1-cycle RAH This register will increase the RASn[0] address hold time. When this bit is set, the address will be multiplexed 1 clock cycle after the falling edge of RAS[0]n. The default setting will multiplex the row/column address 1/2 clock cycle after the falling edge of RAS[1]n. Bits 1-0: Bank 0 Speed Control These registers will control the speed of the DRAM interface for bank 0 when in the non-interleaved mode. This register controls the width of the CASn signal. These bits are ignored in interleaved mode. Bit 1 0 0 1 1 Bit 0 0 1 0 1 Non-Interleaved Operation CASn is 1/2 clock cycle wide. CASn is 1 clock cycle wide. CASn is 2 clock cycles wide for Read and 1 clock cycle wide for write. N/A Address Backup Configuration Register (BackupConfig) $01FF8099 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 Bit 12 Bit 11 Lockenn Timeout Detected Bit 10 SRAM Enable 0 = disable 1 = enable Bit 9 Bank 1 Data interface size: 0 = 8-bit 1 = 16-bit Bit 8 Bank 0 Data interface size: 0 = 8-bit 1 = 16-bit Default Rst. Value xxxxx000b Read Value 00h Internal Batrstn Power Down Detected Select Address Backup Configuration Register (BackupConfig) $01FF8098 Bit 7 Bit 6 Bit 5 Refresh Rate 0 = normal 1 = slow Bit 4 Oscillator Speed 0= 32.768 kHz 1= 65.536 kHz Bit 3 Bank 1 Enable 0 = disable 1 = enable Bit 2 Bank 0 Enable 0 = disable 1 = enable Bit 1 Bank 1 Interleave Enable 0 = non interleaved 1 = 2 way interleaved Bit 0 Bank 0 Interleave Enable 0 = non interleaved 1 = 2 way interleaved Default Rst. Value 00h Read Value 00h DRAM Backup Time 0 = no backup 1 = 1-2 days 2 = 2-3 days 3 = infinite days Register Description: This register is set to all zeros when first powered up and is battery backed up with the RTC Battery during power down. When a time out condition occurs, the RASn and CASn signals are tri-stated. When prime power has returned from a power down sequence, the user will have to perform a checksum on the DRAM data to know if a time out has occurred since there is no indication that the DRAM battery has lost power. The user will have to wait 1ms before accessing the DRAM after prime power has returned. Bits 15-14: Bit 13: Internal Power Down Select 0 = PWRDWNn is generated by or-ing power_down1 with power_down2 1= PWRDWNn is generated by and-ing power_down1 with power_down2 Not used 4-62 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Note: Power_down1 and power_down2 are output signals from the power-down detection circuit 1 and 2. Bit12: Betrstn Detected This bit indicates that a betrstn occurred. To clear this bit, a 1 must be written to this bit. Bit11: This bit indicates that a power down occurred, but no lockout was set within the 1-2 second period. The lockout timer initiated the lockenn to create the lockout condition. Once the lockout condition occurs, if the power down signal is high, the chip will come out of reset after a pud1 delay. To clear this bit a 1 must be written to this bit. SRAM Chip Select Enable This bit enables the SRAM chip select CSN0. Bit10: Bit 9: Bank 1 Interface Size This register defines whether the data bus to the bank 1 DRAMs is 8 bits wide or 16 bits wide. An 8-bit wide DRAM interface uses RASn[1] and CASOn[0]. A 16-bit wide non-interleaved DRAM interface uses RASn[1] and CASOn[1:0]. A 16-bit wide interleaved DRAM interface uses RASn[1], CASEn[1:0], and CASOn[1:0]. Bit 8: Bank 0 Interface Size This register defines whether the data bus to the bank 0 DRAMs is 8 bits wide or 16 bits wide. An 8-bit wide DRAM interface uses RASn[0] and CASOn[0]. A 16-bit wide non-interleaved DRAM interface uses RASn[0] and CASOn[1:0]. A 16-bit wide interleaved DRAM interface uses RASn[0], CASEn[1:0], and CASOn[1:0]. Bits 7-6: DRAM Battery Backup Time These bits control the amount of time that the DRAM controller will spend refreshing the DRAMs when in the battery backup mode. After reset when the CPU is being released to run, the CPU will not be able to write data to bits 7 and 6 of the BackupConfig register immediately since the immediate write will not take effect. The CPU must wait at least one oscillator clock cycle before writing data into bits 7 and 6. Bit 7 0 0 1 1 0 1 0 1 Bit 6 Battery Backup Duration: No battery backup (default) 1-2 days 2-3 days Infinite Bit 5-4: DRAM Refresh Rate These bits are used to set up the DRAM refresh rate. See the following table: 100723A Conexant 4-63 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Refresh Speed: (bit 5) 0 0 Oscillator Speed: (bit 4) Refresh Speed: Description: normal RTC crystal frequency = 32.768 kHz, Refresh clock = the crystal frequency = 32.768 kHz, The refresh cycle time = 15.625 ms/1024 cycles. 0 1 fast RTC crystal frequency = 65.536 kHz, Refresh clock = the crystal frequency = 65.536 kHz, Refresh cycle time = 7.8125 ms/1024 cycles. 1 0 slow RTC crystal frequency = 32.768 kHz, Refresh clock = the crystal frequency/8 = 4.096 kHz Refresh cycle time = 125 ms/1024 cycles. 1 1 slow RTC crystal frequency = 65.536 kHz, Refresh clock = the crystal frequency/16 = 4.096 kHz Refresh cycle time = 125 ms/1024 cycles. Bits 3: Bank 1 Enable This bit controls whether or not the Bank 1 DRAMs will be enabled. The Enable signal will allow CAS before RAS refresh to occur based on the non-interleave or interleave setting. If the bank setting indicates a non-interleaved mode, RASn[1] and CASOn[0] (8-bit mode) or CASOn[1:0] (16-bit mode) will refresh the DRAM. If the bank setting indicates an interleaved mode, RASn[1], CASOn[1:0] and CASEn[1:0] will refresh the DRAM. DWRn will be high during refresh. If bank 1 is disabled, RAS[1]n will be tri-stated and all appropriate CASn's will be tri-stated based on mode settings. This bit controls whether or not the Bank 0 DRAMs will be enabled. The Enable signal will allow CAS before RAS refresh to occur based on the non-interleave or interleave setting. If the bank setting indicates a non-interleaved mode, RASn[0] and CASOn[0] (8-bit mode) or CASOn[1:0] (16-bit mode) will refresh the DRAM. If the bank setting indicates an interleaved mode, RASn[0], CASOn[1:0] and CASEn[1:0] will refresh the DRAM. DWRn will be high during refresh. If bank 0 is disabled, RAS[0]n will be tri-stated and all appropriate CASn's will be tri-stated based on mode settings. This register defines whether the bank 1 DRAMs are to be accessed using 2-way interleave or non interleaved access. 2-way interleaved access is only valid with a 16-bit interface (the 16 bit vs. 8 bit interface size bit for bank 1 is ignored by the DRAM controller, but is used by the SIU to output the data correctly). This register defines whether the bank 0 DRAMs are to be accessed using 2-way interleave or non interleaved access. 2-way interleaved access is only valid with a 16-bit interface (the 16 bit vs. 8 bit interface size bit for bank 1 is ignored by the DRAM controller, but is used by the SIU to output the data correctly). Bit 2: Bank 0 Enable Bit 1: Bank 1 Interleave Enable Bit 0: Bank 0 Interleave Enable 4-64 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 4.5.3 Brief Timing No matter which mode you use and which address you access, the DRAM access timing is lined up with the octal halfword boundary. SIUCLK RASn[0] CASEn[0] DOEEn DWRn ARM ADDR or DMA ADDR SIUADDR EXTADDR DATA ROW a a COL a+1 COL a+2 a+2 COL a+3 a+4 a+4 ROW COL a+5 COL COL OCTAL BOUNDARY NOTE: In this example, a =...01010, a+2=...01110, a+4=...10000 Figure 4-18. 8-bit Memory Data Bus The timing diagram illustrates an 8-bit memory data bus, a burst of halfword transfers (3 halfwords) from the ARM7 or DMA, for 1/2 cycle CASn and PG = zero wait states (non-interleaved). It also illustrates the octal halfword boundary that will cause the SIU to terminate the burst and cause the DRAM Controller to regenerate the RASn precharge time. This interface speed can only be used at slow frequencies. SIUCLK RASn[1] CASOn[1:0] DOEOn DWRn a a a+2 a+4 a+4 a+6 ARMADDR SIUADDR DATA EXTADDR ROW COL COL COL COL Figure 4-19. 16-bit Memory Data Bus 100723A Conexant 4-65 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description The timing diagram illustrates a 16-bit memory data bus, a burst of word transfers (2 words) from the ARM7 for full clock width CASn and PG = one wait state (non-interleaved). It also illustrates that the octal halfword boundary doesn't occur in the middle of the burst of word transfers. SIUCLK RASn[0] CASEn[0] DOEEn DWRn ARM ADDR or DMA ADDR SIU ADDR DATA ROW data COL a a EXT ADDR Figure 4-20. CASn Non-Interleaved 8-bit DRAM Read The timing diagram illustrates a two clock cycle CASn non-interleaved 8-bit DRAM read (Non burst mode). This configuration illustrates the row/column address multiplex occurring 1 cycle after RASn. SIUCLK RASn[0] CASEn[1:0] CASOn[1:0] DOEEn DOEOn DWRn ARM ADDR or DMA ADDR SIU ADDR SIU P_ADDR DATA EXT ADDR ROW COL COL COL a a a +2 +2 +2 +4 +4 +4 +6 +6 +6 +8 +8 +8 +10 +10 +10 NOTE: In this example, a[2:0] = 00x. Also, the external address is created from the pipelined SIU address; however, address pins a1 and a0 are not connected to the external memories. Figure 4-21. 2-Way Interleaved Memory with Halfword Bursts of Data 4-66 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 This example illustrates a read of two-way interleaved memory with halfword bursts of data (6 halfwords). It also illustrates that the octal halfword boundary doesn't occur in the middle of the burst of halfword transfers. It assumes external drivers to minimize the data bus contention and to insure that the data has enough setup time to CLK. This waveform also illustrates, increased RASn precharge time and increased address multiplexing time. Byte bursts of data are not allowed when a 16-bit memory structure is used. SIUCLK RASn[0] CASEn[1:0] CASOn[1:0] DOEEn DOEOn DWRn ARM ADDR SIU ADDR SIU P_ADDR DATA EXT ADDR ROW COL COL COL a a +2 a +2 +4 +4 +6 a+4 +6 +8 +8 +10 a+8 +10 Figure 4-22. 2-Way Interleaved DRAM Read (3 words) The timing diagram illustrates a two-way interleaved DRAM read (3 words). It assumes external drivers to minimize the data bus contention and to insure that the data has enough setup time to CLK. This waveform also illustrates, increased RASn precharge time and increased address multiplexing time. SIUCLK RASn[1] CASEn[1:0] CASOn[1:0] DOEEn DOEOn DWRn ARM ADDR SIU ADDR DATA EXT ADDR ROW COL COL COL a a a+2 a+4 a+4 a+6 a+8 a+8 a+10 Figure 4-23. 2-Way Interleaved DRAM Write 100723A Conexant 4-67 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description The timing diagram illustrates two-way interleaved DRAM write. This configuration assumes that the data bus is available to the DRAM with enough setup time to the CASn falling edge. In addition, this configuration has a 2cycle wide RASn and allows one cycle after the falling edge of RASn before the row/column address mux. tCP SIUCLK RASn[1] CASEn[1:0] CASOn[1:0] DWRn tRAS tRP a refresh cycle Figure 4-24. Refresh Cycle The timing diagram illustrates a refresh cycle. tRAS is three cycles wide to accommodate frequency ranges up to 40 MHz. This timing is used during prime power refresh. During battery backup, a custom refresh circuit is used to generate refreshed timing based on the oscillator clock. 4.5.4 Detailed Timing Measurements SIUCLK tR D RASN[1:0] tR D tC D tC D O tC D Note:1 Note:2 CASEN[1:0], CASON[1:0] tC D 0 Access with 1 or 2 wait states Access with 0 wait states DWRN (read) tD W tD W tC S U 0 tC S U DWRN (write) tR A H 1 A[x:0] (option 1) ROW tR A H 2 COL COL COL A[x:0] (option 2) ROW COL COL COL Figure 4-25. DRAM TimingRead, Write and Wait States for Non-interleave Mode 4-68 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 SIUCLK tR D RASN[1:0] tR D tC D tC D CASEN[1:0] Note:1 tC D tC D CASON[1:0] DOEN[1:0] (WRen/WRon) tD W tD W DWRN Figure 4-26. DRAM Timing for 2-way Interleave Write SIUCLK tR D RASN[1:0] tR D tC D tC D tC D tC D CASEN[1:0] Note:1 tC D tC D CASON[1:0] tO E D tO E D DOEN[1] (WRon) tO E D tO E D tO E D DOEN[0] (WRen) tO E D Figure 4-27. DRAM TimingRead for 2-way interleave mode 100723A Conexant 4-69 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description SIUCLK tR R A S RASN[1:0] tC R D CASEN[1:0], CASON[1:0] tR C A S DWRN Figure 4-28. DRAM Refresh Timing XIN t RRAS RASN[1:0] t CRD t CRD CASEN[1:0], CASON[1:0] t R CAS DWRN Figure 4-29. DRAM Battery Refresh Timing 4-70 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 4-15. DRAM Timing Parameters Parameter RASN delay CASN delay (0 wait state) CASN delay CASN address setup (0 wait state) (10Mhz) CASN address setup (30 MHz) RASN address hold 1 RASN address hold 2 DWRN delay OE delay CASN pulse width RASN pulse width CASN to RASN delay tRD tCD0 tCD tCSU0 tCSU tRAH1 tRAH2 tDW tOED tRCAS tRRAS tCRD 30 30 5 7 7 3 3 20 20 500 500 200 Symbol Min. 20 20 20 Max. Units ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Bit 2 of the DRAM Control Register sets this time to 1/2 or 1 clock cycle. 2. Bit 8 and 9 of the DRAM Control Register sets this time to 1 or 2 clock cycles. 4.5.5 Software Operation Special Cautions * * * * The Backup Configuration register is set to 0000h the initial power up only. This register is backed up during battery power mode. DRAM control signals are tri-stated during battery power if the backup timer is set to 0 or the backup time expires, regardless of how the enable bits are set. After a reset occurs and the CPU is released to run, the CPU cannot write to the Backup Configuration register until one OSCCLK cycle has passed. During power-up, the firmware must pay attention to the power up DRAM requirements specified in the DRAM data books. Typically, DRAMs cannot be accessed for 200s and then must have 8 CASn before RASn refreshes occur before accessing the DRAMs. Within the DRAM Memory address space memory bank mirroring is allowed. Firmware will have to determine the memory size. * 100723A Conexant 4-71 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 4.6 Flash Memory Controller The Flash memory controller provides an interface for both NAND and NOR type flash memory devices. Up to two NOR type Flash memory devices or two NAND type devices can be connected to the ASIC. FCS0n and FCS1n pins are the flash memory control pins. FWRn and FRDn are the flash read and write signals for NAND type devices. Additional pins are required to interface to NAND type flash memory devices. GPIO pins can be used as NAND type flash memory control signals. Figure 4-30 shows the structure of the flash controller. It consists of an address and chip select generator block and a read/write control block. The address and chip select generator block provides up to 21 address lines and 2 chip select signals for the flash memory devices. The read/write control block provides read and write strobes for NAND type devices. 4.6.1 Supported Flash Memory The flash memory controller supports the following types of Flash memory and their equivalents: Flash Memory INTEL 28F400BL/28F004BL-150 28F400BX/28F004BX-80, -120 AMD Samsung Am29F040-70, -90, -120, -150 KM29N040/080-150 Size 512 kB 512 kB 512 kB 512 kB/1 MB Type NOR type NOR type NOR type NAND type Note: This ASIC also supports 1MB and 2MB NOR-type flash memory if the specified timing can be matched. 4.6.2 4.6.2.1 Functional Description Interfacing Flash Memory The two types of flash memory that are supported require separate interface control options. NOR type devices are bus oriented and can be connected to the CPU bus. The ASIC provides address signals to access the memory space and provides the chip select signals. NAND type devices are special purpose peripherals with a specialized interface requiring no address bus signals. The ASIC will use dedicated pins and GPIO pins to interface with the NAND flash control and status lines. 4.6.2.2 NOR Type Flash Memory NOR type devices can be used for both firmware code memory and for data memory. Accesses are performed using normal bus operations. Reading data is performed with a bus read. Programming bytes or erasing sectors requires multiple bus cycles. The CPU writes the command sequences required by the flash memory; then it polls the flash memory's status until the operation is complete. The data address space is available in two separate blocks; the first block of memory is from 00800000h to 009FFFFFh (2Mbyte block) and the other is from 00A00000h to 00BFFFFFh (2Mbyte block). When the CPU accesses the address range 00800000h - 009FFFFFh, FCS0n is activated. When the CPU accesses the address range 00A00000h - 00BFFFFFh, FCS1n is activated. When using FCS0n and FCS1n for NOR-type flash memory, the NAND-type bit (bit 6) of the FlashCtrl register must be set to 0. The FlashCtrl register is described in the SIU section of the Hardware Description. The NOR type flash interface consists of: * * * * 4-72 FCSn[1:0]: The two flash device selection signals. To use FCSn[1:0], bit 6 of the FlashCtrl register must be set to 0. A[20:0]: The external address bus for 2MB address range. RDn and WREn/WROn: The external bus read and write strobes. D[15:0]: The external data bus. Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 4.6.2.3 NAND-Type Flash Memory NAND type devices can only be used for data memory. NAND type flash devices have no address bus. Command, address and data are passed through the external data bus. Accesses are accomplished by first setting the appropriate flash CS and control signals through the FCSn[1:0] and GPIO pins. The actual bus transfer is performed by accessing the NANDFLSH register. When accessing the NANDFLSH register, the appropriate flash data strobe is activated, FRDn for read operations and FWRn for write. FRDn and FWRn are also controlled by the wait state setting in the FlashCtrl register. The NAND-type bit in the FlashCtrl register must be 1. * FCSn[1:0]: The device selection signals for the NAND type flash devices. FCS0n and FCS1n pins act as GPO pins. FCSn[1:0] pins output values which are set to bit 8 and bit 9 of the FlashCtrl register. Note: If FCS0n/PWM[1] and FCS1n/PWM[2] pins are programmed as PWM, any two available GPO's or GPIO's can be used to generate FCS[1:0]n for NAND-type flash memory. * * * * * * * FCLE: The Flash Command Latch Enable. It is programmable via a GPIO pin. FCLE activates the commands sent to the command register. FALE: The Flash Address Latch Enable. It is programmable via a GPIO pin. FALE activates the controls for address or data to the internal address or data registers of the flash device. FRDY: The Flash Ready signal. It can be read from a GPIO pin. FRDY indicates the status of the flash device operation. FRDn: The Flash Read Enable signal. It is a hardware generated signal. It is multiplexed on GPIO[1] and configured in the GPIOConfig register. FRDn enables the data from the flash memory device onto its I/O bus. This signal is active when the CPU reads the NAND flash location of 01FF8824h. FWRn: The Flash Write Enable signal. It is a hardware generated signal. It is multiplexed on GPIO[0] and configured in the GPIOConfig register. FWRn controls writes to the I/O bus. This signal is active when the CPU writes to the NAND flash location of 01FF8824h. WRPROTn: The write protect signal is driven low to protect the flash devices from inadvertent writes during power transitions. It is also controlled by writing to the `Prime Power write protect' bit (bit 11) of the FlashCtrl register. D[15:0]: The external data bus. ADDR[25:0] Flash Address & Chip Select Generator (in SIU Block) FADD[20:0] FCSn[1:0] FRDn SIUCLK RWn Flash Read/Write Control FWRn Figure 4-30. Flash Control Block Diagram 100723A Conexant 4-73 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 4.6.3 Timing All accesses can be performed from zero to seven wait states. The number of wait states is programmable in the FlashCtrl register. During write operations, if one to seven wait states is used, the EarlyOff option must be set in the FlashCtrl register. The EarlyOff option is ignored with zero wait state. Wait states are generated to accommodate slow memory devices, for more details of how the control signals are changed with an inserted wait state, refer to the timing diagram Figure 4-31. * NAND-Type flash For this type of flash, addresses and data are passed through the external data bus. During read operations, the device selection is one of the two Flash Chip Select signals FCSn[1:0], FRDn is the Flash Read Enable signal from the bus interface. FCLE and FALE must be low (inactive) during reads. For zero wait state access, FWRn and FRDn are only half SIUCLK cycle (like RDn and WRn of the normal bus operation). During program/erase operations, the device selection is one of the FCSn[1:0] signals. Command, address and data are all written through the external data bus. The Flash Command Latch Enable (FCLE ) and the Flash Address Latch Enable (FALE) signals are the controls for writing to the Command or the Address register respectively. FCLE and FALE must be low (inactive) during a data write to the flash devices. * NOR-Type Flash Accesses are performed using normal bus operations. During program/erase operations, the device selections are the two Flash Chip Select signals FCSn[1:0], addresses are latched on the falling edge of the Flash Write Enable signal WREn/WROn, and data is latched on the rising edge of WREn/WROn. 4-74 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 SYSCLK tF C S D tF C S D tA L D FCSN[1:0] tA L D FALE (GPIO) FCLE (GPIO) GPIO[0] (FWRN) GPIO[1] (FRDN) D[15:0] (read) tC L D tC L D tF D tF D tF D tF D tF D S U in tW D D tW D H D[15:0] (write) out Figure 4-31. NAND-Type Flash Memory Access with Two Wait States Parameter FCSN delay Flash read/write delay Flash read data setup Flash write data delay Flash write data hold Flash address latch delay Flash command latch delay tFCSD tFD tFDSU tWDD tWDH tALD tCLD 0 16 16 8 21 Symbol Min. 16 16 Max. Units ns ns ns ns ns ns ns 100723A Conexant 4-75 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 4.6.4 Address: Register Description Bit 7 (Not Used) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value xxh Read Value 00h Default: Rst. Value xxh Read Value 00h NANDFlash (NANDFLSH) 00C00001h Address: NANDFlash (NANDFLSH) 00C00000h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reading this location activates the FRDn signal. Writing to this location activates the FWRn signal. No physical register exists for this location. Register description: This register is the IO address space for the NAND type flash. Reading this register activates the FRDn signal. Writing to this register activates the FWRn signal. FCLE, FALE, and FRDY must be setup through the GPIO pins and FCSn[1:0] must be setup through the FlashCtrl register prior to accessing the NANDFlash register. FCLE, FALE, and FRDY must be cleared through the GPIO pins and FCSn[1:0] must be cleared through the FlashCtrl register after the register access. Data written to this register is output on the data bus. When reading this register the flash memory data is placed on the internal CPU bus. The NANDFlash register is only an address location; no register actually exists. 4.7 4.7.1 * * * * * DMA Controller General Description The AMFPC is equipped with thirteen physically arbitrated DMA Channels assigned to either internal or external requests. Each channel provides its own 26-bit address for data access The DMA channel address registers are made up of two programmable half word read/write registers, making up a 26-bit counter (64MB). Minimum DMA acknowledge delay is 2 System Clocks. Maximum DMA acknowledge delay depends on the number of pending higher priority DMA requests and the length of associated bus cycles including wait states and halt states due to DMA/DRAM refresh cycle collisions. Channel Specific Unique Features Double Buffered Address and Block Size This channel is equipped with a double buffered DMA address counter and Block Size register. This allows firmware to set up the DMA address and Block Size values for the next block access while the current one is active. When the DMA channel reaches it's Block Size limit it issues an interrupt, and if a new value has been written into the buffers (Buffer Loaded Flag is set), this value is transferred to the address counter and/or Block Size register. The interrupt is cleared upon writing to the Block Size Buffer register. DMA Block Size An Access Block Size Counter is available to limit the number of DMA access in a given block. Once this counter is set, it will keep track of the number of DMA access. Once the limit has been reached a CPU interrupt will be set and no further accesses will be allowed until the register is reset. The IRQDMA is activated at the falling edge of DMAACK. * 4-76 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Addressing Modes All of the DMA Channels increment by 2 after each access. The external channels 1 and 2, can be set to increment by 1 for byte wide peripherals. The count enable register allows the user to select which address will increment after each access. However, Channels 2 and 3 have the additional functionality allowing them to Increment or Decrement by a specified amount. Channel 2 is controlled by the values in it's control register. Channel 3 is controlled by control signals generated in the Bit Rotation Logic. Priority Shows the overall channel priority in the DMA request arbitrator, with 1 as the highest. Uninterrupted Burst mode Allows the requesting device to hold the Burst DMA Request active (PSEQ), to transfer multiple bytes of uninterrupted data. If higher priority requests occur during the burst operation they will be ignored. This operation is mainly for high speed DRAM access. Also during this mode, the read/write control and the count controls must remain static. Throttle Control A Throttle Value can be set to allow 1 DMA access per a given time period. The throttle time period is a product of the value set and the system clock. Logical Channels This single physical DMA channel is equipped with multiple logical channels that operate independent of each other. Only one logical can be active at any time. 4.7.1 DMA Mode Summary Table 4-16. Feature Matrix Features Channel Double Buffered Control Block Size Limit Address Increment Address Decrement Address Jump Priority U-I Burst Mode Other Features 0 1 1 2 Logical Byte 2 3 4 5 6 7 8 9 10 11 12 3 4 7 8 9 10 11 12 13 5 6 Throttle Throttle Throttle 100723A Conexant 4-77 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Each of the DMA channels, its function, and its characteristics are provided in Table 4-17. Table 4-17. DMA Channel Functions and Characteristics DMA Channel 0 1 Function USB data to/from memory for PC print, PC fax TX, PC Fax RX, PC scan External DMA access only. External DMA Request only Bit Rotation Access (Output) Characteristics DMA Block Size Limit with CPU Interrupt via PIO/USB Interrupt, 4 logical DMA Channels, DMA address and Block Size double buffered, each Read/Write selectable, halfword DMA data access only. Normal and delayed ACK, Read/Write selectable, byte and halfword DMA data access selectable. Address Jump Control, DMA Block Size Limit with Interrupt to IRQ Controller, Burst Mode, Double Buffered Control Registers Read/Write, External Request (Generates a DisDrive to disable the Bus IF output drivers to for external memory writes.) External Request to the DMA controller may be delayed from 1 to 2 clocks for synchronization. Address Jump Control (Controlled by Bit Rotation Block see table4.8.2-1) Read Only, Internal Request. (MAS is always set to 1/2 word) Data write only, halfword DMA data access only Data read only, DMA Block Size Limit (16 kB), Interrupt to IRQ Controller halfword DMA data access only. Throttle Control Read/Write, Internal Request (MAS is always set to 1/2 word) Read Only, Internal Request (MAS is always set to 1/2 word) Disable Address Count for read modify write Read/Write, Internal Request, Read Modify Write Control (MAS is always set to 1/2 word) DMA Block Size Limit. Interrupt to IRQ Controller (MAS is always set to 1/2 word) Throttle control Address Block Size Limit, Interrupt to IRQ Controller Read/Write, Internal Request (MAS is always set to 1/2 word) 1 2 3 4 5 6 Bit Rotation Access (Input) Countach to ARM Memory (c2a) ARM Memory to Countach (a2c) Read/Write T4 Uncoded data from/to Line Buffer to/from T4 Logic Read T.4 Reference Line from the Line Buffer to T.4 logic T4 Resolution Converted data, Line Buffer Access 7 8 9 10 Bi-level resolution conversion logic Read/Write T4 Coded data from/to Page Memory to/from T4 Logic 11 12 P1284 to Memory Memory to P1284 DMA Block Size Limit with CPU Interrupt via PIO Interrupt, Read/Write (Control Bit), Internal Request DMA Block Size Limit with CPU Interrupt via PIO Interrupt, Read/Write (Control Bit), Internal Request (MAS is always set to 1/2 word) Notes: 1. 2. DMA Channel 0 has the highest priority. "AD" means address. 4-78 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 4.7.2 DMA Operation and Timing The DMA controller arbitrates DMA requests from all sources (internal and external), and then acknowledges the request of the source with the highest priority at the start of the next bus cycle. After each request has been issued, the associated acknowledge signal is activated with a minimum delay of 2 internal clock cycles. The maximum delay is dependent on both the number of pending higher priority DMA requests, and the length of the associated bus cycles (including wait states and halt states due to DMA to DRAM and refresh cycle collisions). The DMA controller informs the bus control logic (SIU), and provides the address and read/write signal prior to the next bus cycle. At the time of the next bus cycle, the SIU routes the address and data onto the proper bus. If the external bus is required to complete the DMA transfer, the DMA controller notifies the external bus control logic, which in turn halts the CPU. After the completion of a DMA cycle, the DMA controller increments or decrements the DMA address counter. A non-maskable interrupt (SYSIRQ) to the CPU allows the active DMA to be completed, but locks-out all other DMA acknowledge signals in the event of a power down condition. DMA Channel 3 address progression is controlled by the Bit Rotation logic and is not effected by the DMA acknowledges like other channels. The Bit Rotation Logic provides an address progression value, an increment/ decrement (add/subtract) control and a count strobe. When the strobe is held active during the rising edge of the siuclk, the progression value is either added or subtracted from the current address value. Below is a table showing the control bit assignments. Table 4-18 DMA Channel 3 Control Bit Assignment Count Control Assignments countcntl(11) countcntl(10) countcntl(9) countcntl(8) countcntl(7) countcntl(6) countcntl(5) countcntl(4) countcntl(3) countcntl(2) countcntl(1) countcntl(0) Count Strobe Dec_Incn Cnt_By_32k Cnt_By_16k Cnt_By_8192 Cnt_By_4096 Cnt_By_2048 Cnt_By_1024 Cnt_By_512 Cnt_By_4 Cnt_By_2 Cnt_By_1 NA NA Add_value(15) Add_value(14) Add_value(13) Add_value(12) Add_value(11) Add_value(10) Add_value(9) Add_value(2) Add_value(1) Add_value(0) 4.7.3 4.7.3.1 Timing Internal DMA Requests DMA requests are sourced by sub-blocks or peripherals within the ASIC or by an external device (Ch 0 or 1). Some logic blocks may source multiple DMA request lines. For example, the T4 Logic requires 3 request lines: input data, reference data and output data. These sources will issue DMA request signals, and the sequential access indicator, synchronized to the rising edge of SIUCLK. During the bus cycle that the requests are received, the controller will inform the SIU that the next bus cycle will be a DMA cycle. The DMA controller also provides the address, the sequencial access, and read/write control information to the SIU. The SIU will then activate the DMA bus acknowledge signal when the DMA controller becomes the bus master. On the first rising edge of the SIUCLK after the DMA bus acknowledge signal becomes active, the peripheral DMA acknowledge to the requesting peripheral will be set high indicating the start of the DMA cycle. For a DMA single cycle write, the requesting device must drive data onto the bus during activation of the peripheral DMA acknowledge signal. And for a single 100723A Conexant 4-79 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description cycle DMA read the requesting device must capture the data on the falling edge of the peripheral DMA acknowledge. If a sequential DMA access burst is desired, the peripheral must also activate the sequential access indicator at the time of the initial request and must be cleared at the end of the next to the last DMA cycle. The DMA request st must be deactivated during the final DMA cycle, on the 1 rising edge of the SIUCLK. The peripheral must also capture (read), or drive the next datum onto the data bus on each rising edge of the SIUCLK when the DMA acknowledge is active. During sequential burst accesses the Read/Write control and DMA address count controls must remain static. 4.7.3.2 External DMA requests The external device activates the DMA request signal (DMAREQ) at any time when it wants to do the single DMA access operation. The MFC2000 chip double synchronizes the DMAREQ signal internally to avoid the metastable case. After external DMA request has been issued, the associated acknowledge signal is activated with a minimum delay of 5 internal SIUCLK cycles. The external device must deactivate DMAREQ after the associated acknowledge signal is activated and before the end of this DMA cycle. If the DMA request continues to be activated by the external DMA requesting device, the external DMA requesting device will get the second DMAACK signal for the next single data transfer, when system bus is ready. The MFC2000 chip continues to perform single DMA access as long as the DMAREQ is kept active by the external DMA requesting device. DMAACK is used similarly as chip select to indicate the DMA access cycle is ready for the external DMA requesting device. The delay path within the MFC2000 is longer for DMAACK than for RDn; however, the actual amount of skew between the two signals is dependent on their relative loading at the system board level. If RDn has excessive delay, the DMAACK can be programmed to extend it an extra half SIUCLK cycle. DMA Cycle tDRS SIUCLK tDADN Ext. DMAREQ tDADF Ext. DMAACK tAD Ext. address bus DMA address tDIH Ext. data bus tRD DMA data tRD RDn Figure 4-32: External DMA Read Timing (Single Access, One Wait State) 4-80 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 DMA Cycle tDRS SIUCLK tDADN Ext. DMAREQ tDADF Ext. DMAACK tAD Ext. address bus DMA address tDOH Ext. data bus tWD DMA data tWD WREn Figure 4-33. External DMA Write Timing (Single Access, One Wait State) Parameter RDn delay (ext. load = 50pF) WRn delay (ext. load = 50pF) Address delay (ext. load = 50pF) DMAACK on delay time (ext. load = 15pF) DMAACK off delay time (ext. load = 15pF) DMA Input Data Hold DMA Output Data Hold (ext. load = 50pF) RASn delay (ext. load = 40pF) CASn delay (ext. load = 40pF) DWRn delay (ext. load = 40pF) Notes: Symbol tRD tWD tAD tDADN tDADF tDIH tDOH tRASD tCASD tDWD Min 8 8 - Max 25 25 24 10 5 25 25 20 20 Units ns ns ns ns ns ns ns ns ns ns 1. SIUCLK is the internal system interface clock. These values is for SIUCLK = 30 MHz. 2. The external DMA request set-up time (tDRS) is not required because this input is double synchronized internally for the meta-stable case. 100723A Conexant 4-81 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 4.7.4 USB Block Diagrams Below is a block diagram depicting the four USB logical channels. Each logical channel shows the double buffering of the address and block registers. The right side of the diagram shows the common counters for the block and address. Also shown is the feedback path from the counters to the registers used upon USB ACKs. The select signal for the logical channels are shown at the bottom of the diagram. IPB Data Address 1 Address 2 Adr_Out To IPB Data Out Blk_Out Block 1 Block 2 LCH1 Address 1 Address 2 Addr Counter Block 1 Block 2 LCH2 Address 1 Address 2 Block Counter Block 1 Block 2 LCH3 Address 1 Address 2 Block 1 Block 2 LCH4 Block Feedback Address Feedback Channel Select Note: Selecting Channel Will Load current registers to counter Figure 4-34. USB Logical Channels Block Diagram 4.7.4.1 * * * * USB Logical Channel Assignments Mem to PC, PC to Mem, Mem to PC, PC to Mem, DMA Read only DMA Write only DMA Read only DMA Write only Ch1: Scan Ch2: Print Ch3: FAX Rx Ch4: FAX Tx 4-82 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 4.7.5 DMA Controller Registers USB Logical Channel Assignments DMA Channels 112 addressing is controlled by the following registers. Note: If the DMA address counter points to an invalid location, invalid data is read or written Address: chcsl[10:0] DMA Low Counter (DMAiCntlo) Bit 15 DMA0-12 Addr. Bit 15 Bit 14 DMA0-12 Addr. Bit 14 Bit 13 DMA0-12 Addr. Bit 13 Bit 12 DMA0-12 Addr. Bit 12 Bit 11 DMA0-12 Addr. Bit 10 DMA0-12 Addr. Bit 10 Bit 9 DMA0-12 Addr. Bit 8 DMA0-12 Addr. Bit 8 Default: Rst. Value 00h Read Value 00h Bit 11 Bit 9 Address: chcsl[10:0] DMA Low Counter (DMAiCntlo) Bit 7 DMA0-12 Addr. Bit 7 Bit 6 DMA0-12 Addr. Bit 6 Bit 5 DMA0-12 Addr. Bit 5 Bit 4 DMA0-12 Addr. Bit 4 Bit 3 DMA0-12 Addr. Bit 2 DMA0-12 Addr. Bit 2 Bit 1 DMA0-12 Addr. Bit 0 DMA0-12 Addr. Bit 0 Default: Rst. Value 00h Read Value 00h Bit 3 Bit 1 DMA Channel 012 Lower Address Counter Value DMAUSB0CntLo DMAUSB1CntLo DMAUSB2CntLo DMAUSB3CntLo DMA1CntLo DMA2CntLo DMA3CntLo DMA4CntLo DMA5CntLo DMA6CntLo DMA7CntLo DMA8CntLo DMA9CntLo DMA10CntLo DMA11CntLo DMA12CntLo 01FF81C8-C9 01FF81CE-CF 01FF81D4-D5 01FF81DA-DB 01FF8184-85 01FF8188-89 01FF8190-91 01FF8194-95 01FF8198-99 01FF819C-9D 01FF81A0-A1 01FF81A4-A5 01FF81A8-A9 01FF81AC-AD 01FF81E0-E1 01FF81E6-E7 100723A Conexant 4-83 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: chcsh[10:0] DMA Hi Counter (DMAiCnthi) Bit 15 Not Used Bit 14 Not Used Bit 13 Not Used Bit 12 Not Used Bit 11 Not Used Bit 10 Not Used Bit 9 DMA0-12 Addr. Bit 25 Bit 8 DMA0-12 Addr. Bit 24 Default: Rst. Value 00h Read Value 00h Address:chcsh[10: Bit 7 0] DMA Hi Counter DMA0-12 Addr. (DMAiCnthi) Bit 23 Bit 6 DMA0-12 Addr. Bit 22 Bit 5 DMA0-12 Addr. Bit 21 Bit 4 DMA0-12 Addr. Bit 20 Bit 3 DMA0-12 Addr. Bit 2 DMA0-12 Addr. Bit 18 Bit 1 DMA0-12 Addr. Bit 0 DMA0-12 Addr. Bit 16 Default: Rst. Value 00h Read Value 00h Bit 19 Bit 17 DMA Channel 012 Upper Address Counter Value DMAUSB0CntHi DMAUSB1CntHi DMAUSB2CntHi DMAUSB3CntHi DMA1CntHi DMA2CntHi DMA3CntHi DMA4CntHi DMA5CntHi DMA6CntHi DMA7CntHi DMA8CntHi DMA9CntHi DMA10CntHi DMA11CntHi DMA12CntHi 01FF81CA-CB 01FF81D0-D1 01FF81D6-D7 01FF81DC-DD 01FF8186-87 01FF818A-8B 01FF8192-93 01FF8196-97 01FF819A-9B 01FF819E-9F 01FF81A2-A3 01FF81A6-A7 01FF81AA-AB 01FF81AE-AF 01FF81E2-E3 01FF81E8-E9 4-84 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address:ch0cscntl Bit 15 DMA 0 Configuration Channel Enable (DMA0config) LC3 $xx81B1 Bit 14 Channel Enable LC2 Bit 13 Channel Enable LC1 Bit 12 Channel Enable LC0 Bit 11 Read/Write Mode LC3 Bit 10 Read/Write Mode LC2 Bit 9 Read/Write Mode LC1 Bit 8 Read/Write Mode LC0 Default: Rst. Value 00h Read Value 00h Default: Rst. Value 00h Read Value 00h Address:ch0cscntl Bit 7 DMA 0 Configuration Not Used (DMA0config) $xx81B0 Bit 6 Not Used Bit 5 IRQ LC3 Bit 4 IRQ LC3 Bit 3 IRQ LC3 Bit 2 IRQ LC3 Bit 1 Not Used Bit 0 DMA0 Enable Bit 15-12: Logical Channel Enable Bit 11-8: Read/Write Mode Select. Bit 5-2: Bit 0: Setting the bit to 1 will allow operation of the logical channel, setting the bit to 0 will disable the channel and clear it's registers. Selects the data direction. Read = 1, Write = 0 Interrupts from the individual Logical Channels. Clear by writing to the block size register. Setting this bit to 1 will enable DMA Channel 0. Setting this bit to 0 will fore all of the logical channels into their reset state. Address: chcsl[10:0] DMAUSB Low Counter (DMAiCntlo) Bit 15 DMA0-10 Addr. Bit 15 Bit 14 DMA0-10 Addr. Bit 14 Bit 13 DMA0-10 Addr. Bit 13 Bit 12 DMA0-10 Addr. Bit 12 Bit 11 DMA0-10 Addr. Bit 10 DMA0-10 Addr. Bit 10 Bit 9 DMA0-10 Addr. Bit 8 DMA0-10 Addr. Bit 8 Default: Rst. Value 00h Read Value 00h Bit 11 Bit 9 Address: chcsl[10:0] DMAUSB Low Counter (DMAiCntlo) Bit 7 DMA0-10 Addr. Bit 7 Bit 6 DMA0-10 Addr. Bit 6 Bit 5 DMA0-10 Addr. Bit 5 Bit 4 DMA0-10 Addr. Bit 4 Bit 3 DMA0-10 Addr. Bit 2 DMA0-10 Addr. Bit 2 Bit 1 DMA0-10 Addr. Bit 0 DMA0-10 Addr. Bit 0 Default: Rst. Value 00h Read Value 00h Bit 3 Bit 1 * * DMAUSB Channel 0-3 Lower Address Counter Value. Address will only count by 2. Reading this register will return the active Address value when the last USBACK occurred. Note: This register is double buffered. Writing to this location twice will load the active register as well as the buffer register. Upon a block limit interrupt, the buffer value will be activated therefor a new buffered value should be written to this register. DMAUSB0CntLo DMAUSB1CntLo DMAUSB2CntLo DMAUSB3CntLo 01FF81C8-C9 01FF81CE-CF 01FF81D4-D5 01FF81DA-DB 100723A Conexant 4-85 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: Bit 15 chcsh[10:0] DMAUSB Hi Counter Not Used (DMAiCnthi) Bit 14 Not Used Bit 13 Not Used Bit 12 Not Used Bit 11 Not Used Bit 10 Not Used Bit 9 Not Used Bit 8 Not Used Default: Rst. Value 00h Read Value 00h Address:chcsh[10: Bit 7 0] DMAUSB Hi Counter DMA0-10 Addr. (DMAiCnthi) Bit 23 Bit 6 DMA0-10 Addr. Bit 22 Bit 5 DMA0-10 Addr. Bit 21 Bit 4 DMA0-10 Addr. Bit 20 Bit 3 DMA0-10 Addr. Bit 2 DMA0-10 Addr. Bit 18 Bit 1 DMA0-10 Addr. Bit 0 DMA0-10 Addr. Bit 16 Default: Rst. Value 00h Read Value 00h Bit 19 Bit 17 * * DMAUSB Channel 0-3 Upper Address Counter Value. Address will only count by 2. Reading this register will return the active Address value when the last USBACK occurred. Note: This register is double buffered. Writing to this location twice will load the active register as well as the buffer register. Upon a block limit interrupt, the buffer value will be activated therefor a new buffered value should be written to this register. DMAUSB0CntHi DMAUSB1CntHi DMAUSB2CntHi DMAUSB3CntHi 01FF81CA-CB 01FF81D0-D1 01FF81D6-D7 01FF81DC-DD 4-86 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address:ch4csbs Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h Default: Rst. Value 00h Read Value 00h DMAUSB Transfer USB Channel Stop At Block Size Reg. Block Enable = 1 (DMAUSBBlockSize ) Address:ch4csbs Bit 7 Bit 6 Upper six bits of the Block Size Counter Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DMAUSBTransfer Low Byte Value for USB Memory Block Size Counter Block Size Reg. (DMAUSBBlockSize ) Block Size data written to this register will be placed into the inactive Block Size register. This register will become active once the prior block has completed (USB IRQ). Reading this register will return the Block Size value when the last USBACK occurred. Writing to this will initialize the logical channel. Therefore, when setting up a logical channel, this register should be written to last. Note: This register is double buffered. Writing to this location twice will load the active register as well as the buffer register. Upon a block limit interrupt, the buffer value will be activated therefor a new buffered value should be written to this register. * DMA USB Channel Block Size Limit Counter DMAUSB0 BlkSiz DMAUSB1 BlkSiz DMAUSB2 BlkSiz DMAUSB3 BlkSiz 01FF81CC-CD 01FF81D2-D3 01FF81D8-D9 01FF81DE-DF Bits [13:0] DMAUSB Memory Block Size The block size of DMA channel can range from 1 - 16383 DMA transfers. The Block Size counter will decrement regardless of the DMA Address counter's activity. The block size register content is 0000h when the block size limit is reached. When the block size reaches its limit, an IRQ will be generated upon the next Channel ACK. Writing To this register will clear the IRQ. Bit 14 Note: is entered. When this bit is set, the DMA channel will disable it's self until a new block size If this bit is 0, when a block limit is reached the next block size will be downloaded into the counter along with the next DMA address and transfers will continue within the new block. Upon the next channel ACK, an IRQ will be generated. Bit 15: This bit must be set at all times to enable the channel and is not part of the double buffering process. 100723A Conexant 4-87 MFC2000 Multifunctional Peripheral Controller 2000 Address:ch1cscntl Bit 15 DMA 1 Configuration DMAACK1 (DMA0config) $xx8183 Delay-off 0=normal 1=delay 1/2 SIUCLK cycle Address:ch1cscntl Bit 7 DMA 1 Configuration Read = 1 (DMA0config) $xx8182 Write = 0 Bit 6 Enable 0 = disable 1 = enable Bit 5 Not Used Bit 4 Not Used Bit 3 Not Used Bit 2 Not Used Bit 1 Not Used Bit 14 Not Used Bit 13 Not Used Bit 12 Not Used Bit 11 Not Used Bit 10 Not Used Bit 9 Not Used Hardware Description Bit 8 Not Used Default: Rst. Value 00h Read Value 00h Bit 0 Count By 0=byte 1=halfword Default: Rst. Value 00h Read Value 00h Bit 0: Bit 6: Bit 7: Bit 15: Sets byte or halfword data access to match external devices. This bit controls the channel enable This bit controls the external data direction Setting this bit to a 1 will extend the external DMAACK 1/2 SIUCLK cycle so that it may be used as a chip select. Bit 13 Not Used Bit 12 Not Used Bit 11 Not Used Bit 10 Not Used Bit 9 BRB to Memory, Data Transfer Bit 8 Default: Byte Mode = Rst. Value 0 00h 1/2 Word Read Mode = 1 Value 00h (Write Only) Address:ch2cscnt Bit 15 Bit 14 DMA 2 Configuration DMAACK2 Not Used Delay-off (DMA2config) 0 = normal $xx81B3 1 = delay half SIUCLK cycle (Write Only) Address:ch2cscnt Bit 7 DMA 2 Configuration Read = 1 (DMA2config) $xx81B2 1= Ext Mem Write = 0 0=Bit Rot. Bit 6 Requested Device Bit 5 0 = Inc 1 = Dec Bit 4 Count By 1024 Bit 3 Count By 512 Bit 2 Count By 256 Bit 1 Count By 2 Bit 0 Count By 1 Default: Rst. Value 00H Read Value 00h DMA channel 2 Address Jump, Increment, and Decrement Control. The Count By control bits allows the user to select how the address is progressed after each DMA access. Only one Count By Bit can be set at a time. If there are no Count By control bits selected the address will remain fixed. Bit 15: If DMAACK2 is used as a select signal (like a chip select), the extended DMAACK2 may be needed. This `DMAACK2 delay-off' bit needs to be set to `1' for extending DMAACK2 half SIUCLK cycle. This bit controls the source of the DMA Request. If this bit is set to 0 and bit 6 is set to 0, a external support chip must be used to provide an external DMA Request for transferring printer data. If an external device is not used, the Bit Rotation Block can directly transfer print data to memory. To operate in this mode bit 9 should be set to 1, bit 6 set to 0, and bit 7 set to 0 for DMA writes to memory. If bit 6 is set to 1, bit 9 must be set to 0. Bit 9: 4-88 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Bit 8: If the Bit Rotation Block is selected (bit 6 = 0), and the external data bus for the Print ASIC is byte wide, this bit needs to be `0'. If the Bit Rotation Block is selected (bit 6 = 0), and the external data bus for the Print ASIC is halfword wide, this bit needs to be `1'. If external memory is selected (bit 6 = 1), the external bus data width for the Print ASIC and external memory need to be matched (this bit is not used). Control bit definition is with reference to the DMA requested device and controls the read/write signals during the DMA cycle. If it is set to write, the write strobe will be active during the DMA cycle. If the Bit Rotation Block is selected ( bit 6 = 0), the DMA Request will be held off when the Bit Rotation Block output register is not ready. The ASIC output bus drivers will be disabled during external DMA request write (bit 6 = 1 and bit 7 = 0). Controls the address count direction performed after each DMA cycle. These bits control how the address registers will count after each DMA cycle. Note: If byte mode is set, the Count By 1 should be set. Note: Requests to this channel are delayed by two clocks for synchronization. Bit 7: Bit 6: Bit 5: Bit 4-0: Address:ch2csbs DMA 2 Transfer Block Size Reg. (DMA2BlockSize) $xx81B5 Address:ch2csbs Bit 15 Channel 2 Enable = 1 Bit 14 Not Used Bit 13 Not Used Bit 12 Not Used Bit 11 Not Used Bit 10 Not Used Bit 9 Bit 8 Default: Upper two bits of the Block Rst. Value Size counter 00h Read Value 00h Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 DMA2 Transfer Low Byte Value for the External DMA Block Size Counter Block Size Low Byte Reg. (DMA2BlockSizeLo) $xx81B4 * * DMA Channel 2 Block Size Limit Counter block size of DMA channel 2 (halfwords) - Unlimited block size (block size = ): bit[7:0] of the DMA2BlockSize register = 00h bit[9:8] of the DMA2BlockSize register = 00b. * * * - Limited block size (block size = 1 - 1023) The Block Size counter will decrement regardless of the DMA Address counter's activity. The block size register content is 0000h when the block size limit is reached. Please see the operation description of DMA2BlkSize and DMA2BufBlkSize registers below (in the DMA2BufBlkSize register section). Writing to this register will also clear the DMA channel 2 interrupt. Channel 2 Enable is cleared when the block size limit is reached, and must be set, (enabled) after a new block size is entered. The block size can only be written into the DMA2Blksize register when this bit is 0. Bit 15: 100723A Conexant 4-89 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address:ch2csbbs DMA Ch2 Buffered Transfer Block Size Reg. (DMA2BfBlockSize) $xx81B7 Address:ch2csbbs Bit 15 Ch2 Enable = 1 Bit 14 Not Used Bit 13 Not Used Bit 12 Not Used Bit 11 Not Used Bit 10 Not Used Bit 9 Bit 8 Default: Upper two bits of the Block Rst. Value Size counter 00h Read Value 00h Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 DMA Ch2 Buffered Low Byte Value for the External DMA Block Size Counter Transfer Block Size Low Byte Reg. (DMA2BfBlockSizeLo) $xx81B6 * * DMA Channel 2 Buffered Block Size Limit Counter block size of DMA channel 2 (1/2 Words) - Unlimited block size (block size = ): bit[7:0] of the DMA2BlockSize register = 00h bit[9:8] of the DMA2BlockSize register = 00b. Limited block size (block size = 1 - 1023) - * * * The first transfer block size and the starting address must be set up in the DMA2BlkSize and DMA2 address registers. The second transfer block size and the starting address must be set up in the DMA2BufBlkSize and DMA2 buffered address registers. Then, Firmware only needs to update the DMA2BufBlkSize and DMA2 buffered address registers when the DMA channel 2 interrupt occurs. This allows preloading of the next block size and starting address before the DMA operation for the current block has completed. The Buffered Block Size will be down loaded into the Block Size Counter when the current Block Size is reached and a new value has been written into this buffered block size register. Writing to this register will also clear the DMA channel 2 interrupt. The block size can be written into the DMA2BufBlkSize register only when the value of bit 15 in the DMA2BlkSize register is set to 0. Bit 14 DMAB2 Addr. Bit 14 Bit 6 DMAB2 Addr. Bit 6 Bit 13 DMAB2 Addr. Bit 13 Bit 5 DMAB2 Addr. Bit 5 Bit 12 DMAB2 Addr. Bit 12 Bit 4 DMAB2 Addr. Bit 4 Bit 11 DMAB2 Addr. Bit 11 Bit 3 DMAB2 Addr. Bit 3 Bit 10 DMAB2 Addr. Bit 10 Bit 2 DMAB2 Addr. Bit 2 Bit 9 DMAB2 Addr. Bit 9 Bit 1 DMAB2 Addr. Bit 1 Bit 8 DMAB2 Addr. Bit 8 Bit 0 DMAB2 Addr. Bit 0 Default: Rst. Value 00h Read Value 00h Default: Rst. Value 00h Read Value 00h Address: chcsbl[2] Bit 15 DMA Ch2 Buffered Low Counter (DMA2Cntblo) $xx818D DMA Ch2 Buffered Low Counter (DMA2Cntblo) $xx818C DMAB2 Addr. Bit 15 Address: chcsbl[2] Bit 7 DMAB2 Addr. Bit 7 * * DMA Channel 2 Lower Buffered Address Counter Value The Buffered Address Counter Value will be down loaded into the Address Counter when the current Block Size is reached and a new value has been written into this register. 4-90 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: chcsbh[2] Bit 15 DMA Ch2 Buffered Hi Counter (DMA2Cntbhi) $xx818F DMA Ch2 Buffered Hi Counter (DMA2Cntbhi) $xx818E Not Used Bit 14 Not Used Bit 13 Not Used Bit 12 Not Used Bit 11 Not Used Bit 10 Not Used Bit 9 Not Used Bit 8 Not Used Default: Rst. Value 00h Read Value 00h Default: Rst. Value 00h Read Value 00h Address:chcsbh[2] Bit 7 DMAB2 Addr. Bit 23 Bit 6 DMAB2 Addr. Bit 22 Bit 5 DMAB2 Addr. Bit 21 Bit 4 DMAB2 Addr. Bit 20 Bit 3 DMAB2 Addr. Bit 19 Bit 2 DMAB2 Addr. Bit 18 Bit 1 DMAB2 Addr. Bit 17 Bit 0 DMAB2 Addr. Bit 16 * * DMA Channel 2 Upper Buffered Address Counter Value The Buffered Address Counter Value will be down loaded into the Address Counter when the current Block Size is reached and a new value has been written into the Buffered Block Size register. Address:ch5csbs DMA5 Transfer Block Size Reg. (DMA4BlockSize) $xx81BB Address:ch5csbs DMA5Transfer Block Size Reg. (DMA4BlockSize) $xx81BA Bit 15 Channel 5 Enable = 1 Bit 14 Not Used Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h Default: Rst. Value 00h Read Value 00h Upper six bits of the Block Size counter Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Low Byte Value for the PIO to Memory Block Size Counter * * DMA Channel 5 Block Size Limit Counter block size of DMA channel 5 (bytes) - Unlimited block size (block size = ): bit[13:0] of the DMA5BlockSize register = 0000h Limited block size (block size = 1 - 16380) The Block Size counter will increment regardless of the DMA Address counter's activity * Bit 15: Channel 5 Enable is cleared when the block size limit is reached, and must be set, (enabled) after a new block size is entered. This bit is also inverted and sent to the PIO as MaxDmaCnt. The new block size can only be written when this bit is 0. 100723A Conexant 4-91 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address:ch9csbs DMA9 Transfer Block Size Reg. (DMA9BlockSize) $xx81BF Address:ch9csbs DMA9Transfer Block Size Reg. (DMA9BlockSize) $xx81BE Bit 15 Channel 9 Enable = 1 Bit 14 Not Used Bit 13 Not Used Bit 12 Not Used Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h Default: Rst. Value 00h Read Value 00h Upper four bits of the Block Size counter Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Low Byte Value for the Bi-level resolution conversion logic Block Size Counter * * DMA Channel 9 Block Size Limit Counter block size of DMA channel 9 (bytes) - Unlimited block size (block size = ): bit[11:0] of the DMA9BlockSize register = 000h Limited block size (block size = 1 - 4095) The Block Size counter will decrement regardless of the DMA Address counter's activity. The block size register content is 0000h when the block size limit is reached. Writing to this register will also clear the bi-level resolution conversion interrupt. Channel 9 Enable is cleared when the block size limit is reached, and must be set, (enabled) after a new block size is entered. The new block size can only be written when this bit is 0. Bit 15 Throttle Ch. Select 0= Ch. 6 1= Ch. 10 Bit 7 Throttle Value bit 7 Bit 14 Throttle Value bit 14 Bit 6 Throttle Value bit 6 Bit 13 Throttle Value bit 13 Bit 5 Throttle Value bit 5 Bit 12 Throttle Value bit 12 Bit 4 Throttle Value bit 4 Bit 11 Throttle Value bit 11 Bit 3 Throttle Value bit 3 Bit 10 Throttle Value bit 10 Bit 2 Throttle Value bit 2 Bit 9 Throttle Value bit 9 Bit 1 Throttle Value bit 1 Bit 8 Throttle Value bit 8 Bit 0 Throttle Value bit 0 Default: Rst. Value 00h Read Value 00h Default: Rst. Value 00h Read Value 00h * * Bit 15: Address: DMA6/10 Throttle (DMA6/10Throttle) $01FF81BD Address: DMA6/10 Throttle (DMA6/10Throttle) $01FF81BC * Throttle Value (TV) = 1-32767 (TV= 0; disables Throttle Function) Throttle Value (TV) allows 1 DMA access every "TV*SIUCLK" time period. * DMA Channel 6 OR 10 Throttle Control: This register is loadable while the DMA is active. Write to this register will reset the throttle timer. 4-92 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address:ch10csbs Bit 15 DMA10 Transfer Block Size Reg. (DMA10BlockSize) $xx81C1 DMA10Transfer Block Size Reg. (DMA10BlockSize) $xx81C0 Channel 10 Enable = 1 Bit 14 Not Used Bit 13 Not Used Bit 12 Not Used Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h Default: Rst. Value 00h Read Value 00h Upper four bits of the Block Size counter Address:ch10csbs Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Low Byte Value for the PIO to Memory Block Size Counter * * DMA Channel 10 Block Size Limit Counter block size of DMA channel 10 (bytes) - Unlimited block size (block size = ): bit[11:0] of the DMA10BlockSize register = 000h - Limited block size (block size = 1 - 4095) * * The Block Size counter will decrement regardless of the DMA Address counter's activity. The block size register content is 0001h when the block size limit is reached. Writing to this register will also clear the DMA channel 10 interrupt. Channel 10 Enable is cleared when the block size limit is reached, and must be set, (enabled) after a new block size is entered. The new block size can only be written when this bit is 0. Bit 14 USB3 Inc = 0 Dec = 1 Bit 6 DMA 8 Inc = 0 Dec = 1 Bit 13 USB2 Inc = 0 Dec = 1 Bit 5 DMA 7 Inc = 0 Dec = 1 Bit 12 USB1 Inc = 0 Dec = 1 Bit 4 DMA 6 Inc = 0 Dec = 1 Bit 11 USB0 Inc = 0 Dec = 1 Bit 3 DMA 5 Inc = 0 Dec = 1 Bit 10 DMA 12 Inc = 0 Dec = 1 Bit 2 DMA 4 Inc = 0 Dec = 1 Bit 9 DMA 11 Inc = 0 Dec = 1 Bit 1 DMA 1 Inc = 0 Dec = 1 Bit 8 DMA 10 Inc = 0 Dec = 1 Bit 0 Not Used Default: Rst. Value 00h Read Value 00h Default: Rst. Value 00h Read Value 00h Bit 15: Address: csincconf Bit 15 DMA Increment Configuration (DMAIncConfig) $xx81C3 DMA Increment Configuration (DMAIncConfig) $xx81C2 Not Used Address: csincconf Bit 7 DMA 9 Inc = 0 Dec = 1 * DMA Address Increment Configuration. The Increment Configuration control bit allows the user to Select where the DMA channel Increments or Decrements after each access. 100723A Conexant 4-93 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: cscontenb DMA Count Enable (DMACntConfig) $xx81C5 Bit 15 Not Used Bit 14 Not Used Bit 13 Not Used Bit 12 Not Used Bit 11 Not Used Bit 10 DMA 12 Count Enable Bit 2 DMA 4 Count Enable Bit 9 DMA 11 Count Enable Bit 1 DMA 1 Count Enable Bit 8 DMA 10 Count Enable Bit 0 Not Used Default: Rst. Value 07h Read Value 07h Default: Rst. Value FEH Read Value FEH Address:cscontenb Bit 7 DMA Count Enable (DMACntConfig) $xx81C4 DMA 9 Count Enable Bit 6 DMA 8 Count Enable Bit 5 DMA 7 Count Enable Bit 4 DMA 6 Count Enable Bit 3 DMA 5 Count Enable * DMA Address Count Enable Control. The Count Enable control bit allows the user to enable address Count after each DMA access. If the Count Enable control bit is not set the address will remain fixed. Bit 15 Bit 14 Not Used Bit 13 Not Used Bit 12 DMA 12 Endian Control Bit 4 DMA 4 Endian Control Bit 11 DMA 11 Endian Control Bit 3 DMA 3 Endian Control Bit 10 DMA 10 Endian Control Bit 2 DMA 2 Endian Control Bit 9 DMA 9 Endian Control Bit 1 DMA 1 Endian Control Bit 8 DMA 8 Endian Control Bit 0 Not Used Default: Rst. Value 00h Read Value 00h Default: Rst. Value 00H Read Value 00H Address: cscontenb DMA Endian Control Not Used (DMAEndian) $xx81C7 Address:cscontenb Bit 7 DMA Endian Control DMA 7 (DMAEndian) Endian $xx81C6 Control Bit 6 DMA 6 Endian Control Bit 5 DMA 5 Endian Control * DMA Address Endian Control. If the Endian Control Bit is set to a 1, the data structure will be changed between the Little Endian mode and the Big Endian mode. The current data structure address 00: Byte 0 address 01: Byte 1 address 02: Byte 2 address 03: Byte 3 !" !" !" !" The changed data structure address 11: Byte 0 address 10: Byte 1 address 01: Byte 2 address 00: Byte 3 For DMA 1 (the external DMA channel) and DMA 2 (programmed as external DMA channel), this endian control can't be used for accessing external memory (the associated bit needs to be set to 0). If the external I/O device tries to get/put data from/to internal memory or registers, this endian control can be used with no problem. For example, if the external print ASIC tries to get data from the internal bit rotation block through DMA 2, this endian control can be used with no problem. If the external print ASIC tries to get data from the external memory through DMA 2, this endian control can't be used. In this case, the right endian structure should be prepared when the data is put into the external memory through the other process and DMA channels. 4-94 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 This page is intentionally blank 100723A Conexant 4-95 Multifunctional Peripheral Controller 2000 MFC2000 5. RESET Logic/Battery Backup/Watch Dog Timer 5.1 Reset Logic/Battery Backup The MFC2000 has two power resets, Battery Power Reset and Prime Power Reset. The Battery Power Reset is the primary reset used to initialize battery-powered logic when battery power is first applied. Prime Power Reset initializes all non-battery powered logic whenever system power is applied. A third reset is generated by the watchdog timer or by the RESETn pin. The major logic blocks and associated MFC2000 signals are illustrated in Figure 5-1. Note: Reset logic operation requires use of the RTC Crystal (connected to XIN and XOUT). 100723A Conexant 5-1 MFC2000 Multifunctional Peripheral Controller 2000 MCLK for ARM7 CPU SYSCLK RESET Sync Fax Timing Block Hardware Description local_clk RESETn SIUCLK Power up Delay 2 & Retime to local_clk RESn Battrtc_RESn Prime Power Battery Power Divider XOUT pwrdwn_padn ext_pdsel Pwrdwn select logic pwrdwn Power up Delay 1 clock enable battery refresh inactive SYSIRQ for power down DRAM refresh control Vdd refresh enable clear SYSIRQ routine Lockout Logic lockout to battery register reset CS0n RASn[1:0] CASOn[1:0] CASEn[1:0] DWRn BATRSTn Tristate Control Figure 5-1. Power Reset Block Diagram 5-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 ext_pdsel_padn pwrdwn_padn sia_pwr_down1 1 0 sia_pwr_down2 0 1 int_pwrdwn_sel Figure 5-2. Power-down Select Logic 5.1.1 Battery Power Reset Battery Power Reset is generated when BATRSTn (as shown at lower left in Figure 5-1) is driven low, and initializes the MFC2000 when battery power is first applied, as well as forcing a Prime Power Reset if VDD is present. As long as battery power is maintained, there is no need to reactivate this reset. If the system design does not utilize the MFC2000's battery power features, this reset should be tied to PWRDWNn and be activated upon system power initialization. Battery backup system requirements are undefined when battery power is first applied. Consequently, BATRSTn disables the battery backup control for DRAM and disables SRAM by resetting the BackupConfig register, and inhibits CPU access to this register via the (internal) lockout signal. The disabling of battery backup controls tristates the associated output control signals (i.e., CS[0]n for SRAM, and CASOn[1:0]n, CASEn[1:0], RASn[1:0], and DWRn for DRAM, as shown at lower right in Figure 5-1. Note: The proper off-state logic level for battery backed-up devices external to the MFC2000 must be maintained by external pull-up/pull-down resistors on the appropriate MFC2000 pins. BATRSTn has a Schmitt trigger input buffer to allow the use of an external RC circuit to generate a reset. 5.1.2 Prime Power Reset Prime Power Reset occurs when PWRDWNn (shown at upper left in Figure 5-1) is driven low while prime power is applied. There are two Prime Power Reset operating modes, one for VDD power on and one for VDD power off. 100723A Conexant 5-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description VDD Power On VDD power on occurs when VDD power reaches it's normal operating level and PWRDWNn is driven high, resulting in "Power-Up Delay 1" (PUD1) initiation (shown at upper left in Figure 5-1). PUD1 has a duration of one or two Reset clocks (internal signal), depending on when PWRDWNn is driven high with respect to the Reset clock rising edge. Once PUD1 times out, the internal signal Battrtc_RESn is released. The internal Reset clock signal (RESn) duration is equal to approximately 125 ms for XOUT = 32.768 kHz. Reset clock = XOUT/4096 "Power-Up Delay 2" (PUD2) is a time delay whose duration is approximately 8 periods of SIUCLK (6 SIUCLK periods + time for retiming to AUXCLK). This delay allows CPU pre-operation initialization. Once PUD2 times out, RESETn gets resynchronized to AUXCLK and then, changes from an active low state to a high impedance state. After RESETn goes to the high impedance state, RESn goes high approximately after 8 periods of SIUCLK. After the internal RESn signal goes high, all internal logic gets reset and the battery back-up lockout is removed on the next XOUT rising edge. VDD Power Off VDD power off occurs when PWRDWNn is driven low while VDD is at a normal operating level. As an MFC2000 battery backed up feature, PWRDWNn has been designed to work with an early warning power loss detector. This allows the firmware to backup sensitive variables, and the MFC2000 to protect nonvolatile data from erroneous logic operations while prime power transitions through low voltage levels (i.e., < 3.135V). When PWRDWNn is driven low, an SYSIRQ is issued to the CPU, and the CPU SYSIRQ routine then performs necessary system house cleaning tasks before power loss. The final SYSIRQ routine task is to write to the LockEnn register, which enables the battery lockout logic. The battery lockout logic forces an immediate lockout if battery DRAM operation is not enabled. If DRAM operation is enabled, the battery lockout logic waits for the absence of a VDD refresh cycle before performing the lockout. While in lockout, battery refresh mode commences, Battrtc_RESn becomes active, and the MFC2000 is inactive until the next VDD power on cycle. Time-out Logic for the power-down lockout There is a 1-2 second time-out on lockenn, if power down goes low enough to get latched into the battery logic, but a lockenn doesn't get generated by software. This will guarantee that a reset will occur if power down ever gets set and software doesn't set lockenn so that a reset gets generated. There are two status bits to the backup configuration register. Bit 12 indicates that a battery reset (from the pin batrstn) has been detected. Bit 11 indicates that a lock enable has occurred and was caused by the time-out circuitry or a software write. To reset either of these bits a 1 must be written to the appropriate bit. 5-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 5.1.3 External Reset (RESETn) and Watchdog Reset A driver on the AMPFC's RESETn pin provides a reset signal to external devices whenever the internal Battrtc_RESn or watchdog reset is active (low). This pin also includes an input driver that allows external control circuitry to reset the CPU and all VDD powered registers (including a power-down SYSIRQ condition). The external RESETn and internal RESn are also activated when the watchdog timer times out (refer to the watchdog timer section that follows). An externally generated reset does not affect the battery powered registers nor DRAM refresh operation. [CAUTION] Don't drive the RESETn pin `high' from external. Only drive the RESETn pin `low' to generate the reset from external and don't drive the RESETn pin when external reset is not needed. 5.1.4 Power Reset Timing Diagram The battery and VDD power on reset timing is illustrated in Figure 5-1. The first event shown is the battery voltage and lockout rising together as battery voltage is applied, followed by BATRSTn going high, and the start up of XOUT. On the second falling edge of Reset clock after VDD has been applied and PWRDWNn has been driven high, Battrtc_RESn goes high and approximately eight SIUCLKs are counted as Power-Up Delay 2. At the completion of eight SIUCLKs, battery lockout is removed allowing access to the BackupConfig register. (internal) SIUCLK (internal) Reset Clock - 125ms Battery Voltage Lockout BATRSTn VDD PWRDWNn (internal) Battrtc_RESn (internal) clock enable RESETn (internal) RESn Power up Delay 2 (8 SIUCLKs) Internal clock on Power up Delay 1 (125-250ms) 8 SIUCLKs) Figure 5-3. Power Reset Timing Diagram 100723A Conexant 5-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 5.1.5 5.1.5.1 Power on/off Sequence Power Type +3.3V prime power signal * Connect to VDD pins on the MFC2000 chip to supply prime power to the MFC2000 die in the MFC2000 chip. +5V prime power signal * * Connect to ADVA and ADVD pins on the MFC2000 chip to supply prime power to the ADC die in the MFC2000 chip. Connect to VGG pins on the MFC2000 chip to supply +5v prime power to all +5v tolerant pads in the MFC2000 chip. +3V battery power signal * * Connect to the VBAT pin on the MFC2000 chip to supply battery power to the battery backup RTC in the MFC2000 chip and external SRAM. Connect to the VDRAM pin on the MFC2000 chip to supply battery power to the battery backup DRAM refresh logic in the MFC2000 chip and external DRAM. Prime Power Sequence 5.1.5.2 It is recommended that +3.3v prime power signal is supplied first and then, supply +5v prime power signal for the prime power-on sequence. In other words, The voltage level of +5v prime power signal must be lower than the voltage level of +3.3v prime power signal before +3.3v prime power signal reaches the stable level. V+5 is turned off first and then, turn off V+3.3 for the prime power-off sequence. In other words, The voltage level of +5v prime power signal must be always lower than the voltage level of +3.3v prime power signal during the power-off sequence. The recommended connection between +5v prime power signal and VGG is shown: +5V 1Kohm .1uF VGG Figure 5-4. +5v Prime Power Signal and VGG 5-6 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 5.1.6 Register Description Battery Backup and Prime Power Reset Registers Name/Address Backup Configuration Register (BackupConfig) $01FF8099 Name/Address Backup Configuration Register (BackupConfig) $01FF8098 Bit 7 0 = no backup 1 = 1-2 days 2 = 2-3 days 3 = infinite days Bit 6 Bit 5 Refresh Rate 1 = slow Bit 4 Oscillator Speed 32.768 KHz 1= 65.536 KHz Bit 3 Bank 1 Bit 15 Bit 14 Bit 13 Bit 12 Battery Reset Flag Bit 11 Lockout Time-out Flag Bit 10 SRAM Enable Bit 9 Bank 1 Bit 8 Bank 0 Data interface size: 0 = 8-bit 1 = 16-bit Bit 0 Default Default Rst. Value xxx00000b Read Value 00h (Not Used) (Not Used) Internal Power Down Select Data 0 = disable interface size: 1 = enable 0 = 8-bit 1 = 16-bit Bit 2 Bank 0 Bit 1 Bank 1 Interleave Enable DRAM Backup Time 0 = normal 0 = Bank 0 Rst. Value Interleave 00h Enable Enable Enable 0 = disable 0 = disable Read Value 0 = non 0 = non 1 = enable 1 = enable interleaved interleave 00h 1 = 2 way d interleaved 1 = 2 way interleave d Register Description: This register is set to all zeros when first powered up and is battery backed up with the RTC Battery during power down. When a time out condition occurs, the RASn and CASn signals are tristated. When prime power has returned from a power down sequence, the user will have to perform a checksum on the DRAM data to know if a time out has occurred since there is no indication that the DRAM battery has lost power. The user will have to wait 1ms before accessing the DRAM after prime power has returned. Bits 15-14:Not used Bits 13: Internal Power Down Select 0 = PWRDWNn is generated by or-ing power_down1 with power_down2 1= PWRDWNn is generated by and-ing power_down1 with power_down2 Note: Power_down1 and power_down2 are output signals from the power-down detection circuit 1 and 2. Bit12: Bit11: Battery Reset Flag Lockout Time-out Flag This bit indicates that a BATRSTn occurred. To clear this bit, a 1 must be written to this bit. This bit indicates that a power down occurred, but no lockout was set with in the 1-2 second period. The lockout timer initiated the LOCKENn to create the lockout condition. Once the lockout condition occurs, if the power down signal is high, the chip will come out of reset after a PUD1 delay. To clear this bit, a 1 must be written to this bit. This bit enables the SRAM chip select CSN0. This register defines whether the databus to the bank 1 DRAMs is 8 bits wide or 16 bits wide. An 8-bit wide DRAM interface uses RASn[1] and CASOn[0]. A 16-bit wide non-interleaved DRAM interface uses RASn[1] and CASOn[1:0]. A 16-bit wide interleaved DRAM interface uses RASn[1], CASEn[1:0], and CASOn[1:0]. Bit10: Bit 9: SRAM Chip Select Enable Bank 1 Interface Size 100723A Conexant 5-7 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Bit 8: Bank 0 Interface Size This register defines whether the databus to the bank 0 DRAMs is 8 bits wide or 16 bits wide. An 8-bit wide DRAM interface uses RASn[0] and CASOn[0]. A 16-bit wide non-interleaved DRAM interface uses RASn[0] and CASOn[1:0]. A 16-bit wide interleaved DRAM interface uses RASn[0], CASEn[1:0], and CASOn[1:0]. These bits control the amount of time that the DRAM controller will spend refreshing the DRAMs when in the battery backup mode. After reset when the CPU is being released to run, the CPU will not be able to write data to bits 7 and 6 of the BackupConfiguration register immediately since the immediate write will not take effect. The CPU must wait at least one oscillator clock cycle before writing data into bits 7 and 6. Battery Backup Duration: No battery backup 1-2 days 2-3 days Infinite Bits 7-6: DRAM Battery Backup Time Bit 6 Bit 7 0 0 1 1 0 1 0 1 Bit 5-4: DRAM Refresh Rate Refresh Speed: (bit 5) 0 0 Oscillator Speed: (bit 4) These bits are used to set up the DRAM refresh rate. See the following table: Refresh Speed: Description: normal RTC crystal frequency = 32.768 kHz, Refresh clock = the crystal frequency= 32.768 kHz, The refresh cycle time = 15.625 ms/1024 cycles. 0 1 fast RTC crystal frequency = 65.536 kHz, Refresh clock = the crystal frequency = 65.536 kHz, Refresh cycle time = 7.8125 ms/1024 cycles. 1 0 slow RTC crystal frequency = 32.768 kHz, Refresh clock = the crystal frequency/8 = 4.096 kHz Refresh cycle time = 125 ms/1024 cycles. 1 1 slow RTC crystal frequency = 65.536 kHz, Refresh clock = the crystal frequency/16 = 4.096 kHz Refresh cycle time = 125 ms/1024 cycles. Bits 3: Bank 1 Enable This bit controls whether or not the Bank 1 DRAMs will be enabled. The Enable signal will allow CAS before RAS refresh to occur based on the non-interleave or interleave setting. If the bank setting indicates a non-interleaved mode, RASn[1] and CASOn[0] (8-bit mode) or CASOn[1:0] (16-bit mode) will refresh the DRAM. If the bank setting indicates an interleaved mode, RASn[1], CASOn[1:0] and CASEn[1:0] will refresh the DRAM. DWRn will be high during refresh. CASEn[1:0] will be tristated if Bank 0 is in non-interleaved mode. If this bit is set to a zero, RASn[1] will be tristated. Default disabled. 5-8 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Bit 2: Bank 0 Enable This bit controls whether or not the Bank 0 DRAMs will be enabled. The Enable signal will allow CAS before RAS refresh to occur based on the non-interleave or interleave setting. If the bank setting indicates a non-interleaved mode, RASn[0] and CASOn[0] (8-bit mode) or CASOn[1:0] (16-bit mode) will refresh the DRAM. If the bank setting indicates an interleaved mode, RASn[0], CASOn[1:0] and CASEn[1:0] will refresh the DRAM. DWRn will be high during refresh. CASEn[1:0] will be tristated if Bank 1 is in non-interleaved mode. If this bit is set to a zero, RASn[0] will be tristated. Default disabled. This register defines whether the bank 1 DRAMs are to be accessed using 2-way interleave or non-interleaved access. 2-way interleaved access is only valid with a 16-bit interface (the 16 bit vs. 8 bit interface size bit for bank 1 is not used by the DRAM controller in the interleave mode, but is used by the SIU to output the data correctly). This register defines whether the bank 0 DRAMs are to be accessed using 2-way interleave or non-interleaved access. 2-way interleaved access is only valid with a 16-bit interface (the 16 bit vs. 8 bit interface size bit for bank 1 is not used by the DRAM controller in the interleave mode, but is used by the SIU to output the data correctly). Bit 1: Bank 1 Interleave Enable Bit 0: Bank 0 Interleave Enable Address Lock Enable (LockEnn) 01FF80A1(DW) Address Lock Enable (LockEnn) 01FF80A0 (DW) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default Rst. Value xxh Read Value xxh A Dummy write to the Lock Enable register will enable the battery/prime power lockout sequence for a power down condition. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Rst. Value xxh Read Value xxh A Dummy write to the Lock Enable register will enable the battery/prime power lockout sequence for a power down condition. * A write to this register enables the battery power lockout sequence for a power down condition. Lockout can only be cleared by resn. * This is not a battery backed-up register. 100723A Conexant 5-9 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 5.1.7 POWER DOWN DETECTION The power down detection circuit was only external for the MFC1000 chip. The PWRDWNn input signal to MFC1000 is the output of the external power down detection circuit. The MFC2000 has two internal power down detectors. The PWRDWNn is configurable either from internal power down detectors or from external power down detector. The EXT_PWRDWN_SELn is used to select internal or external power down detector. The external power down detector is selected when the EXT_PWRDWN_SELn pin is low. If the internal power detectors are selected, the combination of two power down detector can be further selected through the internal register. The purpose of having internal power down detector is to automatically generate reset after voltage drop on the power supply without having external power down detector. The power supply voltage is compared with internally generated threshold voltages. In order to prevent erratic resets, the comparator is designed with hysteresis feature. During the power up, the output of the comparator will be low when the power supply voltage is at least Von. Then as the voltage continues to increase and becomes larger than Von, the comparator output will be high. If at any time, the supply voltage drops below the threshold voltage level of Voff, then the comparator output will be low. POWER1 + pwr_down1 POWER2 + pwr_down2 Voltage Detector Reference Voltage Figure 5-5. Internal Power Detection V off V hys Output Voltage (V) ADVA ADGA Input Voltage (V) [Sia2k-comp-tf.vcd] Figure 5-6. Figure Caption Required 5-10 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Voltage Threshold Voff Vhys TADCREF 20 mV Margin 30 mV 2 mV Note: The output voltage to represent logic 0 must be guaranteed to be at ADGA (typically ADGA = GND = 0V). The input resistance to the voltage detector is specified as follows: Min Rin Input Resistance 10 M A voltage divider circuit will be used externally in order to obtain the desired voltage to monitor the power. 5V or 3.3V R1 power1 R2 R in MFC2K ADVA Voltage Detector power_down1 Figure 5-7. Voltage Divider Circuit 5.2 Watchdog Timer The Watchdog Timer is intended to guard against firmware lockup on the part of either Executive-controlled background tasks or Interrupt-driven tasks, and can only be enabled by a sequence of events under control of the Watchdog Control Logic. Once the Watchdog Timer has been enabled, it can not be disabled (inactivated) unless a system reset occurs. The watchdog timer block diagram is provided in Figure 5-8, and the Watchdog Time-Out Timing Diagram is provided in Figure 5-9. The Watchdog Timer is enabled by the following sequence of events, which MUST occur in the order described. 1. Write the value of the desired Time-out interval to the Watchdog Interval register. The first write to this register disables subsequent writes, and enables the next event in the enable sequence. 2. Write $0F followed by $F0 to the WatchdogEnRetrigger register. The data written to this register MUST be in the order specified or it is ignored. 3. After the operations are completed, the value in the Watchdog Interval register is loaded into the Time-out Down Counter. 100723A Conexant 5-11 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 4. As soon as the Watchdog Timer is enabled, the Time-out Down Counter begins counting. The Time-out Down Counter is decremented based on a 1 ms pulse which is derived from (125 s prescaler period /8); the count occurs on the rising edge of SIUCLK. After the Time-out Down Counter reaches 'zero', the (internal) watchdog reset signal becomes active at the next 1 ms pulse. The watchdog reset immediately activates the internal resn and external RESETn signals. These resets are deactivated when the Power Up Delay 2 timer times out (i.e., 8 SIUCLK's). In order to prevent the Watchdog Timer from timing-out and generating a reset pulse, it must be retriggered by writing $0F followed by $F0 to the WatchdogEnRetrigger register. This action causes the value in the WatchdogInterval register to be re-loaded into the Time-out Down Counter. Note: The 125us prescaler must be initialized before activating the watchdog timer. RESETn 1 BLOCK 1, 2, 3, 4, and 5 2 3 WATCHDOG INTERVAL REGISTER DATA BUS DATA BUS WATCHDOG ENRETRIGGER REGISTER WATCHDOG TIMER CONTROL 5 TIME-OUT DOWN COUNTER 4 SIUCLK 1ms pulse WATCHDOG RESET GENERATOR Figure 5-8. Watchdog Timer Block Diagram WDRE S 5-12 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 N-1 0 SIUCLK 1ms (N-1)ms 1ms T1msCI Counter Enable WDRES Figure 5-9. Watchdog Time-Out Timing Diagram 5.2.1 Watchdog Timer Registers Address: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value xxh Read Value 00h Watchdog Enable (Not Used) Retrig. (WatchdogEnRetrigger) 01FF8041 Address: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h Watchdog Enable Writing 0Fh followed by F0h to this register after setting the Watchdog Interval register will enable the Retrig. Watchdog timer. (WatchdogEnRetrigger) (The 125sPrescaler must be initialized before activating the Watchdog timer.) Always reads back `00h'. 01FF8040 (W) 100723A Conexant 5-13 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: Watchdog Interval (WatchdogInterval) 01FF8043 Bit 15 (Not Used) Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value xxh Read Value 00h Address: Watchdog Interval (WatchdogInterval) 01FF8042 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h Watchdog Interval (n = 0-255) (n*1ms) * Once enabled, the Watchdog Timer can only be disabled by reset. * On reset, the Watchdog Timer is disabled until it is enabled by writing to the WatchdogInterval register followed by writing $0F and $F0 to the WatchdogEnRetrigger register. * The basic Watchdog time-out unit (1 ms) is based on the internal 125 sec timer. Therefore, the 125sPrescaler and MSINTPeriod registers (used to activate the timer) must be set in order to operate the Watchdog Timer. * The accuracy of the time-out period is equal to the accuracy of the 125 sec timer with an additional error of up to 1 msec (i.e., the amount of error is dependent on the relationship of the trigger point to the internal 1 msec timer). * If N is programmed into the WatchdogInterval register, the Watchdog Timer time-out period is "N * 1 ms" (N = 0 - 255). * Reading the address of the WatchdogInterval register returns the value of N that was programmed into the WatchdogInterval register. * The following conditions do not enable the watchdog timer: Only the first write to the WatchdogInterval register is valid. The subsequent writes to this register are ignored. Any other data written to the WatchdogEnRetrigger register between the times $0F and $F0 are written is ignored. Once enabled, the Watchdog Timer is retriggered on the writing of alternate $0F and $F0. (Writing of any other data, and the writing of repetitive $0F or $F0 is ignored.) 5-14 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 This page is intentionally blank. 100723A Conexant 5-15 Multifunctional Peripheral Controller 2000 MFC2000 6. Fax Timing Control Interface 6.1 6.1.1 PLL Description The MFC2000 is an ASIC that provides multifunctional control for color fax, color scan and color printing. The ASIC includes an ARM microprocessor running at 30 MHz, 37.5 MHz or 40 MHz and a Countach Imaging DSP running at 100 MHz or 85.7 MHz. Additionally, the ASIC also supports the USB interface running at 48 MHz and the AUXCLK at 10 MHz. The PLL for the ASIC is designed to provide all the above frequencies in six operating modes based on the combination of ARM frequency select and Countach Imaging DSP frequency select. The six operating modes are defined in the following table. 6.1.2 Frequency Requirement The frequencies for the six operation modes are defined as follows: Table 6-1. Operation Mode Frequencies CLKConfig[1:0] 00 01 10 00 01 10 11 CLKConfig[2] 1 1 1 0 0 0 ARM (SIUCLK) 30 MHz 37.5 MHz 40 MHz 30 MHz 37.5 MHz 40 MHz Countach 85.7 MHz 85.7 MHz 85.7 MHz 100 MHz 100 MHz 100 MHz USB 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz AUXCLK 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz Don't Care The MFC2000 can only operate in one mode at a time. The mode selection is made during the reset through clock configuration pins (CLKConfig[2:0]). The input reference frequency is 28.224 MHz, which is generated by a crystal oscillator pad. 28.224MHz is also used for the internal P80 modem DSP. 100723A Conexant 6-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 6.2 Fax Timing Logic The fax timing logic block generates all of the time bases needed by the MFC2000. The fax timing logic block diagram is provided in Figure 6-1. A= [IHSCLK period]+1 A is from 1 to 2 Divide By A IHSCLK IHSCK1X_SELn IHS_LCLPHI I_LCLPHI ICLKand AUXCLK Divide By 8 SIUCLK Divide By B MMCLK B= [ICLK period]+1 B is from 2 to 4 WATCHDOG TIMING GENERATOR Divide By 8 C= [Prescaler]+1 C is from 1 to 256 Divide By C TIM_8MS TIM_1MS_SIUCLK TIM_125US_ICLK TIM_125US_SIUCLK Divide By D D= [MSINT perild]+1 D is from 1 to 64 TIM_MSINT ONEMSCLK (from RTC) 1MS/2MSIRQ GENERATOR TIM_1MS/2MSIRQ Notes: (1) I_LCLPHI is only used internally to indicate the SIUCLK cycle before the last SIUCLK cycle in one ICLK time period. (2) IHS_LCLPHI is only used internally to indicate the SIUCLK cycle before the last SIUCLK cycle in one IHSCLK time period. (3) ICLK is the base clock for internal peripherals and is only used internally to synchronize all the internal logic. The frequency of ICLK must be equal to or less than 10MHz. ICLK duty cycle is 33% when ICLK = SIUCLK/3. (4) IHSCLK is the high speed base clock for the PIO and Bit Rotation blocks and is only used internally to synchronize all the internal logic. The frequency of IHSCLK must be equal to or less than 20MHz. (5) AUXCLK has the same frequency as ICLK and is output to the external world through a pin. AUXCLK is used to synchronize external peripherals. AUXCLK duty cycle is always 50% no matter what is the relationship between ICLK and SIUCLK. (6) MMCLK is the base clock for the motor control logic. (7) TIM_8MS is used by the PIO Block. (8) TIM_1MS is the base clock for the the watchdog timer. (9) TIM_MSINT is used to synchronize the scanning and motor stepping. (10) TIM_1MS/2MSIRQ is used to generate an interrupt every 1ms or 2ms (selectable). The actual period of the 1MSIRQ = 1.00708 ms and 2MSIRQ = 2.01416ms Figure 6-1. Fax Timing Control Logic Block Diagram 6-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 6.3 MFC2000 Timing Chain The MFC2000 timing chain is illustrated in Figure 6-2. SIUCLK Divide by A A = [IHSCLK Period] + 1 125us synchronized to SIUCLK Divide by B B = [ICLK Period] + 1 Divide by 8 Divide by 8 ICLK (AUXCLK) Divide by C C = [125us Prescaler] + 1 Divide by 8 about 8ms IHSCLK for Tone Generator for Watchdog Timer and bell/ring generator about 1ms for Watchdog Timer for PIO Divide by D D = [MSINT Period] + 1 MSINT for scanning and motor stepping synchronization Divide by E E = [ Scan Cycle] + 1 Divide by F F = [ Step Clock ] + 1 ADCLK on/off Control H = [ScanDotPeriod] + 1 Divide by G G = [ScanDotScaler] +1 Divide by 2 Divide by H Divide by 8 Scan Cycle MMCLK STEPCLK for vertical print motor stepping and scan motor stepping ADCLK for ADC die VC1Pos, VC1Neg ScanBytes(2-512 bytes) CLK1, CLK1N CLK2Pos, CLK2Neg StartPos, StartNeg ADCSamplePos VC0Pos, VC0Neg ONEMSCLK(from RTC) 1MS/2MSIRQ Gen. 1MS/2MSIRQ* Figure 6-2. MFC2000 Timing Chain 100723A Conexant 6-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 6.4 Scan Control Timing In this example, the scan motor has the constant speed. The scan motor stepping is synchronized to the MSINT. The scan IRQ is used to disable motor stepping when we want to finish scanning. If the delay time for the scan motor is long enough, the last step will occur after the scan IRQ. Then, we need to use the scan step IRQ (sstepirq) for disabling motor stepping. The detail description for the motor stepping is described in Section 12. MSINT-0 Tics Dela y Time Scan IRQs (Last MSINT) Step Time Step Time Scan Line 2 Shift Out Line 1 Scan Line 3 Shift Out Line 2 Scan Line 1 Shift Out Line 3 Step Step Step Step Step Step - Enable Scan Video Signals - Set GPO mode for SM[3:0] - Set DMA for Line 1 - Scan Once (Line 1) - Set DMA for Line 2 - Scan Once (Line 2) - Disable Step - Set DMA for Line 3 - Scan Once (Line 3) Disable Scan IRQ - Load Delay timer register for scan motor Load Step Timer register for scan motor Set Stepping mode and dir for scan motor Load the initial step pattern Set scan motor mode for SM[3:0] Enable Step Enable Scan IRQ Figure 6-3. Scan Control Timing 6-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 6.5 Address: Fax Timing Registers Bit 15 (Not Used) Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst Value xxh Read Value 00h Default: Rst Value 00h Read Value 00h 125 uS Prescaler (125usPrescaler) 01FF8881 Address: 125 uS Prescaler (125usPrescaler) 01FF8880 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n (8 bits) as applied in the equation: (n+1)*(ICLK period *8) Address: ICLK(AUXCLK) Period (ICLKPeriod) 01FF8883 Address: ICLK(AUXCLK) Period (ICLKPeriod) 01FF8882 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 Bit 9 Bit 8 (Not Used) Default: Rst Value xxh Read Value 00h Default: Rst Value xxxxx111b Read Value 07h (Not Used) (Not Used) Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 (Not Used) Bit 2 IHSCLK Period Bit 1 Bit 0 ICLK (AUXCLK) Period ICLK= SIUCLK/(ICLKPeriod + 1) IHSCLK = MCLK/(IHSCLKPeriod + 1) Address: Mechanical Subsystem (MS) Period (MSINTPeriod) 01FF8885 Address: Mechanical Subsystem (MS) Period (MSINTPeriod) 01FF8884 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst Value xxh Read Value 00h Bit 7 2MSIRQ Select 0=1MSIRQ 1=2MSIRQ Bit 6 (Not Used) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst Value 0x000000b Read Value 0x000000b n (6 bits) as applied in the equation: (n+1)*125 uS Prescaler period) On Reset, the 125usPrescaler, 1-ms Timer, and MSINT counters are disabled. Writing to the MSINTPeriod register enables these timers and counters. In addition, the 125usPrescaler must be set to the appropriate value in order for the WatchDog and timing chains to operate correctly. If a new value is written into the MSINTPeriod register while the MSINT counter is running, the new value is not loaded into the counter until it counts down to 0. 1MS/2MSIRQ is a programmable interrupt source. If the `2MSIRQ Select' bit (bit7) of the MSINTPeriod register is set to 0, the interrupt is generated every 1ms (1.00708ms). If the `2MSIRQ Select' bit (bit7) of the MSINTPeriod register is set to 1, the interrupt is generated every 2ms (2.01416ms). 100723A Conexant 6-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: Interrupt Clear (IntClear) 01FF8887 Address: Interrupt Clear (IntClear) 01FF8886 (W) Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 Bit 9 Bit 8 (Not Used) Default: Rst Value xxh Read Value 00h Default: (Not Used) (Not Used) Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 (Not Used) Bit 2 Bit 1 Bit 0 (Not Used) (Not Used) 1=clear Rst Value 1MS/2MSIRQ xxxxxxx0b Read Value 00h 6-6 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 7. VIDEO/SCANNER CONTROLLER The video/scanner controller consists of three main blocks: * * * Scanner controller Industry standard two-wire serial programming interface Video decoder interface The following diagram shows the block diagram of VSC. MFC2000 Video Decoder chip video LED (s) sensor Two-wire Serial Interface Video Decoder Interface Video/Scan Controller Registers system interface Scanner Controller LEDCtrl sensorCtrl SIACtrl msint counter & irq generator msintcy vsc_irq vsc_adc_start vsc_adc_stop vsc_adc_drdy vsc_adc_dclk vsc_adc_data[7:0] data and clock mux scanin Scan Analog Frontend clamp PGA PADC Figure 7-1. Video/Scanner Controller Block Diagram 100723A Conexant 7-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 7.1 Scanner Controller The function of scanner controller can be divided into three areas: 1. Scanner sensor controller 2. Scanner light controller 3. Scan integrated analog controller Pins related to scanner and external ADC # Scanner related SC_START[0] SC_LEDCTRL[0] SC_LEDCTRL[1]/SC_START[1] SC_LEDCTRL[2]/SC_START[2] SC_CLK1/SC_CLK2A GPIO[0]/EXT_CLAMP GPIO[8]/SC_CLK1/SC_CLK2B GPIO[15]/SC_CLK1/SC_CLK2C GPIO[22]/EADC_SAMPLE/SC_CLK2D EV_VD[5]/ScanIAConfig[5] as GPO EV_VD[4]/ScanIAConfig[4] as GPO EV_VD[3]/SAMPLE/CLK2D EV_VD[2]/CLK1/CLK2C EV_VD[1]/CLK1/CLK2B EV_VD[0]/CLAMP # Ext ADC related 12-bit ADC clk clock data[0] data[1] data[2] data[3] data[11:4] MFC2000 GPIO[22]/ EADC_Sample PM[0]/GPO[0]/SPI_SID/ PM[1]/GPO[1]/SPI_SIC/ GPIO[9]/ EADC_D[2] GPIO[6]/ EADC_D[3] EV_VD[7:0]/ EADC_D[11:4] EADC_D[0] EADC_D[1] data[11:0] # Related GPIO Configuration: Configuration EXT_CLAMP on GPIO[0] SC_CLK1/2B on GPIO[8] SC_CLK1/2C on GPIO[15] EADC_SAMPLE/SC_CLK2D on GPIO[22] Bit on GPIOConfig2 ($01FF8832) set bit 4 set bit 2 set bit 3 set bit 6 7-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 7.1.1 * * * * * * Function Description Features for scanner controller: supports wide variety of CIS and linear CCD scanners (color or monochrome) 13 supports up to 8192 (= 2 ) pixels/line programmable pulse width modulation for light control (up to 3 LEDs) programmable clamping signal (mode, delay, width, length) programmable sampling location (mode, location) supports external 12-bit ADC with programmable latency and programmable data transfer position MFC2000 sc_led0 sc_st0 sc_led0st1 sc_led2st2 sc_clk12a sc_clk12b sc_clk12c LEDCtrl[0] start[0] Pin function Alias scctrl[0] scctrl[1] scctrl[2] scctrl[3] scctrl[4] scctrl[5] scctrl[6] LEDCtrl[1]/start[1] LEDCtrl[2]/start[2] clk1/clk2a clk1/clk2b clk1/clk2c A brief description of signal functionality: start clk1 clk2 LEDCtrl Sensor control signal which is only active at the beginning of a scan cycle in order to initiate the transfer of sensor data Sensor control signal which toggles at pixel boundary; thus the frequency of this signal is half of pixel frequency Sensor control signal whose rising and falling edges are programmable within a pixel period; thus the frequency of this signal is the same as the pixel frequency Light control signal which can either be the envelope or the modulation signal. The rising and falling edge of the envelope and the duty cycle of the modulation are programmable. 7.1.2 Register Description Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 LEDCtrl[2] enable Bit 12 LEDCtrl[1] enable Bit 11 LEDCtrl[0] enable Bit 10 start[2] enable Bit 9 start[1] enable Bit 8 start[0] enable Default Rst. Value xx000000b Read Value 00h Default Rst. Value xxxxxxx0b Read Value 00h Name/Address Scan Control (ScanCtrl) $01FF8541 Name/Address Scan Control (ScanCtrl) $01FF8540 Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 (Not Used) Bit 2 (Not Used) Bit 1 (Not Used) Bit 0 Scan Once Bit 13-11 LEDCtrl[2:0] enable Bit 10-8 Bit 0 start[2:0] enable ScanOnce This bit will be synchronized with "cycle_start", and it is not auto cleared. This bit will be synchronized with "cycle_start", and it is not auto cleared. Writing 1 to this bit will initiate an image line scanning operation. This bit will be cleared automatically once the operation has been completed. 100723A Conexant 7-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Name/Address Scan Control Status (ScanCtrlStat) $01FF8543 Name/Address Scan Control Status (ScanCtrlStat) $01FF8542 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default LEDCtrl[2] LEDCtrl[1] LEDCtrl[0] start[2] start[1] start[0] Rst. Value enable enable enable enable enable enable xx000000b (Read only) (Read only) (Read only) (Read only) (Read only) (Read only) Read Value 00h Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 (Not Used) Bit 2 (Not Used) Bit 1 (Not Used) Bit 0 Default Bit 7 (Not Used) Bit 6 (Not Used) Scan Once Rst. Value (Read only) xxxxxxx0b Read Value 00h This register is read only. The value written in ScanCtrl register will be transferred to this register at the beginning of scan cycle. Name/Address VSC IRQ Status (VSCIRQStatus) $01FF8545 Name/Address VSC IRQ Status (VSCIRQStatus) $01FF8544 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Rst. Value xxh Read Value 00h Default Rst. Value xxxxxx00b Read Value 00h Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 (Not Used) Bit 2 (Not Used) Bit 1 SPI IRQ Bit 0 MSINT IRQ Bit 1 SPI IRQ This is the interrupt status which comes from SPI block. The enable for this interrupt can be found in SPI_Config register. Writing 1 to the status bit will clear the interrupt. Bit 0 MSINT IRQ The scanenable must be set in order to have this interrupt active. The timing of this interrupt is programmable within a scan cycle. Writing 1 to the status bit will clear the interrupt. Name/Address VSC Control (VSCCtrl) $01FF8547 Name/Address VSC Control (VSCCtrl) $01FF8546 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default Rst. Value xxh Read Value 00h Shift Enable[7:0] Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 (Not Used) bus Bit 2 VSC on EV Bit 1 ihsclk period Bit 0 VSC Mode Default Rst. Value xxxxxxx0b Read Value 01h 7-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Bit 15-8 Shift Enable[7:0] These bits are used to shift scanner controller signals by 1/2 ihsclk. By default, all scanner controller signals are synchronized to the rising edge of ihsclk. By setting this bit, the corresponding scanner controller signal will be shifted by 1/2 ihsclk, i.e., it will be synchronized to the falling edge of ihsclk. ShiftEnb[7]: to shift `sample' signal ShiftEnb[6:1]: to shift `scctrl[6:1]' signals ShiftEnb[0]: to shift `clamp' signal Bit 2 VSC on EV bus When this bit is set, the "EV_VD[5:0]" bus will be turned into output with the following signals on the bus: Output signals ScanIAConfig[5] as GPO ScanIAConfig[4] as GPO sample/clk2d clk1/clk2c clk1/clk2b clamp EV_VD[5:0] 5 4 3 2 1 0 Bit 1 ihsclk period 0: ihsclk period = sysclk period 1: ihsclk period = sysclk period/2) This bit determines the period of ihsclk (the primary clock of VSC). Bit 0 VSC Mode 0: scanner 1: video This mode will determine the source of data. Name/Address Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default Rst. Value xxx11111h Read Value 1Fh Scan Cycle (ScanCycle) $01FF8891 MSINT IRQ location Name/Address Bit 7 (Not Used) Scan Cycle (ScanCycle) $01FF8890 Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Rst. Value xxx00000b Read Value 00h Scan Cycle (n) MSINTs per Scan Cycle = (n+1) Bits 12-8 MSINT IRQ location The value written here is double-bufferred. At the beginning of a scan cycle, the value will be transferred into another buffer which is compared to a scan cycle counter. If the value in the buffer matches the value in the counter, then an interrupt will be generated (if it is enabled) at the beginning of the count. (n, n = 0-31; MSINTs per scan cycle = n+1) The value written here is double-buffered. At the beginning of a scan cycle, the value will be transferred into another buffer. Bits 4-0 Scan Cycle 100723A Conexant 7-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Notes 1. Bits [4:0] of this register specify the number of MSINTs (1-32) per Scan Cycle. Total Scan Cycle Period = [MSINT period * (ScanCycle register value + 1)]. 2. The transition from maximum count to 0 determines the start of a scan cycle. 3. Reading bits [4:0] of this register returns the current scan cycle MSINT count. 4. This register must be set up prior to enabling the scan (i.e., setting the "scanenable" bit in ScanConfig register). Name/Address Bit 15 MSINT IRQ Enable Bit 14 scctrl[6] invert Bit 13 scctrl[5] invert Bit 12 scctrl[4] invert Bit 11 scctrl[3] invert Bit 10 scctrl[2] invert Bit 9 scctrl[1] invert Bit 8 scctrl[0] invert Default Rst. Value 00h Read Value 00h Default Rst. Value xx000000b Read Value 00h Scan Configuration (ScanConfig) $01FF8893 Name/Address Bit 7 (Not Used) Scan Configuration (ScanConfig) $01FF8892 Bit 6 External ADC Enable Bit 5 scctrl[6] select 0: clk1 1: clk2c Bit 4 scctrl[5] select 0: clk1 1: clk2b Bit 3 scctrl[4] select 0: clk1 1: clk2a Bit 2 scctrl[3] select 0: led2 1: start Bit 1 scctrl[2] select 0: led1 1: start Bit 0 Scan Enable Bit 15 MSINT IRQ Enable When this bit and ScanEnable bit are set, an interrupt will be generated based on the MSINT IRQ location defined in ScanCycle register. These bits are used to invert the polarity of the corresponding control signal. 0 = internal ADC as the source of adc data 1 = external ADC as the source of adc data These bits are used to configure which scanner controller signals should be connected to the pins. This bit must be set in order to activate the scanner controller logic. Bit 14-8 scctrl[6:0] invert Bits 6 External ADC Enable Bit 5-1 scctrl[6:0] select Bit 0 Scan Enable Name/Address Scan Dot Control (ScanDotCtrl) $01FF8895 Name/Address Scan Dot Control (ScanDotCtrl) $01FF8894 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 (Not Used) Bit 10 Bit 9 Bit 8 Default Rst. Value xxh Read Value 00h Default Rst Value 00h Read Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Scan Dot Scaler Value (0-15) n as used in the following equation: (n+1)*IHSCLK Bit 3 Bit 2 Bit 1 Bit 0 Scan Dot Period (1-15) n as used in the following equation: (n+1)*ScanDotScaler Bits 7-4 Bits 3-0 ScanDotScaler ScanDotPeriod (n: 0-15), (n+1) * IHSCLK period (n: 1-15), (n+1) * ScanDotScaler Note: ScanDotPeriod = 0 is not allowed. 7-6 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Name/Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default Rst. Value xxx00000b Read Value 00h Scan Length (ScanLength) $01FF8897 Name/Address Scan Length (ScanLength) $01FF8896 (Not Used) (Not Used) (Not Used) ScanLength[12:8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Rst. Value 00h Read Value 00h ScanLength[7:0] Bits 12-0 ScanLength[12:0] This register specifies the number of valid pixels in one scan line. The amount of data stored in a line is ScanLength * 2 bytes. Each pixel is represented by 12-bit data, and it is stored in memory as 2 bytes of data. Note: The internal pixel counter is 14-bit wide. The extra bit is used to match the maximum value of clamp delay and LED edges. It is guaranteed that this counter will not roll-over once it reaches its maximum count. Name/Address Scan Start Delay (ScanStartDelay) $01FF8899 Name/Address Scan Start Delay (ScanStartDelay) $01FF8898 Bit 15 Bit 14 Bit 13 (Not Used) (Not Used) (Not Used) Bit 12 Bit 11 Bit 10 Delay [12:8] Bit 9 Bit 8 Default Rst Value xxx00000b Read Value 00h Default Rst Value 00h Read Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Delay [7:0] Bit 2 Bit 1 Bit 0 Bits 12-0 Delay[12:0] 1.) The ScanStartDelay register control the number of scan dots (pixels) that are to be skipped before valid scanner data is available. For example, if ScanStartDelay = 1, the first valid scanner pixel is dot number 2, the second dot after the beginning of the START pulse. 2.) ScanStart Delay Time = (Delay[12:0] +1) * (ScanDotPeriod). Name/Address Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Start Edges (StartEdges) $01FF889B Name/Address Start Edges (StartEdges) $01FF889A Rst Value xxh Read Value 00h Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 StartNeg Value (0-15) Start trailing edge position = (StartNeg+1)*(ScanDotScalerPeriod) StartPos Value (0-15) Start leading edge position = (StartPos+1)*(ScanDotScalerPeriod) Rst Value 00h Read Value 00h 100723A Conexant 7-7 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Bits 7-4 Bits 3-0 StartNeg (0-15) StartPos (0-15) StartNeg establishes the location of the START signal trailing edge. StartNeg establishes the location of the START signal leading edge. Name/Address Bit 15 Guardband Enable for scctrl[6] Bit 7 Bit 14 Guardband Enable for scctrl[5] Bit 6 Bit 13 Guardband Enable for scctrl[4] Bit 5 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default Rst. Value 00h Read Value 00h Start Config (StartConfig) $01FF889D Name/Address Guardband[4:0] (in terms of pixel period) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Rst. Value xxxxxxx0b Read Value 00h Start Config (StartConfig) $01FF889C Offset[3:0] (in terms of pixel period) Length[3:0] (in terms of pixel period) Bit 15-13 Guardband Enable for scctrl[6:4] When a guardband is enabled, then the corresponding control signal will not change (will be "frozen") for the duration specified by "guardband" in bit 12-8. Bit 12-8 Guardband[4:0] Some scanner requires a quiet period while start pulse is active. Within this quiet period, only the start pulse will be toggling while other control signals are prevented from toggling. The duration of this period is determined by guardband * pixelperiod. The start pulse can be moved with respect to the start of scan cycle by this offset value which is expressed in terms of pixel period. The duration of the start pulse is programmable according to this "Length" value. Start pulse duration is [length + 1] * pixel_period Bit 7-4 Bit 3-0 Offset[3:0] Length[3:0] Name/Address Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Clk2a Edges (Clk2aEdges) $01FF889F Name/Address Clk2a Edges (Clk2aEdges) $01FF889E Rst Value xxh Read Value 00h Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Clk2aNeg Value (0-15) Clk2aPos Value (0-15) Rst Value 00h Read Value 00h Bits 7-4 Clk2aNeg Clk2aNeg establishes the trailing edge of the Clk2a signal relative to the start of each dot period, and is specified in ScanDotScaler Clock periods. Clk2aPos establishes the leading edge of the Clk2a signal relative to the start of each dot period, and is specified in ScanDotScaler Clock periods. Bits 3-0 Clk2aPos 7-8 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Name/Address Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Clk2b Edges (Clk2bEdges) $01FF88A1 Name/Address Clk2b Edges (Clk2bEdges) $01FF88A0 Rst Value xxh Read Value 00h Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Clk2bNeg Value (0-15) Clk2bPos Value (0-15) Rst Value 00h Read Value 00h Bits 7-4 Clk2bNeg Clk2bNeg establishes the trailing edge of the Clk2b signal relative to the start of each dot period, and is specified in ScanDotScaler Clock periods. Clk2bPos establishes the leading edge of the Clk2b signal relative to the start of each dot period, and is specified in ScanDotScaler Clock periods. Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Bits 3-0 Clk2bPos Name/Address Bit 15 (Not Used) Clk2c Edges (Clk2cEdges) $01FF88A3 Name/Address Clk2c Edges (Clk2cEdges) $01FF88A2 Rst Value xxh Read Value 00h Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Clk2cNeg Value (0-15) Clk2cPos Value (0-15) Rst Value 00h Read Value 00h Bits 7-4 Clk2cNeg Clk2cNeg establishes the trailing edge of the Clk2c signal relative to the start of each dot period, and is specified in ScanDotScaler Clock periods. Clk2cPos establishes the leading edge of the Clk2c signal relative to the start of each dot period, and is specified in ScanDotScaler Clock periods. Bits 3-0 Clk2cPos Name/Address Bit 15 Mode Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 Default ADCSample Configuration (ADCSampleCfg) (Not Used) Rst Value $01FF88A5 Name/Address ADC Sample Configuration (ADCSampleCfg) 00xxxxxxb Read Value 00h Bit 7 Bit 6 Bit 5 SampleNeg Value (0-15) Bit 4 Bit 3 Bit 2 Bit 1 SamplePos Value (0-15) Bit 0 Default $01FF88A4 Rst Value 00h Read Value 00h 100723A Conexant 7-9 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Bits 15 Mode This mode will only affect the number of sample pulses and not the number of sampled data to be stored into memory. 0 = sampling continuously as long as ScanEnable = 1 1 = sampling valid pixels only Bits 7-4 SampleNeg SampleNeg establishes the trailing edge of the Sample signal relative to the start of each dot period, and is specified in ScanDotScaler clock periods. SamplePos establishes the leading edge of the Sample signal relative to the start of each dot period, and is specified in ScanDotScaler clock periods. Bit 14 Internal Clamp Enable Bit 13 External Clamp Enable Bit 12 External Clamp Guardband Enable Bit 11 External Clamp Invert Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Bits 3-0 SamplePos Name/Address Bit 15 Clamp Mode Clamp Control (ClampCtrl) $01FF88A7 Name/Address Rst Value 0xxxxxxxb Read Value 00h Bit 7 (Not Used) Bit 6 Bit 5 Bit 4 Bit 3 ClampLengh[6:0] Bit 2 Bit 1 Bit 0 Default Clamp Control (ClampCtrl) $01FF88A6 Rst Value x0000000b Read Value 00h Bit 15 ClampMode (1 = line-based, 0 = pixel-based) Setting the ClampMode bit causes line-based clamping to be used. Clearing this bit causes pixel-based clamping to be used. For line-based clamping, the clamp signal is enabled for the number of dots specified in ClampLength register, and can occur either before or after the valid pixel data, as selected by the ClampDelay register. For pixel-based clamping, the clamp signal runs continuously throughout the entire scanline. Bits 6-0 ClampLength[6:0] This value specifies the number of pixels to be used for line-based clamping. Note: Both internal and external clamp share the same control signals for `shift' and `delay'. Name/Address Bit 15 Clamp Delay Clamp (ClampDelay) Position $01FF88A9 Name/Address Clamp Delay (ClampDelay) $01FF88A8 Bit 7 Bit 14 (Not Used) Bit 13 Bit 12 Bit 11 Bit 10 Clamp Delay[13:8] Bit 9 Bit 8 Default Rst Value 0x000000b Read Value 00h Default Rst Value 00h Read Value 00h Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Clamp Delay [7:0] 7-10 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Bit 15 Clamp Position (only valid for line-based clamping) Setting the ClampPosition bit causes the ClampDelay value to be applied from the start of the scanline (i.e., during the ScanStartDelay time). Clearing this bit causes the ClampDelay value to be applied from the first valid pixel of the scanline (i.e., after the ScanStartDelay has been accounted for). Bits 13-0 Clamp Delay[13:0] (only valid for line-based clamping) The ClampDelay register control the number of scan dots (pixels) that are to be skipped before enabling the clamp signal for the number of pixels specified in ClampLength register. Note: If ClampPosition bit = 0 and a new scanline is started before the ClampDelay value has been satisfied, the clamp signal will not activate. The same is true if ClampPosition bit = 1 and the ScanStartDelay value is less than the ClampDelay value. Name/Address Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 Default Clamp Edges (ClampEdges) $01FF88AB Name/Address Clamp Edges (ClampEdges) $01FF88AA (Not Used) Rst Value xxh Read Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default ClampNeg Value (0-15) ClampPos Value (0-15) Rst Value 00h Read Value 00h Bits 7-4 ClampNeg ClampNeg establishes the trailing edge of the Clamp signal relative to the start of each dot period, and is specified in ScanDotScaler clock periods. ClampPos establishes the leading edge of the Clamp signal relative to the start of each dot period, and is specified in ScanDotScaler clock periods. Bits 3-0 ClampPos 100723A Conexant 7-11 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Name/Address Clk2d Control (Clk2dCtrl) $01FF88C5 Name/Address Clk2d Control (Clk2dCtrl) $01FF88C4 Bit 15 Select Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 Shift Bit 11 Delay[1] Bit 10 Delay[0] Bit 9 Invert Bit 8 Enable Default xxx00000b Read Value 00h Guardband Rst. Value Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Rst. Value x0h Read Value 00h Negedge[3:0] PosEdge[3:0] Bit 15 Bit 12 Select Shift 0 = selecting sample signal 1 = clk2d 0 = clk2d synchronous to the rising edge of ihsclk 1 = to the falling edge of ihsclk programmable delay amount 0 = no delay 1 = 1 unit delay 2 = 2 unit delay 3 = 3 unit delay 0 = normal 1 = invert) 0 = no guardband 1 = apply guardband Bit 11-10 Delay Bit 9 Bit 8 Bit 7-4 Bit 3-0 Invert Guardband Enable NegEdge position PosEdge position Name/Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default Rst. Value 00h Read Value 00h LEDCtrl[0] Edges (LED0Edges) 01FF88AD Bit 7 NegEdge[7:0] Trailing edge position = (NegEdge[7:0] * 64) pixels before/after scan start delay Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Rst. Value 00h Read Value 00h LEDCtrl[0] Edges (LED0Edges) 01FF88AC PosEdge[7:0] Leading edge position = (PosEdge[7:0] * 64) pixels before/after scan start delay Bits 15-8 NegEdge[7:0] Bits 7-0 PosEdge[7:0] NegEdge establishes the trailing edge of the envelope for LEDCtrl signal and is specified in 64 pixel clock periods. PosEdge establishes the leading edge of the envelope for LEDCtrl signal and is specified in 64 pixel clock periods. 7-12 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Name/Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default Rst. Value 00h Read Value 00h LEDCtrl[1] Edges (LED1Edges) 01FF88AF Bit 7 NegEdge[7:0] Trailing edge position = (NegEdge[7:0] * 64) pixels before/after scan start delay Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Rst. Value 00h Read Value 00h LEDCtrl[1] Edges (LED1Edges) 01FF88AE PosEdge[7:0] Leading edge position = (PosEdge[7:0] * 64) pixels before/after scan start delay Bits 15-8 NegEdge[7:0] Bits 7-0 PosEdge[7:0] NegEdge establishes the trailing edge of the envelope for LEDCtrl signal and is specified in 64 pixel clock periods. PosEdge establishes the leading edge of the envelope for LEDCtrl signal and is specified in 64 pixel clock periods. Name/Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default Rst. Value 00h Read Value 00h LEDCtrl[2] Edges (LED2Edges) 01FF88B1 Bit 7 NegEdge[7:0] Trailing edge position = (NegEdge[7:0] * 64) pixels before/after scan start delay Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Rst. Value 00h Read Value 00h LEDCtrl[2] Edges (LED2Edges) 01FF88B0 PosEdge[7:0] Leading edge position = (PosEdge[7:0] * 64) pixels before/after scan start delay Bits 15-8 NegEdge[7:0] Bits 7-0 PosEdge[7:0] NegEdge establishes the trailing edge of the envelope for LEDCtrl signal and is specified in 64 pixel clock periods. PosEdge establishes the leading edge of the envelope for LEDCtrl signal and is specified in 64 pixel clock periods. Name/Address Bit 15 Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 Bit 9 clock divider[2:0] Bit 8 Default Rst. Value xxxxx000b Read Value 00h LED0 PWM Config (Not Used) (LED0PWM) $01FF88B3 Name/Address LED0 PWM Config (LED0PWM) $01FF88B2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Rst. Value 00h Read Value 00h duty cycle[7:0] 100723A Conexant 7-13 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Bits 10-8 clock divider[2:0] Bits 7-0 duty cycle[7:0] The clock used for PWM is scaled according to "clock divider" setting. The period of PWM is divided into 256. The high time of PWM is determined by "duty cycle". Min frequency (clk_div = 7) ihsclk = 50 ns pwm clk = T(ihsclk ) * (clk_div + 1) = 50 ns * (7 + 1) = 400 ns pwm period = 400 ns * 256 = 102,400 ns = 102.4 us (9.8 KHz) Max frequency (clk_div = 0) ihsclk = 50 ns pwm clk = ihsclk = 50 ns pwm period = 50 ns * 256 = 12.8 us (78.1 KHz) Note: In order to have a non-modulated signal, the duty cycle must be set to 0xFF. Name/Address Bit 15 Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 Bit 9 clock divider[2:0] Bit 8 Default Rst. Value xxxxx000b Read Value 00h LED1 PWM Config (Not Used) (LED1PWM) $01FF88B5 Name/Address LED1 PWM Config (LED1PWM) $01FF88B4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Rst. Value 00h Read Value 00h duty cycle[7:0] Bits 10-8 clock divider[2:0] Bits 7-0 duty cycle[7:0] The clock used for PWM is scaled according to "clock divider" setting. The period of PWM is divided into 256. The high time of PWM is determined by "duty cycle". Note: In order to have a non-modulated signal, the duty cycle must be set to 0xFF. Name/Address Bit 15 Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 Bit 9 clock divider[2:0] Bit 8 Default Rst. Value xxxxx000b Read Value 00h LED2 PWM Config (Not Used) (LED2PWM) $01FF88B7 Name/Address LED2 PWM Config (LED2PWM) $01FF88B6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Rst. Value 00h Read Value 00h duty cycle[7:0] 7-14 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Bits 10-8 clock divider[2:0] Bits 7-0 duty cycle[7:0] The clock used for PWM is scaled according to "clock divider" setting. The period of PWM is divided into 256. The high time of PWM is determined by "duty cycle". Note: In order to have a non-modulated signal, the duty cycle must be set to 0xFF. Name/Address LEDCtrl Config (LEDConfig) $01FF88B9 Name/Address LEDCtrl Config (LEDConfig) $01FF88B8 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 Default xx000111b Read Value 07h (Not Used) Rst. Value Bit 7 (Not Used) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LEDCtrl[1] position Bit 0 LEDCtrl[0] position Default Rst. Value xx000000b Read Value 00h (Not Used) LEDCtrl[2] LEDCtrl[1] LEDCtrl[0] LEDCtrl[2] sync_select sync_select sync_select position Bits 5-3 LEDCtrl[2:0] sync_select 1 = sync is selected, ignoring LED PWM config & LED Edges settings 0 = normal LEDCtrl When sync_select bit is set and the LED is enabled (by setting the corresponding bit in ScanCtrl register), then the LEDCtrl will be active from the beginning of scancycle until the end of scancycle. In this mode of operation, the corresponding LED PWM & LED Edges settings are ignored. Once the LED is disabled, then at the end of scancycle, the LEDCtrl will not be active anymore. In other words, by setting sync_select bit, the LEDCtrl is outputing the LED enabled which is synchronized with the cyclestart. When sync_select bit is clear and the LED is enabled, then the LEDCtrl operates in normal mode, which depends on the LED PWM & LED Edges settings. Bits 2-0 LEDCtrl[2:0] position 1 = before ScanStartDelay 0 = after ScanStartDelay This position setting only affects the leading edge of LEDCtrl envelope. If the place bit is reset, then the LEDCtrl will be activated after valid pixel. Otherwise, if the place bit is set, then LEDCtrl can be activated right after scancycle. Name/Address Scan IA Config (ScanIAConfig) $01FF88BB Name/Address Scan IA Config (ScanIAConfig) $01FF88BA Bit 15 ADC enable Bit 14 (Not Used) Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default xxx00000b Read Value 00h OffsetSel[5] OffsetSel[4] OffsetSel[3] OffsetSel[2] OffsetSel[1] OffsetSel[0] Rst. Value Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 GPO on EV_VD[5] Bit 4 GPO on EV_VD[4] Bit 3 GainSel[3] Bit 2 GainSel[2] Bit 1 GainSel[1] Bit 0 GainSel[0] Default Rst. Value x0h Read Value 00h 100723A Conexant 7-15 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description In order to apply the content of this register to the analog die, the content must be sent serially by writing to the `ADCSerialCmd' register. Please refer to the `ADCSerialCmd' register description for more information. Bit 15 ADC enable This bit is used to enable the internal adc. The ADC circuit by default is disabled. An analog subtracter is used in conjunction with OffsetSel in order to remove the DC offset from scanner signal. When `VSC on EV bus' bit, i.e., bit 2 of VSCCtrl register, is set, then EV_VD[7:0] bus will function as output.. EV_VD[5] output is connected to this bit to function as general purpose output (GPO). When `VSC on EV bus' bit, i.e., bit 2 of VSCCtrl register, is set, then EV_VD[7:0] bus will function as output.. EV_VD[4] output is connected to this bit to function as general purpose output (GPO). GainSel is connected to a programmable gain amplifier to adjust the gain of the scanner signal. Bit 12-8 Bit 5 OffsetSel[4:0] GPO on EV_VD[5] Bit 4 GPO on EV_VD[4] Bit 3-0 GainSel[3:0] Note: This register is double-buffered. The value written into this register will not be applied to SIA immediately. Rather, the value will be applied after the start of scancycle. Reading this register reflects the value applied to SIA. Name/Address ADCSerialCmd (ADCSerialCmd) $01FF854F Bit 15 Send Status (read only) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 Default xxh Read Value 00h (Not Used) Rst. Value Name/Address ADCSerialCmd (ADCSerialCmd) $01FF854E Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 (reserved) `0' Bit 2 Command Type Bit 1 Transmit Mode[1] Bit 0 Transmit Mode[0] Default Rst. Value xxxx0000b Read Value 00h Bit 15 Send Status (read only) This bit indicates one of the following statuses: waiting for an event to occur, as selected by `transmit mode[1:0]', prior to sending the serial command sending serial command is in progress. The wait for the event can be aborted by clearing `scanenable' bit on `ScanConfig' register, and the command will not be sent. Bit 15 Bit 2 reserved Command Type It is important to always write `0' to this bit. Command Type 0 1 Function To send `offset' and `gain' settings as stored in `ScanIAConfig' register To send `ADC enable' bit as stored in `ScanIAConfig' register 7-16 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Bit 1-0 Transmit Mode[1:0] Prior to writing to this register, check the `Send Status' bit, and make sure that this bit is clear. If this bit is set, then writing to this register will be ignored. If this bit is clear, then writing to this register will cause the following action based on the `Transmit Mode': Transmit Mode 0 1 2 3 right away Time to send the serial data at the beginning of a scan cycle; no `scanonce' operation is involved at the end of valid pixel (i.e. the last valid pixel in a line); `scanonce' operation is involved at the next msint Name/Address Scan Control Delay (ScanCtrlDelay) $01FF88BD Name/Address Scan Control Delay (ScanCtrlDelay) $01FF88BC Bit 15 sample delay[1:0] Bit 14 Bit 13 Scctrl[6] Delay[1:0] Bit 12 Bit 11 scctrl[5] delay[1:0] Bit 10 Bit 9 scctrl[4] delay[1:0] Bit 8 Default Rst. Value xx000000b Read Value 00h Bit 7 scctrl[3] delay[1:0] Bit 6 Bit 5 Scctrl[2] Delay[1:0] Bit 4 Bit 3 scctrl[1] delay[1:0] Bit 2 Bit 1 clamp delay[1:0] Bit 0 Default Rst. Value 00h Read Value 00h Bit 15-14 sample delay Bit 13-12 scctrl[6] delay Bit 11-10 scctrl[5] delay Bit 9-8 Bit 7-6 Bit 5-4 Bit 3-2 Bit 1-0 scctrl[4] delay scctrl[3] delay scctrl[2] delay scctrl[1] delay clamp delay This setting controls the delay for `sample' signal. This setting controls the delay for `scctrl[6]' signal. This setting controls the delay for `scctrl[5]' signal. This setting controls the delay for `scctrl[4]' signal. This setting controls the delay for `scctrl[3]' signal. This setting controls the delay for `scctrl[2]' signal. This setting controls the delay for `scctrl[1]' signal. This setting controls the delay for `clamp' signal. Name/Address ADC Config (ADCConfig) $01FF88BF Name/Address ADC Config (ADCConfig) $01FF88BE Bit 15 Bit 14 Bit 13 AdclkNeg Value (0-15) Bit 12 Bit 11 Bit 10 Bit 9 AdclkPos Value (0-15) Bit 8 Default Rst. Value 00h Read Value 00h Default Rst. Value 00h Read Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Digital Data Capture Position [3:0] (0-15) Bit 3 Bit 2 Bit 1 Data Latency[3:0] (0-15) Bit 0 100723A Conexant 7-17 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Bit 15-12 AdclkNeg (only valid when internal ADC is selected) AdclkNeg establishes the trailing edge of the adclk signal relative to the start of each dot period, and is specified in terms of ScanDotScaler clock periods. Bit 11-8 AdclkPos (only valid when internal ADC is selected) AdclkPos establishes the leading edge of the adclk signal relative to the start of each dot period, and is specified in terms of ScanDotScaler clock periods. Bit 7-4 Digital Data Capture Position (valid for external ADC only) This setting indicates where the digital data from ADC should be captured within a pixel period, and is specified in terms of ScanDotScaler clock periods. Bit 3-0 Data Latency (valid with either internal or external ADC) This setting indicates the latency or pipeline delay as required by ADC, and is expressed in the number of pixel clocks. Important note on how to program adclk & adsample when an internal ADC is selected: 1. The location and the width of adsample must be established first according to the scanner requirement (the analog signal is being sampled while adsample = 1, and at the falling edge of adsample, the signal is stored into an internal capacitor. While adsample = 0, the signal value is being held in the capacitor.) 2. Once adsample has been programmed properly, the adclk must be configured according to the following rule: a) adclk must be low while adsample is high 7-18 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 7.1.3 Timing msintcy scanenb current cycle cycle_start indicates the beginning of a scan cycle write '1' to EnableScan bit in ScanConfig1 register 0 1 scancycle = 3 2 3 0 start[0] enb (write to ScanCtrl reg) write '1' to Start[0]enable bit in ScanCtrl register synchonized to cycle_start startnegedge startlength clampposedge clampnegedge ClampDelay ClampLength clampposedge clampnegedge ClampLength clampposedge clampnegedge start[0] enb_status (read from ScanCtrl Status reg) startposedge start[0] startoffset clamp mode = 1 place = 1 mode = 1 place = 0 mode = 0 place = x clamp ScanStartDelay ClampDelay clamp a d s a m p l e mode = 0 ScanStartDelay ScanLength pixels sampleposedge samplenegedge sampleposedge samplenegedge a d s a m p l e mode = 1 clk1 clk2aposedge clk2anegedge clk2a Figure 7-2. Untitled Timing Diagram 100723A Conexant 7-19 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description firmware change the number of msint in a scancycle setup.scancycles scancycles_sync sccyc_nxt sccyc_ctr sccyc_count one msint period 4 4 1 1 3 3 2 2 3 3 4 4 0 0 sccyc_reset firmware change the location of msint irq setup.msintirqloc msintirqloc_sync scanirq_set scanirq_cur set by hardware (assuming scanirqenb = '1') clear by firmware (writing to bit 0 of VSCIRQStatus register) 3 3 2 2 Figure 7-3. Untitled Timing Diagram msintcy F/W writes to ScanCycle register Scan Cycle (1 st buffer) 3 2 H/W synchonizes the 1st and 2 nd buffer at the beginning of a scan cycle Scan Cycle (2 nd buffer) cycle_start Scan Cycle (counter) 3 The beginning of a scan cycle 2 2 3 0 1 2 0 1 Figure 7-4. Untitled Timing Diagram 7-20 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 ihsclk 50 ns dotscaler_ctr 0 1 0 1 0 1 0 1 0 1 0 1 scan dot scaler =1 dotperiod_ctr 2 0 1 scan dot period = 2 2 0 1 pixaddr_ctr 99 100 one pixel 101 clk1 toggling every pixel clk2a clk2apos = 1 clk2aneg = 2 Figure 7-5. Untitled Timing Diagram Note: The rising and falling edges timing of clk2a also applies to clk2b, clk2c, start, clamp, and adsample. 100723A Conexant 7-21 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description cycle_start write '1' write '0' LEDCtrl[0]enb (write to ScanCtrl reg) synchronized to cycle_start LEDCtrl[0]enb_status (read from ScanCtrl Status reg) LED0PWMClkDiv[2:0] LED0PWMDutyCycle[7:0] LEDCtrl[0] (place = 0) ScanStartDelay write '1' LED0PosEdge LED0NegEdge write '0' LEDCtrl[1]enb (write to ScanCtrl reg) synchronized to cycle_start LEDCtrl[1]enb_status (read from ScanCtrl Status reg) LED1PWMClkDiv[2:0] LED1PWMDutyCycle[7:0] LEDCtrl[1] (place = 0) ScanStartDelay write '1' LED1PosEdge LED1NegEdge write '0' LEDCtrl[2]enb (write to ScanCtrl reg) synchronized to cycle_start LEDCtrl[2]enb_status (read from ScanCtrl Status reg) LED2PWMClkDiv[2:0] LED2PWMDutyCycle[7:0] LEDCtrl[2] (place = 0) ScanStartDelay LED2NegEdge LED2PosEdge vsc_irq time write to vsc_irq clear register write ScanCtrl[13:11] with 001b vsc_irq comes write to vsc_irq clear register write ScanCtrl[13:11] with 010b vsc_irq comes write to vsc_irq clear register write ScanCtrl[13:11] with 100b vsc_irq comes [led-time.vsd] Figure 7-6. Untitled Timing Diagram 7-22 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 ScanCycle[4:0] = 4 (determines the time for scanning a line) msint scCycCur[4:0] start 0 0 2 3 4 0 pixeladr[13:0] HiZ 0 1 3 0 1 2047 2048 2049 4048 xxxx 0 ScanStartDelay[13:0] (in pixel unit) ScanLength[12:0] (Number of valid pixels) LED0Pos[7:0] * 64 LED0Neg[7:0] * 64 LEDCtrl[0] t=0 LED0pad_en = 0 LED0Pos[7:0] * 64 LED0Neg[7:0] * 64 LED on-time (no pwm) LED0pad_en = 1 (default value from reset) Figure 7-7. Untitled Timing Diagram Notes: 1. MSInt_period = (msintPeriod + 1) * 125 us msintPeriod[5:0] is set in MSINTPeriod register (assuming that value in 125usPrescaler register has been adjusted to obtain 125 us period) 2. ScanCycle_period = (ScanCycle + 1) * MSInt_period 3. ScanCycle in conjunction with MSIntPeriod must be selected so that: ihsclk pwmclk clk_div = 1 programmable pwmpr_ctr pwm duty_cycle = 253 * pwmclk_period 255 0 1 253 254 255 0 programmable fixed period = 256 * pwmclk_period Figure 7-8. Untitled Timing Diagram 100723A Conexant 7-23 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description msintcy MSINT IRQ loc current cycle scan_irq generated here because MSINT IRQ location = 3 & current cycle = 3 cleared by writing '1' to bit 0 of VSCIRQStatus register 3 3 0 1 ScanCycle = 3 2 3 0 Figure 7-9. Untitled Timing Diagram The scanner controller will issue adc_start, adc_drdy, and adc_stop as follows: 1 adc_dclk wide adc_start adc_drdy 1 adc_dclk wide adc_stop 1 adc_dclk or more Figure 7-10. Untitled Timing Diagram External ADC timing summary National: ADC 12662 Vin S/H min = 5 ns max = 400 ns Data[11:0] t conv = 510 - 660 ns pipeline delay (latency) = 1 cycles [adc-national-adc12662.vsd] Figure 7-11. Untitled Timing Diagram 7-24 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Analog: AD 9220 S1 S2 S4 S3 min = 45 ns hold sample Vin min = 45 ns CLK min = 100 ns Data[11:0] 8 ns pipeline delay (latency) = 3 clk cycles Data 1 Figure 7-12. Untitled Timing Diagram Linear: LTC 1412 Vin CONVST min = 20 ns Data[11:0] t conv = 240-283 ns pipeline delay (latency) = 1 cycles Figure 7-13. Untitled Timing Diagram 7.1.4 Firmware Operation In order to obtain the optimal digital data, the dynamic range of analog signal must be maximized. In order to maximize the dynamic range of scanner signal, the duration of the light exposure on the sensor must be just right. If it is too short, then the signal will be too low; and if it is too long, then the signal will be saturated. The amount of light exposure can be controlled by having programmable pulse width modulation on the LED control. Typically, the signal from the sensor has a dc offset. This offset must be removed, and the resulting signal can be amplified to restore the dynamic range. Examples of how to setup the registers for various scanners are shown below. These setups are configured for the fastest scanning operation. (only setup, not operation registers are shown) Notes: 1.) The value for scan cycle depends on how msint signal is configured. 2.) The LED setting may need adjustment according to the proper light intensity for different color. 100723A Conexant 7-25 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Manufacturer Part # Type Resolution Pixels/line Scan time (color) Scan time (B/W) Data Rate Main clock `H' duty ROHM IA3008 - ZE22 CIS 300 dpi 2560 9 ms/line 1.8~4.5 ms/line 1.5 MHz (max) 25 - 50 % Interface: Scanner RGND GGND BGND SI CLK Ao Description Red LED control Green LED control Blue LED control Start pulse Main clock Scanner signal MFC2000 LEDCtrl[0] LEDCtrl[1] LEDCtrl[2] start[0] clk2a vin Timing: 50 ns ihsclk dotscaler_ctr dotperiod_ctr clk2a start[0] PixelTime = 700 ns 13 0 1 2 3 4 5 0 6 7 8 9 10 11 12 13 0 LineTime = 3 ms start[0] scanin no delay envelope of analog signal SigTime = 1.792 m s ExpTime =1.12 ms LEDCtrl[0] can be modulated 0 2560 2624 4224 pixel counter 4285 [Rohm-IA3008-ZE22.vsd] Figure 7-14. Untitled Timing Diagram 7-26 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 7-1. Register setup for Rohm-IA3008-ZE22 Register Name ScanConfig ScanDotControl StartConfig Bits Name scctrl[6:0] invert scctrl[6:2] select Scan Dot Scaler[3:0] Scan Dot Period[3:0] GuardbandEnb[6:4] Guardband[4:0] Offset[3:0] Length[3:0] StartEdges ScanStartDelay Clk2aEdges StartPos[3:0] StartNeg[3:0] Delay[12:0] Clk2aPos[3:0] Clk2aNeg[3:0] Clk2bEdges Clk2cEdges ADCSampleCfg ADCConfig Clk2bPos[3:0] Clk2bNeg[3:0] Clk2cPos[3:0] Clk2cNeg[3:0] SamplePos[3:0] SampleNeg[3:0] AdclkPos[3:0] AdclkNeg[3:0] DataPlace[3:0] DataLatency[3:0] ClampCtrl ClampMode ClampEnb ClampLength[6:0] ClampDelay ClampEdges LEDConfig LED0Edges LED1Edges ClampPosition ClampDelay[13:0] ClampPos[3:0] ClampNeg[3:0] LEDCtrl sync_sel[2:0] LEDCtrl place[2:0] LED0Pos[7:0] LED0Neg[7:0] LED1Pos[7:0] LED1Neg[7:0] LED2Edges ScanLength ScanCyles LED2Pos[7:0] LED2Neg[7:0] ScanLength[12:0] ScanCycle[4:0] n/a 0 n/a n/a n/a n/a n/a 0 0 41 66 41 66 41 66 2560 3 ms 0 xx100b 0 13 0 n/a 0 0 0 13 0 7 12 n/a n/a n/a n/a 9 11 0 6 10 Value 100723A Conexant 7-27 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Manufacturer Part # Type Resolution Pixels/line Scan time (color) Scan time (B/W) Data Rate Main clock `H' duty DYNA DL507-07UAH CIS 300 dpi 2552 7.5 ms/line Interface: Scanner LEDR LEDG LEDB SI CLK Description Red LED control Green LED control Blue LED control Start pulse Main clock Scanner signal MFC2000 LEDCtrl[0] LEDCtrl[1] LEDCtrl[2] start[0] clk2a vin 2.0 MHz (typ) 25 % (typ) SIG Timing: 50 ns ihsclk dotscaler_ctr dotperiod_ctr clk2a start[0] PixelTime = 500 ns 9 0 1 2 3 4 5 0 6 7 8 9 0 1 2 3 4 LineTime = 2.5 ms start[0] delay of 2 pixels scanin envelope of analog signal SigTime = 1.276 m s ExpTime =1.12 ms LEDCtrl[0] can be modulated 0 2552 2560 4992 pixel counter 5000 Figure 7-15. Untitled Timing Diagram 7-28 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 7-2. Register setup for Dyna-DL507-07UAH Register Name ScanConfig Bits Name scctrl[6:0] invert scctrl[6:2] select ScanDotControl StartConfig Scan Dot Scaler[3:0] Scan Dot Period[3:0] GuardbandEnb[6:4] Guardband[4:0] Offset[3:0] Length[3:0] StartEdges ScanStartDelay Clk2aEdges Clk2bEdges Clk2cEdges ADCSampleCfg ADCConfig StartPos[3:0] StartNeg[3:0] Delay[12:0] Clk2aPos[3:0] Clk2aNeg[3:0] Clk2bPos[3:0] Clk2bNeg[3:0] Clk2cPos[3:0] Clk2cNeg[3:0] SamplePos[3:0] SampleNeg[3:0] AdclkPos[3:0] AdclkNeg[3:0] DataPlace[3:0] DataLatency[3:0] ClampCtrl ClampMode ClampEnb ClampLength[6:0] ClampDelay ClampEdges LEDConfig ClampPosition ClampDelay[13:0] ClampPos[3:0] ClampNeg[3:0] LEDCtrl sync_sel[2:0] LEDCtrl place[2:0] LED0Edges LED1Edges LED2Edges ScanLength ScanCyles LED0Pos[7:0] LED0Neg[7:0] LED1Pos[7:0] LED1Neg[7:0] LED2Pos[7:0] LED2Neg[7:0] ScanLength[12:0] ScanCycle[4:0] n/a 0 n/a n/a n/a n/a n/a 0 0 40 78 40 78 40 78 2552 2.5 ms 0 xx100b 0 9 0 n/a 0 0 0 9 0 6 8 n/a n/a n/a n/a Value 100723A Conexant 7-29 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Manufacturer Part # Type Resolution Pixels/line Scan time (color) Scan time (B/W) Data Rate Main clock `H' duty Mitsubishi GT3R216 CIS 300 dpi 2552 7.5 ms/line 1.5 ms/line 3 - 4 MHz 20 - 30 % Interface: Scanner LEDr LEDg LEDb SI CLK SIG Description Red LED control Green LED control Blue LED control Start pulse Main clock Scanner signal MFC2000 LEDCtrl[0] LEDCtrl[1] LEDCtrl[2] start[0] clk2a vin Timing: 50 ns ihsclk dotscaler_ctr dotperiod_ctr clk2a start[0] PixelTime = 250 ns 0 4 0 1 2 3 4 0 1 2 3 4 LineTime = 2.5 ms start[0] delay of 1 pixel scanin envelope of analog signal SigTime = 638 s LEDCtrl[0] can be modulated pixel counter 0 2552 2560 9920 Figure 7-16. Untitled Timing Diagram 7-30 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 7-3. Register setup for Mitsubishi-GT3R216 Register Name ScanConfig ScanDotControl StartConfig Bits Name scctrl[6:0] invert scctrl[6:2] select Scan Dot Scaler[3:0] Scan Dot Period[3:0] GuardbandEnb[6:4] Guardband[4:0] Offset[3:0] Length[3:0] StartEdges ScanStartDelay Clk2aEdges StartPos[3:0] StartNeg[3:0] Delay[12:0] Clk2aPos[3:0] Clk2aNeg[3:0] Clk2bEdges Clk2cEdges ADCSampleCfg ADCConfig Clk2bPos[3:0] Clk2bNeg[3:0] Clk2cPos[3:0] Clk2cNeg[3:0] SamplePos[3:0] SampleNeg[3:0] AdclkPos[3:0] AdclkNeg[3:0] DataPlace[3:0] DataLatency[3:0] ClampCtrl ClampMode ClampEnb ClampLength[6:0] ClampDelay ClampEdges LEDConfig LED0Edges LED1Edges ClampPosition ClampDelay[13:0] ClampPos[3:0] ClampNeg[3:0] LEDCtrl sync_sel[2:0] LEDCtrl place[2:0] LED0Pos[7:0] LED0Neg[7:0] LED1Pos[7:0] LED1Neg[7:0] LED2Edges ScanLength ScanCyles LED2Pos[7:0] LED2Neg[7:0] ScanLength[12:0] ScanCycle[4:0] n/a 0 n/a n/a n/a n/a n/a 0 0 40 155 40 155 40 155 2552 2.5 ms 4 4 n/a n/a n/a n/a 0 xx100b 0 4 0 n/a 0 0 0 4 Value 100723A Conexant 7-31 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Manufacturer Part # Type Resolution Pixels/line Scan time (color) Scan time (B/W) Data Rate Main clock `H' duty TOSHIBA CIPS218MC300 CIS pkg w/ CCD 300 dpi 2576 Interface: Scanner *LEDR *LEDG *LEDB *TR *M Description Red LED control Green LED control Blue LED control Start pulse Main clock Clock Clock MFC2000 LEDCtrl[0] LEDCtrl[1] LEDCtrl[2] start[0] clk2a clk2b clk2c 0.1 - 2.5 MHz 50 % *RS *RNC Timing: 50 ns ihsclk dotscaler_ctr dotperiod_ctr clk2a clk2b clk2c PixelTime = 400 ns 7 0 1 2 3 4 5 0 6 7 0 1 2 3 4 5 6 clk2a 50 ns 50 ns 4 clocks (min) start[0] LineTime =2 ms start[0] 17 dummy pixels scanin envelope of analog signal SigTime = 1.0304 m s ExpTime = 1.48 ms LEDCtrl[0] can be modulated 0 2576 4992 pixel counter 5000 Figure 7-17. Untitled Timing Diagram 7-32 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 7-4. Register Setup for Toshiba-CIPS218MC300 Register Name ScanConfig ScanDotControl Bits Name scctrl[6:0] invert scctrl[6:2] select Scan Dot Scaler[3:0] Scan Dot Period[3:0] StartConfig GuardbandEnb[6:4] Guardband[4:0] Offset[3:0] Length[3:0] StartEdges ScanStartDelay Clk2aEdges Clk2bEdges Clk2cEdges ADCSampleCfg ADCConfig StartPos[3:0] StartNeg[3:0] Delay[12:0] Clk2aPos[3:0] Clk2aNeg[3:0] Clk2bPos[3:0] Clk2bNeg[3:0] Clk2cPos[3:0] Clk2cNeg[3:0] SamplePos[3:0] SampleNeg[3:0] AdclkPos[3:0] AdclkNeg[3:0] DataPlace[3:0] DataLatency[3:0] ClampCtrl ClampMode ClampEnb ClampLength[6:0] ClampDelay ClampEdges LEDConfig LED0Edges ClampPosition ClampDelay[13:0] ClampPos[3:0] ClampNeg[3:0] LEDCtrl sync_sel[2:0] LEDCtrl place[2:0] LED0Pos[7:0] LED0Neg[7:0] LED1Edges LED2Edges ScanLength ScanCyles LED1Pos[7:0] LED1Neg[7:0] LED2Pos[7:0] LED2Neg[7:0] ScanLength[12:0] ScanCycle[4:0] 1 1 16 1 0 7 7 0 0 0 78 0 78 0 78 2576 2 ms 0000000b 11100b 0 7 0 n/a 1 4 0 1 16 1 4 2 2 3 0 Value 100723A Conexant 7-33 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Manufacturer Part # Type Resolution Pixels Scan time (color) Scan time (B/W) Data Rate Main clock `H' duty NEC *PD3724 CCD 300 dpi 2700 x 3 Interface: Scanner Description LED control *TG[3:1] SEL1 SEL2 *RB Start pulse Color selector1 Color selector2 Reset clock Shift register clock 1 Shift register clock 2 MFC2000 LEDCtrl[0] start[0] LEDCtrl[1] LEDCtrl[2] clk2a clk1 clk1 3 MHz (max) 50 % *1, *1L *2***2L Timing: 50 ns ihsclk dotscaler_ctr dotperiod_ctr clk1 PixelTime = 350 ns 6 0 1 2 3 4 5 0 6 0 1 2 3 4 5 6 0 inv(clk1) clk2a clk1 3150 ns (guardband) 350 ns start[0] 1050 ns (offset) 1050 ns (length) 1050 ns LineTime =1.5 ms start[0] LEDCtrl[2:1] 3 2 14 dummy + 49 black + 2 invalid pixels 1 scanin envelope of analog signal SigTime = 0.945 ms ExpTime = 1.48 ms LEDCtrl[0] can be modulated 0 2700 4224 pixel counter 4285 Figure 7-18. Untitled Timing Diagram 7-34 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 7-5. Register Setup for NEC - PD3724 Register Name ScanConfig ScanDotControl StartConfig Bits Name scctrl[6:0] invert scctrl[6:2] select Scan Dot Scaler[3:0] Scan Dot Period[3:0] GuardbandEnb[6:4] Guardband[4:0] Offset[3:0] Length[3:0] StartEdges StartPos[3:0] StartNeg[3:0] ScanStartDelay Clk2aEdges Clk2bEdges Clk2cEdges Delay[12:0] Clk2aPos[3:0] Clk2aNeg[3:0] Clk2bPos[3:0] Clk2bNeg[3:0] Clk2cPos[3:0] Clk2cNeg[3:0] ADCSampleCfg ADCConfig SamplePos[3:0] SampleNeg[3:0] AdclkPos[3:0] AdclkNeg[3:0] DataPlace[3:0] DataLatency[3:0] ClampCtrl ClampMode ClampEnb ClampLength[6:0] ClampDelay ClampEdges LEDConfig LED0Edges LED1Edges LED2Edges ScanLength ScanCyles ClampPosition ClampDelay[13:0] ClampPos[3:0] ClampNeg[3:0] LEDCtrl sync_sel[2:0] LEDCtrl place[2:0] LED0Pos[7:0] LED0Neg[7:0] LED1Pos[7:0] LED1Neg[7:0] LED2Pos[7:0] LED2Neg[7:0] ScanLength[12:0] ScanCyle[4:0] 1 1 49 1 13 + 9 = 22 0 1 6 1 0 66 n/a n/a n/a n/a 2700 1.5 ms 0100000b 00100b 0 6 7 8 2 2 0 6 65 + 9 = 74 4 2 n/a n/a n/a n/a 0 1 Value 100723A Conexant 7-35 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Manufacturer Part # Type Resolution Pixels Scan time (color) Scan time (B/W) Data Rate Main clock `H' duty NEC *PD3794 CCD 300 dpi 2700 x 3 Interface: Scanner Description LED control *TG[3:1] SEL1 SEL2 *RB Start pulse Color selector1 Color selector2 Reset clock Shift register clock 1 Shift register clock 2 MFC2000 LEDCtrl[0] start[0] LEDCtrl[1] LEDCtrl[2] clk2a clk2b clk2c 4 MHz (max) *1 *2 Timing: 50 ns ihsclk dotscaler_ctr dotperiod_ctr clk2a clk2b PixelTime = 250 ns 4 0 1 2 3 4 0 0 1 2 3 4 0 1 2 3 4 clk2c clk1 5000 ns (guardband) 250 ns start[0] 1000 ns (offset) 3000 ns (length) LineTime =1 ms 1000 ns start[0] LEDCtrl[2:1] 3 2 14 dummy + 48 black + 2 invalid pixels 1 scanin envelope of analog signal SigTime = 0.675 ms ExpTime = ~1 ms LEDCtrl[0] can be modulated 0 2700 3904 pixel counter 3936 Figure 7-19. Untitled Timing Diagram 7-36 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 7-6. Register setup for NEC - PD3794 Register Name ScanConfig ScanDotControl StartConfig Bits Name scctrl[6:0] invert scctrl[6:2] select Scan Dot Scaler[3:0] Scan Dot Period[3:0] GuardbandEnb[6:4] Guardband[4:0] Offset[3:0] Length[3:0] StartEdges StartPos[3:0] StartNeg[3:0] ScanStartDelay Clk2aEdges Clk2bEdges Clk2cEdges Delay[12:0] Clk2aPos[3:0] Clk2aNeg[3:0] Clk2bPos[3:0] Clk2bNeg[3:0] Clk2cPos[3:0] Clk2cNeg[3:0] ADCSampleCfg ADCConfig SamplePos[3:0] SampleNeg[3:0] AdclkPos[3:0] AdclkNeg[3:0] DataPlace[3:0] DataLatency[3:0] ClampCtrl ClampMode ClampEnb ClampLength[6:0] ClampDelay ClampEdges LEDConfig LED0Edges LED1Edges LED2Edges ScanLength ScanCyles ClampPosition ClampDelay[13:0] ClampPos[3:0] ClampNeg[3:0] LEDCtrl sync_sel[2:0] LEDCtrl place[2:0] LED0Pos[7:0] LED0Neg[7:0] LED1Pos[7:0] LED1Neg[7:0] LED2Pos[7:0] LED2Neg[7:0] ScanLength[12:0] ScanCycle[4:0] 1 1 47 1 33 2 2 6 1 0 60 n/a n/a n/a n/a 2700 0 0000000b 11000b 0 4 6 19 3 11 0 4 83 4 1 3 0 4 4 4 4 Value 100723A Conexant 7-37 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Manufacturer Part # Type Resolution Pixels Scan time (color) Scan time (B/W) Data Rate Main clock `H' duty SONY ILX516K CCD 400 dpi 3648 x 3 Interface: Scanner Description LED control *ROG (3) SEL1 SEL2 *RS Start pulse Color selector1 Color selector2 Reset clock Shift register clock 1 Shift register clock 2 MFC2000 LEDCtrl[0] start[0] LEDCtrl[1] LEDCtrl[2] clk2a clk2b clk2c 5 MHz (max) 50 % *1, *LH *2 Timing: 50 ns ihsclk dotscaler_ctr dotperiod_ctr clk2a clk2b clk2c PixelTime = 200 ns (min) typ = 10 ns typ = 10 ns 3 0 1 2 3 0 1 0 2 3 0 1 2 3 0 1 2 min = 45 ns min = 45 ns valid output clk2b 800 ns (min) start[0] 200 ns (min = 50 ns) 800 ns (min) 200 ns LineTime =1.5 ms start[0] LEDCtrl[2:1] 0 63 dummy pixels 1 2 scanin envelope of analog signal SigTime = 0.7296 m s ExpTime = 1.4976 ms LEDCtrl[0] can be modulated 0 3648 7488 pixel counter 7500 Figure 7-20. Untitled Timing Diagram 7-38 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 7-7. Register Setup for SONY - ILX516K Register Name ScanConfig ScanDotControl Bits Name scctrl[6:0] invert scctrl[6:2] select Scan Dot Scaler[3:0] Scan Dot Period[3:0] StartConfig Guardband[6:4] Guardband[4:0] Offset[3:0] Length[3:0] StartEdges ScanStartDelay Clk2aEdges Clk2bEdges Clk2cEdges ADCSampleCfg ADCConfig StartPos[3:0] StartNeg[3:0] Delay[12:0] Clk2aPos[3:0] Clk2aNeg[3:0] Clk2bPos[3:0] Clk2bNeg[3:0] Clk2cPos[3:0] Clk2cNeg[3:0] SamplePos[3:0] SampleNeg[3:0] AdclkPos[3:0] AdclkNeg[3:0] DataPlace[3:0] DataLatency[3:0] ClampCtrl ClampMode ClampEnb ClampLength[6:0] ClampDelay ClampEdges LEDConfig LED0Edges ClampPosition ClampDelay[13:0] ClampPos[3:0] ClampNeg[3:0] LEDCtrl sync_sel[2:0] LEDCtrl place[2:0] LED0Pos[7:0] LED0Neg[7:0] LED1Edges LED2Edges ScanLength ScanCyles LED1Pos[7:0] LED1Neg[7:0] LED2Pos[7:0] LED2Neg[7:0] ScanLength[12:0] ScanCyle[4:0] 1 1 49 1 10 + 14 = 24 1 1 6 1 0 117 n/a n/a n/a n/a 3648 1.5 ms 0110000b 11100b 0 3 7 9 0 3 1 3 63 + 10 = 73 1 3 2 3 2 3 3 3 Value 100723A Conexant 7-39 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description External circuit required for SONY-ILX516K interface: +12 V 100 Analog Inverter 5.1K +12 V SONY - ILX516K Vout R Vout G Vout B 100 LEDCtrl[2] LEDCtrl[1] MFC2000 scanin 5.1K +12 V 100 Analog MUX 5.1K Figure 7-21. External circuit required for SONY-ILX516K interface LED timing for SONY-ILX516K start[0] LEDCtrl[0] expsoure time as required by RED sensor expsoure time as required by GREEN sensor expsoure time as required by BLUE sensor LEDCtrl[2:1] select Red select Green select Blue Used as selectors for analog MUX Figure 7-22. LED timing for SONY-ILX516K 7-40 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 7.2 Serial Programming Interface The serial programming interface is a two-wire bidirectional serial bus, which provides a simple and efficient way for data exchange between devices. Main Features: * * * * * * * Only two bus lines are required; a serial interface data (SID) and a serial interface clock (SIC) Master-transmitter & master-receiver Schmitt trigger on SID input Synchronization capability (allowing slave to add wait state by pulling the clock low) Optional interrupt or polling operation Optional firmware operation for manual control of the SPI bus Soft reset 7.2.1 Function Description Physical Connection PM[0]/GPO[0]/ SPI_SID / E A D C _ D [ 9 ] / T _ E X T _ B R E Q MFC2K (Master) SID SID in SID_n out SIC in SIC_n out (serial interface data) Slave SID in SID_n out SIC in SIC_n out SIC (serial interface clock) PM[1]/GPO[1]/ SPI_SIC / E A D C _ D [ 8 ] / T _ E X T _ B A C K Figure 7-23. Serial Programming Interface, Physical Connection Notes: 1. Master is the device that initiates a transaction, generates clock signal, and terminates the transaction. 2. Data and clock can only be driven low, and cannot be driven high. The pull-up resistors are responsible to create a logic 1. This configuration forms wire - AND connection. 3. Slave can only drive the clock signal to add wait state. 4. There is no minimum requirement for clock frequency. 100723A Conexant 7-41 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Bus Protocol Data transfer (n bytes + acknowledge) 8-bit ACK Data ACK STOP 7-bit START Slave Address 1-bit R/W ACK 8-bit Data Figure 7-24. Bus Protocol SID SIC b7 b6 b1 b0 b7 b6 b1 b0 A/A Slave Address Start R/W A n x (8-bit DATA) n x (A/A) Stop [spi_timing.vsd] Figure 7-25. Serial Programming Interface, Timing Diagram 7-42 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 START condition SID SIC Data is pulled low while clock is still high, followed by pulling the clock low. Clock and data will be held low. Clock is released to high, followed by releasing data to high. STOP condition SID SIC Bit transfer SID SIC Address/data bit must be valid while SIC is high. Getting ACK SID master slave wire LSB 'z' LSB This is the condition after master transmitted data to slave, which will be referred as WAC (write acknowlege). 'z' '0' '0' 'z' Slave is giving acknowledge by driving the data line low. Master is getting the acknowledge by generating a clock pulse to capture the acknowledge. 'H' 'H' SIC end of write WAC Giving ACK SID master slave wire 'z' 'z' LSB '0' 'z' This is the condition after master received data from slave, which will be referred as RAC (read acknowledge). Master is giving acknowledge to the slave by driving data line low and by generating a clock pulse. LSB 'H' '0' 'H' Slave is receiving the acknowledge from master. SIC end of read RAC 100723A Conexant 7-43 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Clock Stretching Slave can add wait state as needed by stretching the low period of the clock. This will slow down the bus as shown below. Master's SIC Slave's SIC SIC wait state Figure 7-26. Stretching the Low Period of the Clock 7.2.2 Register Description Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 WRI (read only) Default Rst. Value xxxxxxx0b Read Value 00h Default Rst. Value 00h Read Value 00h Name/Address SPI Control (SPICtrl) $01FF854B Name/Address SPI Control (SPICtrl) $01FF854A Bit 7 RST Bit 6 REA Bit 5 STA Bit 4 STO Bit 3 RAC Bit 2 WAC SID Bit 1 SIC Bit 0 Bit 8 Bit 7 WRI - Writing RST - Reset This is a read only bit which indicates the writing operation. Reading a 1 means the SPI is in the process of sending/writing data to slave. Writing a 1 to this bit will cause the SPI logic controller to be resetted. If SPI is in operation while RST bit is set, then the operation will be terminated. Reading a 1 from this bit indicates that RST operation is active. After the reset, both SID and SIC lines will be released. Writing a 1 to this bit will generate 8 clocks to read data from slave, and SPI will capture serial data into the upper byte of `SPI_data' register. Reading a 1 from this bit indicates that REA operation is active. Writing a 1 to this bit will generate START condition. Reading a 1 from this bit indicates STA operation is active. Writing a 1 to this bit will generate STOP condition. Reading a 1 from this bit indicates STO operation is active. Writing a 1 to this bit will generate ACKNOWLEDGE condition after read operation in which the master will: 1. generate clock pulse 2. drive SID low Reading a 1 from this bit indicates RAC operation is active. Bit 6 REA - Read Bit 5 Bit 4 Bit 3 STA - Start STO - Stop RAC - Read Acknowledge 7-44 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Bit 2 WAC - Write Acknowledge Writing a 1 to this bit will generate ACKNOWLEDGE condition after write operation in which the master will: 1. generate clock pulse 2. NOT drive SID but will capture acknowledge bit from slave and store it into bit 8 of `SPI_Stat' register Reading a 1 from this bit indicates WAC operation is active. Bit 1 SID - Serial Input Data This bit is used to control the SID line directly, and it is only valid if the "Manual Operation" bit in SPI_Config is equal to 1. When SID = 1, then SPI is not driving the SID line. When SID = 0, then SPI will drive SID line low. This bit is used to control the SIC line directly, and it is only valid if the "Manual Operation" bit in SPI_Config is equal to 1. When SIC = 1, then SPI is not driving the SIC line. When SIC = 0, then SPI will drive SIC line low. Bit 0 SIC - Serial Input Clock Note: In normal case, only one of bit [7:2] should be set. However, if for some reasons, more than one bits are set, then the hardware will respond according to the following priority. Other bit(s) that are set will be ignored. Priority 1 2 3 4 5 6 7 Operation RST STO STA REA RAC WAC WRI 100723A Conexant 7-45 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Name/Address SPI Status (SPIStat) $01FF854D Name/Address SPI Status (SPIStat) $01FF854C Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 Received ACK (read only) Bit 0 SIC line (read only) Default Rst. Value xxxxxxx0b Read Value 00h Default Rst. Value xxxxxx00b Read Value 00h Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 (Not Used) Bit 2 (Not Used) Bit 1 SID line (read only) Bit 8 Received ACK This is a read only bit which is only valid after writing a 1 to "WAC" bit and after verifying that WAC operation is completed, i.e., WAC bit is 0. After master sends data to slave, master must check if slave has received the data properly. This checking is done by requesting acknowledge from slave. In this situation, master is sending a clock pulse, and capture the acknowledge on SID line while SIC is high. This is the acknowledge stored in bit 8. This is a read only bit which comes directly from the SID pin. This is a read only bit which comes directly from the SIC pin. Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Rst. Value xxh Read Value 00h Default Rst. Value 0xxx0000b Read Value 00h Bit 1 Bit 0 SID - Serial Input Data line SIC - Serial Input Clock line Bit 15 (Not Used) Bit 14 (Not Used) Name/Address SPI Configuration (SPIConfig) $01FF88C1 Name/Address SPI Configuration (SPIConfig) $01FF88C0 Bit 7 Manual Operation Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 SPI Interrupt Enable Bit 2 Bit 1 Bit 0 Clk Divider[0] Clock Mode Clk Divider[1] Bit 7 Bit 3 Manual Operation SPI Interrupt Enable By setting this bit, firmware can control the SID and SIC directly by writing to bit 1 and bit 0 of SPI_Ctrl register. By setting this bit, the interrupt from SPI is enabled. At the end of REA, STA, STO, RAC, WAC, or WRI operation, the interrupt will be active in order to indicate the completion of operation. Once the firmware has serviced this interrupt, it can be cleared by writing a 1 to bit 1 of `VSCIRQStatus' register. Bit 2 Bit 1-0 Clock Mode Clock Divider[1:0] 7-46 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Clock Mode = 0 Div[1:0] 0 1 2 3 SIC Freq 1.2 KHz 9.8 KHz 39 KHz 78 KHz Clock Mode = 1 Div[1:0] 0 1 2 3 SIC Freq 104 KHz 156 KHz 208 KHz 312 KHz Note: The freqencies specified above are based on iclk = 10MHz. Name/Address SPI Data (SPIData) $01FF88C3 Name/Address SPI Data (SPIData) $01FF88C2 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default Read Read Read Read Read Read Read Read Rst. Value Data[6] Data[5] Data[4] Data[3] Data[2] Data[1] Data[0] Data[7] 00h (Read only) (Read only) (Read only) (Read only) (Read only) (Read only) (Read only) (Read only) Read Value 00h Bit 7 Write Data[7] Bit 6 Write Data[6] Bit 5 Write Data[5] Bit 4 Write Data[4] Bit 3 Write Data[3] Bit 2 Write Data[2] Bit 1 Write Data[1] Bit 0 Write Data[0] Default Rst. Value 00h Read Value 00h Bit 15-8 Bit 7-0 Read Data[15:8] Write Data[7:0] The data received is stored in this location. The data transmitted comes from this location. Writing to SPIData register will initiate the transmission of bit[7:0]. It should be noted that if the writing occurs while ACT = 1, then the current transmission will be corrupted. 100723A Conexant 7-47 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 7.2.3 Firmware Operation Initialization: select the desired frequency for SIC by writing the appropriate value to "SPI_Config" register Transmission: START no write 0x0020 to 'SPI_Ctrl' reg Generate START condition receive & clear spi_irq write to 'SPI_Data' reg Send the 7-bit slave address + "W" bit receive & clear spi_irq write 0x0004 to 'SPI_Ctrl' reg Generate WAC condition receive & clear spi_irq write to 'SPI_Data' reg yes Send more data? no write 0x0010 to 'SPI_Ctrl' reg Generate STOP condition END [spi_fw_tx.vsd] Figure 7-27. Firmware OperationTransmission 7-48 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Reception: START no write 0x0020 to 'SPI_Ctrl' reg Generate START condition receive & clear spi irq write to 'SPI_Data' reg Send the 7-bit slave address + "R" bit receive & clear spi irq write 0x0004 to 'SPI_Ctrl' reg Generate WAC condition receive & clear spi irq write 0x0040 to 'SPI_Ctrl' reg Initiate READ operation of sending clock pulses & capturing serial data receive & clear spi irq read 'SPI_Data' reg Expect more data? yes write 0x0080 to 'SPI_Ctrl' reg no Generate RAC condition write 0x0010 to 'SPI_Ctrl' reg Generate STOP condition; END [spi_fw_rx.vsd] Figure 7-28. Firmware OperationReception 100723A Conexant 7-49 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 7.3 Video Controller Main features: * * * * Capture a frame from an external video decoder device Support ITU-R BT.656 or VESA Video Interface Port (VIP) format of YCrCb 4:2:2 Store captured frame into memory in a non-interlace format Software interrupt at the end of a frame capture ITU-R BT.656 * Data format: CB, Y, CR, Y, etc Y CB CR * Control structure: FF, 00, 00, XY XY contains the video timing reference code XY = {1, F, V, H, P3, P2, P1, P0}, where F = Field V = Vertical H = Horizontal (0 = SAV, 1 = EAV) P3, P2, P1, P0 = error protection bits, with P3 = V xor H, P2 = F xor H, P1= F xor V, P0 = F xor V xor H XY 80 9D AB B6 C7 DA EC F1 * Control insertion: 1. at the beginning of a line: SAV (start of active video) 2. at the end of a line: EAV (end of active video) * Number of pixels per line is 720. * The following control codes are inserted for every valid line: Field 0 1 Start Line FF, 00, 00, 80 FF, 00, 00, C7 End Line FF, 00, 00, 9D FF, 00, 00, DA F 0 0 0 0 1 1 1 1 V 0 0 1 1 0 0 1 1 H 0 1 0 1 0 1 0 1 type SAV EAV SAV EAV SAV EAV SAV EAV Y 7-50 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 VESA VIP * Dummy byte/ invalid pixel code: 00 (between SAV and EAV) * Number of pixels per line is not restricted to 720 * The most significant bit of XY byte is called task bit (T-bit), which can be 1 or 0. Convention * F = 0 (Field = 1) is an odd field * F = 1 (Field = 2) is an even field * Odd field is the top field * Even field is the bottom field 7.3.1 Function Description Pins connection to external video capture device: Video Capture MFC2000 clk EV_CLK EV_VD[7:0] /EADC_D[11:4] data[7:0] Figure 7-29. Connection to External Video Capture Device 7.3.2 Register Description Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 Video Error (read only) Default Rst. Value xxxxxxx0b Read Value 00h Default Rst. Value xxxxxxx0b Read Value 00h Name/Address Video Capture Control (VidCaptureCtrl) $01FF8549 Name/Address Video Capture Control (VidCaptureCtrl) $01FF8548 Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 (Not Used) Bit 2 (Not Used) Bit 1 (Not Used) Bit 0 Start Capture Bit 8 Video Error This status bit indicates that error has been detected in capturing the video signal. The error is detected based on the line length comparison between the specified number of bytes per line (i.e., the value in VideoLineCfg register) to the actual number of bytes captured. If any line within a frame does not match VideoLineCfg register, this bit will be set. At the beginning of the next video capture, this error bit will be cleared. Bit 0 Start Capture By setting this bit, the hardware will start the process of capturing a frame of video data. Once a complete frame has been captured, the hardware will clear this bit. The status of capturing process can be known by reading this bit. Reading a 1 indicates that the hardware is busy. 100723A Conexant 7-51 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Name/Address Video Line Config (VidLineCfg) $01FF88C7 Name/Address Video Line Config (VidLineCfg) $01FF88C6 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 Bit 9 Bit 8 LineSize[8] Default Rst. Value xxxxx000b Read Value 00h Default Rst. Value 00h Read Value 00h LineSize[10] LineSize[9] Bit 7 LineSize[7] Bit 6 LineSize[6] Bit 5 LineSize[5] Bit 4 LineSize[4] Bit 3 LineSize[3] Bit 2 LineSize[2] Bit 1 LineSize[1] Bit 0 0 Bit 10-1 LineSize[10:1] This register defines the maximum number of bytes to be captured per line. The value in this register must be written prior to initiating the video capture. Bit 0 is a constant zero in order to ensure that line size is an even number, i.e., on the word boundary. If the number of actual data is more than this value, then the actual data will be truncated. It should be noted that at the end of every line, one or two byte of zeros will be added in order to indicate the end of line, and at the same time the additional zeros will guarantee that the line length is on the word boundary. Whenever the actual data does not match the LineSize, the "Video Error" bit in "Video Capture Config" register will be set to 1. Note: The jump or skip parameter in DMA setting must be at least 1 halfword bigger than the "LineSizeCfg" in order to take into account the additional zeros at the end of line. Example of line too short VidLineCfg = 10 bytes Number of actual data from video decoder = 9 bytes Number of actual data stored into memory = 9 bytes Number of zeros inserted into memory = 1 byte Final line size = 10 bytes Example of line too long VidLineCfg = 10 bytes Number of actual data from video decoder = 11 bytes Number of actual data stored into memory = 10 bytes Number of zeros inserted into memory = 2 byte Final line size = 12 bytes Example of line is just right VidLineCfg = 10 bytes Number of actual data from video decoder = 10 bytes Number of actual data stored into memory = 10 bytes Number of zeros inserted into memory = 2 byte Final line size = 12 bytes 7-52 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Name/Address Bit 15 Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 VidLL[10] (read only) Bit 9 VidLL[9] (read only) Bit 8 VidLL[8] (read only) Default Rst. Value xxxxx000b Read Value 00h Default Rst. Value 00h Read Value 00h Video Line Length (Not Used) Status (VidLLStat) $01FF88C9 Name/Address Bit 7 Bit 6 VidLL[6] (read only) Bit 5 VidLL[5] (read only) Bit 4 VidLL[4] (read only) Bit 3 VidLL[3] (read only) Bit 2 VidLL[2] (read only) Bit 1 VidLL[1] (read only) Bit 0 VidLL[0] (read only) Video Line Length VidLL[7] Status (read only) (VidLLStat) $01FF88C8 Bit 10-0 VidLL[10:0] This register indicates the number of bytes per line and not the number of pixels per line. The value in this register is updated continuously at the end of every line. Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 VidOddFL [8] (read only) Bit 0 VidOddFL [0] (read only) Default Rst. Value xxxxxxx0b Read Value 00h Default Rst. Value 00h Read Value 00h Name/Address Video Odd Field Length Status (VidOddFLStat) $01FF88CB Name/Address Video Odd Field Length Status (VidOddFLStat) $01FF88CA Bit 15 (Not Used) Bit 7 VidOddFL [7] (read only) Bit 6 VidOddFL [6] (read only) Bit 5 VidOddFL [5] (read only) Bit 4 VidOddFL [4] (read only) Bit 3 VidOddFL [3] (read only) Bit 2 VidOddFL [2] (read only) Bit 1 VidOddFL [1] (read only) Bit 8-0 VidOddFL [8:0] This register indicates the number of lines in odd field. The value in this register is updated continuously at the end of every odd field. Name/Address Video Even Field Length Status (VidEvenFLStat) $01FF88CD Name/Address Video Even Field Length Status (VidEvenFLStat) $01FF88CC Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 VidEvenFL [8] (read only) Bit 0 VidEvenFL [0] (read only) Default Rst. Value xxxxxxx0b Read Value 00h Default Rst. Value 00h Read Value 00h Bit 7 VidEvenFL [7] (read only) Bit 6 VidEvenFL [6] (read only) Bit 5 VidEvenFL [5] (read only) Bit 4 VidEvenFL [4] (read only) Bit 3 VidEvenFL [3] (read only) Bit 2 VidEvenFL [2] (read only) Bit 1 VidEvenFL [1] (read only) Bit 8-0 VidEvenFL [8:0] This register indicates the number of lines in even field. The value in this register is updated continuously at the end of every even field. 100723A Conexant 7-53 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 7.3.3 Timing Data is sampled at the rising edge. The control codes indicate the beginning and the end of a valid line, with invalid pixels inserted. Field = 0 Clk Data FF 00 00 80 CB Y CR Y CB Y 00 FF 00 00 9D valid Start of line for Field = 0 One line End of line for Field = 0 Field = 1 Clk Data FF 00 00 C7 CB Y CR Y CB Y 00 FF 00 00 DA valid Start of line for Field = 1 One line End of line for Field = 1 Figure 7-30. Untitled Timing Diagram 7-54 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 7.3.4 Firmware Operation Firmware sequence of operations: 1. Setup the external video capture device via two-wire serial interface 2. Poll the status register in external video capture device via two-wire serial interface 3. Read VidLLStat and VidOddFLStat registers if video signal is detected 4. Setup DMA based on the values stored in VidLLStat and VidOddFLStat registers 5. Write to VidLineSizeCfg register based on the VidLLStat 6. Start the video capture by writing to VidCaptureCtrl register DMA operation: Odd Field Address Start 0 Even Field Address n+1 Step/Jump 1 n+2 2 signal from video decoder device, indicating the end of the odd field n Stop signal from video decoder device, indicating the end of frame capture Figure 7-31. DMA Operation DMA features: * * clear internal counter after address/other registers are written selection bit (scan/video) - scan: 1 address will be used, and operation is simple - video: 2 addresses will be used, and operation is complex as shown above 100723A Conexant 7-55 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description This page is intentionally blank. 7-56 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 8. ADC 8.1 8.1.1 PADC AND SCAN ANALOG FRONT END General description Symbols: adcout[11:0] TADCREF ADVD ADGD ADVA ADGA ADCVC ADCREFP ADCREFN SCIN ext interface (pad & pin) offset[5:0] gain[3:0] sample clamp adclk int interface Signal names: lowercase : digital uppercase: ANALOG gain[3:0] sample Offset Adjustment 3V + clamp offset[5:0] 0V 1.9 V DAC + _ adclk PGA ADCREFP ADC ADCREFN ADCVC adcout[11:0] -0.1 V Reference ADCVC ADCREFP ADCREFN TADCREF Figure 8-1. Untitled Figure 100723A Conexant 8-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Table 8-1. Untitled Table Name adclk Clock for ADC circuit The maximum frequency of this clock is 5 MHz. This clock is guaranteed to be low while "sample" is high. clamp gain[3:0] offset[5:0] sample Clock for clamping circuit The maximum frequency of this clock is 5 MHz. Selector for gain adjustment on PGA circuit Selector for offset adjustment on DAC circuit Clock for sampling circuit The maximum frequency of this clock is 5 MHz. The minimum (high) pulse width is 50 ns. adcout[11:0] TADCREF Digital data from ADC circuit Analog signal as a reference voltage for TADC Description Table 8-2. Untitled Table Name ADCREFN ADCREFP ADGA ADGD ADVA ADVC ADVD SCIN Description An internally generated reference voltage An internally generated reference voltage Ground return from analog circuits Ground return from digital circuits +3.3V power supply for analog circuits An internally generated reference voltage +3.3V power supply for digital circuits Analog input for scanner signal 8.1.2 Offset Adjustment This offset adjustment contains DAC which takes digital input to configure the DAC and analog subtraction to subtract the incoming scanner signal with the analog signal from the DAC. This adjustment is used to remove/reduce the dark level offset on the scanner signal. The adjustment on DAC value is described below: Table 8-3. Offset Adjustment on DAC Parameter offset[5:0] 000000 11111 -0.1 1.9 V V Min Typ Max Units 8-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 8.1.3 Programmable Gain Amplifier (PGA) Table 8-4. Programmable Gain Amplifier (PGA) Parameter Input Voltage Range (Gain = 1) Gain[3:0] (in hex) 0 1 2 3 4 5 6 7 8 9 A B C D E F -1.25 -0.25 0.75 1.75 2.75 3.75 4.75 5.75 6.75 7.75 8.75 9.75 10.75 11.75 12.75 13.75 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -0.75 0.25 1.25 2.25 3.25 4.25 5.25 6.25 7.25 8.25 9.25 10.25 11.25 12.25 13.25 14.25 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Min 0 Typ Max 3 Units V Note: Scanner output will be sampled at the falling edge of the "sample" signal 100723A Conexant 8-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 8.1.4 Pipelined Analog-to-Digital Converter (PADC) Table 8-5. Pipelined ADC (PADC) Parameter Min Typ 12 5 -1 -2 0.5 1 1 $ 16 +1 +2 Max Units Bits MSPS LSB LSB mV/V Binary unsigned ADCLK RESOLUTION SPEED ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) POWER SUPPLY REJECTION OUTPUT FORMAT LATENCY 8.1.5 Timing Diagram a pixel period programmable sample position within pixel period (min width = 50 ns) SCIN (scanner output) sample s1 s2 adclk adcout[11:0] guarantees to be low while sample is high D1 D2 latency Table 8-6. PADC Timing Diagram 8.1.6 ADCVREFP, ADCVREFN, and ADCVC The ADCVREFP and ADCVREFN voltages provide positive and negative references for ADCs while VC is used as common mode voltage in the design of ADC and PGA. These voltages are decoupled with external capacitors (0.1F) to reduce thermal noise and also to provide high frequency ac current for sampling. 8.1.7 TADCREF Parameter Min 2.370 Typ 2.390 Max 2.410 Units V TADCREF 8-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 8.2 8.2.1 TADC Function Description Thermal ADC provides the analog to digital functionality for low speed analog signals. A simplified block diagram of TADC is shown below. senin[0],[1],[2], or TADCREF + 9-bit up/down Counter 6 MSBs 6-bit DAC +/- 1/2 bit AD[5:0] [tadc-simple.vsd] Table 8-7. TADC Block Diagram The TADC includes a 6-bit DAC, a comparator and a 9-bit self tracking up/down counter. The up/down counter is incremented or decremented based on the polarity of the comparator output. The most significant 6 bits of the counter are used to generate the DAC reference signal to the comparator. The comparator compares this reference voltage to the external analog input signals, SENIN[2:0], or TADCREF. After settling, the counter value (and thus the DAC digital value) represents the A-to-D conversion of the input signal. The least significant bits of the counter are used to average out the comparator fluctuations which occurs at the settling point. The counter is set to a mid-point value on the power-on reset so that it settles more quickly. The frequency of updating the counter is programmable. The TADC can be operated in two modes. By default, the manual mode will be selected. In this mode, the firmware will select the analog input. Then, the firmware must wait for at least for 256 * tadcclk period to allow the TADC to settle prior to reading the data. In the automatic mode, the hardware will do the selection for each analog input in rotation. Each analog input will be selected periodically, and the data from each channel will be stored in different register at the same rate as channel selection. 100723A Conexant 8-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 8.2.2 Register Description Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Rst. Value xxh Read Value 00h Default Rst. Value x0000000b Read Value 00h Name/Address TADC Control (TADCCtrl) $01FF8001 Name/Address TADC Control (TADCCtrl) $01FF8000 Bit 7 (Not Used) Bit 6 Tadcclk Select[1] Bit 5 Tadcclk Select[0] Bit 4 Update Select[1] Bit 3 Update Select[0] Bit 2 Channel Select[1] Bit 1 Channel Select[0] Bit 0 Mode Bit 6-5 Tadcclk Select[1:0] The frequency for tadc counter is programmable according to the following table. Tadcclk Frequency Tadcclk Frequency (assuming iclk = 10MHz) Tadcclk Select[1:0] 0 1 2 3 freq(iclk)/64 freq(iclk)/16 freq(iclk)/8 freq(iclk)/4 156 KHz 625 KHz 1.25 MHz 2.5 MHz Bit 4-3 Update Select[1:0] In the auto mode, the frequency of updating each register is determined by the setting on these bits. Update Frequency Update Frequency (with tadcclk = 156 KHz) Update Frequency (with tadcclk = 5 MHz) 2.4 KHz 4.8 KHz 9.8 KHz 19.5 KHz Update Select[1:0] 0 1 2 3 freq(tadcclk)/2048 freq(tadcclk)/1024 freq(tadcclk)/512 freq(tadcclk)/256 76 Hz 152 Hz 304 Hz 609 Hz Bit 2-1 Channel Select [1:0] This channel selection is only valid for manual mode (i.e., Mode = 0). Channel Select[1:0] 0 1 2 3 Selected Channel senin[0] senin[1] senin[2] TADCREF Bit 0 Mode When mode = 0, then the manual mode is selected. In this manual mode, the channel selected must be done by the firmware, by setting the desired channel selection in bit 2 & bit1. When mode = 1, then the automatic mode is selected. In this auto mode, the selection for the analog mux will be performed automatically by the hardware, and the data on three registers corresponding to each channel will be updated accordingly. 8-6 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Note: In automatic mode, only channel 0, 1, and 2 will be automatically selected. Thus, in order to obtain the value for TADCREF, manual mode must be used, and "Channel Select" must be set to 3. Name/Address Bit 15 Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Rst. Value xxh Read Value 00h Default TADC Instant Data (Not Used) (TADCInsData) $01FF8003 Name/Address Bit 7 Bit 6 (Not Used) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TADC Instant Data (Not Used) (TADCInsData) $01FF8002 Data[5] Data[4] Data[3] Data[2] Data[1] Data[0] Rst. Value (Read Only) (Read Only) (Read Only) (Read Only) (Read Only) (Read Only) xx000000b Read Value 00h Bit 5-0 Data The data in this register comes directly from TADC. Thus, it gives the instant value from TADC regardless of the TADC operation mode. Name/Address TADC Ch 0 Data (TADCCh0Data) $01FF8005 Name/Address TADC Ch 0 Data (TADCCh0Data) $01FF8004 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Rst. Value xxh Read Value 00h Default Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data[5] Data[4] Data[3] Data[2] Data[1] Data[0] Rst. Value (Read Only) (Read Only) (Read Only) (Read Only) (Read Only) (Read Only) xx000000b Read Value 00h Bit 5-0 Data This data is only valid when the auto mode is selected. Name/Address TADC Ch 1 Data (TADCCh1Data) $01FF8007 Name/Address TADC Ch 1 Data (TADCCh1Data) $01FF8006 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Rst. Value xxh Read Value 00h Default Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data[5] Data[4] Data[3] Data[2] Data[1] Data[0] Rst. Value (Read Only) (Read Only) (Read Only) (Read Only) (Read Only) (Read Only) xx000000b Read Value 00h Bit 5-0 Data This data is only valid when the auto mode is selected. 100723A Conexant 8-7 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Name/Address TADC Ch 2 Data (TADCCh2Data) $01FF8009 Name/Address TADC Ch 2 Data (TADCCh2Data) $01FF8008 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Rst. Value xxh Read Value 00h Default Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data[5] Data[4] Data[3] Data[2] Data[1] Data[0] Rst. Value (Read Only) (Read Only) (Read Only) (Read Only) (Read Only) (Read Only) xx000000b Read Value 00h Bit 5-0 Data This data is only valid when the auto mode is selected. 8.2.3 Firmware Operation General setup: 1. Select the desired tadclk frequency 2. Select the desired mode of operation In manual mode: 3mm. Select the right channel ("TADCCtrl[2:1]") 4mm. Wait for at least "tadclk" period * 256 for TADC output to be stable 5mm. Read TADC data from "TADCInsData" register. (Then, go to step 3mm to select other channel) In automatic mode: 3am. Select the desired update frequency ("TADCCtrl[4:3]") 4am. Wait for at least TADC update period * 3 (only need to wait once after the above step. This wait guarantees each channel has been selected and its value has been stored in the corresponding register) 5am. Read TADC data from "TADCCh1Data", "TADCCh2Data", "TADCCh3Data" at any time for latest data. 8-8 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 9. BI-LEVEL RESOLUTION CONVERSION 9.1 Functional Description The bi-level resolution conversion logic in the MFC2000 performs expansion (converting from lower to higher resolution) and reduction (converting from higher to lower resolution) of horizontal image data. Vertical line ORing can also be performed for image reduction in the vertical direction. There are two data sources that can be selected for this bi-level resolution conversion block. One is T4/T6 Decompressor and another is the external memory. The data from the T4/T6 Decompressor is serially input to this bi-level resolution conversion logic. The data from the external memory is input to this bi-level resolution conversion logic through the DMA operation. The DMA operation for the data from the external memory uses the DMA channel 9. If the T4/T6 Decompressor is selected as the data source, the DMA channel 9 request is blocked. The data from this resolution conversion logic is output to the external memory also through the DMA operation. The DMA operation for the output data uses the DMA channel 8 (See Figure 9-1). The MFC2K adds the following features to the BRC Block: 1. A first and last black data detector to indicate the first and last halfword out of the BRC that contains printable data. 2. The ability the change the ORing algorithm for hoizontal reduction. Because the bi-level resolution conversion is a slave logic, the DMA channel 9 for inputting data from memory has the block size control function. Once the block size limit is reached during the DMA operation. The DMA Controller gives a signal to the bi-level resolution conversion logic that indicates the end of process. Then, the bilevel resolution conversion logic will deactivate the DMA request, disable the FIFO, and start the flush operation. After the flush operation the bi-level resolution conversion interrupt will be generated to the Interrupt Controller. Before CPU gets out of the interrupt routine, CPU needs to write the new block size into the DMA9BlockSize register of the DMA Controller (even the same block size) to clear the interrupt. Then, CPU needs to write a 1 and then, immediately write a 0 to bit 1 of the BiResConvCtrl register to tell hardware to convert a new line (Reset the Resolution Conversion Logic). If the data from the T4/T6 Decompressor is serially input to this bi-level resolution conversion logic, this bi-level resolution conversion logic is treated as a part of T.4/T6 logic. The T.4 line length (instead of block size of DMA channel 9) and T.4 interrupt (instead of the bi-level resolution conversion interrupt) are used. Furthermore,, this bilevel resolution conversion logic is enabled by setting bit 5 in the `T4Config' register in the T4/T6 Compression/Decompression Logic. The flush operation depends on the FIFO direction. If the FIFO is being read by the local side and written by the system side, a flush will simply reset all of the internal FIFO pointers, thereby removing the data. If the FIFO is being written by the local side and read by the system side, a flush will cause a DMA request to be generated. In addition, if there is a single byte in the holding register, it will be treated as a halfword (the contents of the msbyte of the halfword are indeterminate). Because of this, it is important for firmware to first check for the presence of a single byte in the holding register (via the Byte Present bit in the FIFO Control register). Each FIFO is composed of 4 halfwords, a holding register, and a control register. Firmware can randomly access all the FIFO registers under the following restrictions: * * * When the FIFO is enabled - reads may return invalid data, writes are blocked When the FIFO is disabled - read/write operations are properly performed Random access of the FIFO registers is useful in saving and restoring the state of the FIFO. This should only be done when the FIFO is disabled. 100723A Conexant 9-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 9.1.1 Horizontal Conversion Conversion in the horizontal direction is performed in this logic block by adding or removing a programmable number of pixels at the position which decided by the bi-level resolution conversion algorithm. Pixels are added based on a programmable 7-bit Base-3 counter and the expansion mode bits (2 bits). Input pixel number needs to be a multiple of 16. The output pixel number of this block is also a multiple of 16. Table 9-1. Untitled Table The expected expansion ratio 100% X < 200% 200% X < 300% 300% X < 400% the expansion mode 0 1 2 the programmed expansion ratio X X - 100% X - 200% the expansion result X X X Pixels are removed based on the same programmable 7-bit Base-3 counter used for the expansion. Data can be reduced down to 0.0457% (1/2187 x) and expanded up to 399.95% (~4x). To preserve image quality, it is recommended that an input line be reduced by no more than 2/3 times (66.67%) it's original resolution (this will ensure that 2 consecutive input pixels will never be removed). The following block diagram depicts the BRC block diagram. The functions are broken up into the blocks that represent the imdividule VHDL that make up the BRC design. Note that the two blocks, Vertical ORING and BRC Out FIFO, outputs are tied together. This represents the fact that only one of these output modes are operational at time. Resolution Converter DMA Data In BRC In FIFO DMA Req 9 T4 Serial Data In DMA Data Out Horizontal Shifter Serial To Parallel Vertical ORING DMA Req 8 BRC Counters In Mux ORING Algo. Filter, ORing Parallel to Serial Shingle BRC Out FIFO Figure 9-1: Bi-level Resolution Conversion Block Diagram 9-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 9.1.2 Vertical Conversion Expansion in the vertical direction is accomplished by the processor duplicating lines as needed to achieve the desired expansion ratio. Reduction in the vertical direction is accomplished by the processor either deleting lines or ORing lines together as needed to achieve the vertical reduction ratio. ORing of lines is also done by the resolution conversion logic. When ORing is enabled, each byte of the current line's line buffer data is ORed with the corresponding byte from the previous line. The DMA channel associated with the Resolution Conversion Block performs a read-modify (OR) -write operation. The DMA read and write accesses do not occur on consecutive bus cycles. The firmware should set the DMA channel start address for the line to be ORed equal to the address for the previous line. The threshold of the ORing function is selectable. If the threshold value is 0, all the black pixels in the current line will be used for the ORing function. In order to reduce the background image noise, the threshold value can be set from 1 to 7. If the threshold value is set to 2, the single black pixels and 2 contiguous black pixels in the current line will not be used for the ORing function. 9.1.3 Shingling Shingling is a process in which color intensity was built up in the course of several passes of the head for the inkjet printing. The objective is to print a portion of the data on each of the passes, using a checkerboard mask to decide which pixels to print on each pass and which pixels to mask out. This allows time for dots of ink printed on one pass to dry somewhat before adjacent ink dots are printed on subsequent passes, thereby improving quality. The checkerboard varies with the level of shingling in use. This level is described as a percentage, with 50, 33, and 25 percent shingling levels having been discussed to date. Briefly: 50 percent shingling requires two passes of the head. The matrix below shows a section of the pixels on the page, with the number being the pass of the head on which the pixel in printed: 1212121212121212121212 2121212121212121212121 1212121212121212121212 2121212121212121212121 33 percent shingling requires three passes to build up full intensity: 123123123123123123123123 312312312312312312312312 231231231231231231231231 123123123123123123123123 25 percent shingling requires four passes: 132413241324132413241324 241324132413241324132413 132413241324132413241324 241324132413241324132413 Paper moves a portion of the height of the nozzle array between passes of the head, so different nozzles print different dots on a scanline. In this situation, the data for the scanline must be moved from the band buffers to the print buffers several times, with a mask applied along the way so that only part of the data gets through on each move. Note that printing is slower when shingling is in use, so bandwidth is not significantly affected. Also note that the mask changes between scanlines. 100723A Conexant 9-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 9.1.4 Horizontal Shift Function Assume that the color inkjet head is used. There are 3 color groups. There are 16 nozzles for each color group on the inkjet head. The image data is usually line-based. For the inkjet printing, we can't feed the line based data right into the inkjet head. The line-based image data needs to be rearranged to match the inkjet head firing order and will be no longer line-based. As you can see from the diagram at the next page, if nozzle 1 in the top nozzle group needs the 1st pixel of line 1, nozzle 2 in the top nozzle group needs the (NP)th pixel of line 2. If there is a total of 48 nozzles, we will need to group 3 halfwords (48 pixels) of data from different lines, different columns, and different color planes. Then, another 3 half-word group for the next firing cycle. These 3 half-word groups will be sent to the external print ASIC. The external print ASIC will map these 48 pixels to the right nozzle location and control the fire sequence and timing within one firing cycle. In order to do inkjet printing, the line-based printing data from different color planes for each printing swath need to be prepared by Firmware. Under the assumption above, 48 lines (16 lines/color group) of data need to be prepared for one printing swath by Firmware. The vertical pitch (VP) in the diagram below is taken care of by the Firmware and the DMA operation. Then, Bi-level Resolution Conversion block fetches the line-based printing data through DMA operation. The linebased printing data is serially processed in the Bi-level Resolution Conversion block. The process order is bi-level resolution conversion -> singling -> horizontal shift -> oring (optional). After these processes, the shifted linebased print data will be put back to the printing buffer by the DMA operation. The nozzle pitch (NP) and horizontal pitch (HP) in the diagram below are taken care of by the horizontal shifter in the Bi-level Resolution Conversion block. For example, the NP is 8 pixels and HP is 18 pixels. We want to prepare the shifted line-based printing data for nozzle 1 of the top group in the diagram below, the horizontal shifter will insert (8+18) zeros in the beginning of this line. If we want to prepare the shifted line-based printing data for nozzle 2 of the top group in the diagram below, the horizontal shifter will insert 18 zeros in the beginning of this line. If we want to prepare the shifted line-based printing data for nozzle 1 of the middle group in the diagram below, the horizontal shifter will insert 8 zeros in the beginning of this line. If we want to prepare the shifted line-based printing data for nozzle 2 of the middle group in the diagram below, the horizontal shifter will insert nothing in the beginning of this line. The actual shifting amount for each line needs to be changed according to the inkjet head which you are using and the mechanical orientation. All the pixels needed for one firing cycle will be at the same column after the horizontal shift process. The number of zeros inserted in the beginning of lines is programmable from 0 to 63. If extra zeros (>63 ) are needed, multiple of 16 zeros need to be prepared into memory by firmware. Finally, the Bit Rotation block gets the shifted line-based printing data through the DMA operation. The Bit Rotation block groups 48 pixels at different lines and at the same column to 3-halfword data for one firing cycle (See the Bit Rotation section for details). 9-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 NP 1 3 5 7 1 line 2 lines 2 4 6 8 NP - Nozzle pitch in pels VP - Vertical pitch between nozzle groups in pels HP - Horizontal pitch between nozzle groups in pels. NG - Number of nozzles in nozzle group. NG-3 NG-1 NG-2 NG VP Note: Odd Nozzle Columns are located on the left in this figure. HP Figure 9-2. The Physical Nozzle Diagram for Typical Inkjet Heads The boundary condition also needs to be considered. The line length (pixels/line) of the bi-level resolution conversion input and output data is a multiple of 16 (See the bi-level resolution conversion section for details). If we insert different number of zeros in the beginning of lines, all the lines will end at different columns (not end at the same halfword boundary). Therefore, control bits need to be used. It indicates the total number of halfwords of zeros that needs to be added either at the beginning and at the end of each line (See the diagram below). 0 - 4 halfwords can be set in the register. Example: line1 line2 The register for the total zeros (halfwords) = 2, set for all lines The register for zeros in front (pixels) =26, 18, 8, or 0, set for each line 26 zeros 324 halfwords / line 324 halfwords / line 6 zeros 14 zeros 18 zeros line17 line18 8 zeros 324 halfwords / line 324 halfwords / line 26 zeros 24 zeros 32 zeros line33 line34 324 halfwords / line 324 halfwords / line Figure 9-3. Untitled Figure 6 zeros 14 zeros 18 zeros 100723A Conexant 9-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 9.1.5 First and Last Black Data Detector Design Below is a schematic representation of the Black Data Detector. The counter and registers get cleared at the start of each line. On the left side of the diagram is the half word counter that is incremented each time a half word is pushed into the FIFO (lcl_nxt). When the line starts, each time a lcl_nxt or lcl_wr shifts data into the output FIFO holding register, the serial data is checked for black data. If black data is detected, the End Of White flag is set. Once set, the logic waits until the counter is incremented, (the holding register is pushed into the FIFO data register). Then the new count value is loaded into the First Black Data Register. As data continues to be shifted into the FIFO, the logic at the bottom of the Figure 1-2-2 continues to check for black data. Each time black data is detected the Blk Data Det flag is set. After that half word is loaded into the FIFO data register (counter counts), the counter value is loaded into the Last Black Data Register. 9.2 Register Description External memory setup * * * * The external memory is selected as the data source by setting bit 2 in the BiResConvCtrl register to one in the Bi-level Resolution Conversion block. The block size of the data in the external memory for the Bi-level resolution conversion is set in the DMA9BlockSize register of the DMA Controller. Vertical Line ORing for the resolution converted data is enabled by setting bit 0 in the BiResConvCtrl register in the Bi-level Resolution Conversion block. The Bi-level resolution conversion is initiated by setting bit 1 (first to 1 and then, to 0) in the BiResConvCtrl register in the Bi-level Resolution Conversion block. T4/T6 Control * * T4/T6 Decoder Bi-level resolution conversion is enabled by setting bit 5 in the `T4Config' register in the T4/T6 Compression/Decompression Logic. Vertical Line ORing for the T4 Decoded data is enabled by setting bit 3 in the `T4Control' register in the T4/T6 Compression/Decompression Logic. Vertical ORing for T4 decoded data is only valid if resolution conversion is also enabled. Programming the Expansion/reduction Ratio The Bi-level Resolution Conversion Ratio register (BiResConRatio) controls the horizontal resolution conversion expansion or reduction ratio. The BiResConRatio register is cleared on Reset. The value programmed into the register is the number of pixels to add or remove per 2187 pixels (expressed as a 7 digit base-3 number). 9-6 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Input data FIFO Control register for the data from the external memory (for DMA channel 9): Address: Bi-level Resolution Conversion Input Data FIFO Control (BiRCInFIFOCtrl) $01FF807B Address: Bi-level Resolution Conversion Input Data FIFO Control (BiRCInFIFOCtrl) $01FF807A Bit 15 FIFO Enabled (R) Bit 14 Data Request (R) Bit 13 FIFO Ready (R) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst Value 00h Read Value 00h Default: Rst Value x0x00000b Read Value 00h FIFO DMA Threshold FIFO Output Pointer Bit 7 (Not Used) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Holding (Not Used) Register Full FIFO Data Quantity FIFO Input Pointer Bit 15 Bit 14 Bit 13 This bit indicates that the FIFO is active and capable of generating DMA requests. This bit is essentially a copy of the DMA Request output signal and indicates that the FIFO wishes to transfer data. This bit indicates that the FIFO can accept data transfers to/from the local logic. This bit is low when the data direction is into the local logic and the FIFO is empty or when the data direction is out of the local logic and the FIFO is full. This bit field indicates at which point the FIFO should issue a DMA request. It is compared with the FIFO Data Quantity bit field to determine when this should occur. Legal values are from 0 to 4. Values greater than 4 are treated as 4. This bit field indicates which byte of the FIFO quad halfword structure is the next to be used as output data. This bit indicates that there is a full word in the holding register This bit field indicates the number of quad halfwords that contain data. Valid values are from 0 to 4. This bit field indicates which byte of the FIFO quad halfword structure is the next to receive input data. Note: It is strongly recommended that the FIFO be disabled before firmware writes to the FIFO Control register. The FIFO Control register contains data that is essential to the FIFO's operation. If this data is changed while the FIFO is operating, unpredictable operation will result. Bit 12-10 Bit 9-8 Bit 6 Bit 4-2 Bit 1-0 100723A Conexant 9-7 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Input data Holding Register for the data from the external memory (for DMA channel 9): Address: Bi-level Resolution Conversion Input Data Holding Register (BiRCInHold) $01FF8079 Address: Bi-level Resolution Conversion Input Data Holding Register (BiRCInHold) $01FF8078 Bit 15 data bit 15 Bit 14 data bit 14 Bit 13 data bit 13 Bit 12 data bit 12 Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value 00h Read Value 00h Bit 7 data bit 7 Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 Default: Rst Value 00h Read Value 00h Input data FIFO halfword[3:0] for the data from the external memory (for DMA channel 9): Address: Bi-level Resolution Conversion Input Data FIFO (BiRCInFIFOx) Address: Bi-level Resolution Conversion Input Data FIFO (BiRCInFIFOx) Bit 15 data bit 15 Bit 14 data bit 14 Bit 13 data bit 13 Bit 12 data bit 12 Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value 00h Read Value 00h Default: Rst Value 00h Read Value 00h Bit 7 data bit 7 Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 Address assignment for input FIFO halfword[3:0] The Input FIFO halfword Input FIFO halfword 3 Input FIFO halfword 2 Input FIFO halfword 1 Input FIFO halfword 0 The register name BiRCInFIFO3 BiRCInFIFO2 BiRCInFIFO1 BiRCInFIFO0 Address 01FF8077-76 01FF8075-74 01FF8073-72 01FF8071-70 Output data FIFO Control register for the data to the external memory (for DMA channel 8): Address: Bi-level Resolution Conversion Output Data FIFO Control (BiRCOutFIFOCtrl) $01FF808B Address: Bi-level Resolution Conversion Output Data FIFO Control (BiRCOutFIFOCtrl) $01FF808A Bit 15 FIFO Enabled (R) Bit 14 Data Request (R) Bit 13 FIFO Ready (R) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst Value 00h Read Value 00h Default: Rst Value x0x00000b Read Value 00h FIFO DMA Threshold FIFO Output Pointer Bit 7 (Not Used) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Holding (Not Used) Register Full FIFO Data Quantity FIFO Input Pointer 9-8 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Bit 15 Bit 14 Bit 13 This bit indicates that the FIFO is active and capable of generating DMA requests. This bit is essentially a copy of the DMA Request output signal and indicates that the FIFO wishes to transfer data. This bit indicates that the FIFO can accept data transfers to/from the local logic. This bit is low when the data direction is into the local logic and the FIFO is empty or when the data direction is out of the local logic and the FIFO is full. This bit field indicates at which point the FIFO should issue a DMA request. It is compared with the FIFO Data Quantity bit field to determine when this should occur. Legal values are from 0 to 4. Values greater than 4 are treated as 4. This bit field indicates which byte of the FIFO quad halfword structure is the next to be used as output data. This bit indicates that there is a full word in the holding register This bit field indicates the number of quad halfwords that contain data. Valid values are from 0 to 4. This bit field indicates which byte of the FIFO quad halfword structure is the next to receive input data. Note: It is strongly recommended that the FIFO be disabled before firmware writes to the FIFO Control register. The FIFO Control register contains data that is essential to the FIFO's operation. If this data is changed while the FIFO is operating, unpredictable operation will result. Bit 12-10 Bit 9-8 Bit 6 Bit 4-2 Bit 1-0 Output data Holding Register for the data to the external memory (for DMA channel 8): Address: Bi-level Resolution Conversion Output Data Holding Register (BiRCOutHold) $01FF8089 Address: Bi-level Resolution Conversion Output Data Holding Register (BiRCOutHold) $01FF8088 Bit 15 data bit 15 Bit 14 data bit 14 Bit 13 data bit 13 Bit 12 data bit 12 Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value 00h Read Value 00h Bit 7 data bit 7 Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 Default: Rst Value 00h Read Value 00h 100723A Conexant 9-9 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Output data FIFO halfword[3:0] for the data to the external memory (for DMA channel 8): Address: Bi-level Resolution Conversion Output Data FIFO (BiRCOutFIFOx) Address: Bi-level Resolution Conversion Output Data FIFO (BiRCOutFIFOx) Bit 15 data bit 15 Bit 14 data bit 14 Bit 13 data bit 13 Bit 12 data bit 12 Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value 00h Read Value 00h Default: Rst Value 00h Read Value 00h Bit 7 data bit 7 Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 Address assignment for output FIFO halfword[3:0] The output FIFO halfword Output FIFO halfword 3 Output FIFO halfword 2 Output FIFO halfword 1 Output FIFO halfword 0 The register name BiRCOutFIFO3 BiRCOutFIFO2 BiRCOutFIFO1 BiRCOutFIFO0 Address 01FF8087-86 01FF8085-84 01FF8083-82 01FF8081-80 Bi-level Resolution Converter Ratio Registers: Address: Bi-level Resolution Conversion Ratio (BiResConRatio) 00FF807D Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst Value 00h Read Value 00h Add/Delete 729 or 1458 pixels per 2187 input pixels 0:= 0 pixels 1:= Not allowed 2:= 729 pixels 3:= 1458 pixels Bit 7 Bit 6 Add/Delete 243 or 486 pixels per 2187 input pixels 0:= 0 pixels 1:= Not allowed 2:= 243 pixels 3:= 486 pixels Bit 5 Bit 4 Add/Delete 81 or 162 pixels per 2187 input pixels 0:= 0 pixels 1:= Not allowed 2:= 81 pixels 3:= 162 pixels Bit 3 Bit 2 Add/Delete 1or 2 pixels per 2187 input pixels 0:= 0 pixels 1:= Not allowed 2:= 1pixels 3:= 2 pixels Add/Delete 27 or 54 pixels per 2187 input pixels 0:= 0 pixels 1:= Not allowed 2:= 27 pixels 3:= 54pixels Bit 1 Bit 0 Expansion/R Simple OR eduction Enable Mode 0=Exp. 1=Red. Address: Bi-level Resolution Conversion Ratio Control (BiResConRatio) 01FF807C Default: Rst Value 00h Read Value 00000000 b Add/Delete 9 or 18 pixels per 2187 input pixels 0:= 0 pixels 1:= Not allowed 2:= 9 pixels 3:= 18 pixels Add/Delete 3 or 6 pixels per 2187 input pixels 0:= 0 pixels 1:= Not allowed 2:= 3 pixels 3:= 6 pixels Bit 15-2 Bit 1 Bit 0 Sets Ratio for Reduction/Expansion of image data Sets Expansion or Reduction mode Turns on simple oring mode of 2 pixels for horizontal reduction 9-10 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Bi-level Resolution Conversion Control Register: Address: Bi-level Res. Conversion Control (BiResConCtrl) 01FF807F Address: Bi-level Res. Conversion Control (BiResConCtrl) 01FF807E Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 Flush FIFO (W) Flush Status (R) Bit 0 Enable Or of orig. line buffer with current scan line Default: Rst Value xxxxxxx0b Read Value 00h Default: Rst Value 00h Read Value 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Data Source Selection 0=T4/T6 1=Ext. Mem. Bit 1 New line Write 1 and then, 0 " convert a new line Expansion Mode 0 = 100% X < 200% 1 = 200% X < 300% 2 = 300% X < 400% ORing Threshold Setting 0= no threshold 1-7= threshold value 1-7 Bit 8 Bit 7-6 For write, 1 " flush FIFO. For read, 1 " flush needed. These two bits sets the resolution conversion hardware's expansion range. If the value of these two bits is `n' and the expected expansion ratio is X, the ratio `X-(n* 100%)' needs to be set into the BiResConRatio register. n = the threshold value for the ORing function, n = 0-7. It means that Oring is done to (n+1) contiguous 1's only when bit 0 is set to 1. Data Source selection When this bit is set to 0, data is serially from the T4/T6 decompressor. When this bit is set to 1, data is from the external memory through the DMA operation (DMA channel 9). Resolution Conversion Logic is reset. Firmware needs to write a 1 and then, immediately write a 0 to tell hardware to convert a new line. Enable OR of orig. line buffer with current scan line (ScanOrEnb) (This bit is only used when the external scan device is selected as the data source of the resolution conversion). 1 = enable Bi-level Vertical OR'ing of the scanner line buffer data. This bit can be used to accomplish normal mode OR'ing and vertical reduction. Bit 5-3 Bit 2 Bit 1 Bit 0 Convert a new line Note: If you don't want to do image expansion or image reduction, the resolution conversion ratio is 100%. You need to program bits[7:6] of the BiResConCtrl register to `00b' and program the BiResConRatio register to `0000h'. 100723A Conexant 9-11 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Shingling Mask Register: Address: Shingling Mask Register (ShinglingMask) $01FF808D Address: Shingling Mask Register (ShinglingMask) $01FF808C Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 Mask bit 11 Bit 10 Mask bit 10 Bit 9 Mask bit 9 Bit 8 Mask bit 8 Default: Rst Value xxxx1111h Read Value 0Fh Default: Rst Value FFh Read Value FFh Bit 7 Mask bit 7 Bit 6 Mask bit 6 Bit 5 Mask bit 5 Bit 4 Mask bit 4 Bit 3 Mask bit 3 Bit 2 Mask bit 2 Bit 1 Mask bit 1 Bit 0 Mask bit 0 This is a loadable circular right-shift register which firmware can load a mask. A 1 in a mask bit means to let that pixel pass through and A 0 in a mask bit means to block that pixel and output 0 for that pixel. The output of this shift register (LSB) gates with the serial data from the resolution convertor on each bi-level resolution conversion clock. The shift register is clocked in sync with the serial to parallel converter so that the mask rotates in sync with the serial data. This 12-bit shingling mask register supports 50, 33, and 25 percent shingling. For example, for the 33 percent shingling, firmware should load 001001001001, 010010010010, or 100100100100, depending on the scanline and pass in question. The number of zeros inserted in a line for the Horizontal Shifter: Address: The Number of Zeros in a line (HSZeroNo) $01FF808F Address: The Number of Zeros in a line (HSZeroNo) $01FF808E Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 data bit 2 Bit 9 data bit 1 Bit 8 data bit 0 Default: Rst Value xxxxx000b Read Value 00h Default: Rst Value xx000000b Read Value 00h Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 Bit 10-8 The total number of zeros (halfwords) in a line 0 = nothing is added 1 = 1 halfword (16 zeros) 2 = 2 halfwords (32 zeros) 3 = 3 halfwords (48 zeros) 4 = 4 halfwords (64 zeros) 5-7 = not used Bit 5-0 The number of zeros (pixels) in the beginning of a line, from 0 to 63 zeros Note: If value 5, 6, or 7 is put into this register, 4 halfword (64 zeros) will be used. 9-12 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 First Black Data: Address: Bit 15 Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value xxxx0000b Read Value 00h Default: Rst Value 00000000b Read Value 00h The First Black Data (Not Used) Location Count (FirstBlkDatCnt) $01FF806D Address: Bit 7 The First Black Data data Location Count bit 7 (FirstBlkDatCnt) $01FF806C Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 Bit 11-0 The First Black Data Location Gives the half word count that black data first appeared in output of the BRC. If the first half word contains black data the register will remain at 000H. If the second half word contains data the register will contain 0001H Etc. If black data in not present in the entire line (all white line), register will be equal to the line length. First Half Word Location = Register Value + 1. Note: Starting a new line will reset the counter Last Black Data: Address: Bit 15 Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value xxxx0000b Read Value 00h Default: Rst Value 00000000b Read Value 00h The Last Black Data (Not Used) Location Count (LastBlkDatCnt) $01FF806F Address: Bit 7 The Last Black Data data Location Count bit 7 (LastBlkDatCnt) $01FF806E Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 Bit 11-0 The Last Black Data Location Gives the half word count that black data last appeared in output of the BRC. If black data in not present in the entire line (all white line), register will read 000H. If only the first half word contains black data the register will read 001H. If the second half word contains data the register will contain 0002H Etc. If the last half word contains black data the register will be equal to the total number of half words out of the BRC for that line. Last Half Word Location = Register Value. Note: Starting a new line will reset the counter 100723A Conexant 9-13 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Total Colored Pixel Counter: Address: Bit 15 Bit 14 (Not Used) Bit 13 data bit 13 (TotalBlkDatCntr) $01FF806B Address: Bit 7 Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 Read Value 00h Default: Rst Value 00000000b Read Value 00h Bit 12 data bit 12 Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value xxxx0000b Total Colored Pixels (Not Used) Printer Total Colored Pixels data Printer (TotalBlkDatCntr) bit 7 $01FF806A Bit 13-0 Total Colored Pixel Counter Reading this register will return the total number of colored pixels printed since the last time the register was cleared. Writing to this register will clear it. 9-14 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 9.3 Resolution Conversion Programming Examples Figure 9-4 is a flowchart that shows the procedure for determining the resolution conversion register values for both expansion and reduction modes: Expand Expand or Reduce ? Reduce Compute pixels to add per 2187 input pixels: Int{[(Output-(m+1)*Input)/Input] * 2187 + 2/3} m: expansion mode Compute pixels to remove per 2187 input pixels: Int{[(Output-Input)/Input] * 2187} Represent pixels to add as a sum of numbers: (3**n) and ( 2 * (3**n) ) where n=0, 1, ... 6 Represent pixels to remove as a sum of numbers: (3**n) and (2 * (3**n)) where n = 0, 1, ...6 Fill in both registers according to sum and register definition Fill in both registers according to sum and register definition Notes: 1) Input = Input Resolution (number of pixels/input line) 2) Output = Output Resolution (number of pixels/output line) 3) For expansion, Output < (4*Input) 4) For reduction, Output < Input 5) For best results in reduction, (Input-Output)/Input <= 1/3 Figure 9-4: Resolution Conversion Programming The number of pixels to add in expansion mode is determined from the integer portion of: Pixels to add per 2187 input pixels = {[ (Output pixels per line - (m+1) * Input pixels per line)/input pixels per line ] * 2187 +2/3} m: the expansion mode Note: 2/3 is added in this equation in order to guarantee that the truncated result will be greater than or equal to the desired number of output pixels per line. The number of pixels to remove in reduction mode is determined from the integer portion of: Pixels to remove per 2187 input pixels = {[(Input pixels per line - Output pixels per line)/input pixels per line] * 2187} Note: For best results, the number of pixels removed (per 2187 pixels) in reduction mode should be less than or equal to 729. {i.e., [(Input Pixels - Output pixels)/Input pixels] < = 1/3} 100723A Conexant 9-15 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description The number of pixels to add or remove per 2187 pixels is next converted to a 7 digit base-3 number. Each digit in the Base-3 number is weighted as: MSD Digit n Weight 0 1/3 1 1/9 2 1/27 3 1/81 4 1/243 5 1/729 LSD 6 1/2187 Note: MSD = most significant digit, LSD = lease significant digit. Each digit can take on 3 possible values: 0, 1, or 2; corresponding to adding or removing (0, 1 or 2) * 3(6-n) pixels for every 37 input pixels or, equivalently, adding or removing 0,1, or 2 pixels for every 3(n+1) pixels. Note: The actual number of pixels output from the resolution conversion block will always be a multiple of 16 pixels. Example: Reduction of 2048 pixel/line to 1728 pixel/line (B4 to A4 Reduction) Given: Input Resolution = 2048 pixel/line Output Resolution = 1728 pixel/line Notes: 1. Output Resolution must be a multiple of 16. 2. (Input Resolution - Output Resolution)/Input Resolution < = 1/3 for best results (i.e., consecutive pixels will not be removed)) In this case, (Input Resolution - Output Resolution)/Input Resolution = 320/2048 = 5/32. Therefore, ideally 5 pixels will be removed for every 32 input pixels. Compute the number of pixels to remove per 2187 input pixels: Int{ [(Input-Output)/Input]*(2187) } = Int{ [(2048-1728)/2048]*(3**7) } = Int { [320/2048]*2187 } = Int { 341.71875 } = 341 Therefore, 341 pixels will be removed for every 2187 input pixels. Represent the number of pixels to add per 2187 input pixels using powers of 3: Using Figure 9-1 determine which combination of powers of 3 digits are required to represent 341. The table should be filled from top to bottom. The sum of the enabled digits should equal 341 as illustrated below: 341 = 243 + 81 + 9 + 6 + 2 Therefore, digits 243, 81, 9, 6, and 2 should be enabled in the table. 9-16 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 9-2: Procedure to determine Pixels to remove Pixels to Remove per 2187 Input Pixels 1458 729 486 243 162 81 54 27 18 9 6 2 1 Yes/No N N N Y N Y N N N Y N Y N Table 9-3 lists common resolution conversion values. Table 9-3: Resolution Conversion Examples Conversion dots/inch 200 to 300 200 to 300 200 to 360 200 to 600 200 to 720 200 to 300 200 to 360 200 to 600 200 to 720 200 to 200 Input dots/line 1728 1728 1728 1728 1728 2048 2048 2048 2048 2048 Output dots/line 2456 2400 2952 3280 3280 2456 2952 3280 3280 1728 Ideal # of pixels/line to insert (remove) 728 672 1224 1552 1552 408 924 1232 1232 (320) Pixels to insert (remove) per 2187 922 851 1549 1964 1964 436 966 1316 1316 (341) ResConMSD (hex value) $8E $8A $C8 $F0 $F0 $2E $8F $B8 $B8 $28 ResConLSD (hex value) $28 $AC $88 $CC $CC $28 $E0 $CC $CC $BE 100723A Conexant 9-17 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description This page is intentionally blank 9-18 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 10. External Print ASIC Interface The interface signals used between the MFC2000 and the external Print ASIC are described in this section. They are basically the external ARM system bus interface signals. Conexant's Alcore chip is an external Print ASIC and it has the P1284 master port to talk to the P1284 slave port in the Printer. 10.1 Interface Between the MFC2000 and External Print ASIC The MFC2000 ASIC is the master that controls the system bus and all other control signals. The MFC2000 firmware configures and controls the external Print ASIC by setting registers in the external Print ASIC through the system bus. See Figure 10-1. AUXCLK can be used as the clock base for the external Print ASIC. No matter AUXCLK or external OSC is used for the external Print ASIC, the external Print ASIC needs to resynchronize all the signals and accesses for the metastable problems caused by different clocks. The MFC2000 internally uses SIUCLK and ICLK which are different from the external Print ASIC. The interrupt PRTIRQn is used to tell the MFC2000 that further settings or actions are needed for the external Print ASIC. The register bits in the external Print ASIC may be used to indicate which settings or actions need to be performed. If the extra interrupt channel is required, the external IRQ13n and IRQ11 can be also used for the external Print ASIC. These three interrupt input signals are resynchronized twice for the metastable issues. The external Print ASIC needs to be designed with the compatible CPU read/write bus timing and DMA bus timing used in the MFC2000 ASIC. The external DMA channel between the MFC2000 ASIC and the external Print ASIC is DMA channel 2. The external Print ASIC may get the print data from the bit rotation block if the bit rotation block is used or get the print data from the external memory if the bit rotation is done by host or the external Print ASIC. 1. The external Print ASIC gets the print data from the external memory. When the external Print ASIC generates the DMA request (DMAREQ2) to request the printing data, the MFC2000 will respond with the DMA acknowledge (DMAACK2) at the valid access cycle. At the same cycle, the MFC2000 will generate the read strobe, address, and the external chip select signals to read one byte or halfword of print data out of the external memory and put on the data bus. At the rising edge of the read strobe when DMAACK2 is high (DMAACK acts as a chip select), the external Print ASIC latches this one byte or halfword printing data in. If additional data bytes or halfwords are required by the external ASIC, it may leave the DMAREQ2 active. If no additional data is required, the ASIC should pull the DMAREQ2 inactive immediately after DMAACK goes low. DMA address will be incremented, decremented, or jumped during the DMA operation according to the fetch order of the print data in the external memory (See the DMA Controller Section). Note: No matter the data bus is byte or halfword wide, the memory data bus size must match with the data bus size of the external Print ASIC. The Endian control bit for the DMA2 needs to be 0. The Endian mode can't be changed during the DMA operation. 2. The external Print ASIC gets the print data from the bit rotation block. When the external Print ASIC generates the DMA request (DMAREQ2) to request the printing data, the MFC2000 will respond with the DMA acknowledge (DMAACK2) at the valid access cycle after the print data ready in the output register of the Bit Rotation Block. At the same cycle, the MFC2000 will generate the read strobe, address, and internal chip select signals to read one halfword of print data out of the output register of the Bit Rotation block and put on the data bus. The MFC2000's SIU may generate two access cycles for the byte-wide external data bus (the bit 8 of the DMA2Config register needs to be set to 0) or one access cycle for the halfword-wide external data bus (the bit 8 of the DMA2Config register needs to be set to 1). At the rising edge of the each read strobe when DMAACK2 is high (DMAACK acts as a chip select), the external Print ASIC latches this one byte or halfword printing data in. If additional data bytes or halfwords are required by the external ASIC, it may leave the DMAREQ2 active. If no additional data is required, the ASIC should pull the DMAREQ2 inactive immediately after DMAACK goes low. The DMA address is fixed during the DMA operation (See the DMA Controller section and the Bit Rotation section). 100723A Conexant 10-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description * CS4n, CS3n, or CS2n may be used as the chip select signal for accessing registers in the external Print ASIC (See Memory Map Section) AMFPC AUXCLK PRTIRQn DMAREQ2 DMAACK2 Print ASIC System Data Bus System Address Bus CS Figure 10-1. Print ASIC Interface 10.1.1 Examples 10.1.2 Motor Control Examples of the Inkjet Print Head Module Vertical Movement The vertical motor stepping control logic in the MFC2000 may be used for the Inkjet printing (See Section 12.1). For Laser printing, this internal vertical motor stepping control logic is not used. Horizontal Movement The horizontal stepper motor control logic or the horizontal DC motor control logic should be in the external print ASIC. Whenever the external print ASIC needs the new timer value(s) or the PWM value(s) which is used to control the time interval between steps or the DC motor speed, the external print ASIC generates the interrupt (PRTIRQn) to the MFC2000 ASIC. Then, the MFC2000 CPU will write the new timer value(s) to the register(s) in the external print ASIC in the interrupt subroutine. 10-2 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 11. Bit Rotation Logic 11.1 Functional Description Bit Rotation Logic is responsible for preparing line-based image data to be used for a color or mono inkjet head. It is designed to be completely universal, so that any inkjet head may be supported regardless of nozzle configuration, provided there is only one nozzle per line of the printed image. An example of a typical 3-color inkjet head is shown. NP 1 3 5 7 2 lines Color1 NG-3 NG-1 2 4 6 8 1 line NP - Nozzle pitch in pels VP - Vertical pitch between nozzle groups in pels HP - Horizontal pitch between nozzle groups in pels. NG - Number of nozzles in nozzle group. NG-2 NG VP Color2 Color3 HP Figure 11-1. Nozzle Diagram of a Typical Programmable Inkjet Head The inkjet head shown is only an example. There are many other configurations that may be supported. The BiLevel Resolution Conversion block works in conjunction with firmware to ensure that all parameters that correspond to nozzle shifts are removed before the image data is deposited in the swath buffer for removal by the Bit Rotation Block. In addition, the Bit Rotation block does not need to distinguish the difference between mono or inkjet color modes. A few examples of nozzle configurations that can be supported are shown in the figures. These are only to show examples of the universal design. 100723A Conexant 11-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Line 1 Line 2 Line 3 etc... Nozzle Example A Nozzle Example B Figure 11-2. Examples of Nozzle Head Configurations Because the firmware and Bi-Level Resolution Conversion block work in conjunction to remove all nozzle shift parameters, the Bit Rotation Block may always view the data in such a way that it views the nozzles as always being one column of N nozzles, where N corresponds to the number of nozzles on the inkjet head itself. In fact, the only configuration information that the Bit Rotation block needs to know is the number of nozzles on the inkjet head, the shuttle direction, the width of the line being printed, and the warp. The figure shows how the Bit Rotation Block views the swath regardless of the actual physical nozzle configuration. Line 1 Line 2 Line 3 N = Number of nozzles in inkjet head Line N Figure 11-3. Nozzle Configuration by Bit Rotation Block (Regardless of Physical Nozzle Configuration) The BRB works in conjunction with 2 DMA channels of the DMA controller. Within the MFC2000, the DMA channels used are channels 2 and 3. Channel 3 is used to "fetch" data from the external swath buffer that resides in the system's image memory, and is referred to as the Swath Fetcher DMA channel from here on. DMA Channel 2 is used to transfer "packed" or rotated image data to the External Print ASIC, and will be referred to as the Bit Packer DMA channel from here on. The BRB uses a local memory (in the BRB block) to perform its rotation operation. Words are "fetched into the local memory, and then bits are picked out of the halfword and then "packed" or shifted into an output register, in effect, rotating the swath image data by 90 degrees. The internal buffer size within the Bit Rotation Block is 512 x 1 halfword (16 bits). This buffer is further subdivided into two separate 256 x 16 bit "banks" for reasons of system performance. While one 256 x 16-bit buffer is being operated upon, the other 256x16-bit buffer may be filled by the Fetcher DMA channel. Because of this, the system only needs to keep up with the print rate, which in the worst case scenario, is 256 bits every fire cycle if 256 nozzles are used. 11-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Once the data is prepared for output by the Bit Rotation Block, it may be retrieved by the External Print ASIC via the Bit Packer DMA channel. The BRB issues the ready signal to indicate that a halfword of data is ready for retrieval to the DMA Controller. Then, the DMA Controller will grant the DMA channel 2 access cycle by activating the DMAACK2 when system bus is available if DMAREQ2 is active and BRB output ready signal is active. 11.2 Block Diagram A high-level block diagram of the Bit Rotation Block is shown. Note that the internal RAM is double-banked, so that these operations of fetching and packing can occur simultaneously (however, they are not allowed to occur to/from the same bank at the same time). brb_regsThis block is used to hold the internal registers of the BRB. The registers are split into setup registers, operation registers, and test registers. Each group has a separate chip select sent by the SIU. brb_memifThis block has three separate interfaces: the SIU, the Swath Fetcher, and the Bit Packer. If a bit rotation operation is in progress (rotateStart = 1 in the RotCtrl register), SIU local memory access is locked out, and only the swath Fetcher and Bit Packer blocks may access the memory at this time. If the rotateStart bit is not set, then the SIU has access to the 1 kB memory through locations 01FF9000h-01FF93FFh. Swath FetcherThis block works in conjunction with channel 3 of the DMA Controller to transfer image data from the swath buffer to the local SRAM for Bit Rotation. Bit PackerThis block is responsible for the actual rotation of image data. It performs this rotation by picking bits out the local SRAM and constructing the final rotated output data for the External Print ASIC. brbsyncThe brb_regs and Swath Fetcher blocks operate at the SIUCLK frequencies, while the Bit Packer and the brb_memif blocks operate at IHSCLK frequencies. The purpose of this block is to synchronize communications between the internal blocks of the BRB. siuclk ihsclk resn DMA control and handshaking signals Swath Fetcher Bit Packer brbsync BRB Control and register rd/wr signals ipb_di[15:0] ipb_do[15:0] Control, Status , and Data Registers BRB Local SRAM Memory Controller BRB local memory access control signals Data Mux BRB Block 512 x 16 Local SRAM Figure 11-4. MFC2000 Bit Rotation Block Diagram 100723A Conexant 11-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 11.2.1 Swath Fetcher The Swath Fetcher block is responsible for initiating as well as controlling the order of the transfer of data from the swath buffer to the internal RAM of the Bit Rotation Block. There are several control signals provided to the Swath Fetcher DMA channel for controlling what order the channel will read data out of image memory. The Fetcher DMA will not support burst mode. This is due to the fact that in order to use burst mode, the DRAM that comprises the image memory must be accessed using page mode. When accessing DRAM for the Bit Rotation block, the sequential data stream rarely contains elements out of the same page of DRAM. Because of this, in most cases, only single-access cycles can be realized when reading data out of the image memory for the Bit Rotation Block. The order in which data is fetched out of the swath buffer depends on shuttle direction only. The way data is fetched out of the swath buffer is best described pictorially. In the figure, each cell corresponds to a halfword (16 bits) in memory. The gray portion represents the printable image region, and a full line corresponds to the warp of the swath buffer. The general order in which halfwords are fetched from the swath buffer is indicated by the arrows. The starting address value that the firmware must program into the Swath Fetcher DMA channel depends on the shuttle direction. While printing in a left-to-right fashion (when viewing the print on the page), the value must correspond to the halfword of the upper left-hand corner of the image in the swath buffer (in the example shown, this address would be base+6H. While printing in a right-to-left fashion, the value must correspond to the upper right-hand corner of the image (in the figure, this would be base+AH). The value that would be programmed in the Rotation Line Length (RotLine) register in this example would be 0005H (one less than the actual number of bytes that comprise the image). base+2H base+4H base+6H base+8H base+AH base+CH base base+warp base+2*warp base+3*warp base+4*warp base+5*warp base+warp-2H Left-to-Right Shuttle Direction Fetch Order base+(NG-1)*warp base+2H base+4H base+6H base+8H base+AH base+CH base base+warp base+2*warp base+3*warp base+4*warp base+5*warp base+warp-2H Right-to-Left Shuttle Direction Fetch Order base+(NG-1)*warp Figure 11-5. Fetcher DMA Channel Fetch Order 11-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 11.2.2 Bit Packer The Bit Packer block is responsible for performing the actual rotation of the image data. It accomplishes this task by "picking" the bits out of the internal Bit Rotation RAM one bit at a time and packing them into the appropriate format such that the final output image is rotated 90 degrees. The Bit Packer circuits also contain the bit counter that describes the total number of printable bytes contained in the swath. The overall control of the print operation is controlled by this block. The parameters that are required by this block are: the Line Length (LL), the Nozzle Number (NN), the shuttle direction, and the packing order. In addition, this circuit also detects when there is an underrun condition. An underrun condition occurs when the system is not able to keep up with the print rate. Finally, the interface to the External Print ASIC is provided by this block. 11.2.3 Local Bit Rotation RAM This memory is 512x16. Functionally, this memory consists of 2 banks of 256x16 memories, and only one of these buffers is used at a time for rotating image memory data. The double-buffering is used for reasons of system performance. When using the double-buffering mechanism, the system only needs to transfer the data at a rate that corresponds to the print rate. This is due to the fact that while one bank is being loaded with swath data, the other bank is being operated upon, or rotated and shipped to the External Print ASIC. This memory is accessible by three resources: the SIU, the Swath Fetcher, and the Bit Packer. When a bit rotation operation is in progress (when rotateStart in the ROTCTRL register is set to 1), then the SIU may not access this memory. During this time, both the Swath Fetcher and the Bit Packer may access this memory, but not the same bank simultaneously. When no bit rotation operation is in progress (the rotateStart bit is set to 0), then only the SIU has access to this memory through address locations 01FF9000h-01FF93FFh. 11.2.4 BRB Local SRAM Memory Controller (brb_memif) The brb_memif block is responsible for controlling all accesses to Local BRB SRAM. During Bit Rotation operation, it will lock out all SIU accesses. At this time, it will allow both the Bit Packer and the Swath Fetcher blocks to access the SRAM. The Swath Fetcher block is a write-only resource, and the Bit Packer is a read-only resource. Arbitration to the SRAM by each of these resources is controlled with a rotating priority to ensure that neither the Swath Fetcher or the Bit Packer get locked out for any length of time. 11.2.5 Control, Status, and Data Registers (brb_regs) This block provides all required registers used in Bit Rotation operation. These registers are described in detail later in section 11.3. The functional registers are spilt into two separate areas: Operation registers, and Setup registers. The Operation registers are those registers that are meant for access during Bit Rotation. The Setup registers are those register that are intended to be used once to set up the next print swath for printing. The Operation registers for the Bit Rotation block are located at 01FF8060h-01FF806Fh, however, only locations 01FF8060h-01FF8063h are used. The Setup Registers are located at 01FF8870h-01FF888Fh, however, only locations 01FF8870h-01FF8875h are used. The registers are summarized. Register Address 01FF8060h 01FF8874h 01FF8870h 01FF8872h 01FF8062h Register Name Rotation Control - RotCtl Rotation Line Length - RotLine Nozzle Number - RotNN BRB Warp - BRBWarp Packing Register - RotPack Summarized Description Provides programmability of parameters, initiates Rotation, and provides status. Contains the value of the line length in terms of bytes. Provides programmability of number of nozzles on inkjet head. Provides programmability of swath warp in increments of 32 bytes, up to 4096 bytes. Provides the data for the External Print ASIC 100723A Conexant 11-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 11.2.6 BRB Synchronization The Swath Fetcher and the brb_regs blocks operate at SIUCLK frequencies, while the brb_memif, and the Bit Packer circuits operate at ihsclk frequencies. The reason for this is to control power consumption and noise, as the higher SIUCLK frequency is not required for operation of the Bit Packer and the BRB Local SRAM Controller. Because of these different frequencies, a synchronization block is required to allow these blocks to communicate in a reliable fashion. 11.3 Register Description Rotation Control Register Address Rotation Control Register (RotCtrl) 01FF8061 Bit 15 Bit 14 Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 Default Rotate Start (Not Used) (W) Rotate Status (R), 1:busy (Not Used) Rst. Value 0xxxxxxxb Read Value 00h Address Rotation Control Register (RotCtrl) 01FF8060 Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 Packing Order 0: odd then even 1: even then odd Bit 2 Underrun 0: No underrun 1: Underrun occurred. Bit 1 Packed-byte status 0: not ready 1: ready Bit 0 Shuttle Direction 0: Left to Right 1: Right to left Default Rst. Value xxxx0000b Read Value 00h Bit 15 To start the bit rotation function, the CPU should write a 1 to this bit location. Reading this bit location indicates the status of the block rotation function. 0 = Not busy, 1 = busy. This bit will be set to 0 at the end of a print swath, and all bit rotation circuits will be reset with the exception of the BRB registers. If an unrecoverable error condition occurs within the system, then the BRB block may be reset by creating a falling edge on the RotateStart bit. Not used The packing order allows the order of the groups of odd and even bits to be switched. Bit 3 = 0 => Odd bit is output first. 18 nozzles Bit 15 2nd DMA Ch2 halfword n17 n18 Bit 14-4 Bit 3 Bit 0 x x x x x x x x x x x x x x 1st DMA Ch2 halfword n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 n16 Bit 3 = 1 => Even bit is output first 11-6 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 18 nozzles Bit 15 2nd DMA Ch2 halfword n18 n17 Bit 0 x x x x x x x x x x x x x x 1st DMA Ch2 halfword n2 n1 n4 n3 n6 n5 n8 n7 n10 n9 n12 n11 n14 n13 n16 n15 Bit2 This bit indicates whether a print underrun condition has occurred. Basically, an underrun condition exists if the system is not able to keep up with the print rate. Once a halfword has been packed and is ready for output to DMA channel 2, a 1 will be indicated in this bit of the register. This bit directly reflects the state of the output signal brb_ch2rdy, and is intended only for status purposes. Once the data has been read, the bit is cleared automatically. The bit is also reset by creating a falling edge on the RotateStart bit. This bit is written by the CPU and indicates which direction the print head is moving as viewed when looking at the print on the page. 0 = left to right shuttle motion 1 = right to left shuttle motion Bit 1 Bit 0 Rotation Line Length Register Address Rotation Line Length Register (RotLineLength) 01FF8875 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 LL10 LL9 Bit 9 Bit 8 LL8 Default Rst. Value xxxxx000b Read Value 00h Address Rotation Line Length Register (RotLineLength) 01FF8874 LL7 Bit 7 Bit 6 LL6 Bit 5 LL5 Bit 4 LL4 LL3 Bit 3 LL2 Bit 2 LL1 Bit 1 Bit 0 LL0 Default Rst. Value 00h Read Value 00h Bits 15-11 Bits 10-0 Not used The value in this field indicates the length in bytes of the actual printable data. The value programmed into this register is one less than the actual value in bytes. The printable data in a swath can be between 1 and 2048 bytes. 100723A Conexant 11-7 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Rotation Nozzle Number Register Address Rotation Nozzle Number Register (RotNN) 01FF8871 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 Default (Not Used) Rst. Value xxh Read Value 00h Address Rotation Nozzle Number Register (RotNN) 01FF8870 Bit 7 NN7 Bit 6 NN6 Bit 5 NN5 Bit 4 NN4 Bit 3 NN3 Bit 2 NN2 Bit 1 NN1 Bit 0 NN0 Default Rst. Value 00h Read Value 00h Bits 15-8 Bits 7-0 Not used This value describes the total number of nozzles on the inkjet head. The value written into this register is one less than the actual number of physical nozzles. The total number of nozzles that can be supported is between 1 and 256. BRB Warp Address BRB Warp Register (BRBWarp) 01FF8873 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 BW11 Bit 10 BW10 Bit 9 BW9 Bit 8 BW8 Default Rst. Value xxxx0000b Read Value 00h Address BRB Warp Register (BRBWarp) 01FF8872 Bit 7 BW7 Bit 6 BW6 Bit 5 BW5 Bit 4 (Not Used) Bit 3 (Not Used) Bit 2 (Not Used) Bit 1 (Not Used) Bit 0 Default (Not Used) Rst. Value 000xxxxxb Read Value 00h Bits 15-12 Bits 11-5 Not used These bits are used to define the warp of the swath, or the actual jump line size. The smallest resolution of the warp is 32 bytes. The value that is written into this register is the actual value that will be used in the jump. The warp value can range from 0000h to 0FE0h. Not used Bits 4-0 11-8 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Packing Register Address Rotation Packed Data Register (RotPackedData) 01FF8063 Bit 15 RP15 Bit 14 RP14 Bit 13 RP13 Bit 12 RP12 Bit 11 RP11 Bit 10 RP10 Bit 9 RP9 Bit 8 RP8 Default Rst. Value 00h Read Value 00h Address Rotation Packed Data Register (RotPackedData) 01FF8062 Bit 7 RP7 Bit 6 RP6 Bit 5 RP5 Bit 4 RP4 Bit 3 RP3 Bit 2 RP2 Bit 1 RP1 Bit 0 RP0 Default Rst. Value 00h Read Value 00h Bits 15-0 This register shows the contents of the halfword content that will be sent to the External Print ASIC via the Bit Packer DMA controller channel. 100723A Conexant 11-9 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 11.4 Firmware Operation 11.4.1 Bit Rotation Setup and Operation The following describes how to setup and operate the Bit Rotation Block for printing of image swaths. The following example assumes that there is a 8Mbyte DRAM residing in bank 0 of the system in question. It is also assumed that the swath buffer that resides in this DRAM is located at the base address of this device and grows up. Since the memory grows down from address 03000000h, the base address for the DRAM is at 02800000. In addition, I am assuming that the image that is to be printed is 72 bytes wide, has a warp of 96 bytes, shuttle direction is right-to-left, and the number of nozzles is 56. Program the DMA Controller - Channel 2 and 3 1. Program the address of the Bit Rotation Packing Register (01FF8062h) into the DMA High Address Counter (01FF818Ah) and the DMACNT2LO (01FF8188h) and the DMA2CNTHI (01FF818Ah) registers: (DMACNT2LO) <= 8062h; (DMACNT2HI) <= 01ffh; 2. Program the DMA2CONFIG register (01FF81B2h). It must know that it is being used for Bit Rotation as well as for reads and halfword mode: (DMA2CONFIG) <= 0180h; 3. Program the DMA Channel 2 block size. Here, we set up for unlimited block size. Bit 15 is the enable bit for this channel. (DMA2BLKSIZE) <= 8000h; 4. The only registers that you need to program the DMA Channel 3 controller with is the address of the image memory: Since the shuttle direction is right-to-left, we must initialize these registers with the upper right-hand corner of the swath buffer. (DMA3CNTLO) <= 0046h; (DMACNT3HI) <= 0280h; Program the BRB 1. First, load the Rotation Line Length Register (ROTLINE - 01FF8874h) with one less than the length of the image which would be 72 bytes - 1 = 71 = 47h. (ROTLINE) <= 0047h; 2. Program the BRBWARP (01FF8872h) register with the actual warp value. Here, the warp is 96 bytes = 60h. (BRBWARP) <= 0060h; 3. Program the Nozzle Number into ROTNN (01FF8870h) with the number of nozzles -1. In this case, the actual number of nozzles is 56. So, we need to program the ROTNN with 56 - 1 = 55 = 37h. (ROTNN) <= 0037h; 4. Program the ROTCTRL (01FF8060h) with the proper value. In this case, the shuttle direction is right-to-left. (ROTCTRL) <= 8001h; Once the Rotation bit has been set, then Bit Rotation starts. The status bit (bit 15 of ROTCTRL) may then be polled to determine when the swath is completed with printing. On the next shuttle stroke, Only the address in channel 3 of the DMA controller needs to be changed as well as the shuttle direction bit within the ROTCTRL register. These should be the only parameters that need to change, once the initial parameters have been set up. 11-10 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 11.4.2 Swath Loader Requirements (Software Issues) Due to the fact that the color nozzles are staggered as well as the fact that there is a physical separation VP of the color groups themselves, there are very special requirements imposed on the swath loader. In a situation where the mode is black only, then a minimum of two block buffers within image memory are required. This is due to the fact that while one block buffer is being printed, the other buffer may be simultaneously filled by the image loader. Color mode is quite different from black-only print mode. In color mode, three separate colors are used: yellow, magenta, and cyan. The order of these colors may differ from one printhead to another. This is why the colors have been assigned simply as "Color1", "Color2", and "Color3" in Figure 11-1. On the first print swath of a page, Color3 is printed. On the next print block, Color3, and NG-VP + 1 nozzles of Color2 are printed. On the third pass, Color3, Color2, and NG-(2*VP) + 1 nozzles of Color1 are fired. In looking at this pattern, we see that two buffers are required to deal with printing Color3 (one block history required), three buffers are required in printing Color2 (two block history required), and four buffers are required in printing Color1 (three block history required). Peerless PCL has a limitation that the color blocks that comprise the image data cannot be easily split up in order to take into account the VP parameter. The color data must be contiguous within the blocks. Due to this fact (along with the fact that the CPU may need to perform some preprocessing of the image prior to printing), the color buffers that are provided for use by the Bit Rotation Block are prepared by the CPU in the background. The figure shows the typical preparation of these buffers in the background by the CPU. Note: Before scanning starts, the two prepared color buffers must be zero-filled by the CPU for reasons of top-of-page boundary conditions. If, at the end of the printed page, there are fewer lines than the number in the prepared buffers, then the remainder of the prepared buffers must be zero-filled to account for bottom-of-page boundary conditions. 100723A Conexant 11-11 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Note: Each Buffer is NG Lines deep Note: This example shows what these buffers should look like if printing swaths 3 and 4 starting with swath 1. Two buffers prepared in background by CPU Color 3, Buffer 0, lines 0 to NG Color3, Buffer 0 Color3, Buffer 1 Color 2, Buffer 1 Lines 0 to NG-VP lines 0 to (2*VP) - 1 are zero-filled. Color 1, Buffer 0, lines 0 to NG - (2*VP) . Color 2, Buffer 0 Lines NG-VP+1 to NG Data Buffers Dynamically Allocated by CPU for swath 3 Color2, Buffer 0 Color2, Buffer 1 Color 2, Buffer 2 for swath 4 Color 3, Buffer 1, lines 0 to NG Color 2, Buffer 1, lines NG - (VP+1) to NG. Color 2, Buffer 2, lines 0 to NG-VP. Color 1, Buffer 0, lines NG - (2*VP) + 1 to NG. Color 1, Buffer 1, lines 0 to NG - (2*VP) . Color1, Buffer 0 Color1, Buffer 1 Color1, Buffer 2 Color1, Buffer 3 Note: NG is one less than the physical number of nozzles in the color group. VP is the vertical distance between nozzle groups Figure 11-6. CPU Background Print Data Preparation During black-only printing, the two buffers that are prepared for color printing simply become the two buffers that are used for the black-only print mode. Each of these buffers will contain as many lines as there are nozzles on the printhead. Image Format The data that is presented to the Bit Rotation Block is always in little-endian format. The data within the system is in 2 separate formats: big-endian and little-endian. However, if the data in image memory is in big-endian format, then the SIU will translate that data to a little-endian format during the DMA operation with the endian conversion bit enabled, to ensure that the Bit Rotation Block only needs to deal with little-endian formatted data. The little endian format that the Bit Rotation Block expects to see is shown in the following illustration: 11-12 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Image Memory Increasing Addresses b 7 Byte 0 b 0 b 7 Byte 1 b 0 b 7 Byte 2 b 0 b 7 Byte 3 b 0 b 7 Byte 4 b 0 P15 P16 P23 P24 P31 P32 P7 P8 P47 0 P0 byte lineSize byte lineSize*2 AMFC LittleEndian Format Figure 11-7. MFC2000 Little-Endian Format 100723A Conexant 11-13 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description This page is intentionally blank 11-14 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 12. Printer and Scanner Stepper Motor Interface 12.1 Vertical Print Stepper Motor Interface 12.1.1 Vertical Print Stepper Motor Control Description The stepper motor can be controlled by this block to run at constant speed, increasing speed (acceleration), or decreasing speed (deceleration). The control logic is based on a loadable step timer and a step timer register. A pulse and interrupt are generated when the step timer expires (timed-out) and at the same time, the content of the step timer register is automatically loaded into the step timer. The pulse is used to change the phase pattern to the next one in the Motor Pattern Control Sub-block and the interrupt is used to inform CPU to load the new step timer value to the step timer register if necessary for the step after the next step (See Figure 12-1). MFC2000 Chip The Vertical Printer Motor Control Block External Circuit Internal Bus Interface and VPM Logic Control VPM_PWRCTRL motor moving clock (MMCLK) STEPCLK divider stepping clock (STEPCLK) Motor Timer Motor Pattern Control External Motor Driver stepping pulse (STEPPULSE) Motor vertical print stepping interrupt (VPSTEPIRQ) Figure 12-1. Vertical Printer Motor Control Block Diagram The printer motor control lines are the four pins PM[3:0]/GPO[3:0]. These pins are selected as printer motor control lines when bit 0 in the GPIOconfig register is set to 0 (default), and are selected as GPO's when this bit is set to 1. The printer pattern or GPO data is output on pins PM[3:0]/GPO[3:0] from bits [3:0] (VPMF[3:0]) of the VPMPattern register. When selected as GPO's, data written by CPU to the VPMPattern register is immediately output on the GPO pins and output data are not changed unless CPU writes another new data to the VPMPattern register. When selected as printer motor control lines, data is not allowed to be written to the VPMPattern register no matter whether the motor stepping is disabled or enabled. At the beginning of the motor moving process, CPU needs to write the stepping mode and the stepping direction to the VPStepCtrl register, the initial vertical print motor pattern to the VPMPattern register, and the 1st step timer value to the VPStepTimer register (used to define the time interval between enabling stepping and the 1st step). 100723A Conexant 12-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Caution: The vertical print motor pattern register (VPMPattern register) can only be written when it is used as the GPO function. In other words, bit 0 of the GPIOConfig register is set to 1. Then, CPU sets bit 0 of the GPIOConfig register to 0 and enables the vertical print motor stepping. The content (the 1st step timer value) of the step timer register is automatically loaded into the step timer and at the same time an interrupt is generated (the step pulse is blocked at this time). CPU writes the 2nd step timer value into the step timer register in the stepping interrupt routine. When the step timer expires (timed-out), A pulse is generated to change the phase pattern to the next one (the 1st step) and the content (the 2nd step timer value) of the step timer register is automatically loaded into the step timer and an interrupt is generated to inform CPU to load the 3rd step timer value to the step timer register. At the near end of the motor stepping, a pulse is generated to change the phase pattern to the next one (the `n-2' step, n: the last step) and the content of the step timer register (the time interval between the `n-2' and `n-1 steps) is automatically loaded into the step timer and an interrupt is generated to inform CPU to load the last step timer value to the step timer register when the step timer expires (timed-out). When the step timer expires again (timedout), A pulse is generated to change the phase pattern to the next one (the `n-1' step) and the content (the last step timer value) of the step timer register is automatically loaded into the step timer and an interrupt is generated to inform CPU to load the large dummy timer value to the step timer register. Finally, a pulse is generated to change the phase pattern to the next one (the last step) and the content (the large dummy timer value) of the step timer register is automatically loaded into the step timer and an interrupt is generated to inform CPU to disable the motor stepping. The step timer is cleared to 0 and the stepping pulse is blocked immediately after CPU disables the motor stepping. The step enable bit in the VPStepCtrl register only controls if the motor pattern is allowed to change to the next one. The motor pattern in the VPMPattern register always goes out. CPU has the responsibility to write value `00h' to the VPMPattern register or set bit 4 of the VPStepCtrl register to a proper value according to the external power control circuit for not driving the vertical print motor. Bit 4 value of the VPStepCtrl register directly goes out of the MFC2000 chip through the GPIO[13]/SASTXD/PMPWRCTRL pin. Caution: The GPIO[13]/SASTXD/PMPWRCTRL pin can only be used as the PMPWRCTRL pin when bit11 of the GPIOConfig1 register is `0' and bit 12 of the GPIOConfig1 register is `1'. The time interval between two adjacent stepping pulses (for example, t1 and t2) is determined by the timer value. The min. time difference between two adjacent stepping pulses (It is called the timer resolution, for example, t = | t2-t1|.) is determined by the frequency of the stepping clock (See Figure 12-2). STEPPULSE (in the speed-up period) t1 t2 time is controlled by the step timer Figure 12-2. Stepping Timing 12-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 The change sequence of the phase pattern in the Motor Pattern Control Sub-block is as follows: after the CPU gives the initial phase pattern (any column in the following tables), the phase pattern will automatically change to the next one after getting the time-out pulse of the timer (the stepping pulse) according to the clockwise (CW) or counterclockwise (CCW) rotation in the following tables. Table 12-1. Full Step/Single Phase Excitation -------------------------> CW rotation Step pattern 1 VPM [0](phase A) VPM [1](phase B) VPM [2](phase C) VPM [3](phase D) 1 0 0 0 Step pattern 2 0 1 0 0 Step pattern 3 0 0 1 0 Step pattern 4 0 0 0 1 Step pattern 1 1 0 0 0 <------------------------ CCW rotation Table 12-2. Full Step/Two Phase Excitation -------------------------> CW rotation Step pattern 1 VPM [0](phase A) VPM [1](phase B) VPM [2](phase C) VPM [3](phase D) 1 1 0 0 Step pattern 2 0 1 1 0 Step pattern 3 0 0 1 1 Step pattern 4 1 0 0 1 Step pattern 1 1 1 0 0 <------------------------ CCW rotation Table 12-3. Half-Step Excitation -------------------------> CW rotation Step FP1 VPM [0] VPM [1] VPM [2] VPM [3] 1 1 0 0 Step HP2 0 1 0 0 Step FP3 0 1 1 0 Step HP4 0 0 1 0 Step FP5 0 0 1 1 Step HP6 0 0 0 1 Step FP7 1 0 0 1 Step HP8 1 0 0 0 <------------------------ CCW rotation Note: FPx: full step pattern and x: 1-4, HPx: half step pattern and x:1-4 Programmability: * * * * * * The frequency of STEPCLK is programmable (around 1.25 MHz39 KHz) if the ICLK (internal) frequency is 10 MHz. The step timer value is programmable (around 1us400ms) if the ICLK (internal) frequency is 10 MHz. The Motor moving direction (clockwise or counterclockwise) and the stepping mode (full step or half step) is programmable. The motor phase pattern is programmable. Control bits for clearing the stepping interrupt and enabling the stepping logic are included. A control bit for the vertical print motor power on/off. 100723A Conexant 12-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 12.1.2 Register Description Address: Vertical Printer Motor Pattern Register (VPMPattern) 01FF805D Address: Vertical Printer Motor Pattern Register (VPMPattern) 01FF805C Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Rst. Value 00h Read Value 00h Bit 7 VPMH[3] Bit 6 VPMH[2] Bit 5 VPMH[1] Bit 4 VPMH[0] Bit 3 VPMF[3] Bit 2 VPMF[2] Bit 1 VPMF[1] Bit 0 VPMF[0] For the full step excitation, the phase pattern VPM[3:0] (See Table 12-1 and Table 12-2) needs to be put into VPMF[3:0] of this VPMPattern register. Bit[7:4] of this register are `don't care'. For the half step excitation, two adjacent phase patterns (See Table 12-3) need to be put into the VPMPattern register: VPM[3:0] at FP[x] column needs to be put into VPMF[3:0] and VPM[3:0] at HP[x] column needs to be put into VPMH[3:0]. The current output at PM[3:0] is VPMF[3:0]. Address: Bit 15 Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Rst. Value xxx00000b Read Value 00h Step Clock Register (Not Used) (VPStepClk) 01FF8853 Address: Bit 7 Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 bit 4 of the step clock divider Bit 3 bit 3 of the step clock divider Bit 2 bit 2 of the step clock divider Bit 1 bit 1 of the step clock divider Bit 0 bit 0 of the step clock divider Step Clock Register (Not Used) (VPStepClk) 01FF8852 * STEPCLK = ICLK/(8 * (n+1)), n (bit[4:0] of the step clock divider): from 0 to 31 Address: Step Control Register (VPStepCtrl) 01FF8059 Address: Step Control Register (VPStepCtrl) 01FF8058 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Rst. Value xxx00000b Read Value 00h Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 Bit 3 Bit 2 Motor Direction 0: CW 1: CCW Bit 1 Bit 0 Vertical Print Stepping Motor Power Mode Control 0: full step 1: half step Step Enable STEPIRQ Clear 0: disable 1: enable 1:clear 12-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: Bit 15 Bit 14 (Not Used) Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 bit 8 of the step timer Default: Rst. Value xx000000b Read Value 00h Default: Rst. Value 00h Read Value 00h Step Timer Register (Not Used) (VPStepTimer) 01FF805B Address: Bit 7 bit 13 of the bit 12 of the bit 11 of the bit 10 of the bit 9 of the step timer step timer step timer step timer step timer Bit 6 bit 6 of the step timer Bit 5 bit 5 of the step timer Bit 4 bit 4 of the step timer Bit 3 bit 3 of the step timer Bit 2 bit 2 of the step timer Bit 1 bit 1 of the step timer Bit 0 bit 0 of the step timer Step Timer Register bit 7 of the step timer (VPStepTimer) 01FF805A * The Time interval between two adjacent step pulses = (n+1)/STEPCLK, n (bit[13:0] of the step timer): from 0 to 16383 12.2 Scanner Stepper Motor Interface 12.2.1 Scanner Stepper Motor Control Description The stepper motor can be controlled by this block to run at constant speed, increasing speed (acceleration), or decreasing speed (deceleration). The Motor Timer Sub-block contains two sets of loadable timers and timer registers. One is used for the step control logic and the other is used for the delay control logic. The step control logic is based on a loadable step timer and a step timer register. A pulse and interrupt are generated when the step timer expires (timed-out) and at the same time, the content of the step timer register is automatically loaded into the step timer. The pulse is used to change the phase pattern to the next one in the Motor Pattern Control Sub-block and the interrupt is used to inform CPU to load the new step timer value to the timer register if necessary for the step after the next step (See Figure 12-3). MFC2000 Chip The Scan Motor Control Block MSINT0 Internal Bus Interface and SM Logic Control SM_PWRCTRL External Circuit motor moving clock (MMCLK) STEPCLK divider stepping clock (STEPCLK) Motor Timer Motor Pattern Control External Motor Driver stepping pulse (STEPPULSE) Motor vertical print stepping interrupt (SSTEPIRQ) Figure 12-3. Scan Motor Control Diagram 100723A Conexant 12-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description The scan motor stepping needs to synchronize to the scan cycle during scanning. Signal MSINT0 is used to indicate the beginning of the scan cycle. MSINT0 synchronization can be enabled or disabled through the register setting. This is the main difference between the Vertical Print Motor Control block and the Scan Motor Control block. The delay control logic is based on a loadable delay timer and a delay timer register. The MSINT0 and the delay timer control when the Motor Timer Sub-block sends out the first stepping pulse after CPU enables the scan motor stepping. Once, CPU enables the scan motor stepping, the Motor Timer Sub-block waits for the MSINT0 pulse to load the delay timer value from the delay timer register and activate the delay timer if the MSINT0 synchronization is enabled. Otherwise, the Motor Timer Sub-block loads the new timer value from the delay timer register and activates the delay timer immediately. The first stepping pulse will be sent to the Motor Pattern Control Sub-block when the delay timer expires (timed-out). The delay timer only works once after CPU enables the scan motor stepping for the first step. The scan motor control lines are the four pins SM[3:0]/GPO[7:4]. These pins are selected as scanner motor control lines when bit 1 in the GPIOconfig register is set to 0 (default), and are selected as GPO's when this bit is set to 1. The scanner motor pattern or GPO data is output on pins SM[3:0]/GPO[7:4] from bits [3:0] of the SMPattern register. When selected as GPO's, data written by CPU to the SMPattern register is immediately output on the GPO pins and output data are not changed unless CPU writes another new data to the SMPattern register. When selected as scanner motor control lines, data is not allowed to be written to the SMPattern register no matter whether the motor stepping is disabled or enabled. Caution: The vertical print motor pattern register (SMPattern register) can only be written when it is used as the GPO function. In other words, bit 1 of the GPIOConfig register is set to 1. At the beginning of the motor moving process, CPU needs to write the stepping mode and the stepping direction to the SStepCtrl register, the initial scan motor pattern to the SMPattern register, the delay timer value to the SDelayTimer register, and the 1st step timer value to the SStepTimer register (used to define the time interval between the 1st and 2nd steps). Then, CPU sets bit 1 of the GPIOConfig register to 0 and enables the scan motor stepping. If the MSINT0 synchronization is disabled, the content of the delay timer register is immediately loaded into the step timer. If the MSINT0 synchronization is enabled, the delay timer loading will be delayed until the beginning of the scan (seeing the MSINT0 pulse). After Motor Timer Sub-block loads the new timer value from the delay timer register, It activates the delay timer immediately. The first stepping pulse will be sent to the Motor Pattern Control Sub-block when the delay timer expires (timed-out). At the same time, the content (the 1st step timer value) of the step timer register is automatically loaded into the step timer and an interrupt is generated. CPU writes the 2nd step timer value into the step timer register in the stepping interrupt routine. When the step timer expires (timed-out), A pulse is generated to change the phase pattern to the next one (the 2nd step) and the content (the 2nd step timer value) of the step timer register is automatically loaded into the step timer and an interrupt is generated to inform CPU to load the 3rd step timer value to the step timer register. At the end of the motor stepping, a pulse is generated to change the phase pattern to the next one (the `n-2' step, n: the last step) and the content of the step timer register (the time interval between the `n-2' and `n-1 steps) is automatically loaded into the step timer and an interrupt is generated to inform CPU to load the last step timer value to the step timer register when the step timer expires (timed-out). When the step timer expires again (timedout), A pulse is generated to change the phase pattern to the next one (the `n-1' step) and the content (the last step timer value) of the step timer register is automatically loaded into the step timer and an interrupt is generated an interrupt is generated to inform CPU to load the large dummy timer value to the step timer register. Finally, a pulse is generated to change the phase pattern to the next one (the last step) and the content (the large dummy timer value) of the step timer register is automatically loaded into the step timer and an interrupt is generated to inform CPU to disable the motor stepping. The step and delay timers are cleared to 0 and the stepping pulse is blocked immediately after CPU disables the motor stepping. 12-6 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 The step enable bit in the SStepCtrl register only controls if the motor pattern is allowed to change to the next one. The motor pattern in the SMPattern register always goes out. CPU has the responsibility to write value `00h' to the SMPattern register or set the bit 5 of the SStepCtrl register to a proper value according to the external motor power control circuit for not driving the scan motor. Bit 5 value of the SStepCtrl register directly goes out of the MFC2000 chip through the GPIO[12]/SASCLK/SMPWRCTRL pin. Caution: The GPIO[12]/SASCLK/SMPWRCTRL pin can only be used as the SMPWRCTRL pin when bit 9 of the GPIOConfig1 register is `0' and bit 10 of the GPIOConfig1 register is `1'. The step time interval between two adjacent stepping pulses (for example, t1 and t2) is determined by the timer value. The min. time difference between two adjacent stepping pulses (It is called the timer resolution, for example, t = | t2-t1|.) is determined by the frequency of the stepping clock (See Figure 12-4). (in the speed-up period) STEPPULSE t1 t2 time is controlled by the step timer Figure 12-4. Stepping Timing The change sequence of the phase pattern in the Motor Pattern Control Sub-block is as follows: after the CPU gives the initial phase pattern (any column in the following tables), the phase pattern will automatically change to the next one after getting the time-out pulse of the timer (the stepping pulse) according to the clockwise (CW) or counterclockwise (CCW) rotation in the following tables. Table 12-4. Full Step/Single Phase Excitation -------------------------> CW rotation Step pattern 1 SM [0](phase A) SM [1](phase B) SM [2](phase C) SM [3](phase D) 1 0 0 0 Step pattern 2 0 1 0 0 Step pattern 3 0 0 1 0 Step pattern 4 0 0 0 1 Step pattern 1 1 0 0 0 <------------------------ CCW rotation Table 12-5. Full Step/Two Phase Excitation -------------------------> CW rotation Step pattern 1 SM [0](phase A) SM [1](phase B) SM [2](phase C) SM [3](phase D) 1 1 0 0 Step pattern 2 0 1 1 0 Step pattern 3 0 0 1 1 Step pattern 4 1 0 0 1 Step pattern 1 1 1 0 0 <------------------------ CCW rotation 100723A Conexant 12-7 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Table 12-6. Half-Step Excitation -------------------------> CW rotation Step FP1 SM [0] SM [1] SM [2] SM [3] 1 1 0 0 Step HP2 0 1 0 0 Step FP3 0 1 1 0 Step HP4 0 0 1 0 Step FP5 0 0 1 1 Step HP6 0 0 0 1 Step FP7 1 0 0 1 Step HP8 1 0 0 0 <------------------------ CCW rotation Note: FPx: full step pattern and x: 1-4, HPx: half step pattern and x:1-4 Programmability: * * * * * * * * The frequency of STEPCLK is programmable (around 1.25 MHz39 KHz) if the ICLK (internal) frequency is 10 MHz. The step timer value is programmable (around 1us400ms) if the ICLK (internal) frequency is 10 MHz. The delay timer value is programmable (around 1us400ms). The Motor moving direction (clockwise or counterclockwise) and the stepping mode (full step or half step) is programmable. The motor phase pattern is programmable. Control bits for clearing the stepping interrupt and enabling the stepping logic are included. The MSINT0 synchronization can be enabled and disabled. A control bit for the scan motor power on/off. 12-8 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 12.2.2 Scan Motor Current Control The current control logic is added to this block. Two current control output signals (SMI[1:0]) are needed to control 4 different current modes. Three different current modes can be used within the time period of one step (See Figure 12-5). T1 and T2 are programmable in one step period. The current mode in each current period of one step period is programmable. CPU can load T1 and T2 values and current modes of three current periods within one step for the next step at the same time when CPU loads the next step timer value by using the scan step interrupt (SSTEPIRQ). In other words, T1, T2, and current modes are double buffered. SMI[0] output value is 1 and SMI[1] output value is 1 after reset and when SM[3:0] pins are used as GPO's. The default current mode is also programmable when SM[3:0] pins are used as motor control pins and motor stepping is disabled. one step period one step period one step period different current modes different current modes different current modes T1 T2 T1 T2 T1 T2 changing step pattern (stepping to the next step) Figure 12-5: Current Control Diagram Two current control signals (SMI1 and SMI0) share same pins with PM[3]/GPO[3] and PM[2]/GPO[2]. There is a SMI[1:0] output select bit in the SStepCtrl Register to select which signals output on PM[3:2] pins. 12.2.3 Register Description Address: Scanner Motor Pattern Register (SMPattern) 01FF8057 Address: Scanner Motor Pattern Register (SMPattern) 01FF8056 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Rst. Value 00h Read Value 00h Bit 7 SMH[3] Bit 6 SMH[2] Bit 5 SMH[1] Bit 4 SMH[0] Bit 3 SMF[3] Bit 2 SMF[2] Bit 1 SMF[1] Bit 0 SMF[0] For the full step excitation, the phase pattern SM[3:0] (See Table 12-4 and Table 12-5) needs to be put into SMF[3:0] of this SMPattern register. Bit[7:4] of this register are `don't care'. For the half step excitation, two adjacent phase patterns (See Table 12-6) need to be put into the SMPattern register: SM[3:0] at FP[x] column needs to be put into SMF[3:0] and SM[3:0] at HP[x] column needs to be put into SMH[7:4]. The current output at PM[3:0] is SMF[3:0]. 100723A Conexant 12-9 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: Bit 15 Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Rst. Value xxx00000b Read Value 00h Step Clock Register (Not Used) (SStepClk) 01FF8851 Address: Bit 7 Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 bit 4 of the step clock divider Bit 3 bit 3 of the step clock divider Bit 2 bit 2 of the step clock divider Bit 1 bit 1 of the step clock divider Bit 0 bit 0 of the step clock divider Step Clock Register (Not Used) (SStepClk) 01FF8850 * STEPCLK = ICLK/(8 * (n+1)), n (bit[4:0] of the step clock divider): from 0 to 31 Address: Step Control Register (SStepCtrl) 01FF8051 Address: Step Control Register (SStepCtrl) 01FF8050 Bit 15 I31 Bit 14 I30 Bit 13 I21 Bit 12 I20 Bit 11 I11 Bit 10 I10 Bit 9 DI1 Bit 8 DI0 Default: Rst. Value FFh Read Value FFh Default: Rst. Value x0000000b Read Value 00h Bit 7 (Not Used) Bit 6 SMI Output Select Bit 5 Bit 4 Bit 3 Stepping Mode 0: full step 1: half step Bit 2 Motor Direction 0: CW 1: CCW Bit 1 Bit 0 Scan Motor MSINT0 Power Sync Control 0: disabled 1: enabled Step Enable STEPIRQ Clear 0: disable 1:clear 1: enable Bits 15-14 Bits 13-12 Bits 11-10 Bits 9-8 The third current control values go out to the scan current control pins (SMI1 and SMI0) within one step time period. The second current control values go out to the scan current control pins (SMI1 and SMI0) within one step time period. The first current control values go out to the scan current control pins (SMI1 and SMI0) within one step time period. The default current control values go out to the scan current control pins (SMI1 and SMI0) when the motor stepping is disabled and SM[3:0] is used for motor control. Control which signal output to PM[3:2] pins (SMI[1:0] output signals or PM[3]/GPO[3] and PM[2]/GPO[2] output signals). 0: Output PM[3]/GPO[3] and PM[2]/GPO[2] signals, 1: Output SMI[1:0] signals. Bits 6 Address: Bit 15 Bit 14 (Not Used) Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 bit 8 of the step timer Default: Rst. Value 00h Read Value 00h Default: Rst. Value 00h Read Value 00h Step Timer Register (Not Used) (SStepTimer) 01FF8053 Address: Bit 7 bit 13 of the bit 12 of the bit 11 of the bit 10 of the bit 9 of the step timer step timer step timer step timer step timer Bit 6 bit 6 of the step timer Bit 5 bit 5 of the step timer Bit 4 bit 4 of the step timer Bit 3 bit 3 of the step timer Bit 2 bit 2 of the step timer Bit 1 bit 1 of the step timer Bit 0 bit 0 of the step timer Step Timer Register bit 7 of the step timer (SStepTimer) 01FF8052 * The Time interval between two adjacent step pulses = (n+1)/STEPCLK, n (bit[13:0] of the step timer): from 0 to 16383 12-10 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: Step Delay Timer Register (SSDelayTimer) 01FF8055 Address: Step Delay Timer Register (SSDelayTimer) 01FF8054 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 bit 8 of the delay timer Default: Rst. Value 00h Read Value 00h Default: Rst. Value 00h Read Value 00h bit 13 of the bit 12 of the bit 11 of the bit 10 of the bit 9 of the delay timer delay timer delay timer delay timer delay timer Bit 7 bit 7 of the delay timer Bit 6 bit 6 of the delay timer Bit 5 bit 5 of the delay timer Bit 4 bit 4 of the delay timer Bit 3 bit 3 of the delay timer Bit 2 bit 2 of the delay timer Bit 1 bit 1 of the delay timer Bit 0 bit 0 of the delay timer * The delay time interval before stepping = (n+1)/STEPCLK, n (bit[13:0] of the step delay timer): from 0 to 16383 Address: Current Timer 1 Register (SSCurTimer1) 01FF804D Address: Current Timer 1 Register (SSCurTimer1) 01FF804C Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Bit 7 Bit 6 bit 13 of the bit 12 of the bit 11 of the bit 10 of the bit 9 of the bit 8 of the Rst. Value current timer current timer current timer current timer current timer current timer xx000000b Read Value 00h Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: bit 7 of the bit 6 of the bit 5 of the bit 4 of the bit 3 of the bit 2 of the bit 1 of the bit 0 of the Rst. Value current timer current timer current timer current timer current timer current timer current timer current timer 00h Read Value 00h * This register defines when to change the first driving current to the second driving current within one step time period. The current timer 1 value in this register must be less than the step timer value set in the SStepTimer register for the same step and greater than 0. Otherwise, the current will not be changed. Once the step timer counts down to the current timer 1 value, the current control signals changes to I20 and I21 from I10 and I11 in the SStepCtrl register. I10 and I11 are the initial values of the current control signals within a step. Address: Current Timer 2 Register (SSCurTimer2) 01FF804F Address: Current Timer 2 Register (SSCurTimer2) 01FF804E Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: bit 13 of the bit 12 of the bit 11 of the bit 10 of the bit 9 of the bit 8 of the Rst. Value current timer current timer current timer current timer current timer current timer xx000000b Read Value 00h Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Bit 7 Bit 6 bit 7 of the bit 6 of the bit 5 of the bit 4 of the bit 3 of the bit 2 of the bit 1 of the bit 0 of the Rst. Value current timer current timer current timer current timer current timer current timer current timer current timer 00h Read Value 00h * This register defines when to change the second driving current to the third driving current within one step time period. The current timer 2 value in this register must be less than the current timer 1 value set in the SSCurTimer1 register for the same step and greater than 0. Otherwise, the current will not be changed. Once the step timer counts down to the current timer 2 value, the current control signals changes to I30 and I31 from I20 and I21 in the SStepCtrl register. 100723A Conexant 12-11 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description This page is intentionally blank 12-12 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 13. General Purpose Inputs/Outputs (GPIO) 13.1 GPIO Signals The AMFPC provides 31 GPIO lines (GPIO[30:0]) typically used for I/O control, each of which is multiplexed with other signals. The direction of each GPIO line (input or output) is programmable using the hardware registers shown in Section 13.3. GPIO0 GPIO0 is multiplexed with the flash memory write enable signal (FWRn) for the NAND-type flash memory, this GPIO0 pin is also multiplexed with W_Rn. This pin is selected as a GPIO when bit 2 of the GPIOConfig1 register is set to 0 and Emulator signals are not enabled, in this case, the direction of this pin is controlled by bit 0 of the GPIODir register. If GPIODir[0] is set to one, this pin will ouput the value of the bit 0 from GPIOData register, and, if GPIODir[0] is set to zero, the value of the GPIO0 can be read back by reading GPIOdata[0]. This pin is selected as FWRn when the GPIOConfig1 bit is set to 1, in this case, this pin becomes an output pin regardless of the value in the GPIODir[0]. This pin is selected as W_Rn when EMUSIG_EN is set to 1, refer to Testmgr section for EMUSIG_EN signal definition. GPIO1 GPIO1 is multiplexed with the flash memory read enable signal (FRDn) for the NAND-type flash memory, this GPIO1 pin is also multiplexed with XAKn. This pin is selected as a GPIO when bit 2 of the GPIOConfig1register is set to 0 and, in this case, the direction of this pin is controlled by bit 1 of the GPIODir register. If GPIODir[1] is set to one, this pin will ouput the value of the bit 1 from GPIOData register, and, if GPIODir[1] is set to zero, the value of the GPIO1 can be read back by reading GPIOdata[1]. This pin is selected as FWRn when the GPIOConfig1 bit is set to 1, in this case, this pin becomes an output pin regardless of the value in the GPIODir[1]. This pin is selecetd as XAKn when EMUSIG_EN is set to 1, refer to Testmgr section for EMUSIG_EN signal definition. GPIO2 GPIO2 is multiplexed with SSCLK2, this pin is also used for the DMA request input from DMA channel 1 (DMAREQ1). If this pin is used as DMAREQ1, the direction of this pin needs to be set as input. If SSCLK2 function is used, the bit 0 of GPIOConfig2 register needs to be set to 1. If this pin is used as SSCLK2, the GPIO2 direction and data setting for this pin is no longer valid. When bit 16 of GPIOCofig register is set to 0, this pin can be used as GPIO2, in this case, the direction of this pin is controlled by bit 2 of the GPIODir register. The GPIO2 input/output value is controlled by bit 2 of the GPIOData register. 100723A Conexant 13-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description GPIO3 GPIO3 is multiplexed with the DMA acknowledge of the DMA channel 1 (DMAACK1), it is also used as SSRXD2 input. If this pin is used as SSRXD2, the direction of this pin needs to be set as input and the DMAACK1 function must be disabled. If this pin is used as DMAACK1, the GPIO direction and data setting for this pin is no longer valid. This function is enabled by setting EXTDMA1SEL to 1. If this pin is used as GPIO, the direction of this pin is controlled by bit 3 of the GPIODir register. The GPIO3 input/output value is controlled by bit 3 of the GPIOData register. GPIO[7:4] GPIO[7:4] are multiplexed with general chip selects on pins GPIO7/CS5n, GPIO6/CS4n, GPIO5/CS3n, and GPIO4/CS2n. These pins are selected as GPIO when the corresponding bits in the GPIOConfig1 register are set to 0. The direction of these pins is controlled by the bits 7-4 in the GPIODir register. The GPIO[7:4] input/output values are controlled by the bits 7-4, respectively, of the GPIOData register. In addition, the GPIO[5]/CS3n pin is also multiplexed with the PWM3 signal. See the register description in the PWM section for settings. GPIO6 can also used as input pin for EV_CLK and EADC_D[3], if this function is selected, the direction control for GPIO6 must be set to 0. GPIO8 GPIO8 is multiplexed with SSSTA1 and SC_CLK1/2B, this pin is also used as the interrupt request 11 (IRQ11) input. If this pin is used as IRQ11, the direction of this pin needs to be set as input. If this pin is not used as IRQ11, the interrupt channel 11 needs to be disabled by setting the IRQEnable register in the Interrupt Controller. If SSSTA1 function is selected, the bit 15 of GPIOConfig1 register must be set to 1. To enable SC_CLK1/2B function, bit 15 of GPIOConfig1 must be set to 0 and bit 18 of this register set to 1. Only when both bit15 and bit2 of the GPIOConfig2 register are set to 0, the GPIO8 pin is enabled as GPIO. When GPIO function is enabled, the direction of this pin is controlled by bit 8 of the GPIODir register. The GPIO8 input/output value is controlled by bit 8 of the GPIOData register. GPIO9 GPIO9 is also used as the interrupt request 13 (IRQ13n) input or EADC_D[2] input. If this pin is used as IRQ13n or EADC_D[2], the direction of this pin needs to be set as input. If this pin is not used as IRQ13n, the interrupt channel 13 needs to be disabled by setting the IRQEnable register in the Interrupt Controller. The direction of this pin is controlled by bit 9 of the GPIODir register. The GPIO9 input/output value is controlled by bit 9 of the GPIOData register. 13-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 GPIO10 GPIO10 is multiplexed with the PWM[4] signal, this pin is also used for P80_PB3 as input. When P80_PB3 function is used, the direction of this pin needs to be set as input. This pin is selected as a GPIO when bit 7 of the GPIOConfig1 register is set to 0. The direction of this pin is controlled by bit 10 of the GPIODir register, and the input/output value is controlled by bit 10 of the GPIOData register. The PWM[4] function is enabled by setting bit 7 of the GPIOConfig1 register to 1, additional control is required to use PWM[4], refer to PWM section for detail. GPIO11 GPIO11 is also used for the Calling Party Control Input (CPCIN) pin and multiplexed with the ALTTONE output signal on pin GPIO11/CPCIN/ALTTONE. This pin is selected as a GPIO by setting bit 8 of the GPIOConfig1 register to 0. The direction of this pin is controlled by bit 11 in the GPIODir register, and the input/output value is controlled by bit 11 in the GPIOData register. The ALTTONE output signal is selected by setting bit 8 of the GPIOConfig1 register to 1 and setting bit 11 of the GPIODir register to 1. If this pin is used as the CPCIN signal input pin, the bit 11 of the GPIODir register is set to 0. In addition, the GPIO11/CPCIN/ALTTONE pin is also multiplexed with the PWM0 signal. See the register description in the PWM section for settings. GPIO[14:12] GPIO[14:12] are multiplexed with the scan/print motor power control output signals, the RINGER output signal, and the SASIF signals on pin GPIO14/SASRXD/RINGER, GPIO13/SASTXD/PMPWRCTRL, and GPIO12/SASCLK/SMPWRCTRL. These pins are selected as a GPIO by setting bit[12:9] in the GPIOConfig1 register to zero. The direction of these pins are controlled by bit[14:12] of the GPIODir register, and the input/output value is controlled by bit[14:12] of the GPIOData register. These pins are selected as the SASIF signals or RINGER/PMPWRCTRL/SMPWRCTRL signals by setting bit[14:9] in the GPIOConfig1 register (refer to GPIOConfig1 register description). Firmware needs to program GPIO[14:12] pins to use SASRXD, SASTXD, and SASCLK for the sync mode. If the async mode of SASIF is used, firmware only needs to program GPIO[14:13] pins to use SASRXD and SASTXD. GPIO[12] can be still used as GPIO. GPIO15 is multiplexed with SC_CLK1/2C signals, this pin is also used as IRQ16 input. If this pin is used as IRQ16, the direction of this pin needs to be set as input. If this pin is not used as IRQ16, the interrupt channel 16 needs to be disabled by setting the IRQEnable register in the Interrupt Controller. If SC_CLK1/2C function is selected, the bit 3 of GPIOConfig2 register must be set to 1. To enable GPIO15 function, bit 3 of GPIOConfig2 must be set to 0. When GPIO function is enabled, the direction of this pin is controlled by bit 15 of the GPIODir register. The GPIO15 input/output value is controlled by bit 15 of the GPIOData register. GPIO15 100723A Conexant 13-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description GPIO[21:16] GPIO[21:16] are multiplexed with six P80 modem IA signals; in addition, GPIO19 can be used for MIRQn input signal, and GPIO20 is further multiplexed with MCSn. Six P80 modem IA signals are M_TXSIN, M_CLKIN, M_RXOUT, M_SCK, M_STROBE and M_CNTRL_SIN, they are multiplexed with GPIO16 through GPIO21 respectively. The control signals of this multiplexing are EXTIA_MODE and EXTIA_SEL, they are generated from SSD_P80. When EXTIA_MODE is 1, the six P80Modem signals will appear on the GPIO pins, these signals can be used to either interface to Data IA (when EXTIA_SEL is 0) or Voice IA (when EXTIA_SEL is 1). When EXTIA_MODE is 0, the GPIO[21:16] become GPIO and they are controlled by GPIODir and GPIOData registers as usual except GPIO20 can become MCSn if bit 5 GPIOConfig2 is set to 1 and GPIO19 can be used as MIRQn input. GPIO22 is multiplexed with EADC_Sample signals. If EADC_Sample function is selected, the bit 6 of GPIOConfig2 register must be set to 1. To enable GPIO22 function, bit 6 of GPIOConfig2 must be set to 0. When GPIO function is enabled, the direction of this pin is controlled by bit 22 of the GPIODir register. The GPIO22 input/output value is controlled by bit 22 of the GPIOData register. GPIO22 GPIO[30:23] GPIO[30:23] are multiplexed with PIOD[7:0] signals respectively; If GPIO function is selected, bit 8 of GPIOConfig2 register must be set to 1, else, PIOD function is selected. When GPIO function is enabled, the direction of this pin is controlled by bit 30-23 of the GPIODir register. The GPIO[30:23] input/output value is controlled by bit 30-23 of the GPIOData register. 13-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 13.2 GPO/GPI Signals The MFC2000 also provides eight GPO lines (GPO[7:0]), which are multiplexed with printer and scanner motor control signals. GPO[3:0] GPO[3:0] are multiplexed with the printer motor control lines on the four pins PM[3:0]/GPO[3:0]. These pins are selected as GPO's when bit 0 in the GPIOConfig1 register is set to 1, and are selected as printer motor control lines when this bit is set to 0. When these pins are selected as GPO's, the GPO[3:0] output values are controlled by the lowest 4 bits in the VPMPattern register, and appear on the output pins immediately. GPO[7:4] are multiplexed with the scanner motor control lines on the four pins SM[3:0]/GPO[7:4]. These pins are selected as GPO's when bit 1 in the GPIOConfig1 register is set to 1, and are selected as scanner motor control lines when this bit is set to 0. When these pins are selected as GPO's, the GPO[7:4] output values are controlled by the lowest 4 bits in the SMPattern register, and appear on the output pins immediately. If the PIO Interface is not enabled, the pins for PIODIR, BUSY, ACKn, SLCTOUT, PE and FAULTn will become GPIO8-GPIO13 respectively. These pins are selected as GPO function when bit8 of GPIOConfig2 register is set to 1, otherwise, PIO interface will be selected. The GPO[13:8] data is controlled by bit 5-0 of GPOData register. GPO[17:14] are multiplexed with AO3, AE3, AO2 and AE2 respectively, in addition, GPO14 is multiplexed with SSTXD2 and GPO15 is with SSSTA2. The multiplexing selection is controlled by bit 0 and bit 1 of the GPIOConfig2 register. When bit0 of the GPIOConfig2 register is 1, the SSTXD2/SSSTA2 function is selected, when bit 0 is 0 and bit 1 is 1, the GPO[17:14] function is enabled and the output value of the GPO[17:14] is controlled by bit 9-6 of GPOData register. To select AO[3:2]/AE[3:2], both bit 0 and bit 1 of the GPIOConfig2 register must be 0. Four PIO Interface input pins can be used as GPI when PIO interface is not used, the value on these GPI pins can be read from bit 15-12 of the GPOData register. GPO[7:4] GPO[13:8] GPO[17:14] GPI[3:0] 100723A Conexant 13-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 13.3 GPIO Control and Data Registers Address: GPIO Configuration 1 (GPIOConfig1) 01FF8831 Bit 15 0=GPIO[8] 1=SSSTAT1 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: GPIO[14] Select bits GPIO[13] Select bits GPIO[12] Select bits 0=GPIO11 Rst Value 1=ALTTONE xxx00000b Read Value 00h Address: GPIO Configuration 1 (GPIOConfig1) 01FF8830 Bit 7 Bit 6 Bit 5 0=GPIO6 1=CS4n Bit 4 0=GPIO5 1=CS3n Bit 3 0=GPIO4 1=CS2n Bit 2 Bit 1 Bit 0 0=Prt Mot. PM[3:0] 1= GPO[3:0] Select Default: Rst Value 00h Read Value 00h 0=GPIO10 1= 0=GPIO7 PWM4 1=CS5n Enable 0=GPIO[1:0] 0=scan mot. 1=FRDn and SM[3:0] FWRn 1= GPO[7:4] Select Register Description: GPIO Configuration1 Register Bit 14-13: Bit 14 0 0 1 1 Bit 13 0 1 0 1 GPIO[14] SASRXD Ringer (Not used) GPIO[14] or ringer or SASRXD is selected. the GPIO[14]/Ringer/SASRXD pin Bit 12-11: Bit 12 0 0 1 1 Bit 11 0 1 0 1 GPIO[13] or PMPWRCTRL or SASTXD is selected. the GPIO[13]/PMPWRCTRL/SASTXD pin GPIO[13] SASTXD PMPWRCTRL (Not used) Bit 10-9: Bit 10 0 0 1 1 Bit 9 0 1 0 1 GPIO[12] or SMPWRCTRL or SASCLK is selected. the GPIO[12]/SMPWRCTRL/SASCLK pin GPIO[12] SASCLK SMPWRCTRL (Not used) 13-6 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: GPIO Configuration 2 (GPIOConfig2) 01FF8833 Bit 15 Not Used Bit 14 Not Used Bit 13 Bit 12 Not Used Bit 11 Bit 10 Not Used Bit 9 Bit 8 0=PIO Select 1=GPO[13:8 ]/GPIO[30:2 3] Default: Rst Value xxx00000b Read Value 00h Address: GPIO Configuration 2 (GPIOConfig2) 01FF8832 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst Value 00h Read Value 00h 0=PM[1:0] 0=GPIO22 0=GPIO2 Not Used 1= 1=EADC_S 0 SPI_SIC/SPI ample 1=MCSn _SID 0=GPIO15 0=GPIO8 0=AE[3:2]/AO 0=GPIO[3:2 ] 1=SC_CLK1/ 1=SC_CLK1/ [3:2] 2C 2B 1=GPO[17:14 1= SS2 ] Select Select Register Description: GPIO Configuration2 Register Address: GPI/GPO Data (GPOData) 01FF883D Bit 15 GPI3 Bit 14 Bit 13 GPI1 Data Bit 12 GPI0 Data Bit 11 Not Used Bit 10 Not Used Bit 9 GPO17 Data Bit 8 GPO16 Data Default: Rst Value 00000000b Read Value xxxx00xxb Data GPI2 Data Address: GPI/GPO Data (GPOData) 01FF883C Bit 7 GPO15 Data Bit 6 GPO14 Data Bit 5 GPO13 Data Bit 4 GPO12 Data Bit 3 GPO11 Data Bit 2 GPO10 Data Bit 1 GPO9 Data Bit 0 GPO8 Data Default: Rst Value 00h Read Value xxh Register Description: GPO Data Register Address: GPIO Data 1 (GPIOData1) 01FF8835 Bit 15 GPIO15 Data Bit 14 GPIO14 Data Bit 13 GPIO13 Data Bit 12 GPIO12 Data Bit 11 GPIO11 Data Bit 10 GPIO10 Data Bit 9 GPIO9 Data Bit 8 GPIO8 Data Default: Rst Value x0000000b Read Value 0xxxxxxxb Address: GPIO Data 1 (GPIOData1) 01FF8834 Bit 7 GPIO7 Data Bit 6 GPIO6 Data Bit 5 GPIO5 Data Bit 4 GPIO4 Data Bit 3 GPIO3 Data Bit 2 GPIO2 Data Bit 1 GPIO1 Data Bit 0 GPIO0 Data Default: Rst Value 00h Read Value xxh Address: GPIO Data 2 (GPIOData2) 01FF8837 Bit 15 (Not Used) Bit 14 GPIO30 Data Bit 13 GPIO29 Data Bit 12 GPIO28 Data Bit 11 GPIO27 Data Bit 10 GPIO26 Data Bit 9 GPIO25 Data Bit 8 GPIO24 Data Default: Rst Value x0000000b Read Value 0xxxxxxxb Address: GPIO Data 2 (GPIOData2) 01FF8836 Bit 7 GPIO23 Data Bit 6 GPIO22 Data Bit 5 GPIO21 Data Bit 4 GPIO20 Data Bit 3 GPIO19 Data Bit 2 GPIO18 Data Bit 1 GPIO17 Data Bit 0 GPIO016 Data Default: Rst Value 00h Read Value xxh Register Description: GPIO Data 1/2 Register 100723A Conexant 13-7 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: GPIO Direction 1 (GPIODi1) 01FF8839 Bit 15 Bit 14 Bit 13 GPIO13 0=in 1=out Bit 12 GPIO12 0=in 1=out Bit 11 GPIO11 0=in 1=out Bit 10 GPIO10 0=in 1=out Bit 9 GPIO9 0=in 1=out Bit 8 GPIO8 0=in 1=out Default: Rst Value x0000000b Read Value 00h GPIO15 GPIO14 0=in 1=out 0=in 1=out Address: GPIO Direction 1 (GPIODir1) 01FF8838 Bit 7 GPIO7 0=in 1=out Bit 6 Bit 5 Bit 4 GPIO4 0=in 1=out Bit 3 GPIO3 0=in 1=out Bit 2 GPIO2 0=in 1=out Bit 1 GPIO1 0=in 1=out Bit 0 GPIO0 0=in 1=out Default: Rst Value 00h Read Value 00h GPIO6 GPIO5 0=in 0=in 1=out 1=out (Must be set to 0 if sartsel=1) Address: GPIO Direction 2 (GPIODir2) 01FF883B Bit 15 (Not Used) Bit 14 GPIO30 0=in 1=out Bit 13 GPIO29 0=in 1=out Bit 12 GPIO28 0=in 1=out Bit 11 GPIO27 0=in 1=out Bit 10 GPIO126 0=in 1=out Bit 9 GPIO25 0=in 1=out Bit 8 GPIO24 0=in 1=out Default: Rst Value x0000000b Read Value 00h Address: GPIO Direction 2 (GPIODir2) 01FF883A Bit 7 GPIO23 0=in 1=out Bit 6 GPIO22 0=in 1=out Bit 5 GPIO21 0=in 1=out Bit 4 GPIO20 0=in 1=out Bit 3 GPIO19 0=in 1=out Bit 2 GPIO18 0=in 1=out Bit 1 GPIO17 0=in 1=out Bit 0 GPIO16 0=in 1=out Default: Rst Value 00h Read Value 00h Register Description: GPIO Direction 1/2 Register 13-8 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 14. Compressor and Decompressor 14.1 Functional Description The T.4 data compression/decompression process is primarily implemented in hardware within the MFC2000 (see Figure 14-2). Hardware provides compression and decompression of data within a line, and adds fill bits at the end of a line to cause the number of bits (coded plus fill) to be a multiple of 16 (halfword justified) for T.4 MH and MR. For coding (compression), firmware (T.4 subsystem task) appends end-of-line characters and, if required, fill bits to support the minimum line times of CCITT T.4. On the receive side, firmware passes the coded line to the T.4 hardware. Data flow control, to prevent buffer overflow/underflow, is also the responsibility of the firmware. Line times less than 5 msec per line are supported by the MFC2000s' T.4 hardware; the line time supported by the overall system depends on other system factors (e.g. resolution, concurrency, etc). T4 line lengths up to 2046 bytes are supported. There are three FIFOs contained in the compressor/decompressor block. All FIFOs operate identically from both a hardware and firmware standpoint. The FIFO structure is illustrated in Figure 14-2. The FIFOs consist of a quad halfword FIFO structure and a single halfword holding register. The quad FIFO structure is emptied and filled by either DMA or CPU operations. The holding register is emptied and filled by the compressor/decompressor logic. All locations within the FIFO can also be arbitrarily read and written by firmware. This allows firmware to save the entire FIFO state and restore it at a later point in time, thereby permitting an unlimited number of data streams to be concurrently processed. T4/T6 Compression/Decompression CPU Data Mux DMA Ch 10 Data T4Data FIFO3 T4 (MH, MR), T6(MMR) Code or Decode Line Reference Line Buffer Data (Uncoded Data) DMA Ch 7 Current Line Buffer Data (Uncoded Data) DMA Ch 6 T4 Bi-Level Resolution Conversion DMA Ch 8 Figure 14-1. Data Flow for Compression/Decompression 100723A Conexant 14-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description S yste m D a ta B u s Q u a d H a lfw o rd 0 Q u a d H a lfw o rd 1 Q u a d H a lfw o rd 2 Q u a d H a lfw o rd 3 H o ld in g R e g iste r FIFO C o n tro l L o ca l D a ta B u s Figure 14-2. Compressor/Decompressor FIFO Structure 14.2 Register Description Address T4 Configuration (T4Config) $01FF8171 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 Disable Hardware DMA CH10 Bit 9 Disable Hardware DMA CH6 Bit 8 Disable Hardware DMA CH7 Default Rst. Value xxxxx000b Read Value: 00000000b Address T4 Configuration (T4Config) $01FF8170 Bit 7 (Not Used) Bit 6 Enable smart EOL operation Bit 5 Enable noninverted flush (zero fill) Bit 4 Compressed data src./dest. 00=T4Data0 01=T4Data1 10=T4Data2 11=T4Data3 Bit 3 Bit 2 Bit 1 Bit 0 Default Rst. Value x0000000b Read Value: 00000000b Enable T4 Coding/Decoding Mode Decompressi 00=MH on 01=MR 1-dimensional 10-MR 2-dimensional 11=MMR Bit 15-11: Bit 10: Not used Disable coded hardware DMA. Setting this bit to 1 disables hardware DMA accesses to the coded data FIFOs (DMA CH10). Clearing this bit allows hardware DMA to the coded data FIFOs. This bit should be set when firmware DMA is to be carried out to the coded data FIFO. Disable uncoded hardware DMA. Setting this bit to 1 disables hardware DMA accesses to the uncoded data FIFO (DMA CH6). Clearing this bit allows hardware DMA to the uncoded data FIFO. This bit should be set when firmware DMA is to be carried out to the uncoded data FIFO. Bit 9: 14-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Bit 8: Disable reference hardware DMA. Setting this bit to 1 disables hardware DMA accesses to the reference data FIFO (DMA CH7). Clearing this bit allows hardware DMA to the reference data FIFO. This bit should be set when firmware DMA is to be carried out to the reference data FIFO. Bit 7: Bit 6: Enable smart EOL operation. Not used Setting the smart EOL operation bit causes the posting of an EOL in the T4 Status register to be delayed until the selected T4Data FIFO has transferred all of its data. Clearing the bit causes EOL to be set as soon as the EOL has been processed, regardless of the condition of the FIFO. Setting the non-inverted flush bit causes the flush operation to use zero as fill bits rather than the inverted value of the last CW bit. Inverted fill allows the user to determine the number of fill bits added to halfword align the last CW. Bit 5: Enable Non-inverted flush. Bit 4-3: Compressed data source/destination. 00=T4Data0 (default) 01=T4Data1 10=T4Data2 11=T4Data3 Warning: No distinction is made between FIFO accesses by either the DMA channel or the CPU. This means it is possible for both sources to modify the FIFO contents, resulting in unpredictable operation of the compressor/decompressor. Firmware must ensure that the CPU does not modify the FIFO contents without first disabling the DMA channel. Bit 2: Bits 1-0: Enable Decompression T4 Coding/Decoding Mode 00=MH01=MR 1-d 10=MR 2-d11=MMR When MMR compression is selected, 2-d coding will occur (similar to MR 2-d), however, the last CW in the line will not be halfword aligned by adding fill bits. Code words from the next compressed line will be concatenated to whatever is already in the selected T4Data FIFO. MMR decompression is similar to MR 2-d decoding, except that the end-of-line condition is based on the number of decoded bits rather than an EOL code word. 100723A Conexant 14-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address T4 Control (T4Control) $01FF8173 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Rst. Value xxh Read Value: 00h Address T4 Control (T4Control) $01FF8172 Bit 7 Reset T4 Block (w) Bit 6 Bit 5 Bit 4 Decode Output Enable Bit 3 Bit 2 Bit 1 Start coding or decoding Bit 0 Flush CW (completes byte) Default Rst. Value x0000000b Read Value 00h Terminating Enable BiCode Error level Resolution Conversion Vertical OR Reset/Halt enable Coding or (decompress decoding mode only) Bit 15-8: Bit 7: Not used Writing a 1 to this bit causes the T4 logic to be reset, including all internal state machines and FIFOs. This bit is useful when switching between compression and decompression modes. A Terminating Code Error is indicated when a run length = 0 code is expected but not received at the end of a line, and the Terminating Code Error also sets the Line error bit Enable Bi-level Resolution Conversion. Bi-level resolution conversion is only valid in decompression mode. When this bit is set, horizontal resolution conversion will be performed on the decoder output. Both the unconverted line and the converted line will be output to the line buffer. The converted line will be written to the line buffer via DMA channel 8. Bit 6: Bit 5: Bit 4: Decode output enable. Decode Output Enable allows decoded data to be output to the line buffers. This bit should not be set in MH or MR decoding until the first EOL has been found. The decoder output should also be disabled after an error line until the next EOL is found. This bit should always be set for the MMR decoder. The Vertical OR bit is only valid in decompression mode when the bilevel resolution conversion bit in the T4Config register is also set. When the Vertical OR bit is set, the resolution converted decoded output data is ORed with the corresponding byte from the previous line before storing. Bit 3: Vertical OR enable. Bit 2: Reset or halt the coding or decoding. Setting the Reset/Halt bit immediately halts coding or decoding of a line, resets all the T4 Status bits, and clears the active T4Data FIFO. All other bits in this register are ignored if the Reset/Halt bit is set. When coding or decoding is in progress, writing to any bit in this register except Reset/Halt is ignored. Bit 1: Start coding or decoding. The Start bit begins the coding or decoding of the line according to the configuration selected per the T4Config register. 14-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Bit 0: Flush the code word. The Flush CW bit is only valid during MMR compression mode. Writes to this bit are ignored when coding/decoding is in progress, or when decompression is selected. When the Flush CW bit is set at the end of coding a line, it causes any data in the active T4Data FIFO to be filled in order to make a complete halfword which can then be read by the CPU or DMA controller. The fill bits are the opposite value of the last CW bit, unless the non-inverted flush bit in the T4Config register is set. In this case, the data is flushed with zeros. One halfword is always output when the flush bit is set even if the last CW is already halfword aligned. Address T4 Status (T4Status) $01FF8174 (R) Bit 15 T4 Datax DMA Page Boundary Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write Reference FIFO Ready Default Rst. Value 00h Read Value 00h T4 Datax T4 Datax FIFO DMA FIFO DMA Acknowledge Request Write Read Write Read T4Datax T4Datax Uncoded Uncoded FIFO Ready FIFO Ready FIFO Ready FIFO Ready Address T4 Status (T4Status) $01FF8175 (R) Bit 7 EOL Condition Bit 6 Tag Bit Bit 5 Bit 4 Bit 3 Line Error Type Bit 2 Bit 1 Bit 0 All White Line Default Rst. Value 00h Read Value 00h Line Error nonConsecutive EOL/ MMREOL Bit 15: This a copy of the hardware signal from the DMA channel indicating when the DMA block size has been reached and is used by the FIFO to prevent its DMA request from being asserted if Smart EOL Operation has been enabled via the T4 Configuration register. This is a copy of the hardware signal from the DMA channel indicating a DMA transfer is in progress. This is a copy of the hardware signal to the DMA channel indicating the desire to initiate a DMA transfer. The WrT4DataFIFORdy bit is set during decompression mode when the active T4Data FIFO is not full and is cleared when the FIFO is full. The RdT4DataFIFORdy bit is set when compressed data is available in the active T4Data FIFO. This bit is cleared when there is no data available. The WrUncodedFIFORdy bit is set during compression mode when the Uncoded Line FIFO is not full and is cleared when the FIFO is full. The RdUncodedFIFORdy bit is set when uncompressed data is available in the Uncoded Line FIFO. This bit is cleared when there is no data available. The WrRefFIFORdy bit is set during either MR/MMr compression or decompression mode when the Reference Line FIFO is not full and is cleared when the FIFO is full. Bit 14: Bit 13: Bit 12: Bit 11: Bit 10: Bit 9: Bit 8: 100723A Conexant 14-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Bit 7: End of Line Conditions. For coding, the End-of-line Condition occurs when all data in the line has been compressed and the last codeword has been written to the T4Data FIFO. For decoding, the End-of-line Condition occurs when the decoding of a line is complete, and all decoded data has been written to the line buffer. For MH and MR modes, decoding is complete when the EOL codeword (and Tag bit if in MR mode) have been decoded. For MMR mode, decoding is complete when the number of bytes specified by the T4Bytes register have been decoded. Bit 6: Bit 5: Bit 4: Line Error. The Tag bit is only valid when the End-of-line Condition bit is also set. The NonConsecutiveEOL/MMREOL is only valid when the End-of-line Condition bit is also set. Line errors apply to the decoding mode only. If a line error occurs while decoding a line, the T.4 hardware will set the LineError bit. Decoding will continue until an EOL code is found (MH and MR modes only), but data decoded following the error will not be output to the line buffer.. The type of line error can be determined by examing the Line Error Type bit field. When a line error occurs, the type of line error is placed in this bit field. The following line errors are detected by the T.4 hardware: Error: No error RTC (Return to Control) Error Terminating Code Error Fill bits occurred between consecutive EOL codewords. Codewords for white or black run lengths equal to zero which occur at the end of a line are missing. When this error occurs the TC error bit (T4Status register) is set as well as the normal error bit; this is to allow the user to ignore these errors if desired. Description: Bit 3-1: Line Error Type. LineError Code: 000b 001b 010b 011b 100b 101b 110b 111b Reserved Line Too Short Line Too Long Code Word Error Reserved EOL code found before the number of bytes specified in the T4Bytes register have been decoded. The number of data bytes decoded before the EOL code is received exceeds the line length specified in the T4Bytes register. An invalid code word was decoded. Bit 0: Indicate the decoded line is all white when this bit is set. This bit is reset when the decoding of a line is started. Notes: 1. An IRQ is generated whenever any of the shaded bits shown in the T4 Status register (bits 4, 7-9) and their associated bits in the T4IntMask register are both set. 2. Bits 0-6, and 9 only apply to decompression mode. 3. Bits 0-7 are cleared at the start of a new line. 14-6 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address T4 Line Length (T4Halfwords) $01FF8179 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 Bit 8 Default Rst. Value xxxxxx00b Read Value 00h Line Length bits 9-8 Address T4 Line Length (T4Halfwords) $01FF8178 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Rst. Value 00h Read Value 00h Line Length bits 7-0 Bit 15-10: Bit 9-0: Line Length Not used The T4 Line Length register defines the number of bytes in the line to be coded or decoded. Line length values from 001h through 3ffh correspond to 1 through 1023 halfwords of data. Address T4 Interrupt Mask (T4IntMask) $01FF8177 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 Enable Wr T4Data FIFO Rdy Bit 11 Bit 10 Bit 9 Enable Rd Uncoded FIFO Rdy Bit 8 Enable Wr Ref FIFO Rdy Default Rst. Value xxx00000b Read Value: 00h Enable Rd Enable Wr T4Data FIFO Uncoded Rdy FIFO Rdy Address T4 Interrupt Mask (T4IntMask) $01FF8176 Bit 7 Enable End of Line Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 Bit 3 Bit 2 (Not Used) Bit 1 (Not Used) Bit 0 (Not Used) Default Rst. Value 0xx0xxxxb Read Value 00h Enable Line (Not Used) Error Bit 15-13: Bit 12: Bit 11: Bit 10: Bit 9: Bit 8: Bit 7: Bit 6-5: Bit 4: Bit 3-0: Line Error Enable Interrupt. Not used WrT4DataFIFORdy Enable Interrupt RdT4DataFIFORdy Enable Interrupt WrUncodedFIFORdy Enable Interrupt RdUncodedFIFORdy Enable Interrupt WrRefFIFORdy Enable Interrupt End of Line Enable Interrupt. Not used Not used The four interrupt enable bits correspond to bits in the T4 Status register. The position of each interrupt enable bit is in the same place as its corresponding bit in the T4 Status register (bit 7 - End of Line Enable Interrupt corresponds to bit 7 - EOL Condition). 100723A Conexant 14-7 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address T4 FIFO Bits Remaining Register (T4FIFOBitRem) $01FF817B Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Rst. Value xxh Read Value: 00h Address T4 FIFO Bits Remaining Register (T4FIFOBitRem) $01FF817A Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 Bits remaining Bit 2 Bit 1 Bit 0 Default Rst. Value xxxx0000b Read Value x0000000b Bit 15-4: Bit 3-0: Not used Number of bits remaining in FIFO (holding register), with values ranging from 0 to 15. The interpretation of bits remaining depends on the direction of data flow. If the compressor/decompressor is emptying the FIFO, bit remaining is the number of that contain data that have yet to be processed. If the compressor/decompressor is filling the FIFO, bits remaining is the number of bits that are empty. T.4 data FIFO halfword[3:0] for the coded data to/from the external memory (for DMA channel 10): Address: T.4 Data FIFO (T4Data1FIFOx) Bit 15 data bit 15 Bit 14 data bit 14 Bit 13 data bit 13 Bit 12 data bit 12 Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value xxh Read Value xxh Default: Rst Value xxh Read Value xxh Address: T.4 Data FIFO (T4Data1FIFOx) Bit 7 data bit 7 Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 * Address assignment for T.4 Data FIFO halfword[3:0] FIFO halfword FIFO halfword 3 FIFO halfword 2 FIFO halfword 1 FIFO halfword 0 The register name T4DataFIFO3 T4DataFIFO2 T4DataFIFO1 T4DataFIFO0 Address 01FF8117-16 01FF8115-14 01FF8113-12 01FF8111-10 14-8 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 T.4 Ref. line Data FIFO halfword[3:0] for the uncoded data to/from the external memory (for DMA channel 7): Address: T.4 Reference Line Data FIFO (T4RefDataFIFOx) Address: T.4 Reference Line Data FIFO (T4RefDataFIFOx) Bit 15 data bit 15 Bit 14 data bit 14 Bit 13 data bit 13 Bit 12 data bit 12 Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value xxh Read Value xxh Default: Rst Value xxh Read Value xxh Bit 7 data bit 7 Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 * Address assignment for T.4 Ref. Line Data FIFO halfword[3:0] FIFO halfword FIFO halfword 3 FIFO halfword 2 FIFO halfword 1 FIFO halfword 0 The register name T4RefDataFIFO3 T4RefDataFIFO2 T4RefDataFIFO1 T4RefDataFIFO0 Address 01FF8157-56 01FF8155-54 01FF8153-52 01FF8151-50 T.4 Current line Data FIFO halfword[3:0] for the uncoded data to/from the external memory (for DMA channel 6): Address: T.4 Current Line Data FIFO (T4CurDataFIFOx) Address: T.4 Reference Line Data FIFO (T4CurDataFIFOx) Bit 15 data bit 15 Bit 14 data bit 14 Bit 13 data bit 13 Bit 12 data bit 12 Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value xxh Read Value xxh Default: Rst Value xxh Read Value xxh Bit 7 data bit 7 Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 * Address assignment for T.4 Current Line Data FIFO halfword[3:0] FIFO halfword FIFO halfword 3 FIFO halfword 2 FIFO halfword 1 FIFO halfword 0 The register name T4CurDataFIFO3 T4CurDataFIFO2 T4CurDataFIFO1 T4CurDataFIFO0 Address 01FF8167-66 01FF8165-64 01FF8163-62 01FF8161-60 100723A Conexant 14-9 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description T.4 Data FIFO Holding Register for the coded data to/from the external memory (for DMA channel 10): Address: T.4 Data FIFO Holding Register (T4Data1Hold) $01FF8119 Address: T.4 Data FIFO Holding Register (T4Data1Hold) $01FF8118 Bit 15 data bit 15 Bit 14 data bit 14 Bit 13 data bit 13 Bit 12 data bit 12 Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value xxh Read Value xxh Default: Rst Value xxh Read Value xxh Bit 7 data bit 7 Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 T.4 Ref. Line Data FIFO Holding Register for the Uncoded data to/from the external memory (for DMA channel 7): Address: T.4 Ref. Line Data FIFO Holding Register (T4RefDataHold) $01FF8159 Address: T.4 Ref. Line Data FIFO Holding Register (T4RefDataHold) $01FF8158 Bit 15 data bit 15 Bit 14 data bit 14 Bit 13 data bit 13 Bit 12 data bit 12 Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value xxh Read Value xxh Default: Rst Value xxh Read Value xxh Bit 7 data bit 7 Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 T.4 Current Line Data FIFO Holding Register for the Uncoded data to/from the external memory (for DMA channel 6): Address: T.4 Current Line Data FIFO Holding Register (T4CurDataHold) $01FF8169 Address: T.4 Current Line Data FIFO Holding Register (T4CurDataHold) $01FF8168 Bit 15 data bit 15 Bit 14 data bit 14 Bit 13 data bit 13 Bit 12 data bit 12 Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value xxh Read Value xxh Default: Rst Value xxh Read Value xxh Bit 7 data bit 7 Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 14-10 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 T.4 Data FIFO Control register for the coded data to/from the external memory (for DMA channel 10): Address: T.4 Data FIFO Control Register (T4Data1FIFOCtrl) $01FF811B Address: T.4 Data FIFO Control Register (T4Data1FIFOCtrl) $01FF811A Bit 15 FIFO Enabled (R) Bit 7 (Not Used) Bit 14 Data Request (R) Bit 6 Bit 13 FIFO Ready (R) Bit 5 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst Value 00h Read Value 00h Default: Rst Value x0x00000b Read Value 00h FIFO DMA Threshold FIFO Output Pointer Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Holding (Not Used) Register Full FIFO Data Quantity FIFO Input Pointer Bit 15 Bit 14 Bit 13 This bit indicates that the FIFO is active and capable of generating DMA requests. This bit is essentially a copy of the DMA Request output signal and indicates that the FIFO wishes to transfer data. This bit indicates that the FIFO can accept data transfers to/from the local logic. This bit is low when the data direction is into the local logic and the FIFO is empty or when the data direction is out of the local logic and the FIFO is full. This bit field indicates at which point the FIFO should issue a DMA request. It is compared with the FIFO Data Quantity bit field to determine when this should occur. Legal values are from 0 to 4. Values greater than 4 are treated as 4. This bit field indicates which byte of the FIFO quad halfword structure is the next to be used as output data. This bit indicates that there is a full word in the holding register This bit field indicates the number of quad halfwords that contain data. Valid values are from 0 to 4. This bit field indicates which byte of the FIFO quad halfword structure is the next to receive input data. Note: It is strongly recommended that the FIFO be disabled before firmware writes to the FIFO Control register. The FIFO Control register contains data that is essential to the FIFO's operation. If this data is changed while the FIFO is operating, unpredictable operation will result. Bit 12-10 Bit 9-8 Bit 6 Bit 4-2 Bit 1-0 100723A Conexant 14-11 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description T.4 Ref. Line Data FIFO Control register for the Uncoded data to/from the external memory (for DMA channel 7): Address: Bit 15 Bit 14 Data Request (R) Bit 13 FIFO Ready (R) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst Value 00h Read Value 00h Default: Rst Value x0x00000b Read Value 00h T.4 Ref. Line Data FIFO FIFO Control Enabled Register (R) (T4RefDataFIFOCtrl) $01FF815B Address: Bit 7 T.4 Ref. Line Data (Not Used) FIFO Control Register (T4RefDataFIFOCtrl) $01FF815A FIFO DMA Threshold FIFO Output Pointer Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Holding (Not Used) Register Full FIFO Data Quantity FIFO Input Pointer T.4 Current Line Data FIFO Control register for the Uncoded data to/from the external memory (for DMA channel 6): Address: Bit 15 Bit 14 Data Request (R) Bit 13 FIFO Ready (R) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst Value 00h Read Value 00h Default: Rst Value x0x00000b Read Value 00h T.4 Current Line FIFO Data FIFO Control Enabled Register (R) (T4CurDataFIFOCtrl) $01FF816B Address: Bit 7 T.4 Current Line (Not Used) Data FIFO Control Register (T4CurDataFIFOCtrl) $01FF816A FIFO DMA Threshold FIFO Output Pointer Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Holding (Not Used) Register Full FIFO Data Quantity FIFO Input Pointer T.4 Data FIFO Data Port for the coded data to/from the external memory: Address: T.4 Data FIFO Data Port (T4Data1Port) $01FF811D Address: T.4 Data FIFO Data Port (T4Data1Port) $01FF811C Bit 15 data bit 15 Bit 14 data bit 14 Bit 13 data bit 13 Bit 12 data bit 12 Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value xxh Read Value xxh Default: Rst Value xxh Read Value xxh Bit 7 data bit 7 Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 14-12 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address T4 Data FIFO Data Port Transfer (T4Data1PortTfr) $01FF814F (DW) Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Rst. Value xxh Read Value: xxh Address T4 Data FIFO Data Port Transfer (T4Data1PortTfr) $01FF814E (DW) Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 (Not Used) Bit 2 (Not Used) Bit 1 (Not Used) Bit 0 (Not Used) Default Rst. Value xxh Read Value xxh Bit 15-0: Not used. Writing any value to this register causes the data in FIFO to push or pop data through the FIFO data port and the FIFO Quad Halfword 1-4 registers. The FIFO operation depends on the direction of data flow. If the compressor/decompressor is emptying the FIFO, data is transferred from the FIFO data port register to the FIFO Quad Halfword 1 register, simultaneously with data transfer from Quad Halfword 1 to Quad Halfword 2, Quad Halfword 2 to Quad Halfword 3, and Quad Halfword 3 to Quad Halfword 4, with the original data of Quad Halfword 4 being lost. If the compressor/decompressor is filling the FIFO, data is transferred from the FIFO Quad Halfword 1 register to the FIFO data port register, simultaneously with data transfer from Quad Halfword 2 to Quad Halfword 1, Quad Halfword 3 to Quad Halfword 2, and Quad Halfword 4 to Quad Halfword 3, with the contents of Quad Halfword 4 becoming indeterminate. T.4 Ref. Line Data FIFO Data Port for the Uncoded data to/from the external memory: Address: T.4 Ref. Line Data FIFO Data Port (T4RefDataPort) $01FF815D Address: T.4 Ref. Line Data FIFO Data Port (T4RefDataPort) $01FF815C Bit 15 data bit 15 Bit 14 data bit 14 Bit 13 data bit 13 Bit 12 data bit 12 Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value xxh Read Value xxh Default: Rst Value xxh Read Value xxh Bit 7 data bit 7 Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 Address T4 Ref. Line Data FIFO Data Port Transfer (T4RefDataPortTfr) $01FF815F (DW) Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Rst. Value xxh Read Value: xxh Address T4 Ref. Line Data FIFO Data Port Transfer (T4RefDataPorTfrt) $01FF815E (DW) Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 (Not Used) Bit 2 (Not Used) Bit 1 (Not Used) Bit 0 (Not Used) Default Rst. Value xxh Read Value xxh 100723A Conexant 14-13 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Bit 15-0: Not used Writing any value to this register causes the data in FIFO to push or pop data through the FIFO data port and the FIFO Quad Halfword 1-4 registers. The FIFO operation depends on the direction of data flow. If the compressor/decompressor is emptying the FIFO, data is transferred from the FIFO data port register to the FIFO Quad Halfword 1 register, simultaneously with data transfer from Quad Halfword 1 to Quad Halfword 2, Quad Halfword 2 to Quad Halfword 3, and Quad Halfword 3 to Quad Halfword 4, with the original data of Quad Halfword 4 being lost. If the compressor/decompressor is filling the FIFO, data is transferred from the FIFO Quad Halfword 1 register to the FIFO data port register, simultaneously with data transfer from Quad Halfword 2 to Quad Halfword 1, Quad Halfword 3 to Quad Halfword 2, and Quad Halfword 4 to Quad Halfword 3, with the contents of Quad Halfword 4 becoming indeterminate. T.4 Current Line Data FIFO Data Port for the Uncoded data to/from the external memory: Address: Bit 15 Bit 14 data bit 14 Bit 13 data bit 13 Bit 12 data bit 12 Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value xxh Read Value xxh Default: Rst Value xxh Read Value xxh T.4 Current Line data Data FIFO Data Port bit 15 (T4CurDataPort) $01FF816D Address: Bit 7 T.4 Current Line data Data FIFO Data Port bit 7 (T4CurDataPort) $01FF816C Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 Address Bit 15 Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Rst. Value xxh Read Value: xxh T4 Current Line Data (Not Used) FIFO Data Port Transfer (T4CurDataPortTfr) $01FF816F (DW) Address Bit 7 Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 (Not Used) Bit 2 (Not Used) Bit 1 (Not Used) Bit 0 (Not Used) Default Rst. Value xxh Read Value xxh T4 Current Line Data (Not Used) FIFO Data Port Transfer (T4CurDataPortTfr) $01FF816E (DW) Bit 15-0: Not used Writing any value to this register causes the data in FIFO to push or pop data through the FIFO data port and the FIFO Quad Halfword 1-4 registers. The FIFO operation depends on the direction of data flow. If the compressor/decompressor is emptying the FIFO, data is transferred from the FIFO data port register to the FIFO Quad Halfword 1 register, simultaneously with data transfer from Quad Halfword 1 to Quad Halfword 2, Quad Halfword 2 to Quad Halfword 3, and Quad Halfword 3 to Quad Halfword 4, with the original data of Quad Halfword 4 being lost. If the compressor/decompressor is filling the FIFO, data is transferred from the FIFO Quad Halfword 1 register to the FIFO data port register, simultaneously with data transfer from Quad Halfword 2 to Quad Halfword 1, Quad Halfword 3 to Quad Halfword 2, and Quad Halfword 4 to Quad Halfword 3, with the contents of Quad Halfword 4 becoming indeterminate. 14-14 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 15. Synchronous/Asynchronous Serial Interface (SASif) 15.1 Functional Description The SASIF is a Synchronous/Asynchronous Receiver/Transmitter which performs serial-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion of data for transmission to a peripheral device. The interface consists of serial transmit data (SASTXD), serial receive data (SASRXD), and a serial clock (SASSCLK) signals. Figure 15-1 is a block diagram of the SASIF. The SASIF includes a programmable baud rate generator for asynchronous and synchronous operations. Four interrupts can be generated for the ARM. These are Transmit Shift Register empty, Transmit Buffer Register Empty, or Receive Buffer Register full, and Receive FIFO Timeout. These interrupts can each be uniquely enabled or disabled. The SASIF can also be set to FIFO mode. In this mode, the ARM will be relieved of excessive interrupt handling and will allow for an overall faster transmit and receive speed. A FIFO mode can be enabled for either the receive portion or the transmit portion of the SASIF. When the transmit FIFO is enabled, a 16-byte FIFO will be used to hold up to 16 bytes of data to be transmitted. The Transmit Buffer Empty interrupt will only be generated if the transmit FIFO has no new data to transmit (it is empty). When the receive FIFO is enabled, a 16-byte FIFO will be used to store up to 16 bytes of data which are received from the receive shift register. The Receive Buffer Full interrupt will only be generated if the receive FIFO has no room left for incoming data (it is full). The receive FIFO also includes a timeout function. If the receive FIFO is not full, but the last newly received byte was longer than four byte times ago (based on the programmed baud rate), then a timeout interrupt will be generated. A "byte time" is the time in which it takes to receive one byte of data. The receive and transmit data is double buffered to provide more time for the ARM to process receive data. The data shifting order, MSB to LSB or LSB to MSB, and the SASCLK polarity are programmable. The synchronous communication mode enables the ARM to transmit and receive data synchronous referencing to the serial clock. The ARM can read the status of the SASIF at any time during operation. Status includes IRQ source (SASTXD or SASRXD) and operation mode (synchronous or asynchronous). During the Input/Output mode the SASTXD, SASRXD, and SASSCLK values can also be read or written by the ARM. The contents of each byte within the transmit and receive fifo can be read any time during operation, as well as the input and output pointers to both fifos. Following is the feature summary of the Serial Interface: * * * * * * * * * * * Full duplex, three wire system: SASSCLK (serial clock), SASTXD (Transmit data), SASRXD (Receive data) Independent transmit data shift register and receive data shift register Double buffered receive and transmit data register Programmable 7 or 8 data bit asynchronous serial-interface with a start bit, a stop bit and no parity 8 data bit synchronous serial-interface with programmable data shifting order Programmable baud rate generator supports up to 14400 baud asynchronous transmit and receive (when in fifo mode is not on), and up to 2 ICLK synchronous transmit and receive Supports up to 115.2 Kbaud asynchronous transmit and receive when in FIFO mode Single interrupt generation for Transmit Data Shift Register empty, Transmit Data Buffer Register empty, Receive Data Buffer Register full, and Receive FIFO Timeout In the FIFO mode, transmitter and receiver are each buffered with 16 byte FIFO's to reduce the number of interrupts to the ARM. Maximum 1% SASTXD Async transmit baud rate error Maximum 2.5% SASRXD Async receive baud rate allowable error 100723A Conexant 15-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description SclkCtrlLo SclkCtrlHi SASIrqCtrl IRQSASIf ClockGen TxRxControl IOControl SASIRQ Control SASTXD SASRXD SASSCLK SASCommand Reg TxBuffer Reg (SASData) TxShift Reg RxBuffer Reg (SASData) CPU Bus RxShift Reg Figure 15-1. SASIF Block Diagram 15-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 15.2 Register Description Address: SASCmd 01FF80F1 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Rst. Value X0000000b Read Value 00h Address: SASCmd 01FF80F0 Bit 7 (Not Used) Bit 6 TxFIFOEnb Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 SASMode Bit 0 RxFIFOEnb L2MSB SASSCLKPo DataLen l Register Description: SASIF Command Register Bit 15-7: Not used Bit 6: TxFIFOEnbRead/Write bit. This bit controls whether or not the 16-byte transmit FIFO is to be used. When the TxFIFOEnb is cleared (default), the transmit FIFO will not be used and an interrupt will be generated each time a byte is sent. If TxFIFOEnb is set, the transmit FIFO will be used and an interrupt will be generated only when the FIFO is completely emptied. This should ONLY be written to during setup and not after the SASIF has started sending or receiving data, as data loss could occur. This bit controls whether or not the 16-byte receive FIFO is to be used. When the RxFIFOEnb is cleared (default), the receive FIFO will not be used and an interrupt will be generated for each byte received. If RxFIFOEnb is set, then the receive FIFO will be used and an interrupt will only be generated if the FIFO is full or a receive FIFO timeout occurs. This should ONLY be written to during setup and not after the SASIF has started sending or receiving data, as data loss could occur. This bit controls the shifting order of the transmit and receive registers. When the L2MSB bit is cleared (default) and the SASIF is set to the AsyncMode or SyncMode, the transmit and receive shift register will shift from the MSB to the LSB. When the L2MSB bit is set, the transmit and receive register will shift from the LSB to MSB. Bit 5: RxFIFOEnbRead/Write bit. Bit 4: L2MSBRead/Write bit. Bit 3: SASSCLKPolRead/Write bit. This bit controls the polarity of the SASSCLK pin for the sync mode. When the SASSCLKPol bit is cleared (default) and the SASIF is set to AsyncMode or SyncMode, the SASSCLK polarity will be non-inverted, which will enable the external logic to clock the SASTXD pin on the rising edge of the SASSCLK pin. When the SASSCLKPol bit is set and the SASIF is set to AsyncMode or SyncMode, the SASSCLK polarity will be inverted, which will enable the external logic to clock the SASTXD pin on the falling edge of the SASSCLK pin. Bit 2: DataLenRead/Write bit. This bit controls the number of bit for AsyncMode transmit. This bit is not effective for the SyncMode. When the DataLen is cleared (default) and the SASIF is set to the AsyncMode, the TxBuffer register bit 7 will be the MSB and bit 0 will be the LSB for asynchronous transmit. The transmit shifting order is controlled by the L2MSB bit. When the DataLen is set and the SASIF is set to the AsyncMode, the TxBuffer register bit 6 will be the MSB and bit 0 will be the LSB for asynchronous transmit. 100723A Conexant 15-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Bit1-0: SASModeRead/Write bits. These two bits control the SASIF operation modes. 00: AsyncMode (default) 01: SyncMode 10 & 11: Reserved Note: The TxFIFO enable and the RxFIFO enable should either be set or cleared once in the setup of the SASIF device. Enabling or disabling the FIFOs once the MFC is up and running could have unpredicted results if data is being received or sent by the shift registers. Address: SASRxData 01FF80F3 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Rst. Value 00h Read Value 00h Address: SASRxData 01FF80F2 Bit 7 SASRx Data(7) Bit 6 SASRx Data(6) Bit 5 SASRx Data(5) Bit 4 SASRx Data(4) Bit 3 SASRx Data(3) Bit 2 SASRx Data(2) Bit 1 SASRx Data(1) Bit 0 SASRx Data(0) Register Description: SASIF Rx Data Buffer Register Note: This is the Receive buffer data register. Reading from this register will return the data in the Rxbuffer (for fifo disabled) or the oldest valid received data (for fifo enabled). However, after a read, a write MUST be done to this register in order to let the SASIF know that data has been read. This was done to help with emulation testing. Writing to the SASData Register will clear the RxBufFull or RxFifoThresh status bits. Address: SASTxData 01FF80FB Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Rst. Value 00h Read Value 00h Address: SASTxData 01FF80FA Bit 7 SASTx Data(7) Bit 6 SASTx Data(6) Bit 5 SASTx Data(5) Bit 4 SASTx Data(4) Bit 3 SASTx Data(3) Bit 2 SASTx Data(2) Bit 1 SASTx Data(1) Bit 0 SASTx Data(0) Register Description: SASIF Tx Data Buffer Register (write only) Note: This is the Transmit buffer data register. It is a write only register. Writing to this register placed data into the transmit buffer register (or the transmit fifo if TxFifo is enabled). Writing to the SASTxData Register will clear the TxBufEmpty or TxFifoThresh status bits. 15-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: SASFifoPtr 01FF80F7 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h Default: Rst. Value 00h Read Value 00h Tx Input Pointer Tx Output Pointer Address: SASFifoPtr 01FF80F6 Bit 7 Bit 6 Bit 5 Rx Input Pointer Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rx Output Pointer Register Description: SASIF Fifo Pointer Register Bit 15-12: Transmit FIFO input pointer Bit 11-8: Transmit FIFO output pointer Bit 7-4: Bit 3-0: Address: SASFifoQty 01FF80FD (Read Only bit) (Read Only bit) (Read Only bit) (Read Only bit) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value X0000011b Read Value 00000011b Default: Rst. Value X0000011b Read Value 00000011h Receiver FIFO input pointer Receiver FIFO output pointer Bit 15 (Not Used) Bit 14 Bit 13 Tx FIFO Quantity TxFIFOThreshVal Address: SASFifoQty 01FF80FC Bit 7 (Not Used) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rx FIFO Quantity RxFIFOThreshVal Register Description: SASFifoQty Register Bit 15: Not Used Bit 14-10: TxFIFOQty (Transmit FIFO Quantity)Read Only bits. These five bits hold the value of the amount of bytes stored within the transmit FIFO. As data is written to or removed from the TxFIFO, the quantity will be adjusted accordingly. Bit 9-8: TxFIFOThreshVal (Transmit FIFO Threshhold value)Read/Write bits. Depending on how these two bits are set, will affect when the transmit FIFO considers itself empty enough to cause an interrupt. Bit Value "00" "01" "10" "11" # of bytes left in TxFIFO which should cause interrupt 12 8 4 2 Bit 7: Not Used 100723A Conexant 15-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Bit 6-2: RxFIFOQty (Receive FIFO Quantity)Read Only bits. These five bits hold the value of the amount of bytes stored within the receive FIFO. As data is written to or removed from the RxFIFO, the quantity will be adjusted accordingly. Bit 1-0: RxFIFOThreshVal (Receive FIFO Threshhold value)Read/Write bits. Depending on how these two bits are set, will affect when the receive FIFO considers itself full enough to cause an interrupt. Bit Value "00" "01" "10" "11" # of bytes filled in RxFIFO which should cause interrupt 4 8 12 14 Address: SASIrqSts 01FF80F9 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 RxFifo Overrun (Read only) Bit 4 Bit 11 TxFifoFull (Read only) Bit 10 Bit 9 Bit 8 Default: TxFifoEmpty RxFifoFull (Read only) (Read only) Address: SASIrqSts 01FF80F8 Bit 7 RxTimeout Elapsed (Read only) Bit 6 RxTimeout Enb Bit 5 Bit 3 Bit 2 Bit 1 RxFifoEmpt Rst. Value y XXh (Read only) Read Value 05h Bit 0 Default: Rst. Value X0XXX000b Read Value 30h TxBufIrqEnb TxShfIrqEnb RxBufIrqEn TxBufEmpty TxShfEmpty RxBufFull b (Read only) Or Or RxFifoThres TxFifoThres h h (Read only) (Read only) Register Description: SerSASIrqCtrl Register Bit 15-13: Bit 12: Not Used RxFifoOverrun(Receive FIFO data loss)Read only bit. This bit goes high when the receive FIFO is completely full, but an extra byte has just been received by the RxShiftReg. This will not cause an interrupt, but the RxFifoThresh should already have done so. Bit 11: TxFifoFull(Transmit FIFO full)Read only bit. This bit goes high when the transmit FIFO is completely full. Data cannot be written to the transmit FIFO after this point. This will not cause an interrupt. This is helpful when trying to figure out if more bytes can be written to the transmit FIFO. Bit 10: TxFifoEmpty(Transmit FIFO empty)Read only bit. This bit goes high when the transmit FIFO is completely empty. This will not cause an interrupt, but the TxFifoThresh should have already done so. 15-6 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Bit 9: RxFifoFull(Receive FIFO full)Read only bit. This bit goes high when the receive FIFO is completely full. New received data received from the RxShiftReg will be thrown away. This will not cause an interrupt, but the RxFifoThresh should have already done so. Bit 8: RxFifoEmpty(Receive FIFO empty)Read only bit. This bit goes high when the receive FIFO is completely empty. This will not cause an interrupt. This can be helpful in trying to figure out if more data can be read from the receive FIFO. Bit 7: RxTimoutElapsed (Receive FIFO Timeout occurred)Read only bit. The RxTimoutElapsed shows the status of the Timeout function of the receive FIFO. When the RxTimoutElapsed is set, the Timer has timed out which means that the FIFO has not received any new data for too long of a time, but the FIFO is not full. When this bit is cleared, the receive FIFO is running properly. This will cause an interrupt in conjunction with RxTimeoutEnb Bit 6: RxTimeoutEnb (Receive Timeout Interrupt Enable)Read/Write bit. When the RxTimerEnb is cleared (default), the RxTimeoutIRQ signal will be disabled. When the RxTimerEnb bit is set, the RxTimeoutIRQ will be enabled. Bit 5: TxBufEmpty/TxFifoThresh (Transmit Data Buffer Register Empty or Transmit FIFO Threshhold met)Read only bit. The TxBufEmpty bit shows the status of the transmit buffer register when TxFIFO is disabled. The transmit buffer register is empty when this bit is set. The transmit buffer register is when this bit is cleared. When TxFIFO is enabled, the transmit FIFO has met its threshhold limit when this bit is set, and is not yet emptied to its threshhold when this bit is cleared. This bit will cause an interrupt in conjunction with TxBufIRQEnb. Bit 4: TxShfEmpty (Transmit Shift Data Register Empty)Read only bit. The TxShfEmpty bit shows the status of the transmit shift register. The transmit shift register is empty when this bit is set. The transmit shift register is full when this bit is cleared. Bit 3: RxBufFull/RxFifoThresh (Receive Buffer Register Full or Receive FIFO Threshhold met)Read only bit. The RxBufFull bit show the status of the receive buffer register (when RxFIFO is disabled). The receive buffer register is empty when this bit is cleared. The receive buffer register is when this bit is set. When RxFIFO is enabled, the receive FIFO has met its threshhold when this bit is set, and is not yet filled to its threshhold limit when this bit is cleared. This bit will cause an interrupt in conjunction with RxBufIRQEnb. 100723A Conexant 15-7 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Bit 2: TxBufIrqEnb (Transmit Buffer IRQ Enable)Read/Write bit. When the TxBufIrqEnb bit is cleared (default), the TxBufIRQ signal is disabled. The TxBufIRQ will be activated, when the TxBufIrqEnb control bit and the TxBufEmpty status bit are set. Bit 1: TxShfIrqEnb (Transmit Shift Empty IRQ Enable)Read/Write bit. When the TxShfIrqEnb bit is cleared (default), the TxShfIRQ signal will be disabled. The TxShfIRQ will be activated, when the TxShfIrqEnb control bit and the TxShfEmpty status bit are set. Bit 0: RxBufIrq (Receive Buffer IRQ Enable)Read/Write bit. When the RxBufIrqEnb bit is cleared (default), the RxBufIRQ signal will be disabled. The RxBufIRQ will be activated, when the RxBufIrqEnb control bit and the RxBufFull status bit are set. For monitoring the TxBuffer, TxShift, and RxBuffer Register status, the SASIF has four status bits. They are TxBufEmpty, TxShfEmpty, RxBufFull, and RxTimerElapsed status bits. Following are the conditions when the status bits are set and cleared: TxBufEmpty Set when 1. the system resets, or 2. the last bit of the TxShift Register is sent to the SASTXD pin Cleared when 1. the CPU writes to the SASData Register, and 2. the TxShfEmpty status bit is cleared. TxShfEmpty 1. the system resets, or 2. the TxBufEmpty status bit is set and the last bit of the TxShift Register is sent to the SASTXD pin. 1. the CPU writes to the SASData Register, and 2. the TxBufEmpty status bit is set. RxBufFull1 1. the stop bit is received by the SASRXD pin. 1. the system reset, or 2. the CPU reads the SASData Register. RxTimerElapsed Set when When all of these are true for the time it would take to receive 4 bytes into the Rx buffer. The RxFIFO is not full, No start bit has been received, the SASRxData Register has not been read and written back to. Cleared when 1. the system resets 2. the CPU writes to the SASRxData Register 15-8 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 For keeping track of the transmit and receive activities, the SASIF has four separate interrupts -- the TxBufIRQ, TxShfIRQ, RxBufIRQ, and RxTimeoutIRQ. Any of these interrupt activate will turn on the IRQSASIF. Following are the conditions when they are set and cleared: TxBufIRQ Activated when Deactivated when 1. the TxBufEmpty status bit is set, and 2. the TxBufIrqEnb control bit is set. 1. the TxBufEmpty status bit is cleared, or 2. the TxBufIrqEnb control bit is cleared. TxShfIRQ 1. the TxShEmpty status bit is set, and 2. the TxShfIrqEnb control bit is set, and 1. the TxShEmpty status bit is cleared, or 2. the TxShfIrqEnb control bit is cleared. RxBufIRQ1 1. the RxBufFull status bit is set, and 2. the RxBufIrqEnb control bit is set. 1. the RxBufFull status bit is cleared, or 2. the RxBufIrqEnb control bit is cleared. RxTimeoutIRQ Activated when Deactivated when 1. the RxTimerElapsed status bit is set, and 2. the RxTimerEnb control bit is set. 1. the RxTimerElapsed status bit is cleared, or 2. the RxTimerEnb control bit is cleared. Note: The RxBufFull status bit and the RxBufIRQ is valid in the AsyncMode only. During the SyncMode, data receive to the SASIF is synchronous with the transmit data, therefore, the RxBufFull status bit and the RxBufIRQ signal is not used in the SyncMode. 100723A Conexant 15-9 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: SASDiv 01FF80F5 Bit 15 SASRXD Early 1 - Early Bit 7 Bit 14 (Not Used) Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 0x000000b Read Value 00h Default: Rst. Value 00h Read Value 00h SASSCLK Divisor Upper Bits (13-8) Address: SASDiv 01FF80F4 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SASSCLK Divisor Lower Bits (7-0) Register Description: This register controls bits of the SASSCLK Divisor. Bit 15: SASRXDEarly (Receive Data Early)Read/Write Bit. If this bit is set to one (default = 0), the input data will be sampled 1/2 shift clock early from what is illustrated in Figure 15-2. This is only for the sync mode. Bit 14: Not used Bit 13-8: DivHi (Divisor High Register)Read/Write bits. The DivHi Register is the higher bits (bit 13-8) of the SASSCLKDivisor Register, which defines the SASSCLK frequency. Bit 7-0: DivLo (Divisor Low Register)Read/Write bits. The DivLo Register is the lower bits (bit 7-0) of the SASSCLKDivisor Register, which defines the SASSCLK frequency. Writing the DivLo register will cause the SASIF logic to load the DivHi and DivLo to the internal counter. Firmware can transmit data with the right speed immediately after the SASSCLK setup. The SASSCLK Divisor Register defines the SASSCLK frequency, which depends on the AUXCLK frequency (fTstClk). The SASSCLKDivisor Register has a fourteen bit divisor region. The SASSCLK frequency (fSClk)and Divisor relationship is: For the sync mode, f SClk = INT ( f SClk = INT ( fAUXCLK ) 2 * Divisor + 2 fAUXCLK ) 8 * Divisor + 8 For the async mode, 15-10 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: SASTxFIFOn Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h Default: Rst. Value 00h Read Value 00h SASIF Tx FIFO Byte (2n + 1) Address: SASTxFIFOn Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SASIF Tx FIFO Byte (2n) Register Description: SASTxFIFO Register SASTxFIFO0 - Byte 0, 1 SASTxFIFO1 - Byte 2, 3 SASTxFIFO2 - Byte 4, 5 SASTxFIFO3 - Byte 6, 7 SASTxFIFO4 - Byte 8, 9 SASTxFIFO5 - Byte A, B SASTxFIFO6 - Byte C, D SASTxFIFO7 - Byte E, F 0x01FF8600-01 0x01FF8602-03 0x01FF8604-05 0x01FF8606-07 0x01FF8608-09 0x01FF860A-0B 0x01FF860C-0D 0x01FF860E-0F Address: SASRxFIFOn Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h Default: Rst. Value 00h Read Value 00h SASIF Rx FIFO Byte (2n + 1) Address: SASRxFIFOn Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SASIF Rx FIFO Byte (2n) Register Description: SASRxFIFO Register (Read Only Register) SASRxFIFO0 - Byte 0, 1 SASRxFIFO1 - Byte 2, 3 SASRxFIFO2 - Byte 4, 5 SASRxFIFO3 - Byte 6, 7 SASRxFIFO4 - Byte 8, 9 SASRxFIFO5 - Byte A, B SASRxFIFO6 - Byte C, D SASRxFIFO7 - Byte E, F 0x01FF8610-01 0x01FF8612-03 0x01FF8614-05 0x01FF8616-07 0x01FF8618-09 0x01FF861A-0B 0x01FF861C-0D 0x01FF861E-0F 100723A Conexant 15-11 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 15.3 SASIF Timing 15.3.1 SASSCLK Timing When SASSCLK is on (Figure 15-2), the duty cycle of SASSCLK is always 50%. AUXCLK Tserd SASSCLK Tserd SASTXD Tserd SASRXD Tserd applies to SASSCLK, SASTXD, and SASRXD when they are in output configuration Figure 15-2. SASSCLK Timing Diagram In Figure 15-2, TSERd is the AUXCLK to SASSCLK, SASRXD and SASTXD delay. TSERd applies to SASSCLK, SASTXD, and SASRXD when they are in output configuration. The SASSCLK polarity is controlled by the SAS Command Register SASSCLKPol Bit. When the SASSCLKPol bit is cleared (default), the SASTXD signal transition is on the SASSCLK falling edge. External logic can latch the SASTXD signal on the SASSCLK rising edge. When the SASSCLKPol bit is set, the SASTXD signal transition is on the rising edge of the SASSCLK. External logic can latch the SASTXD signal on the SASSCLK falling edge. When configured in the SyncMode, the SASSCLK will be active for eight cycles for each write to the empty SASData Register. Continuous SASSCLK can be achieved by keeping the transmit buffer register full. When there is no data on the SASTXD pin, the SASSCLK will stay in idle state, which is logic zero as the SASSCLKPol bit is clear and logic one as the SASSCLKPol bit is set. When configured in the AsyncMode, the SASSCLK is a free running signal at the SASSCLKDivisor pre-defined clock rate. 15.3.2 Synchronous Mode Timing When the SASIF is configured to the SyncMode, the SASIF generates the SASSCLK signal to synchronize data transmit and receive. Therefore, only the transmitter related status bit and IRQ signals are used, and the RxBufFull status bit and the RxBufIRQ signal are not used. 15.3.2.1 FIFOs Disabled The TxBufEmpty and TxShfEmpty status bits are both set on system reset. When the FIFOs are disabled and both the TxBuffer and TxShift Register are empty, writing to the SASData Register will clear the TxShfEmpty status bit, and will fill the TxShift Register with the TxBuffer Register content. When the TxBuffer is empty and the TxShift Register is non-empty, writing to the TxBuffer Register will clear the TxBufEmpty status bit, and the TxShift Register is unaffected. When the TxBuffer is full and the TxShift Register is empty, the TxBuffer Register value will be loaded into the TxShift Register. The TxBufEmpty status bit will be set, and the TxShfEmpty flag is unaffected. 15-12 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 When both the TxBuffer Register and TxShift register are empty, the TxShfEmpty status bit will be set when the last bit of the data is shifted to the SASTXD pin. 15.3.2.2 FIFOs Enabled When FIFOs are enabled and the transmit FIFO is completely empty and TxShift Register is empty, writing to the SASData Register will clear the TxShfEmpty status bit, keep the TxBufEmpty bit set and will fill the TxShift Register with the contents of the first FIFO location written to. When the transmit FIFO is completely empty and the TxShift Register is non-empty, writing to the transmit FIFO (accomplished by writing SASData) will clear the TxBufEmpty status bit and the TxShift Register is unaffected (it will stay filled and the TxShfEnpty will stay cleared). When the transmit FIFO is not empty and the TxShift Register is empty, the value of the oldest valid FIFO location will be loaded into the TxShift Register. The TxBufEmpty status bit will be set only if the last valid FIFO location was just transferred to the TxShift Register. The TxShfEmpty flag is unaffected. When the transmit FIFO is completely empty and TxShift register are empty, the TxShfEmpty status bit will be set when the last bit of the data is shifted to the SASTXD pin. 15.3.2.3 Transmiting and Sampling The SASRXD signal is sampled on the falling edge of the SASSCLK when the SASSCLKPol bit is cleared. SASRXD signal is sampled on the rising edge of the SASSCLK when the SASSCLKPol bit is set. If the SASRXDEarly bit is set the SASRXD signal will be sampled 1/2 SASSCLK early. When the L2MSB control bit is cleared, the MSB to the LSB of the TxShift Register will be shifted to the SASTXD pin, and the SASRXD signal will be shifted into the MSB of the RxShift Register. If the L2MSB bit is set, the LSB to the MSB of the TxShift Register will be shifted to the SASTXD pin, and the SASRXD signal will be shift into the LSB of the RxShift Register. The DataLen bit is not used in the SyncMode, eight data bits will be transmitted or received regardless of setting. SASSCLK SASTXD SASRXD SASCs TxBufEmpty TxShfEmpty Figure 15-3. Synchronous Mode Timing MSB MSB Wr SerData LSB LSB D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 15.3.3 Asynchronous Mode Transmitter Timing Once AsyncMode is set, the transmitter logic will set SASTXD to logic one and will stay in the transmitter idle state. After the ARM writes to the SASData Register, SASTXD will output the Start bit (logic 0) on the next SASSCLK falling edge. Starting from LSB of the TxShift Register (when L2MSB is set), a total of 7 or 8 bits of data (depending on the DataLen bit) will be sent. The bit next to the last data bit is the Stop bit. Similarly to the SyncMode transmit timing, the TxBufEmpty, TxShfEmpty status bits, and the TxBufIRQ, TxShfIRQ has the same timing sequence. See Figure 15-4. 100723A Conexant 15-13 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description SASTXD SASSCLK LSB Start Wr SerData Stop SASCs TxBufEmpty TxShfEmpty Figure 15-4. Asynchronous Transmitter Timing The bit capture timing above is identical whether FIFO mode is enabled or disabled. At the end of each transmitted byte, a new byte will be loaded from the TxBuffer Register when FIFO mode is disabled, or from the oldest valid location with the FIFO when FIFO mode is enabled. Following are the timing sequence for the interrupt control and byte loading control for both FIFO enabled and FIFO disabled modes: SAS DATA WR SAS DATA WR bytes SASCSn SASTXD TxFIFOEnb Txload TxBufEmpty TxShfEmpty 1 2 3 15 16 1 Figure 15-5. Asynchronous Transmitter byte TimingFIFO Mode Enabled 15.3.3.1 Asynchronous Mode Receiver Timing Once AsyncMode is set, the receiver logic will look for a falling edge in the SASRXD signal and will stay in the receiver idle state. While SASRXD stays high, the receiver idles. When the Start bit comes, the SASIF EdgeDetector is triggered by the falling edge. Until the next internal 8X baud rate clock arrives, the beginning of this character is defined. Each bit has 8 8X baud rate clock pulses in it. Data is sampled on the fourth Baud8X clock from the receiving bit boundary. See Figure 15-6. If the sampling value of the Start bit is a logic 1, that start bit is regarded as a glitch or an invalid character, no RxBufIRQ will be generated. Start bit Baud8X Sampling SASRXD LSB Figure 15-6. Asynchronous Receiver Bit Timing 15-14 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 After receiving the Stop bit, when FIFO mode is disabled, the SERIRQ and the RxBufFull will both rise to a logic 1. RxBufFull and the SERIRQ will be cleared by reading of the SASData Register. SASRXD SASCs RxBufFull Start Bit LSB Stop Bit MSB Rd SerData Figure 15-7. Asynchronous Receiver Byte Timing - FIFO mode disabled When FIFO-mode is enabled, after receiving the stop bit, the SERIRQ and the RxBufFull will change to a logic 1 only if the receive FIFO becomes full as a result of adding that last byte. Both the interrupt and RxBufFull bit will be cleared when the SASData Register is read. SAS DATA RD SASCSn SASRXD RxFIFOEnb Rxload RxBufFull 1 bytes 2 3 15 16 Figure 15-8. Asynchronous Receiver Byte Timing - FIFO mode enabled The last feature of the FIFO mode is the timeout interrupt. In normal cases, the receive FIFO only causes an interrupt when it is completely full. However, in the case where less than 16 bytes were received and no more bytes are being sent to the SASIF, the timeout function tells the ARM that no data has been received within the required amount of time, so a RxTimeoutIRQ occurs. The time required to cause this interrupt is based on the baud rate and is 4 times the ammount of time that it would take to send one byte of data into the RxShift Register. So if no byte is transferred from the RxShift Register to the receive FIFO, nor is any bit shifted onto the RxShift Register in that time, then the RxTimeoutIRQ will occur. Here is an example of that: SAS DATA RD SASCSn SASRXD RxFIFOEnb Rxload TxBaudend RxTimerElapsed 1 2 3 4 32 beats without a Rxload Figure 15-9. Asynchronous Receiver FIFO TimeoutFIFO Mode Enabled 100723A Conexant 15-15 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 15.4 Firmware Operation 15.4.1 SASIF SyncMode Operation SyncMode Setup 1. 2. 3. 4. Set the SASSCLKDivisor Register for proper transmission rate. Set the L2MSB bit for proper shifting order. Set the SASSCLKPol bit for proper SASSCLK polarity. Set the transmit FIFO or receiver FIFO to be enabled if lower system overhead or faster transfer rate is required. By default, the two FIFO's are disabled. 5. Clear the TxBufIrqEnb bit and/or the TxShfIrqEnb bit if continuous transmitting is not required (lower CPU interrupt overhead and lower transfer rate), or set the TxBufIrqEnb bit and the TxShfIrqEnb bit if continuous transmission is needed (higher CPU interrupt overhead and higher transfer rate). 6. Set the SASMode bit to select SyncMode operations. Note: Steps 1 through 5 can be done in a setup-table load. Data Transmit and Receive Example - FIFO mode disabled Case when the TxBufIRQ and the TxShfIRQ are enabled: 1. The ARM writes first data to the SASData Register, and sets the TxBufIrqEnb and the TxShfIrqEnb bits. 2. The SASIF loads the TxBuffer Register (SASData Register ) to the TxShift Register and clears the TxShfEmpty status bit. 3. The SASIF transmits, and receives bits 7 through bit 0 (if the L2MSB bit is cleared) or bit 0 through bit 7 (if the L2MSB bit is set). 4. By the end of the step 3 data shifting, the ARM gets the TxBufIRQ, which indicates that the TxBuffer is ready for next transmit and the RxBuffer is full. 5. The ARM reads the SASData Register for the RxBuffer Register data, and clears the TxBufIRQ by writing to the TxBuffer Register with the next data. If no more data, the ARM clears the TxBufIrqEnb bit. If only transmit is desired, the ARM can ignore the data in the RxBuffer Register. 6. If the TxBufEmpty status bit is cleared at the end of the data shifting, the SASIF will set the TxBufEmpty bit and goto step 2. However, if the TxBufEmpty bit is set, the SASIF will set the TxShfEmpty status bit and generates the TxShfIRQ. 7. The ARM gets the TxShfIRQ, which indicates the end of all data shifting. If no data is wished to be sent or received, the ARM can then clear the TxShfIrqEnb bit. Data Transmit and Receive Example - FIFO mode (both FIFO's enabled) Case when the TxBufIRQ and the TxShfIRQ are enabled: Note: When using FIFO mode in synchonous mode, both FIFO's must be enabled. This ensures that the RxFIFO will contain the same number of bytes of data by the time the TxBufIRQ occurs that were originally written to the TxFIFO. Otherwise, since only Tx interrupts are used, it will be impossible to grab the received data if no received FIFO is used, and data will be lost if no TxFIFO is used when an RxFIFO is used. 1. The ARM writes first data to the SASData Register up to sixteen times in a row, filling up the TxFIFO as much as desired, and sets the TxBufIrqEnb and the TxShfIrqEnb bits. 15-16 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 2. The SASIF loads the oldest unused byte from the Tx FIFO to the TxShift Register and clears the TxShfEmpty status bit. If this is the last byte held within the FIFO, then a TxBufIRQ and TxBufEmpty status bit will be set, which indicates that the Tx FIFO is ready for next data to be loaded into it. 3. The SASIF transmits, and receives bits 7 through bit 0 (if the L2MSB bit is cleared) or bit 0 through bit 7 (if the L2MSB bit is set). 4. By the end of the step 3 data shifting, if the Tx FIFO is empty then the ARM will receive the TxBufIRQ and TxBuffEmpty status bit will be set, 5. If the TxBufEmpty is cleared at the end of the data shifting (meaning there was leftover data in the TxFIFO), the SASIF will set go back to step 2. However, if the TxBufEmpty bit is set, the SASIF will set the TxShfEmpty status bit and generate the TxShfIRQ. 6. The ARM gets the TxShfIRQ, which indicates the end of all data shifting. The ARM reads the SASData Register as many times as it wrote to the SASData Register when filling up the Tx FIFO. After this, the next batch of data can be written to the Tx FIFO by writing up to sixteen times to SASData. This clears the TxBufEmpty bit and the TxShfEmpty bit. If no more data needs to be sent, the ARM clears the TxBufIrqEnb and TxShfIrqEnb bit. If only transmit is desired, the ARM can ignore the data in the Rx FIFO. 15.4.2 SASIF AsyncMode Operations AsyncMode Setup Set the SASSCLKDivisor Register for proper transmission rate. Set the L2MSB bit for proper shifting order. Set the SASSCLKPol bit for proper SASSCLK polarity. Set the DataLen bit for proper data length. Choose whether to use the transmit fifo or the receive fifo. Either, both, or neither can be used. Clear the TxBufIrqEnb bit, the TxShfIrqEnb, and the RxBufEnb bit for lower CPU interrupt overhead and lower transfer rate, or set the TxBufIrqEnb bit, the TxShfIrqEnb, and the RxBufEnb bit for higher CPU interrupt overhead and higher transfer rate. 7. Set the SASMode bit to select AsyncMode operations. 1. 2. 3. 4. 5. 6. Note: Steps 1 through 7 can be done in a setup-table load. Asynchronous Transmitter - FIFO mode disabled Case when the TxBufIRQ and the TxShfIRQ are enabled: 1. The CPU writes data to the SASData Register (TxBuffer Register). This data is written at that time to the TxBuffer Register. 2. This data will automatically be transferred to the TxShift Register. 3. The SASIF automatically transmits the start bit. 4. The SASIF automatically clears the TxShfEmpty status bit in the SerCmd Register or the TxBufEmpty bit will be cleared if the TxShfEmpty was already cleared. 5. The SASIF automatically sends bits 0 through bit 6 (if 7 bit data is selected) or bit 7 (if 8 bit data is selected). 6. The SASIF transmits the stop bit, sets the TxBufEmpty bit only if the TxBuffer Register contains data (which will soon be transferred to the TxShift Register), or sets the TxBufEmpty and the TxShfEmpty bit if the TxBuffer Register is empty. If the TxBufEmpty status bit is set and the TxBufEnb is set, the the ARM will receive a TxBufIRQ. If the TxShfEmpty status bit is set and the TxShfEnb is set, the the ARM will receive a TxShfIRQ. 7. Upon receiving these interrupts, the TxShfEnb or TxBufEnb can be cleared if no more data is wished to be sent, or a new byte of data can be written to the SASData Register. In the latter case, the TxShfIRQ will be cleared and steps 2 through 6 will be repeated. 100723A Conexant 15-17 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Asynchronous Transmitter - FIFO mode disabled Case when the TxBufIRQ and the TxShfIRQ are enabled: 1. The CPU writes up to 16 bytes in a row of data to the SASData Register (TxBuffer Register). This data will be written to the most current empty locations within the transmit fifo. 2. Upon first writing to the transmit fifo, the data will automatically be transferred to the TxShift Register if the TxShift Register is currently empty. 3. The SASIF automatically transmits the start bit. 4. The SASIF automatically clears the TxShfEmpty status bit in the SerCmd Register. 5. SASIF automatically sends bits 0 through bit 6 (if 7 bit data is selected) or bit 7 (if 8 bit data is selected). 6. The SASIF transmits the stop bit, sets the TxBufEmpty bit only if the Tx FIFO is out of data (or is transfering its last byte to the TxShift Register), or sets the TxBufEmpty and the TxShfEmpty bit if the Tx FIFO is empty and has no data to give to the TxShift Register. If the TxBufEmpty status bit is set and the TxBufEnb is set, the the ARM will receive a TxBufIRQ. If the TxShfEmpty status bit is set and the TxShfEnb is set, the the ARM will receive a TxShfIRQ. 7. Upon receiving these interrupts, the TxShfEnb or TxBufEnb can be cleared if no more data is wished to be sent, or steps 1 through 6 can be repeated. Asynchronous Receiver - FIFO mode disabled 1. The receiver is in idle state (SASRXD high) when the SASIF receiver is waiting for falling a edge of the SASRXD (start bit) 2. The start bit activates the SASIF receiver. 3. After receiving 7 or 8 data bits, SASIF receiver looks for stop bit. 4. After receiving the stop bit, the SASIF receiver will set the RxBufFull bit, and will generate a RxBufIRQ if the RxBufEnb interrupt enable bit is set. 5. This serially received data is automatically transferred to the RxBuffer Register. 6. An ARM Read of the SASData Register will retreive the data from the Rx Buffer Register and will clear the RxBufFull status bit and the RxBufIRQ. Asynchronous Receiver - FIFO mode enabled 1. The receiver is in idle state (SASRXD high) when the SASIF receiver is waiting for falling a edge of the SASRXD (start bit) 2. The start bit activates the SASIF receiver. 3. After receiving 7 or 8 data bits, SASIF receiver looks for stop bit. 4. After receiving the stop bit, the SASIF receiver will set the RxBufFull bit, and will generate a RxBufIRQ if the RxBufEnb interrupt enable bit is set. 5. This serially received data is automatically transferred to the current open location in the Rx FIFO. If the addition of this data makes the Rx FIFO full, then the RxBufIRQ will be activated (if the RxBufEnb is set). When an interrupt is received, 16 bytes have been stored in the Rx FIFO. 6. An ARM Read of the Rx FIFO Register (SASData Register) will clear the RxBufFull status bit and the RxBufIRQ, however it is advised that 16 consecutives reads take place at this time to fully empty out the Rx FIFO. 7. In the case that less than 16 bytes reside in the Rx FIFO but no more will be sent, if the RxTimerEnb is set, then after the Rx Timer times out, then a RxTimeoutIRQ will be sent to the ARM. Note: Each mention in the above descritions of RxTimeoutIRQ, RxBufIRQ, TxShfEmpty, and TxBufEmpty are actually all received by the ARM as a single interrupt: SERIRQ. In order to figure out which interrupt was received, the SASIrqStatus Register must be read, and then the appropriate action be taken. 15-18 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 16. USB INTERFACE 16.1 Function Description The USBIF interface block interfaces to the PC, IPB bus and the DMA block. It bridges print and scan data between the MFC2000 and the PC. It is compliant with USB protocol revision 1.1 and supports device remotewakeup feature. There are six endpoints in the MFC2000, two control endpoints (including endpoint 0), two BULK IN endpoints and two BULK OUT endpoints. The MaxPacketSize for both the control endpoints are 8 byte and the MaxPacketSize for the four bulk transfer pipes are 64 byte. Endpoint 0 supports the Get_Descriptor and USB Vendor/Class commands. The USBIF contains in-silicon USB device controller core, four uni-directional FIFOs and two bi-directional buffers. Description of USB device controller core can be found in UDC specification document. 16.2 Register Description Address: USBEP1Fifo1 (R/W) $01FF8581 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Reset. Value 00h EP1 Bulkin Half Word 1 Address: USBEP1Fifo1 (R/W) $01FF8580 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Reset. Value 00h EP1 Bulkin Half Word 1 Bits 15-0: Endpoint 1 FIFO Quad Half word 1 Address: USBEP1Fifo2 (R/W) $01FF8583 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Reset. Value 00h Read Value 00h EP1 Bulkin FIFO 2 Address: USBEP1Fifo2 (R/W) $01FF8582 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Reset. Value 00h Read Value 00h EP1 Bulkin Half Word 2 Bits 15-0: Endpoint 1 FIFO Quad Half word 2 Address: USBEP1Fifo3 (R/W) $01FF8585 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Reset. Value 00h Read Value 00h EP1 Bulkin Half Word 3 Address: USBEP1Fifo3 (R/W) $01FF8584 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Reset. Value 00h Read Value 00h EP1 Bulkin Half Word 3 Bits 15-0: Endpoint 1 FIFO Quad Half word 3 100723A Conexant 16-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: USBEP1Fifo4 (R/W) $01FF8587 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Reset. Value 00h Read Value 00h EP1 Bulkin Half Word 4 Address: USBEP1Fifo4 (R/W) $01FF8586 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Reset. Value 00h Read Value 00h EP1 Bulkin Half Word 4 Bits 15-0: Address: USBEP1Hold (R/W) $01FF8589 Endpoint 1 FIFO Quad Half word 4 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Reset. Value 00h Read Value 00h EP1 Bulkin Holding Register Address: USBEP1Hold (R/W) $01FF8588 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Reset. Value 00h Read Value 00h EP1 Bulkin Holding Register Bits 15-0: Endpoint 1 FIFO Quad Holding Register Address: USBEP1Ctrl (R/W) $01FF858B Bit 15 Bit 14 Bit 13 Fifo Ready Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h Fifo Enabled Data (Read Only) Request (Read Only) Fifo DMA Threshold Fifo Output Pointer Address: USBEP1Ctrl (R/W) $01FF858A Bit 7 unused Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value x0000000b Read Value 00h Holding Reg Byte Present Fifo Data Quantity Full Fifo Input Pointer Bit 15: This bit indicates that the FIFO is active and capable of generating DMA requests. This bit generally follows the setting of the LCL_ENB input signal except the FIFO Enabled register bit will remain asserted if the LCL_ENB input signal is set to false while the FIFO is executing a DMA transfer. In this case, the register bit will remain set for the duration of the DMA transfer and then become cleared. This bit is similar to the DMA_REQ signal except that it is not blocked when DMA_TC0 is set. It indicates that the programmed threshold has been met or exceeded and that the FIFO requires data transfers either by enabling hardware DMA through DMA_TC0 or by executing software DMA cycles. Bit 14: 16-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Bit 13: This bit indicates that the FIFO can accept data transfers to/from the local logic. This bit is low when the data direction is into the local logic and the FIFO is empty or when the data direction is out of the local logic and the FIFO is full. This bit field indicates at which point the FIFO should issue a DMA request. It is compared with the FIFO Data Quantity bit field to determine when this should occur. Legal values are from 1 to 4. A value of zero causes no data transfers to occur. Values greater than 4 are treated as 4. This bit field indicates which byte of the FIFO quad halfword structure is the next to be used as output data. Not used This bit indicates that there is a full word in the holding register. This bit indicates that there is a single byte in the holding register. This bit field indicates the number of quad halfwords that contain data. Valid values are from 0 to 4. This bit field indicates which byte of the FIFO quad halfword structure is the next to receive input data. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Reset Value 00h Read Value 00h Bit 12-10: Bit 9-8: Bit 7: Bit 6: Bit 5: Bit 4-2: Bit 1-0: Address: USBEP1Data (R/W) $01FF858D EP1 Bulkin Dataport Register Address: USBEP1Data (R/W) $01FF858C Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Reset Value 00h Read Value 00h EP1 Bulkin Dataport Register Bits 15-0: Endpoint 1 FIFO Dataport Register Address: USBEP1Tran (W) $01FF858F Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Reset. Value xxh EP1 Transition Register Address: USBEP1Tran (W) $01FF858E Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Reset. Value xxh EP1 Transition Register 100723A Conexant 16-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Bit 15-0: Not used Writing any value to this register causes a push or pop of data through the FIFO data port and the FIFO Quad Halfword 1-4 registers. The FIFO operation depends on the direction of data flow. If system bus (CPU or DMA) is writing (filling) the FIFO, data is transferred from the FIFO data port register to the FIFO Quad Halfword 1 register, simultaneously with data transfer from Quad Halfword 1 to Quad Halfword 2, Quad Halfword 2 to Quad Halfword 3, and Quad Halfword 3 to Quad Halfword 4, with the original data of Quad Halfword 4 being lost. If the system bus is reading (emptying) the FIFO, data is transferred from the FIFO Quad Halfword 1 register to the FIFO data port register, simultaneously with data transfer from Quad Halfword 2 to Quad Halfword 1, Quad Halfword 3 to Quad Halfword 2, and Quad Halfword 4 to Quad Halfword 3, with the contents of Quad Halfword 4 becoming indeterminate. Address: USBEP2Fifo1 (R/W) $01FF85A1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h EP2 Bulkout Half Word 1 Address: USBEP2Fifo1 (R/W) $01FF85A0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h EP2 Bulkout Half Word 1 Bits 15-0: Endpoint 2 FIFO Quad Half word 1 Address: USBEP2Fifo2 (R/W) $01FF85A3 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h EP2 Bulkout Half Word 2 Address: USBEP2Fifo2 (R/W) $01FF85A2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h EP2 Bulkout Half Word 2 Bits 15-0: Endpoint 2 FIFO Quad Half word 2 16-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: USBEP2Fifo3 (R/W) $01FF85A5 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h EP2 Bulkout Half Word 3 Address: USBEP2Fifo3 (R/W) $01FF85A4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h EP2 Bulkout Half Word 3 Bits 15-0: Endpoint 2 FIFO Quad Half word 3 Address: USBEP2Fifo4 (R/W) $01FF85A7 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h EP2 Bulkout Half Word 4 Address: USBEP2Fifo4 (R/W) $01FF85A6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h EP2 Bulkout Half Word 4 Bits 15-0: Endpoint 2 FIFO Quad Half word 4 Address: USBEP2Hold (R/W) $01FF85A9 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h EP2 Bulkout Holding Register Address: USBEP2Hold (R/W) $01FF85A8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h EP2 Bulkout Holding Register Bits 15-0: Endpoint 2 FIFO Holding Register 100723A Conexant 16-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: USBEP2Ctrl (R/W) $01FF85AB Bit 15 Bit 14 Bit 13 Fifo Ready Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h Fifo Enabled Data (Read Only) Request (Read Only) Fifo DMA Threshold Fifo Output Pointer Address: USBEP2Ctrl (R/W) $01FF85AA Bit 7 unused Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value x0000000b Read Value 00h Holding Reg Byte Present Fifo Data Quantity Full Fifo Input Pointer Bit 15: This bit indicates that the FIFO is active and capable of generating DMA requests. This bit generally follows the setting of the LCL_ENB input signal except the FIFO Enabled register bit will remain asserted if the LCL_ENB input signal is set to false while the FIFO is executing a DMA transfer. In this case, the register bit will remain set for the duration of the DMA transfer and then become cleared. This bit is similar to the DMA_REQ signal except that it is not blocked when DMA_TC0 is set. It indicates that the programmed threshold has been met or exceeded and that the FIFO requires data transfers either by enabling hardware DMA through DMA_TC0 or by executing software DMA cycles. This bit indicates that the FIFO can accept data transfers to/from the local logic. This bit is low when the data direction is into the local logic and the FIFO is empty or when the data direction is out of the local logic and the FIFO is full. This bit field indicates at which point the FIFO should issue a DMA request. It is compared with the FIFO Data Quantity bit field to determine when this should occur. Legal values are from 1 to 4. A value of zero causes no data transfers to occur. Values greater than 4 are treated as 4. This bit field indicates which byte of the FIFO quad halfword structure is the next to be used as output data. Not used This bit indicates that there is a full word in the holding register. This bit indicates that there is a single byte in the holding register. This bit field indicates the number of quad halfwords that contain data. Valid values are from 0 to 4. This bit field indicates which byte of the FIFO quad halfword structure is the next to receive input data. Bit 14: Bit 13: Bit 12-10: Bit 9-8: Bit 7: Bit 6: Bit 5: Bit 4-2: Bit 1-0: 16-6 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: USBEP2Data (R/W) $01FF85AD Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h EP2 Bulkout Dataport Register Address: USBEP2Data (R/W) $01FF85AC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h EP2 Bulkout Dataport Register Bits 15-0: Endpoint 2 FIFO Data Port Register Address: USBEP2Tran (W) $01FF85AF Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value xxh Endpoint 2 Tran Address: USBEP2Tran (W) $01FF85AE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value xxh Endpoint 2 Tran Bit 15-0: Not used Writing any value to this register causes a push or pop of data through the FIFO data port and the FIFO Quad Halfword 1-4 registers. The FIFO operation depends on the direction of data flow. If system bus (CPU or DMA) is writing (filling) the FIFO, data is transferred from the FIFO data port register to the FIFO Quad Halfword 1 register, simultaneously with data transfer from Quad Halfword 1 to Quad Halfword 2, Quad Halfword 2 to Quad Halfword 3, and Quad Halfword 3 to Quad Halfword 4, with the original data of Quad Halfword 4 being lost. If the system bus is reading (emptying) the FIFO, data is transferred from the FIFO Quad Halfword 1 register to the FIFO data port register, simultaneously with data transfer from Quad Halfword 2 to Quad Halfword 1, Quad Halfword 3 to Quad Halfword 2, and Quad Halfword 4 to Quad Halfword 3, with the contents of Quad Halfword 4 becoming indeterminate. 100723A Conexant 16-7 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Bit 15 Address: USBEP3Fifo1 (R/W) $01FF85B1 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h EP3 bulk-in Half Word 1 Address: USBEP3Fifo1 (R/W) $01FF85B0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h EP3 bulk-in Half Word 1 Bits 15-0: Address: USBEP3Fifo2 (R/W) $01FF85B3 Endpoint 3 FIFO Quad Half word 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h EP3 Bulk-in Half Word 2 Address: USBEP3Fifo2 (R/W) $01FF85B2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h EP3 Bulk-in Half Word 2 Bits 15-0: Endpoint 3 FIFO Quad Half word 2 Bit 15 Address: USBEP3Fifo3 (R/W) $01FF85B5 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h EP3 Bulk-in Half Word 3 Address: USBEP3Fifo3 (R/W) $01FF85B4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h EP3 Bulk-in Half Word 3 Bits 15-0: Endpoint 3 FIFO Quad Half word 3 16-8 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: USBEP3Fifo4 (R/W) $01FF85B7 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h EP3 Bulk-in Half Word 4 Address: USBEP3Fifo4 (R/W) $01FF85B6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h EP3 Bulk-in Half Word 4 Bits 15-0: IsocIn FIFO Quad Half word 4 Address: USBEP3Hold (R/W) $01FF85B9 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h EP3 bulk-in Holding Register Address: USBEP3Hold (R/W) $01FF85B8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h EP3 bulk-in Holding Register Bits 15-0: Endpoint 3 FIFO Holding Register Address: USBEP3Ctrl (R/W) $01FF85BB Bit 15 Bit 14 Bit 13 Fifo Ready Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h Fifo Enabled Data (Read Only) Request (Read Only) Fifo DMA Threshold Fifo Output Pointer Address: USBEP3Ctrl (R/W) $01FF85BA Bit 7 unused Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value x0000000b Read Value 00h Holding Reg Byte Present Fifo Data Quantity Full Fifo Input Pointer Bit 15: This bit indicates that the FIFO is active and capable of generating DMA requests. This bit generally follows the setting of the LCL_ENB input signal except the FIFO Enabled register bit will remain asserted if the LCL_ENB input signal is set to false while the FIFO is executing a DMA transfer. In this case, the register bit will remain set for the duration of the DMA transfer and then become cleared. This bit is similar to the DMA_REQ signal except that it is not blocked when DMA_TC0 is set. It indicates that the programmed threshold has been met or exceeded and that the FIFO requires data transfers either by enabling hardware DMA through DMA_TC0 or by executing software DMA cycles. Bit 14: 100723A Conexant 16-9 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Bit 13: This bit indicates that the FIFO can accept data transfers to/from the local logic. This bit is low when the data direction is into the local logic and the FIFO is empty or when the data direction is out of the local logic and the FIFO is full. This bit field indicates at which point the FIFO should issue a DMA request. It is compared with the FIFO Data Quantity bit field to determine when this should occur. Legal values are from 1 to 4. A value of zero causes no data transfers to occur. Values greater than 4 are treated as 4. This bit field indicates which byte of the FIFO quad halfword structure is the next to be used as output data. Not used This bit indicates that there is a full word in the holding register. This bit indicates that there is a single byte in the holding register. This bit field indicates the number of quad halfwords that contain data. Valid values are from 0 to 4. This bit field indicates which byte of the FIFO quad halfword structure is the next to receive input data. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h Bit 12-10: Bit 9-8: Bit 7: Bit 6: Bit 5: Bit 4-2: Bit 1-0: Address: USBEP3Data (R/W) $01FF85BD EP3 Dataport Register Address: USBEP3Data (R/W) $01FF85BC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h EP3 Dataport Register Bits 15-0: Endpoint 3 FIFO Data Port Register 16-10 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: USBEP3Tran (W) $01FF85BF Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Ep3 Transition Register Address: USBEP3Tran (W) $01FF85BE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Ep3 Transition Register Bit 15-0: Not used Writing any value to this register causes a push or pop of data through the FIFO data port and the FIFO Quad Halfword 1-4 registers. The FIFO operation depends on the direction of data flow. If system bus (CPU or DMA) is writing (filling) the FIFO, data is transferred from the FIFO data port register to the FIFO Quad Halfword 1 register, simultaneously with data transfer from Quad Halfword 1 to Quad Halfword 2, Quad Halfword 2 to Quad Halfword 3, and Quad Halfword 3 to Quad Halfword 4, with the original data of Quad Halfword 4 being lost. If the system bus is reading (emptying) the FIFO, data is transferred from the FIFO Quad Halfword 1 register to the FIFO data port register, simultaneously with data transfer from Quad Halfword 2 to Quad Halfword 1, Quad Halfword 3 to Quad Halfword 2, and Quad Halfword 4 to Quad Halfword 3, with the contents of Quad Halfword 4 becoming indeterminate. Address: USBEP4Fifo1 (R) $01FF85C1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Reset. Value 00h Read Value 00h EP4 Fifo Half Word 1 Address: USBEP4Fifo1 (R) $01FF85C0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Reset. Value 00h Read Value 00h EP4 Fifo Half Word 1 Bits 15-0: Endpoint 4 FIFO Quad Half word 1 100723A Conexant 16-11 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: USBEP4Fifo2 (R) $01FF85C3 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Reset. Value 00h Read Value 00h EP4 Fifo Half Word 2 Address: USBEP4Fifo2 (R) $01FF85C2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Reset. Value 00h Read Value 00h EP4 Fifo Half Word 2 Bits 15-0: Endpoint 4 FIFO Quad Half word 2 Address: USBEP4Fifo3 (R) $01FF85C5 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Reset Value 00h Read Value 00h EP4 Fifo Half Word 3 Address: USBEP4Fifo3 (R) $01FF85C4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Reset. Value 00h Read Value 00h EP4 Fifo Half Word 3 Bits 15-0: Endpoint 4 FIFO Quad Half word 3 Address: USBEP4Fifo4 (R) $01FF85C7 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Reset Value 00h Read Value 00h EP4 Fifo Half Word 4 Address: USBEP4Fifo4 (R) $01FF85C6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Reset Value 00h Read Value 00h EP4 Fifo Half Word 4 Bits 15-0: Endpoint 4 FIFO Quad Half word 4 16-12 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: USBEP4Hold (R) $01FF85C9 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Reset Value 00h Read Value 00h EP4 Fifo Holding Register Address: USBEP4Hold (R) $01FF85C8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Reset Value 00h Read Value 00h EP4 Fifo Holding Register Bits 15-0: Endpoint FIFO Holding Register Address: USBEP4Ctrl (R/W) $01FF85CB Bit 15 Bit 14 Bit 13 Fifo Ready Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Reset Value 00h Read Value 00h Fifo Enabled Data (Read Only) Request (Read Only) Fifo DMA Threshold Fifo Output Pointer Address: USBEP4Ctrl (R/W) $01FF85CA Bit 7 unused Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Reset Value 00h Read Value 00h Holding Byte Present Fifo Data Quantity Register Full Fifo Input Pointer Bit 15: This bit indicates that the FIFO is active and capable of generating DMA requests. This bit generally follows the setting of the LCL_ENB input signal except the FIFO Enabled register bit will remain asserted if the LCL_ENB input signal is set to false while the FIFO is executing a DMA transfer. In this case, the register bit will remain set for the duration of the DMA transfer and then become cleared. This bit is similar to the DMA_REQ signal except that it is not blocked when DMA_TC0 is set. It indicates that the programmed threshold has been met or exceeded and that the FIFO requires data transfers either by enabling hardware DMA through DMA_TC0 or by executing software DMA cycles. This bit indicates that the FIFO can accept data transfers to/from the local logic. This bit is low when the data direction is into the local logic and the FIFO is empty or when the data direction is out of the local logic and the FIFO is full. This bit field indicates at which point the FIFO should issue a DMA request. It is compared with the FIFO Data Quantity bit field to determine when this should occur. Legal values are from 1 to 4. A value of zero causes no data transfers to occur. Values greater than 4 are treated as 4. This bit field indicates which byte of the FIFO quad halfword structure is the next to be used as output data. Not used This bit indicates that there is a full word in the holding register. Bit 14: Bit 13: Bit 12-10: Bit 9-8: Bit 7: Bit 6: 100723A Conexant 16-13 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Bit 5: Bit 4-2: Bit 1-0: This bit indicates that there is a single byte in the holding register. This bit field indicates the number of quad halfwords that contain data. Valid values are from 0 to 4. This bit field indicates which byte of the FIFO quad halfword structure is the next to receive input data. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Reset Value 00h Read Value 00h Address: USBEP4Data (R/W) $01FF85CD EP4 Endpoint Dataport Register Address: USBEP4Data (R/W) $01FF85CC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Reset Value 00h Read Value 00h EP4 Endpoint Dataport Register Bits 15-0: Endpoint 4 FIFO Data Port Register Address: USBEP4Tran (W) $01FF85CF Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: EP4 Transition Register Address: USBEP4Tran (W) $01FF85CE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: EP4 Transition Register Bit 15-0: Not used Writing any value to this register causes a push or pop of data through the FIFO data port and the FIFO Quad Halfword 1-4 registers. The FIFO operation depends on the direction of data flow. If system bus (CPU or DMA) is writing (filling) the FIFO, data is transferred from the FIFO data port register to the FIFO Quad Halfword 1 register, simultaneously with data transfer from Quad Halfword 1 to Quad Halfword 2, Quad Halfword 2 to Quad Halfword 3, and Quad Halfword 3 to Quad Halfword 4, with the original data of Quad Halfword 4 being lost. If the system bus is reading (emptying) the FIFO, data is transferred from the FIFO Quad Halfword 1 register to the FIFO data port register, simultaneously with data transfer from Quad Halfword 2 to Quad Halfword 1, Quad Halfword 3 to Quad Halfword 2, and Quad Halfword 4 to Quad Halfword 3, with the contents of Quad Halfword 4 becoming indeterminate. 16-14 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: USBEP0Buf2 (R/W) $01FF85D1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h EP0 Buffer 2 Address: USBEP0Buf1 (R/W) $01FF85D0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 EP0 Buffer 1 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Bits 15-8: Bits 7-0: 2 data byte of endpoint 0 buffer 1 data byte of endpoint 0 buffer st nd Address: USBEP0Buf4 (R/W) $01FF85D3 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h EP0 Buffer 4 Address: USBEP0Buf3 (R/W) $01FF85D2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 EP0 Buffer 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Bits 15-8: Bits 7- 0: Address: USBEP0Buf6 (R/W) $01FF85D5 4th data byte of endpoint 0 buffer 3rd data byte of endpoint 0 buffer Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h EP0 Buffer 6 Address: USBEP0Buf 5 (R/W) $01FF85D4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 EP0 Buffer 5 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Bits 15-8: Bits 7- 0: 6th data byte of endpoint 0 buffer 5th data byte of endpoint 0 buffer 100723A Conexant 16-15 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: USBEP0Buf8 (R/W) $01FF85D7 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h EP0 Buffer 8 Address: USBEP0Buf7 (R/W) $01FF85D6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 EP0 Buffer 7 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Bits 15-8: Bits 7- 0: 8th data byte of endpoint 0 buffer 7th data byte of endpoint 0 buffer Address: USBEP5Buf2 (R/W) $01FF85D9 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h EP5 Buffer 2 Address: USBEP5Buf1 (R/W) $01FF85D8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 EP5 Buffer 1 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Bits 15-8: Bits 7- 0: 2 data byte of endpoint 5 buffer 1 data byte of endpoint 5 buffer st nd address: USBEP5Buf4 (R/W) $01FF85DB Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h EP5 Buffer 4 Address: USBEP5Buf3 (R/W) $01FF85DA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 EP5 Buffer 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Bits 15-8: Bits 7-0: 4 byte of the endpoint 5 buffer 3 byte of the endpoint 5 buffer rd th 16-16 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: USBEP5Buf6 (R/W) $01FF85DD Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h EP5 Buffer 6 Address: USBEP5Buf5 (R/W) $01FF85DC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 EP5 Buffer 5 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Bits 15-8: Bits 7-0: Address: USBEP5Buf8 (R/W) $01FF85DF 6 byte of the endpoint 5 buffer 5 byte of the endpoint 5 buffer Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h th th EP5 Buffer 8 Address: USBEP5Buf7 (R/W) $01FF85DE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 EP5 Buffer 7 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Bits 15-8: Bits 7-0: 8 byte of the endpoint 5 buffer 7 byte of the endpoint 5 buffer th th Address: USBEP5StDat2 (R) $01FF85E1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h EP5 Setup Packet Data 2nd byte Address: USBEP5StDat1 (R) $01FF85E0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h EP5 Setup Packet Data 1st byte Bits 15-8: Bits 7:0: 2 data byte of the setup packet for EP5 1 data byte of the setup packet for EP5 st nd 100723A Conexant 16-17 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: USBEP5StDat4 (R) $01FF85E3 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h EP5 Setup Packet Data 4th byte Address: USBEP5StDat3 (R) $01FF85E2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h EP5 Setup Packet Data 3rd byte Bits 15-8: Bits 7:0: 4 data byte of the setup packet for EP5 3 data byte of the setup packet for EP5 rd th Address: USBEP5StDat6 (R) $01FF85E5 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h EP5 Setup Packet Data 6th byte Address: USBEP5StDat5 (R) $01FF85E4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h EP5 Setup Packet Data 5th byte Bits 15-8: Bits 7:0: 6 data byte of the setup packet for EP5 5 data byte of the setup packet for EP5 th th Address: USBEP5StDat8 (R) $01FF85E7 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h EP5 Setup Packet Data 8th byte Address: USBEP5StDat7 (R) $01FF85E6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h Read Value 00h EP5 Setup Packet Data 7th byte Bits 15-8: Bits 7:0: 8 data byte of the setup packet for EP5 7 data byte of the setup packet for EP5 th th 16-18 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: USBIRQ (R) $01FF85E9 Bit 15 Ep4 Interrupt Bit 14 Bit 13 Bit 12 EP5 Write Ack Bit 11 EP5 Read Ack Bit 10 EP0 Write Ack Bit 9 EP0 Read Ack Bit 8 USB Reset Interrupt Default: Rst. Value 00h Ep2 Interrupt Suspend status Address: USBIRQ (R) $01FF85E8 Bit 7 Suspend Interrupt Bit 6 DMA Interrupt Bit 5 EP5 Write Interrupt Bit 4 EP5 Read Interrupt Bit 3 EP5 Setup Interrupt Bit 2 EP0 Write Interrupt Bit 1 EP0 Read Interrupt Bit 0 EP0 Setup Interrupt Default: Rst. Value 00h Bit 15: Bit 14: Bit 13: This bit indicates that an odd packet is received at endpoint 4. This bit indicates that an odd packet is received at endpoint 2. When it is "1", it indicates that the device is in suspend mode. If the PC does a global wake up, this bit will be reset to "0". The firmware can reset this bit to "0" by performing a device remote wakeup (setting the resume bit to be "1" in USBClrIRQ register). This bit indicates that if the control write on endpoint 5 is successful. "1" - Ack. "0" - Nack. This bit indicates that if the control read on endpoint 5 is successful. "1" - Ack. "0" - Nack. This bit indicates that if the control write on endpoint 0 is successful. "1" - Ack. "0" - Nack. This bit indicates that if the control read on endpoint 0 is successful. "1" - Ack. "0" - Nack. This bit indicates that a USB reset is detected on the bus. This bit indicates a suspend is detected on the bus. This bit indicates the DMA has reached its block size. This bit indicates that the endpoint 5 data buffer is full. This bit indicates that the data in endpoint 5 buffer has been send. This bit indicates that a set up packet has been send to endpoint 5 and the endpoint 5 setup data buffer is full. This bit indicates that the endpoint 0 data buffer is full. This bit indicates that the data in endpoint 0 buffer has been send. This bit indicates that a set up packet has been send to endpoint 5 and the endpoint 5 setup data buffer is full. Bit 12: Bit 11: Bit 10: Bit 9: Bit 8: Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: 100723A Conexant 16-19 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: USBClrIRQ (R/W) $01FF85EB Bit 15 unused Bit 14 Clear EP4 Interrupt Bit 13 Clear EP2 Interrupt Bit 12 Clear USB Reset Interrupt Bit 11 Bit 10 Bit 9 EP0 Write Buffer Read Bit 8 EP0 Read Buffer Written Default: Rst. Value 00h EP5 Write EP5 Read Buffer Read Buffer Written Address: USBClrIRQ (R/W) $01FF85EA Bit 7 Clear Suspend Interrupt Bit 6 Resume Device Bit 5 Clear EP5 Write Interrupt Bit 4 Clear EP5 Read Interrupt Bit 3 Clear EP5 Setup Interrupt Bit 2 Clear EP0 Write Interrupt Bit 1 Clear EP0 Read Interrupt Bit 0 Clear EP0 Setup Interrupt Default: Rst. Value 00h Bit 15: Bit 14: Bit 13: Bit 12: Bit 11: Bit 10: Bit 9: Bit 8 Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: Unused Set this bit to "1" to clear the endpoint 4 interrupt. Set this bit to "1" to clear the endpoint 2 interrupt. Set this bit to "1" to clear the usb reset interrupt. Set this bit to "1" to indicate that the endpoint 5 buffer is empty. Set this bit to "1" to indicate that the endpoint 5 buffer is full. Set this bit to "1" to indicate that the endpoint 0 buffer is empty. Set this bit to "1" to indicate that the endpoint 0 buffer is full. Set this bit to "1" to clear the suspend interrupt. Set this bit to "1" to perform device remote wake-up. Set this bit to "1" to clear endpoint 5 write interrupt. Set this bit to "1" to clear endpoint 5 read interrupt. Set this bit to "1" to clear endpoint 5 setup interrupt. Set this bit to "1" to clear endpoint 0 write interrupt. Set this bit to "1" to clear endpoint 0 read interrupt. Set this bit to "1" to clear endpoint 0 setup interrupt. Address: USBSofReset (W) $01FF85ED Bit 15 Unused Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Address: USBSofReset (W) $01FF85EC Bit 7 Unused Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Software Reset Default: Rst. Value 01h Bit 15:1: Bit 0: Not used Set this bit to "1" reset usb interface block. 16-20 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: USBStall (R/W) $01FF85EF Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Unused Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Address: USBStall(R/W) $01FF85EE Bit 7 Unused Bit 6 Bit 5 EP5 Stalled Bit 4 EP4 Stalled Bit 3 EP3 Stalled Bit 2 EP2 Stalled Bit 1 EP1 Stalled Bit 0 Default: EP0 Stalled Rst. Value 01h Bit 15:6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: Address: USBEP0StDat2 (R) $01FF85F1 Not used Set this bit to "1" to indicate that the endpoint 5 is stalled. Set this bit to "1" to indicate that the endpoint 4 is stalled. Set this bit to "1" to indicate that the endpoint 3 is stalled. Set this bit to "1" to indicate that the endpoint 2 is stalled. Set this bit to "1" to indicate that the endpoint 1 is stalled. Set this bit to "1" to indicate that the endpoint 0 is stalled. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h Read Value 00h EP0 Setup Packet Data 2nd byte Address: USBEP0StDat1 (R) $01FF85F0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h EP0 Setup Packet Data 1st byte Bits 15-8: Bits 7:0: 2 data byte of the setup packet for EP0 1 data byte of the setup packet for EP0 st nd Address: USBEP0StDat4 (R) $01FF85F3 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h EP0 Setup Packet Data 4th byte Address: USBEP0StDat3 (R) $01FF85F2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h EP0 Setup Packet Data 3rd byte Bits 15-8: Bits 7:0: 4 data byte of the setup packet for EP0 3 data byte of the setup packet for EP0 rd th 100723A Conexant 16-21 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: USBEP0StDat6 (R) $01FF85F5 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h EP0 Setup Packet Data 6th byte Address: USBEP0StDat5 (R) $01FF85F4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h EP0 Setup Packet Data 5th byte Bits 15-8: Bits 7:0: 6 data byte of the setup packet for EP0 5 data byte of the setup packet for EP0 th th Address: USBEP0StDat8 (R) $01FF85F7 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 00h EP0 Setup Packet Data 8th byte Address: USBEP0StDat7 (R) $01FF85F6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 00h EP0 Setup Packet Data 7th byte Bits 15-8: Bits 7:0: 8 data byte of the setup packet for EP0 7 data byte of the setup packet for EP0 th th 16-22 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 16.3 Firmware Operation 16.3.1 Setup Transfer During the setup transfer, a setup interrupt will be generated to the ARM. ARM can determine it is a setup interrupte by reading the interrupt register and clear the interrupt by setting the clear endpoint 0 or 5 setup interrupt bit of the USBClrIrq register. The 8 bytes of setup packet data can be read from the endpoint 0 or 5 setup buffer. 16.3.1.1 USB Standard Commands Since the UDC core decodes and acts upon the USB standard commands except Get_Descriptor, the setup packet data of all standard commands (except Get_Descriptor ) will not be stored in the setup buffers neither the setup interrupt will be generated during a starndard command transfer. 16.3.1.2 Get_Descriptor Command The Get_Descriptor command is supported by endpoint 0. The ARM needs to decode the setup packet and load the descriptor data into the endpoint 0 buffer then set the ep0 read buffer written bit. 16.3.2 Control Read Transfer During a control read transfer, an interrupt will be generated along with read status bit after the data in the ep0/ep5 buffer are send to the host. ARM can determine the type of interrupt by reading the interrupt register and clear the interrupt by setting the corresboing bit in the clear interrupt register. ARM needs to check the ep0/ep5 read status bit to find out if the control read is successful or not. 16.3.3 Control Write Transfer During a control write transfer, the data from the PC will be written to an internal buffer first. After the control write transfer finished, an interrupt along with write status bit will be generated. ARM can determine the interrupt by reading the interrupt register and clear the interrupt by writing to the corresbonding bit in the clear_interrupt register. Then ARM can read data from the endpoint 0 or endpoint 5 data buffers. After all the data have been read , ARM will set the endpoint 0 or endpoint 5 write_buffer_read bit in the endpoint status register. 16.3.4 BULK_IN Transfer The MaxPacketSize for both bulk in pipes are 64 bytes. DMA channel 0 is assigned to USB and it has four logic channels. Endpoint 1 and 3, which are bulk in endpoints, are assigned to logic channel 0 and 2. The procedures of programming the registers are: 1. Enable DMA channel 0 by writing 1 to bit[0] of DMA 0 configuration register. 2. Enable logic channel 0 or 2 and set logic channel 0 or 2 to be read mode by setting the corresbonding bits in DMA 0 configuration register. 3. Set memory address in DMAUSB0CntLo and DMAUSB0CntHi or DMAUSB2CntLo and DMAUSB2CntHi. 4. Define block size in DMAUSB0BlkSiz or DMAUSB2BlkSiz. 5. If more than one memory block is needed, repeat step 3 and 4 to set desired memory blocks. 6. Load 4 half words into endpoint 1 or 3 internal fifo by writing to endpoint 1 or 3 data port register and transition register OR by writing to the endpoint 1 or 3 halfword fifos. 7. Set endpoint 1 or 3 control register. 100723A Conexant 16-23 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description If the PC has read all the data in the memory blocks successfully, an interrupt will be generated. ARM can read the USBIRQ register to determine that it is DMA channel 0 interrupt. By reading DMA 0 configuration register can determine it is a logic channel 0 or 2 interrupt. Then ARM can repeat step 3 and 4 to set more memory blocks. 1.1.516.3.5 BULK_OUT Transfer The MaxPacketSize for both bulk in pipes are 64 bytes. DMA channel 0 is assigned to USB and it has four logic channels. Endpoint 2 and 4, which are bulk out endpoints, are assigned to logic channel 1 and 3. The procedures of programming the registers are: 1. Enable DMA channel 0 by writing 1 to bit[0] of DMA 0 configuration register. 2. Enable logic channel 1 or 3 and set logic channel 1 or 3 to be write mode by setting the corresbonding bits in DMA 0 configuration register. 3. Set memory address in DMAUSB1CntLo and DMAUSB1CntHi or DMAUSB3CntLo and DMAUSB3CntHi. 4. Define block size in DMAUSB1BlkSiz or DMAUSB3BlkSiz. 5. If more than one memory block is needed, repeat step 3 and 4 to set desired memory blocks. 6. Set endpoint 2 or 4 control register. If the PC has write to all the memory blocks successfully, an interrupt will be generated. ARM can read the USBIRQ register to determine that it is DMA channel 0 interrupt. By reading DMA 0 configuration register can determine it is a logic channel 1 or 3 interrupt. Then ARM can repeat step 3 and 4 to set more memory blocks. If the PC send an odd byte count packet in the middle of a bulkout transaction, an interrupt will be generated to indicate that an single byte has been send to the memory location. 1.1.616.3.6 USB Suspend and Device Remote Wake-up The MFC2000 supports device remote wake-up. If the UDC core detected the USB bus being idle for 3 ms, it will generated a suspend signal and an interrupt will be generated. ARM can determine that it is a suspend interrupt by reading the usb interrupt register then clear the interrupt by setting the clear_suspend_int bit in the clear interrupt register. The suspend status bit will remain high until the PC performs a global wake up or the ARM performs a device remote wake up. The ARM performs a device remote wake up by setting the resume_device bit in the endpoint status register to be "1". 1.1.716.3.7 USB Reset An interrupt will be generated if a USB reset is detected on the USB bus. ARM can determine that it is a usb_reset_interrupt by reading the usb interrupt register then clear the interrupt by setting the clear_usb_reset_int bit in the clear interrupt register. 1.1.816.3.8 Software Reset The ARM can reset the UDC core and related logic by setting the bit 0 in USBSofReset register. 16-24 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 17. Bi-directional Parallel Peripheral Interface The Parallel Peripheral Interface(PPI) controller incorporates the IEEE-1284 Compatibility/Nibble/ Byte/ ECP protocols to offer flexible high-speed parallel data transfer. Furthermore, the PPI fully supports all variants of these modes, including device ID requests and run-length encoded data compression. All protocols are signalcompatible with classic parallel interfaces. The default protocol for the PPI is the Compatibility mode. The PPI contains specific hardware to support automatic handshaking during host to peripheral,or forward, data transfers in compatible and ECP modes, and run-length detection. The PPI also supports automatic handshaking during peripheral to host, or reverse, data transfers in the Nibble, Byte and ECP modes. The hardware handshaking can also be completely disabled to allow software to directly control the peripheral port interface signals and to support new protocols as they arise in the future. 17.1 Operational Modes The PPI supports three hardware handshaking modes for host to peripheral, or forward, data transfers. Each mode can be enabled or disabled by software. One mode supports forward data transfers during compatibility mode, and the other two modes support forward data transfers during ECP mode. Only one of the three modes can be enabled at a time, or all modes can be disabled. When disabled, software must assume full responsibility for handshaking, and use the Parallel Port Interface Register and the Parallel Port Data Register to read and control the logic levels on all parallel port pins. The hardware handshaking modes for peripheral to host, or reverse, data transfers are provided for Nibble, Byte and ECP modes explained. 17.1.1 Compatibility Mode The interface is always initialized to the compatibility Mode, a conventional, unidirectional host-to peripheral interface. From the compatibility Mode the host may transmit data to peripheral or direct the interface to a mode capable of transmitting data to the host. Compatibility mode hardware handshaking is enabled by setting the MODE field to 1 in the Parallel Port Control Register. When compatibility mode is selected, the PPI interacts with host using STROBEn, BUSY and ACKn signals. 17.1.2 P1284 Negotiation The negotiation phase is performed under firmware control. During the negotiation, the firmware will respond to the host stimulus by setting ACKn low, FAULTn high, SLCTOUT(XFlag) high, PE high as defined in the IEEE 1284 Specification. After the host responds to the prior signal setting, the firmware will respond with a PE low and a FAULTn low if data to the host is available. The SLCTOUT is set to it's appropriate value corresponding to the extensibility feature requested by the host. (Refer to the IEEE 1284 Specification for a more complete definition of this phase). 17.1.3 Nibble Mode Provides an asynchronous, reverse (peripheral-to-host) channel, under control of the host. Data bytes are transmitted as two sequential, four bit nibbles using four peripheral-to-host status lines. In Nibble Mode(MODE=4), one byte of status data can be put to the PPI data register by CPU or DMA operation. The PPI Logic will separate the one byte data into two nibbles and send them in sequence. The signals used in the Nibble mode are AUTOFDn and ACKn for handshake and FAULTn, SLCTOUT, PE and BUSY for data transfer. 17.1.4 Byte Mode Provides an asynchronous, byte-wide reverse peripheral-to-host channel using eight data lines of the interface for data and the control/status lines for handshaking. The PPI hardware can control the handshake of the reverse data transfer. The CPU must provide the status to send the next byte or to terminate the protocol. The MODE=5 for the Byte mode which enables a peripheral to send an entire byte of data to the PC in one data transfer cycle using the 8 data lines, rather than the two cycles using the Nibble mode.The handshake signals are AUTOFDn, ACKn and STROBEn. 100723A Conexant 17-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 17.1.5 ECP Forward Extended Capabilities Port (ECP) Mode provides an asynchronous, byte-wide, bi-directional channel. The data can be received by DMA mode or CPU mode as described in the Compatibility Mode section. The ECP protocol provides the Data and command cycles types in both forward and reverse directions. The MODE = 2 and 3 for the forward mode with RLE . When MODE is set to 2, ECP mode hardware handshaking is enabled during forward data transfers, without RLE support. When mode 2 is programmed, the PPI responds to a high to low transition on STROBEn (HostClk), and automatically sets and clears the BUSY bit in the Parallel Port Interface Register and the BUSY to handshake with the host.. MODE may be reprogrammed at any time, but if an ECP cycle is currently in progress, it completes as normal. 17.1.6 ECP Reverse After a successful Forward to Reverse phase switch, the ECP changes into the reverse phase in MODE = 6. When the 1284 interface is idle, this is the desired mode of operation. This mode will allow the MFC2000 ASIC to inform the host of incoming fax data. The ECP Reverse mode can operate under CPU interrupt driven control or automated DMA control. In CPU control, the software writes the outgoing byte into the output buffer and then sets ACKn low to send the data. After the host completes the data transfer, the ACKn is automatically set high and the CPU is free to respond to any PPI interrupts that have been enabled or to initiate an additional data transfer if needed. The handshake signals are INITn, PE, ACKn, AUTOFDn and BUSY. 17.1.7 The Non-standard Dribble Mode The dribble mode was used for the slower PC before P1284 is standardized. Dribble mode is similar to ECP in that the channel can be reversed without having to go through a negotiation phase to turn the channel around. It sends two bits at a time on the nPeriphRequest and XFlag signals rather than using the PIO data bus. In this respect, it is similar to nibble mode's data transfer phase in that it uses HostBusy and PtrClk to transfer each portion of the data byte. The dribble mode can only operate under CPU interrupt-driven control (no DMA mode). Note: This is not an IEEE-1284 mode but is useful to support certain product interfaces created prior to the IEEE-1284 specification. 17.2 Additional Features 17.2.1 Filter A digital filter is provided for incoming host control and data signals. SLCTINn, STROBEn, AUTOFDn, and INITn are provided with digital filter circuits which are collectively controlled by software. IF DFIL =0, then no digital filtering is selected. Note that synchronization plus digital filtering adds up to four CLK periods of delay before a level change at one of the host inputs appears in the Parallel Port Control Register, and five periods of delay before an output responds to an input (e.g., before BUSY responds to STROBEn). Likewise, synchronization and digital filtering of STROBEn affect the point at which ippid[7-0] and AUTOFDn are latched into the parallel Port Data Register. Without a DFIL=3, ippid[7-0] and AUTOFDn are sampled an the fourth rising edge of CLK after STROBEn is sampled. With digital filtering, ippid7-0 and AUTOFDn are sampled on the fifth rising edge of CLK after STROBEn is sampled. 17-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 17.3 Functional Description The PPI contains an interface controller, which consists of: a data receive and transmit latch, run-length encoding decompression logic, input conditioning logic, and edge detector logic. The RLE decompression is accomplished through a state machine and additional control logic. There is input conditioning logic to filter the incoming control signals. The peripheral interface block supports four IEEE 1284 communication modes: compatibility, nibble, byte, and enhanced capabilities port (ECP) mode. The interface with the DMA controller requires storing data into 8 bit bytes before transferring to the four half word FIFO for burst operation. There will be a counter within the FIFO that keeps track of the bytes transferred to the FIFO. There is a control bit allowing FIFO flush to be done. If firmware detects the end of transfer to the PPI, it can flush the FIFO by forcing the flush bit. The timing of the F/W flush is based on a fixed time from the last DMA access and the FIFO not empty status and there will be a busy status bit set by F/W to stop further transmission from the host. The DMA or the interrupt operations are enabled under the control of the F/W. The PPI has fifteen sources of interrupt that can each be individually enabled or disabled and they are all ORed together to generate one PPI IRQ interrupt for the CPU. RPPD(7:0) DATA TRANSMIT LATCH oppid(7:0) ippid(7:0) DATA RECEIVE LATCH FPPD(7:0) CONTROL REGISTERS IP_BUS BUSY ACKn FAULTn SLCTOUTn PE Freq INITn AUTOFDn STROBEn SLCTINn inib DIGITAL FILTER IP_BUS DMAREQ DMARWN DMAACK DMA_TC Fack STATE MACHINE afdb strb sinb Rreq Rack DMA FIFOs Figure 17-1. Parallel Port Interface Controller Block Diagram 100723A Conexant 17-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 17.4 Register Description Parallel Port Control Register Address Bit 15 Bit 14 (Not Used) Bit 13 TRIZN Bit 12 PPIRSTN Bit 11 MODE Bit 10 MODE Bit 9 RFULL (R) Bit 8 FFULL (R) Default Rst. Value xx000000b Read Value 00h Parallel Port Control (Not Used) Reg. (PIOCtrl) $01FF8201 Address Parallel Port Control Reg. (PIOCtrl) $01FF8200 Bit 7 RLD (R) Bit 6 ABRT Bit 5 PDOE (R) Bit 4 ERRC Bit 3 MODE Bit 2 MODE Bit 1 DFIL Bit 0 DFIL Default Rst. Value 00h Read Value 00h DFIL Digital Filter This 2 bit field controls the number of clocks of digital filtering to be applied on the four host control signal inputs, SLCTINn, STROBEn, AUTOFDn, and INITn. From 0 to 3 clocks of digital filtering may be selected. This 4 bit field(bits 11,10,3,2) selects and enables a hardware handshaking mode for forward data transfers. MODE 0 1 2 3 4 5 6 7 8-15 Fwd Fwd Fwd Rev Rev Rev Rev Direction Disable Compatibility mode ECP-fwd without RLE mode ECP-fwd with RLE mode Nibble mode Byte mode ECP-rev mode Dribble mode Reserved Function MODE Mode Error Cycles This bit is used to execute an error cycle when in compatibility mode (mode 1). When set, ERRC immediately forces the BUSY pin high. If ERRC is set when a compatibility mode handshake sequence is in process, the BUSY remains high beyond the end of the cycle. ERRC does not affect an ACKn pulse that is already active, but does prevent an ACKn pulse if it is about to be generated. While ERRC is set, software may set or clear SEL, PERR, and NFLT in the Parallel Port Interface Register. When ERRC is cleared, the PPI generated an ACKn pulse and tries to lower BUSY to conclude the error cycle. If, however, FBSY is set, BUSY remains high until FBSY is cleared. When MODE is set to any value except 1, setting ERRC has no effect. Setting MODE to 1 when ERRC is already set causes the handshake controller to immediately begin an error cycle. 17-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 PDOE Parallel Data Output Enable This bit performs two functions. It controls the state of the PD bus three-state output drives, and it qualifies the latching of data from the PD bus into the Parallel Port Data Register. When set, PDOE enables the PD bus output pin drivers, and prevents data from being latched into the Parallel Port Register. Setting ABRT affects the operation of PDOE. IF ABRT is set, SLCTINn (1284ACTIVE) must remain high to allow PDOE to be set or remain set. If ABRT is set and SLCTINn (1284Active) goes low, PDOE is cleared, and setting PDOE has no effect. ABRT Abort This causes the PPI to use SLCTINn (1284Active) to detect when the host suddenly aborts a reverse transfer and returns to compatibility mode. If ABRT is set, a low level on SLCTINn (1284 Active) causes PDOE to be cleared and the PD bus output drivers to be three-stated. In fact, if ABRT is set and SLCTINn (1284Active) is low, setting PDOE has no effect. This protection logic, as all internal logic, operates from a synchronized and optionally digitally filtered SLCTINn (1284Active) that is latched into the parallel Port Interface Register. This is a read-only status bit which indicates when run-length decompression is taking place during ECP forward data transfers. RLD is set when a run-length count is received and loaded into the internal counter, and cleared when the last read of the Parallel Port Data Register takes place. This bit can only be set when ECP with RLE (mode 3) is enabled. If MODE is reprogrammed during a decompression, decompression continues and RLD remains set until the operation is completed. RLD is cleared when RST is issued. This is a read-only status bit that indicates when parallel port data from the host is latched in the Parallel Port Data Register. FFULL is cleared when the Parallel Port Data Register is read. When handshaking and DMA is enabled, FFULL sets and clears as data is latched and read during forward data transfers. FFULL is also cleared when RST is issued. This is a read-only status bits indicates when parallel port data to the host is latched in the Parallel Port Data Register. RFULL is cleared when the Parallel Port Data Register is sent. When handshaking and DMA is enabled, RFULL sets and clears as data is latched and sent during reverse data transfers. RFULL is also cleared when RST is issued. Active low resets all the state machines and is programmable using this register bit. During the normal operation this bit needs to be set to allow the state machine to start. Active low to enable tri-state input during the forward(PC to printer) transfers. RLD Run Length Decompression FFULL Forward Data Register Full RFULL Reverse Data Register Full PPIRSTN Parallel port software reset TRIZN Tri-state output enable 100723A Conexant 17-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Parallel Port Interface Register The Parallel Port Interface Register is a read/write register that contains eleven bits to control the parallel port interface signals. Four read-only bits are used to read the logic level of host input pins, two read-only bits are used to read the logic level on the BUSY and ACKn printer output pins, and five read/write bits control the logic levels on the printer output pins. When hardware handshaking is enabled(mode 1,2,3) BUSY and ACKn are controlled by the PPI state machine. When hardware handshaking is disabled (mode 0) and the PPI state machine is idle BUSY and ACKn may be controlled by the software using the FBSY and FACK bits. Note: NFLT,SEL,PERR and FBSY are arranged as register bits 0, 1, 2, and 3, respectively, to correspond to their use as parallel data lines during nibble mode reverse data transfers. Address Parallel Port Interface Reg. (PIOIF) $01FF8203 Bit 15 (Not Used) Bit 14 FRDA Bit 13 SPER (R) Bit 12 SSEL (R) Bit 11 SNFL (R) Bit 10 NINI (R) Bit 9 NAFD (R) Bit 8 NSTR (R) Default Rst. Value x0000000b Read Value 07h Address Parallel Port Interface Reg. (PIOIF) $01FF8202 Bit 7 NSIN (R) Bit 6 NACK (R) Bit 5 BUSY (R) Bit 4 FACK Bit 3 FBSY Bit 2 PERR Bit 1 SEL Bit 0 NFLT Default Rst. Value 08h Read Value 08h NFLT SEL PERR FBSY FAULTn SLCTOUT Paper Error Force Busy This bit controls the logic level driven on FAULTn output pin. Setting NFLT drives a high level and clearing SEL drives a low level. This controls the logic level driven on the SLCTOUT output pin. Setting SEL drives a high level and clearing SEL drives a low level. This bit controls the logic level driven on the PE output pin. Setting PERR drives a high level and clearing PERR drives a low level. This bit force a high level to be driven on the BUSY output pin. Normally this is done when hardware handshaking is disabled(mode 0), and the PPI state machine is idle. The FBSY bit is OR'ed with the BUSY output from the PPI state machine before driving the BUSY output pin. IF FBSY is set, then the BUSY output pin is forced high, and the BUSY bit is read high. This bit is set on reset. This bit forces a low level to be driven on the ACKn output pin. Normally this is done when hardware handshaking is disabled (mode 0), and the PPI state machine is idle. The FACK bit is NOR'ed with the ACKn output from the PPI state machine before driving the ACKn output pin. If FACK is set, then the ACKn output pin is forced low, and the NACK bit is to be read low. This status bit indicates the level driven on the BUSY output pin. This bit is the FBSY bit OR'ed with BUSY output from the PPI state machine. Since FBSY is set on reset, this bit will appear set on reset. This is a read-only status bit. FACK Force Ack BUSY 17-6 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 NACK ACKn This status bit indicates the level driven on the ACKn output pin. This bit is the FACK bit NOR'ed with the ACKn output from the PPI state machine. Since FACK is cleared on reset, this bit will appear set on reset. This is read-only status bit. This status bit indicates the level read on the SLCTINn* input pin after synchronization and optional digital filtering. This is a read-only status bit. This status bit indicates the level read on the STROBE* input pin after synchronization and optional digital filtering. This is a read-only status bit. This status bit indicates the level read on the AUTOFDn input pin after synchronization and optional digital filtering. This is a read-only status bit. This status bit indicates the level read on the INITn input after synchronization and optional digital filtering. This is a read-only status bit. This status bit indicates the level read on the FAULTn output pin. This is a read-only status bit. This status bit indicated the level read on the SLCTOUT output pin. This is a read-only status bit. This status bit indicated the level read on the PE output pin. This is a read-only status bit. This bit controls the RDA status during Nibble Mode and Byte Mode when DMA is not used. NSIN SLCTINn NSTR Strobe* NAFD AUTOFDn NINI INITn SNFL SSEL SPER FRDA FAULTn Status SLCTOUT Status Paper Error Status Force Reverse Data Available Parallel Port Data Register The parallel Port Data Register is a 9-bit read/write register that is used to control the parallel port data bus. Reading this register provides the latched logic levels at PD7-0 and AUTOFDn pin. Data is latched on every high to low transition of STROBEn (HostClk), when PDOE is clear in the Parallel Port Control Register. If PDOE is set, the Parallel Port Data Register is frozen, and unaffected by the transitions on STROBEn. Reading this register clears the FULL bit, and clears the PDMA request. This register should not be read while the PDMA channel is enabled. Address Parallel Port Data Reg. (PIOData) $01FF8205 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 NCMD Default Rst. Value xxxxxxx0b Read Value 00h Address Parallel Port Data Reg. (PIOData) $01FF8204 Bit 7 DATA(7) Bit 6 DATA(6) Bit 5 DATA(5) Bit 4 DATA(4) Bit 3 DATA(3) Bit 2 DATA(2) Bit 1 DATA(1) Bit 0 DATA(0) Default Rst. Value 00h Read Value 00h DATA Data This field is an 8-bit read/write field. When used, DATA provides the latched logic levels on PD7-0 when STROBEn (HostCLk) last transmitted from high to low with PDOE clear. When written, the DATA value defines the logic levels to be driven by the QP1700 when PD7-0 is enabled by the PDOE bit. The most significant bit of the DATA field corresponds to PD7 and the least significant bit to PD0. 100723A Conexant 17-7 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description NCMD Command When read, this bit provides the logic level of the AUTOFDn pin when STROBEn (hostClk) transitioned from high to low with PDOE clear. If set, AUTOFDn was latched high. If low, AUTOFDn was latched low. This is a read-only data bit. Writing NCMD has no effect. Parallel Port ACK Pulse Width Register The Parallel Port ACK Pulse Width Register is an 8-bit read/write register that defines the pulse width of ACKn during compatibility mode (MODE = 1), and setup timing relative to ACKn during reverse transfer modes (MODE=4,4,6). The Parallel Port ACKn Pulse Width Register can be written and rewritten to program different timing values as transitions are made to new transfer modes. An ACKn pulse width can be programmed to be 0 to 255 IHSCLK periods wide. At 20MHZ, this allows software to set pulse widths anywhere in the range of 0 to 12.75us. If ACKW is set to zero, no ACKn pulse is generated at the end of compatibility mode cycles. Setup timing relative to ACKn during reverse transfer modes can be programmed to be 1 to 256 IHSCLK periods. During nibble or byte modes(MODE=4,5), ACKW defines the setup timing from nibble or byte data (event 8 or 15) and the falling edge of ACKn (event 9), or from peripheral status (event 13) to the rising edge of ACKn (event 11). During ECP reverse transfers (MODE = 6), ACKW defines the setup timing from reverse data (event 42) to the falling edge of ACKn (event 43). Address Parallel Port ACK Pulse Width Reg. (PIOAckPW) $01FF8207 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Rst. Value xxh Read Value 00h Address Parallel Port ACK Pulse Width Reg. (PIOAckPW) $01FF8206 Bit 7 ACKW(7) Bit 6 ACKW(6) Bit 5 ACKW(5) Bit 4 ACKW(4) Bit 3 ACKW(3) Bit 2 ACKW(2) Bit 1 ACKW(1) Bit 0 ACKW(0) Default Rst. Value 00h Read Value 00h ACKW ACKn Pulse Width This 8 bit field defines the pulse width of ACKn during compatibility mode transfers (MODE = 1), and the setup relationship relative to ACKn during reverse transfer modes (MODE=4,5,6). A pulse width from 0 to 255 IHSCLK periods can be programmed. Parallel Port Reverse Data Status Register Address Bit 15 Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Rst. Value xxh Read Value 00h Parallel Port Reverse (Not Used) Data Status Reg. (PIORevDataSTS) $01FF8209 (R) Address Bit 7 Bit 6 RVDAT(6) Bit 5 RVDAT(5) Bit 4 RVDAT(4) Bit 3 RVDAT(3) Bit 2 RVDAT(2) Bit 1 RVDAT(1) Bit 0 RVDAT(0) Default Rst. Value 00h Read Value 00h Parallel Port Reverse RVDAT(7) Data Status Reg. (PIORevDataSTS) $01FF8208 (R) REVDATA Reverse Data This 8-bit field is the status of the reverse data that was written into the Parallel Port Data Register oppid[7:0]. This normally is needed only for diagnostic purposes. This is a read-only status register. 17-8 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Parallel Port Data Bus Status Register Address Parallel Port Data Bus Status Reg. (PIODataBusSTS) $01FF820B (R) Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Rst. Value xxh Read Value 00h Address Parallel Port Data Bus Status Reg. (PIODataBusSTS) $01FF820A (R) Bit 7 PDBUS(7) Bit 6 PDBUS(6) Bit 5 PDBUS(5) Bit 4 PDBUS(4) Bit 3 PDBUS(3) Bit 2 PDBUS(2) Bit 1 PDBUS(1) Bit 0 PDBUS(0) Default Rst. Value 00h Read Value 00h PPDBUS Data Bus Status This 8 bit field is the status of the parallel port data bus ippid[7:0]. This normally is needed only for diagnostic purposes. This is a read-only status register. Parallel Port Host Timeout Register Address Parallel Port Host Timeout Reg. (PIOHostTimeOut) $01FF820D Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Rst. Value xxh Read Value 00h Address Parallel Port Host Timeout Reg. (PIOHostTimeOut) $01FF820C Bit 7 HTIM(7) Bit 6 HTIM(6) Bit 5 HTIM(5) Bit 4 HTIM(4) Bit 3 HTIM(3) Bit 2 HTIM(2) Bit 1 HTIM(1) Bit 0 HTIM(0) Default Rst. Value 00h Read Value 00h HTIM Host Timeout This 8 bit field controls the timer for the host timeout error interrupt HTE. The timer counts from the system timer which is usually programmed to count every 8 msec. HTTM is usually programmed with a value of 0x7d (125) so that a host timeout interrupt occurs after 1 sec. If the host timeout error interrupt HTE is not desired, then interrupt enable should be false. 100723A Conexant 17-9 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Interrupt Status Register Address Bit 15 Bit 14 DMARIRQ Bit 13 DMAFIRQ Bit 12 HTE Bit 11 RDX Bit 10 IVT Bit 9 CRX Bit 8 DRX Default Rst. Value x0000000b Read Value 00h Parallel Port Interrupt (Not Used) Status (PIOIRQSTS) $01FF820F Address Bit 7 Bit 6 INIH Bit 5 AFDL Bit 4 AFDH Bit 3 STRL Bit 2 STRH Bit 1 SINL Bit 0 SINH Default Rst. Value 00h Read Value 00h Parallel Port Interrupt INIL Status (PIOIRQSTS) $01FF820E SINH SINL STRH STRL AFDH AFDL INIH INIL DRX CRX IVT RDX THE FDM AIRQ SLCTINn high edge interrupt. SLCTINn low edge interrupt. STROBEn high edge interrupt. STROBEn low edge interrupt. AUTOFDn high edge interrupt. AUTOFDn low edge interrupt. INITn high edge interrupt. INITn low edge interrupt. data received interrupt. command received interrupt. invalid transition interrupt. rev data sent interrupt. host timeout interrupt. Forward transfer DMA end of block interrupt RDM AIRQ Reverse transfer DMA end of block interrupt Clearing any interrupt requires writing a 1 to the corresponding bit in the interrupt status register. 17-10 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Interrupt Mask Register Address Bit 15 Bit 14 DMARIRQ MASK Bit 13 DMAFIRQ MASK Bit 12 HTE MASK Bit 11 RDX MASK Bit 10 IVT MASK Bit 9 CRX MASK Bit 8 DRX MASK Default Rst. Value x0000000b Read Value 00h Parallel Port Interrupt (Not Used) Mask. (PIOIRQMask) $01FF8211 Address Bit 7 Bit 6 INIH MASK Bit 5 AFDL MASK Bit 4 AFDH MASK Bit 3 STRL MASK Bit 2 STRH MASK Bit 1 SINL MASK Bit 0 SINH MASK Default Rst. Value 00h Read Value 00h Parallel Port Interrupt INIL Mask (PIOIRQMask) MASK $01FF8210 The mask register will be used to enable the interrupts when writing one to each corresponding bit and disable the interrupts when writing zero to the corresponding bit. FIFO Interface Register Address Parallel Port FIFO Interface PIOFIFOIF 01FF8213 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default REVFIFO_ REVFIFO_ REVFIFO_ LCLCLEARI LCLFLUSHI LCLREQ NG NG (RD) (RD) (RD) FWDFIFO_ FWDFIFO_ LCLCLEARI LCLFLUSHI NG NG (RD) (RD) FWDFIFO_ Rst. Value LCLREQ xx000000b Read Value 00h (RD) Address Parallel Port FIFO Interface PIOFIFOIF 01FF8212 Bit 7 REVFIFO_ LCLCLR Bit 6 Bit 5 Bit 4 FWDFIFO_ ENABLE Bit 3 FWDFIFO_ FLUSH Bit 2 REVFIFO_ TC0EN Bit 1 REVFIFO_ ENABLE Bit 0 REVFIFO_ FLUSH Default Rst. Value 00h Read Value 00h FWDFIFO_ FWDFIFO_ LCLCLR TC0EN REVFIFO_FLUSH REVFIFO_ENABLE REVFIFO_TC0EN FWDFIFO_FLUSH FWDFIFO_ENABLE FWDFIFO_TC0ENA FWDFIFO_LCLCLR REVFIFO_LCLCLR FWDFIFO_LCLREQ FWDFIFO_LCLFLUSHING FWDFIFO_LCLCLEARING REVFIFO_LCLREQ REVFIFO_LCLFLUSHING REVFIFO_LCLCLEARING causes the reverse FIFO to execute a flush of its contents. enables the reverse FIFO operation. When false, any pending DMA requests are first completed before the reverse FIFO becomes disabled. When low it enables the reverse FIFO DMA operation. causes the forward FIFO to execute a flush of its contents. enables the forward FIFO operation. When false, any pending DMA requests are first completed before the forward FIFO becomes disabled. When low it enables the forward FIFO DMA operation. FWD FIFO local asynchronous clear except waits for any pending DMA requests to finish before reset. REV FIFO local asynchronous clear except waits for any pending DMA requests to finish before reset. FWD FIFO local request is similar to dmareq but ignores dmaEq0 input. Used for firmware DMA as a status signal. high when lclFlush is pulsed high and stays high until the FIFO is flushed. high when lclClr is pulsed and stays high until the clear can be done(no dmaReq). REV FIFO local request is similar to dmareq but ignores dmaEq0 input. Used for firmware DMA as a status signal. high when lclFlush is pulsed high and stays high until the FIFO is flushed. high when lclClr is pulsed and stays high until the clear can be done (no dmaReq). 100723A Conexant 17-11 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description DMA FIFO Registers There will be two 4 half word FIFOs used for forward and reverse DMA transfers. The FIFO locations will be accessed from CPU as well as DMA. The address locations for the forward DMA FIFO will be 01FF8220 to 01FF822F. The address locations for the reverse FIFO will be 01FF8230 to 01FF823F. Output data FIFO halfword[3:0] for the data to the external memory (the forward direction) (for DMA channel 11): Address: Parallel Port Output Data FIFO (PIOOutFIFOx) Address: Parallel Port Output Data FIFO (PIOOutFIFOx) Bit 15 data bit 15 Bit 14 data bit 14 Bit 13 data bit 13 Bit 12 data bit 12 Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value 00h Read Value 00h Default: Rst Value 00h Read Value 00h Bit 7 data bit 7 Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 * Address assignment for Output FIFO halfword[3:0] The Input FIFO halfword Output FIFO halfword 3 Output FIFO halfword 2 Output FIFO halfword 1 Output FIFO halfword 0 The register name PIOOutFIFO3 PIOOutFIFO2 PIOOutFIFO1 PIOOutFIFO0 Address 01FF8227-26 01FF8225-24 01FF8223-22 01FF8221-20 Output data FIFO Holding Register for the data to the external memory (the forward direction) (for DMA channel 11): Address: Parallel Port Output Data FIFO Holding Register (PIOOutHold) $01FF8229 Address: Parallel Port Output Data FIFO Holding Register (PIOOutHold) $01FF8228 Bit 15 data bit 15 Bit 14 data bit 14 Bit 13 data bit 13 Bit 12 data bit 12 Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value xxh Read Value xxh Default: Rst Value 00h Read Value 00h Bit 7 data bit 7 Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 17-12 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Output data FIFO Control Register for the data to the external memory (the forward direction) (for DMA channel 11): Address: Parallel Port Output Data FIFO Control Register (PIOOutFIFOCtrl) $01FF822B Address: Parallel Port Output Data FIFO Control Register (PIOOutFIFOCtrl) $01FF822A Bit 15 FIFO Enabled (R) Bit 14 Data Request (R) Bit 13 FIFO Ready (R) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst Value 00h Read Value 00h Default: Rst Value x0000000b Read Value 00h FIFO DMA Threshold FIFO Output Pointer Bit 7 (Not Used) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Holding Byte Present FIFO Data Quantity Register Full FIFO Input Pointer Bit 15: This bit indicates that the FIFO is active and capable of generating DMA requests. This bit generally follows the setting of the LCL_ENB input signal except the FIFO Enabled register bit will remain asserted if the LCL_ENB input signal is set to false while the FIFO is executing a DMA transfer. In this case, the register bit will remain set for the duration of the DMA transfer and then become cleared. This bit is similar to the DMA_REQ signal except that it is not blocked when DMA_TC0 is set. It indicates that the programmed threshold has been met or exceeded and that the FIFO requires data transfers either by enabling hardware DMA through DMA_TC0 or by executing software DMA cycles. This bit indicates that the FIFO can accept data transfers to/from the local logic. This bit is low when the data direction is into the local logic and the FIFO is empty or when the data direction is out of the local logic and the FIFO is full. This bit field indicates at which point the FIFO should issue a DMA request. It is compared with the FIFO Data Quantity bit field to determine when this should occur. Legal values are from 1 to 4. A value of zero causes no data transfers to occur. Values greater than 4 are treated as 4. This bit field indicates which byte of the FIFO quad halfword structure is the next to be used as output data. Not used This bit indicates that there is a full word in the holding register. This bit indicates that there is a single byte in the holding register. This bit field indicates the number of quad halfwords that contain data. Valid values are from 0 to 4. This bit field indicates which byte of the FIFO quad halfword structure is the next to receive input data. Note: It is strongly recommended that the FIFO be disabled before firmware writes to the FIFO Control register. The FIFO Control register contains data that is essential to the FIFO's operation. If this data is changed while the FIFO is operating, unpredictable operation will result. Bit 14: Bit 13: Bit 12-10: Bit 9-8: Bit 7: Bit 6: Bit 5: Bit 4-2: Bit 1-0: 100723A Conexant 17-13 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Input data FIFO halfword[3:0] for the data from the external memory (the reverse direction) (for DMA channel 12): Address: Parallel Port Input Data FIFO (PIOInFIFOx) Address: Parallel Port Input Data FIFO (PIOInFIFOx) Bit 15 data bit 15 Bit 14 data bit 14 Bit 13 data bit 13 Bit 12 data bit 12 Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value 00h Read Value 00h Default: Rst Value 00h Read Value 00h Bit 7 data bit 7 Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 * Address assignment for Input FIFO halfword[3:0] The Input FIFO halfword Input FIFO halfword 3 Input FIFO halfword 2 Input FIFO halfword 1 Input FIFO halfword 0 The register name PIOInFIFO3 PIOInFIFO2 PIOInFIFO1 PIOInFIFO0 Address 01FF8237-36 01FF8235-34 01FF8233-32 01FF8231-30 Input data FIFO Holding Register for the data from the external memory (the reverse direction) (for DMA channel 12): Address: Parallel Port Input Data FIFO Holding Register (PIOInHold) $01FF8239 Address: Parallel Port Input Data FIFO Holding Register (PIOInHold) $01FF8238 Bit 15 data bit 15 Bit 14 data bit 14 Bit 13 data bit 13 Bit 12 data bit 12 Bit 11 data bit 11 Bit 10 data bit 10 Bit 9 data bit 9 Bit 8 data bit 8 Default: Rst Value 00h Read Value 00h Default: Rst Value 00h Read Value 00h Bit 7 data bit 7 Bit 6 data bit 6 Bit 5 data bit 5 Bit 4 data bit 4 Bit 3 data bit 3 Bit 2 data bit 2 Bit 1 data bit 1 Bit 0 data bit 0 17-14 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Input data FIFO Control Register for the data from the external memory (the Reverse direction) (for DMA channel 12): Address: Parallel Port Input Data FIFO Control Register (PIOInFIFOCtrl) $01FF823B Address: Parallel Port Input Data FIFO Control Register (PIOInFIFOCtrl) $01FF823A Bit 15 FIFO Enabled (R) Bit 14 Data Request (R) Bit 13 FIFO Ready (R) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst Value 00h Read Value 00h Default: Rst Value x0000000b Read Value 00h FIFO DMA Threshold FIFO Output Pointer Bit 7 (Not Used) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Holding Byte Present FIFO Data Quantity Register Full FIFO Input Pointer Bit 15: This bit indicates that the FIFO is active and capable of generating DMA requests. This bit generally follows the setting of the LCL_ENB input signal except the FIFO Enabled register bit will remain asserted if the LCL_ENB input signal is set to false while the FIFO is executing a DMA transfer. In this case, the register bit will remain set for the duration of the DMA transfer and then become cleared. This bit is similar to the DMA_REQ signal except that it is not blocked when DMA_TC0 is set. It indicates that the programmed threshold has been met or exceeded and that the FIFO requires data transfers either by enabling hardware DMA through DMA_TC0 or by executing software DMA cycles. This bit indicates that the FIFO can accept data transfers to/from the local logic. This bit is low when the data direction is into the local logic and the FIFO is empty or when the data direction is out of the local logic and the FIFO is full. This bit field indicates at which point the FIFO should issue a DMA request. It is compared with the FIFO Data Quantity bit field to determine when this should occur. Legal values are from 1 to 4. A value of zero causes no data transfers to occur. Values greater than 4 are treated as 4. This bit field indicates which byte of the FIFO quad halfword structure is the next to be used as output data. Not used This bit indicates that there is a full word in the holding register. This bit indicates that there is a single byte in the holding register. This bit field indicates the number of quad halfwords that contain data. Valid values are from 0 to 4. This bit field indicates which byte of the FIFO quad halfword structure is the next to receive input data. Note: It is strongly recommended that the FIFO be disabled before firmware writes to the FIFO Control register. The FIFO Control register contains data that is essential to the FIFO's operation. If this data is changed while the FIFO is operating, unpredictable operation will result. Bit 14: Bit 13: Bit 12-10: Bit 9-8: Bit 7: Bit 6: Bit 5: Bit 4-2: Bit 1-0: 100723A Conexant 17-15 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 17.5 Timing 17.5.1 Compatibility Timing When this mode of handshaking is enabled, the PPI automatically generates BUSY upon reception of the leading edge of STROBEn from the host, and latches the logic levels to the ippid bus and AUTOFDn in the Parallel Port Data Register. The PPI then waits for the STROBEn to de-assert and the Parallel Port Data Register to be read. After the later of these events occurs, the PPI asserts ACKn for the duration specified in the Parallel Port ACK Pulse Width Register and then de-asserts ACKn and BUSY to conclude the data transfer. When data is latched into the Parallel Port Data Register, the PPI controller generates two events: an internal parallel port DMA request, and a processor interrupt request. Software may alternate between DMA and interrupt based data transfers. The DMA request remain active until the data is read by either the DMA channel, or the processor in response to the interrupt request. If the Forward DMA FIFO has been enabled, the Forward DMA FIFO generates fdmareq after reading the Parallel Port Data Register and writing the data to its internal half word quad registers. When the fdmack is generated the DMA channel reads the Forward FIFO internal Registers, ACKn is pulsed, BUSY is deserted, and the fdmack is cleared. 17.5.1.1 Compatibility Mode Timing Diagram 1. 2. 3. 4. 5. Host writes data to the data bus If obusy is not active, the host will assert the istroben low. Peripheral will assert obusy high to indicate data transfer cycle. Host will set the istroben and at the rising edge, the peripheral will latch the data . Peripheral asserts oackn low to acknowledge the transfer and drops the obusy. IPPID[7:0] STROBEn BUSY ACKn Latch data Request Interrupt Read data Make ACK pulse Figure 17-2. Compatibility Mode Timing Diagram 17-16 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 17.5.2 Nibble Mode Timing The Nibble mode is the most common way to get reverse channel from printer or peripheral. This mode is usually combined with the compatibility mode or a proprietary forward channel mode to create a complete bi-direction channel. The Nibble Mode Phase transitions: 1. 2. 3. 4. 5. Host signal ability to take data by asserting AUTOFDn low Peripheral responses by placing first nibble on status lines(FAULTn,SLCTOUT,PE and BUSY) Peripheral signals valid nibble by asserting ACKn low Host sets AUTOFDn high to indicate that it has received the nibble and is not ready for another nibble. Peripheral set ACKn high for the second nibble. AUTOFDn ACKn FAULTn SLCTOUT PE BUSY BITS[1:4] BITS[5:8] Figure 17-3. Nibble Mode Data Transfer Cycle 100723A Conexant 17-17 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 17.5.3 Byte Mode Timing Byte mode is a reverse channel data transfer used to provide data rates into the PC approaching that of compatibility mode. The byte mode signal handshaking is as follows: 1. 2. 3. 4. 5. 6. Host signals ability to take data by asserting AUTOFDn low Peripheral responds by placing first byte on data lines Peripheral signals valid byte by asserting ACKn low Host sets AUTOFDn high to indicate it has received data Peripheral sets ACKn high to acknowledge host Host pulses STROBEn as an acknowledge to the peripheral. AUTOFDn ACKn OPPID[7:0] STROBEn Figure 17-4. BYTE Mode Data Transfer Cycle 17-18 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 17.5.4 ECP Mode Timing Two modes of hardware handshaking are offered for ECP forward transfers. ECP mode hardware handshaking is enabled by setting the MODE field in the Parallel Port Control Register to 2. The ECP mode hardware handshaking with RLE is enabled by setting MODE to 3. When either mode is enabled, the PPI automatically responds to STROBEn (HostClk) by latching the logic levels on the PD bus and AUTOFDn in the Parallel Data Register. When the Parallel Port Data Register is read, the PPI drives BUSY high,waits for STROBEn to high, and then drives BUSY (periphAck) low to conclude the cycle. The BUSY signal is controlled by the PPI automatically if the data is received using DMA mode. Note that since no ACKn pulse is generated, the pulse width duration specified in the Parallel Port ACK Pulse Width Register is not used in any manner. As in the compatibility handshake mode, data is latched at the leading edge of STROBEn. This then causes a DMA request and posting of DRX (data received) interrupt event. DMA and interrupt operation is the same as explained in the compatibility mode. In mode 2, reception of both run-length counts and channel addresses causes a CRX interrupt event to be posted. Software is responsible for responding to channel addresses and performing data decompression. When MODE is set to 3, ECP mode hardware handshaking is enabled during forward data transfers, with Run Length Encoding(RLE) data compression support. If MODE is reprogrammed when decompression is taking place, that is, when RLD is set, the decompression continues unhindered to completion. 17.5.4.1 Forward ECP Transfer Handshake: The host places data on the data lines and indicates a data cycle by setting AUTOFDn high. 1. 2. 3. 4. 5. Host asserts STROBEn low to indicate valid data. Peripheral acknowledges host by setting BUSY high. Host sets STROBEn high and the data is clocked in to the peripheral. Peripheral sets BUSY low to indicate that it is ready for the next byte. The cycle repeats, but this time it is a command cycle because AUTOFDn is low. DATA STROBEn BUSY Latch data Request Interrupt Figure 17-5. ECP Mode Timing Diagram Read data 100723A Conexant 17-19 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 17.5.4.2 Reverse ECP Transfer Handshake 1. 2. 3. 4. 5. 6. 7. 8. The host requests a reverse channel transfer by setting INITn low. The peripheral signals that it is OK to proceed by setting PE low. The peripheral places data on the data lines and indicates a data cycle by setting BUSY high. The peripheral asserts ACKn low to indicate valid data. The host acknowledges by setting AUTOFDn high. The peripheral sets ACKn high to clock the data in to the host. The host sets AUTOFDn low to indicate that it is ready for the next byte. The cycle repeats, but this time it is a command cycle because ACKn is low. INITn PE OPPID[7:0] DATA ACKn AUTOFDn BUSY Figure 17-6. Reverse ECP Transfer Timing 17-20 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 17.5.5 Error Cycle Timing Error cycles are performed by a printer to alert the host of a change in the operational status of the printer. Error cycles include such events as the user taking the printer off-line, the occurrence of a paper jam, or the printer running out of paper. An error cycle consists of raising BUSY, and then changing the state of any one or more of the three status lines, SLCTOUT, PE and FAULTn to reflect the error condition. The ERRC bit in the control register prevents handshake logic from generating ACKn and BUSY in the compatibility mode. ERRC SLCTOUT PE FAULTn BUSY ACKn Figure 17-7. Error Cycle Timing Diagram 100723A Conexant 17-21 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 17.6 Firmware Operation All the Parallel Port negotiations will be done in firmware. 17.6.1 Disabling All Hardware Handshaking When hardware handshaking is disabled(MODE=0), software is then responsible for controlling the parallel port interface. Software can control all parallel port operations including negotiation and termination phases, as well as reverse channel transfers. This provides flexibility to adapt to existing protocols as they are revised and to new protocols as they are created. Software can control the BUSY and ACKn interface pins with the FBSY (force BUSY) and FACK (force ACKn) bits in the Parallel Port Interface Register. The FBSY bit is OR'ed with the BUSY output from the PPI state machine before driving the BUSY interface pin, and the FACK bit is NOR'ed with the ACKn output from the PPI state machine before driving the ACKn interface pin. Normally the PPI state machine should be idle when using FBSY and FACK. Even with all hardware handshaking disabled, the Parallel port register continues to latch parallel port data on the leading edge of the STROBEn. Software can issue a RST in the Parallel Port Control Register to immediately force the PPI state machine to idle. 17.6.2 Software Interrupts The following is a list of P1284 signal transition interrupts provided for ease of use: SLCTINn STROBEn INITn AUTOFDn DRX CRX IVT RDX HTE Rising and Falling Rising and Falling (remains high until data is fetched from PPI) Rising and Falling Rising and Falling Data Received Command Received Invalid Transition Reverse Data Transmitted Host Time-out Error 17.6.3 Interrupt Operation There will be a bit corresponding to each interrupt in the interrupt enable register that enables the interrupt. When the event corresponding to an interrupt occurs, this bit needs to be set at the following rising edge of the SIU clock. The PPI Interface possesses 15 sources of interrupts. Each source can post an event in the interrupt status register and each event can be individually enabled or disabled in the interrupt mask register. The fifteen interrupts have been in Section 17. The first eight interrupt events signal level changes that occur at the host control signal input pins. Note that these events are detected after the host inputs are synchronized, digitally filtered, and recorded in the parallel Port Interface Register. 17-22 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 18. Real-Time Clock 18.1 Description The Real-Time Clock (RTC) circuit is required to maintain current time information under MFC2000 primary power and battery backup conditions. The RTC Circuit consists of six binary counters that track seconds, minutes, hours, days, months, and years elapsed since the reference year, 1992. Each counter can be read from the appropriate register described. The tracking range of the RTC is up to 32 years, and automatic compensation is made for leap years. A 32768 Hz signal is required to operate RTC counters and logic. A 32768 Hz (watch) crystal should be used. The RTC block diagram is illustrated in Figure 18-1. C O = 24 32 768 H z 15 B IT PR E SC A L ER 1 Hz 6 B IT SECOND S CO=60 6 B IT M IN U T ES C O = 60 5 B IT HOURS B U S Y F LA G C LE AR BU SY DE TEC T BU S Y F L AG 5 B IT DA YS C O = 28,29 , 30, or 30 4 B IT MO NTHS C O = 12 5 BIT YE AR S M O NT H D E CO D ER L EA P YE A R D E C O D ER 3 S TA TE D R IV E R Figure 18-1. RTC Block Diagram 100723A Conexant 18-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 18.2 Real-Time Clock (RTC) Registers Note: All RTC registers are cleared only by battery power-on reset or a write to the RTC control register. As you can see, second and minute are in the same 16-bit register. Hour_Day, and Month_Year registers have the same arrangement. If CPU does a 16-bit write to the Hour_Day register, both hour and day will increment. If CPU only writes to the lower 8-bit or the upper 8-bit, only hour or only day will increment. The Month_Year register operates in the same manner. The Sec_Min register operates differently. If CPU does a 16-bit write or a lower 8-bit write to the Sec_Min register, year, month, day, hour, and minute will increment once. If CPU only writes to the upper 8-bit, only minute will increment. Address: Second and Minute (Sec_Min) 01FF8091 Bit 15 Busy Flag (R) Bit 14 (Not Used) Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 0x000000b Read Value 00h Read: Data Range 000000 - 111011 Write: increment minute, (data is a don't care) Address: Second and Minute (Sec_Min) 01FF8090 Bit 7 Busy Flag (R) Bit 6 (Not Used) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 0x000000b Read Value 00h Read: Data Range 000000 - 111011 Write: increment all - year,month,day,hour and minute registers, (data is a don't care) Increment all will increment the year, month, day, hour, and minute registers by one. Address: Hour and day (Hour_Day) 01FF8093 Bit 15 Busy Flag (R) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 0xx00000b Read Value 00h Read: Data Range 00000 - 11110 Write: increment day (data is a don't care) Address: Hour and Day (Hour_Day) 01FF8092 Bit 7 Busy Flag (R) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value 0xx00000b Read Value 00h Read: Data Range 00000 - 10111 Write: increment hour (data is a don't care) Address: Month and Year (Month_Year) 01FF8095 Bit 15 Busy Flag (R) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value 0xx00000b Read Value 00h Read: Data Range 00000 - 11111 Write: increment year (data is a don't care) Address: Month and Year (Month_Year) 01FF8094 Bit 7 Busy Flag (R) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst.Value 0xxx0000b Read Value 00h Read: Data Range 0000 - 1011 Write: increment month, (data is a don't care) 18-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: Bit 15 Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Real Time Clock Ctrl (Not Used) (RTC) 01FF8097 Address: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value xxh Read Value 00h Real Time Clock Ctrl Read: Clears the busy flag (data is undefined) (RTC) Write: Resets the Real Time Clock (RTC), (data is a don't care) 01FF8096 Read: clear BUSY flag, data is undefined. Write: reset the RTC, data is 'don't care'. 18.3 RTC Operations 18.3.1 Power-Up/Power-Down Operation When prime power is applied to the MFPC and battery reset (BATRSTn) is generated, all counters in the RTC are reset to 0 and the RTC becomes accessible after a delay of from 125 to 250 ms, provided that the crystal clock is running. (Note: The RTC is also software resetable.) When prime power drops below a level where the power-down input (PWRDWNn) becomes active, an internal lockout signal prevents read and write access of the RTC, and RTC operation switches to battery power. Inactivation of the PWRDWNn pin (when prime power is restored) removes the lockout condition, and the RTC is again accessible. (Note: activation of external reset, RESETn, does not affect RTC operation.) 18.3.2 Setting Time The first step in setting the time is to reset the time counters by writing to the RTC Control register. The user can then set the current year (number of years elapsed since the reference year, 1992) into the upper 8bit of the month_year register. Each write to the year register increments the year counter by one. The month is then set by writing to the lower 8-bit of the month_year register, and each write increments the month counter by one. The same procedure should then be used to set the correct day, hour, and minute by writing to the corresponding registers. Writing to month_year, hour_day, or sec_min register resets the seconds counter to all zeros. Note that the RTC updates the second counter once per second independent of read or write operations to RTC registers. 18.3.3 Reading Time Each 8-bit (upper or lower) of the time interval registers can be independently read. The upper most bit of each 8bit section is a Busy Flag, which when set, indicates that a one second clock edge has occurred, and that the time is being updated in all registers. If the Busy Flag is set when reading any of the time registers, the user must issue a read to the RTC Control register to clear the Busy Flag, and then re-read all of the time registers until all Busy Flags are 0. 100723A Conexant 18-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 18.3.4 Crystal Oscillator Specifications for the clock crystal, a crystal oscillator schematic and circuit board layout recommendations follow. 18.3.5 RTC Crystal Specifications Table 18-1. RTC Crystal Specifications for 32.768 kHz Characteristic Nominal Frequency @25C (F) Turnover Temperature (To) Temperature Characteristic (K)* Temperature Stability Quality Factor Load Capacitance Series Resistance Motional Capacitance Shunt Capacitance Maximum Drive Level Aging ( F/f) Operating Temperature Value for 32.768 kHz 32.768 kHz 20 ppm 25C 5C -0.038 ppm/C2 Typ -160 ppm, Typ @ -40C -137 ppm, Typ @ +85C 100,000 Typ 12.5 pF 2% 30 K Max 3.5 pF Typ 1.7 pF Typ 1.0 W 5.0 ppm, First Year -10C to +60C *( F/f) = K(To-T)2 where T= point of temperature comparison Recommended RTC Crystal Interface Circuit Typical Values Fc R1 R2 C1 C2 32.768 kHz 10 M 0 K 22 pf 22 pf A M F PC X IN R1 X O UT R2 Fc C1 C2 Note: Adjustment to the values of C1 and C2 may be required to obtain the correct operating frequency due to stray capacitance on the Developer's circuit board. 18-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Circuit Layout Criteria For best performance the following design steps should be followed: 1. 2. 3. 4. 5. Keep stray capacitance and resistance to a minimum. Run XIN and XOUT traces as far apart as possible. Clear the ground plane from under the interface circuit. Keep digital signals away from this interface. This is a high impedance circuit; residual contamination (e.g., water soluble flux) of this circuit may cause unreliable operation. 100723A Conexant 18-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description This page is intentionally blank. 18-6 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 19. Synchronous Serial Interface (SsIF) 19.1 Introduction and Features 19.1.1 Introduction There are two identical SSIFs in the MFC2000. The common signal and block names are used in the functional and timing descriptions without indicating which SSIF. Two SSIFs are distinguished as SSIF1 and SSIF2 only in the register description. The SSIF built into the MFC2000, allows system peripherals to communicate with the MFC2000. The SSIF provides separate signals for Data (SSTXD, SSRXD), Clock (SSCLK), and optional (SSREQ) and Data Acknowledge (SSACK). The SSIF may be configured to operate as either a master or slave interface. After reset, SSTXD is 0 and SSSTAT is 1. The following describes the operation of this synchronous only serial interface. 19.1.2 Features * * * * * * * Full duplex, three wire system Master or slave operation (Bi-directional Clock) Programmable bit rates with maximum frequency = AUXCLK/2 and minimum = AUXCLK/32 with a 50% duty cycle. Programmable clock polarity and phase Internal interrupt for Receive Register Full (mask-able at the Interrupt Controller) Optional data request/acknowledge interface during slave mode 8 data bit synchronous serial-interface with programmable data shifting order A U X C LK S eria l C lk D ev id er5 b it C arry D ata B u s C lo ck D r iv er & C on tro l Ser l C lk S SC LK IR Q S SIf R d/W r A ddr W rite C on tro l R eg ister S er ia l O u t R ead SSTX D CS C nt = 8, IR Q D iv 8 R st C ou nter S er ia l In Set SSRX D S S ST A T A ck L atch C lr W r & Slav e M o d e Figure 19-1. SSIF Block Diagram 100723A Conexant 19-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 19.2 Register Description 19.2.1 The 1st SSIF (SSIF1) Address: SSData1 01FF8103 Bit 15 (Not Used) Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value xxh Read Value 00h Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value xxh Read Value xxh Address: SSData1 01FF8102 Bit 7 SSData1 (7-0) Register Description: SSIF1 Data Register Note: The SSData1 Register serves as Transmit Shift Register (TxBuffer1) during CPU write, or as Receive Shift Register (RxBuffer1) during CPU read. Reading the SSData1 Register will clear the SSInFull1 Interrupt bit. Writing to the SSData1 Register will reset the shift bit counter, overwrite the output register and initiate an 8 bit serial shift while in serial mode. A bit called SSSTATOut1 is added into the SSCmd1 register. The SSSTATOut1 value will be output to the SSSTAT1/GPIO[8] pin as the GPIO[8] data when the SSSTAT1/GPIO[8] pin is programmed as GPIO[8] through the GPIOConfig register. Address: SSCmd1 01FF8101 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 Default: SSSTATOut Rst. Value 1 xxxxxxx0b Read Value 00h Address: SSCmd1 01FF8100 Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 L2MSB1 Bit 3 Bit 2 Bit 1 SSCLKPol1 SSCLKPhas (Not Used) 1 Bit 0 Mode11 0 - Master 1 - Slave Default: Rst. Value xxx000x0b Read Value 00h Register Description: SSIF1 Command Register Bit 8: The SSSTATOut1 bit is used only when the SSSTAT1/GPIO[8] pin is programmed as GPIO[8] through the GPIOConfig register. The data value in the SSSTATOut1 bit is the GPIO[8] data value. L2MSB1, Read/Write bit. This bit controls the shifting order of the transmit and receive registers. When the L2MSB1 bit is cleared (default), the transmit and receive shift register will shift from the MSB to the LSB. When the L2MSB1 bit is set, the transmit and receive register will shift from the LSB to MSB. Bit 4: 19-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Bit 3: SSCLKPol 1, Read/Write bit. This bit controls the polarity of the SSCLK1 pin. The default value is zero. When the SSMode1 is configured at the IOMode1, the SSCLKPol1 bit will not affect the SSCLK1 pin value. The default value is zero. Description (used for both master and slave modes) Bit 2: SSCLKPhas1, Read/Write bit. SSCLKPhas1 0 1 0 1 SSCLKPol1 0 0 1 1 Enable the external logic to clock the SSTXD1 pin on the rising edge of the SSCLK1 pin. The SSCLK1 pin's first transition will be in the middle of the first bit. Enable the external logic to clock the SSTXD1 pin on the falling edge of the SSCLK1 pin. The SSCLK1 pin's first transition will occur at the beginning of the first bit. Enable the external logic to clock the SSTXD1 pin on the falling edge of the SSCLK1 pin. The SSCLK1 pin's first transition will be in the middle of the first bit. Enable the external logic to clock the SSTXD1 pin on the rising edge of the SSCLK1 pin. The SSCLK1 pin's first transition will occur at the beginning of the first bit. SSCLK1 (SSCLKPol1=0, SSCLKPhas1=0) SSCLK1 (SSCLKPol1=0, SSCLKPhas1=1) SSCLK1 (SSCLKPol1=1, SSCLKPhas1=0) SSCLK1 (SSCLKPol1=1, SSCLKPhas1=1) SSTXD1 Internal strobe for data capture(all modes) MSB 6 5 4 3 2 1 LSB Figure 19-2. SSCLK1 Diagram Note: SSCLK1 is used to synchronize the movement of data both in and out of device through SSRXD1 and SSTXD1 pins. The master and slave devices are capable of exchanging a data byte of information during a sequence of eight clock pulses. Both master and slave devices must be operated in the same timing mode as controlled by SSCLKPol1 and SSCLKPhas1 signals. Bit 0: Mode11, Read/Write bit. This bit controls the SSIF1 master/slave modes. 0: Master (default) 1: Slave When in the Master Mode, the SSCLK1 pin is configured as an output pin. When in the Slave Mode, SSCLK1 signal is an input to the SSIF1. 100723A Conexant 19-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: SSDiv1 01FF8105 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 Default: (Not Used) Rst. Value xxh Read Value 00h Bit 0 Default: Rst. Value 0xxx0000b Read Value 00h Address: SSDiv1 01FF8104 Bit 7 SSInFull1 Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 Bit 2 Bit 1 SSCLK1 Divisor Register Description: This register controls the bits of the SSCLK1 Divisor. Bit 7: SSInFull1, Read bit. This bit indicates the status of the input register. 0: Empty (default) 1: Full This bit allows the Firmware to poll the status of the serial interface when the use of the interrupt is not desired and is cleared by reading the in SSIF1 Data Register. SSInFull1 is active on the falling edge of AUXCLK1 and is used by Interrupt controller where it masked. Bit 6-4: Bit 3-0: Not used DivReg (Divisor Register), Read/Write bits. The Div Register is the SSCLK1 Divisor Register, which defines the SSCLK1 frequency. Writing the DivReg register will cause the SSIF1 logic to load the internal counter. Firmware can transmit data with the right speed immediately after the SSCLK1 setup. The SSCLK1 Divisor Register defines the SSCLK1 frequency, which depends on the AUXCLK frequency. The SSCLK1 Divisor Register is a five bit register. The SSCLK1 frequency (fSCK)and Divisor relationship is: FSCK = AUXCLK 2 * ( Divisor + 1) 19-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 19.2.2 The 2nd SSIF (SSIF2) Address: SSData2 01FF810B Bit 15 (Not Used) Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: Rst. Value xxh Read Value 00h Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: Rst. Value xxh Read Value xxh Address: SSData2 01FF810A Bit 7 SSData2 (7-0) Register Description: SSIF2 Data Register Note: The SSData2 Register serves as Transmit Shift Register (TxBuffer2) during CPU write, or as Receive Shift Register (RxBuffer2) during CPU read. Reading the SSData2 Register will clear the SSInFull2 Interrupt bit. Writing to the SSData2 Register will reset the shift bit counter, overwrite the output register and initiate an 8 bit serial shift while in serial mode. A bit called SSSTATOut2 is added into the SSCmd2 register. The SSSTATOut2 value will be output to the SSSTAT2/AO[2]/GPO[15] pin as the GPO[15] data when the SSSTAT2/GPO[15] pin is programmed as GPO[15]. Address: SSCmd2 01FF8109 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Address: SSCmd2 01FF8108 Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 L2MSB2 Bit 3 Bit 2 Bit 1 SSCLKPol2 SSCLKPhas (Not Used) 2 Bit 8 Default: SSSTATOut Rst. Value 2 xxxxxxx0b Read Value 00h Bit 0 Default: Rst. Value Mode12 xxx000x0b 0 - Master Read 1 - Slave Value 00h Register Description: SSIF2 Command Register Bit 8: The SSSTATOut2 bit is used only when the SSSTAT2/AO[2]/GPO[15] pin is programmed as GPO[15]. The data value in the SSSTATOut2 bit is the GPO[15] data value. L2MSB2, Read/Write bit. This bit controls the shifting order of the transmit and receive registers. When the L2MSB2 bit is cleared (default), the transmit and receive shift register will shift from the MSB to the LSB. When the L2MSB2 bit is set, the transmit and receive register will shift from the LSB to MSB. This bit controls the polarity of the SSCLK2 pin. The default value is zero. When the SSMode2 is configured at the IOMode2, the SSCLKPol2 bit will not affect the SSCLK2 pin value. The default value is zero. Bit 4: Bit 3: SSCLKPol2, Read/Write bit. Bit 2: SSCLKPhas2, Read/Write bit. 100723A Conexant 19-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description SSCLKPol2 0 0 1 1 SSCLKPhas2 0 1 0 1 Description (used for both master and slave modes) Enable the external logic to clock the SSTXD2 pin on the rising edge of the SSCLK2 pin. The SSCLK2 pin's first transition will be in the middle of the first bit. Enable the external logic to clock the SSTXD2 pin on the falling edge of the SSCLK2 pin. The SSCLK2 pin's first transition will occur at the beginning of the first bit. Enable the external logic to clock the SSTXD2 pin on the falling edge of the SSCLK2 pin. The SSCLK2 pin's first transition will be in the middle of the first bit. Enable the external logic to clock the SSTXD2 pin on the rising edge of the SSCLK2 pin. The SSCLK2 pin's first transition will occur at the beginning of the first bit. SSCLK2 (SSCLKPol2=0, SSCLKPhas2=0) SSCLK2 (SSCLKPol2=0, SSCLKPhas2=1) SSCLK2 (SSCLKPol2=1, SSCLKPhas2=0) SSCLK2 (SSCLKPol2=1, SSCLKPhas2=1) SSTXD2 Internal strobe for data capture(all modes) MSB 6 5 4 3 2 1 LSB Figure 19-3. SSCLK2 Diagram Note: SSCLK2 is used to synchronize the movement of data both in and out of device through SSRXD2 and SSTXD2 pins. The master and slave devices are capable of exchanging a data byte of information during a sequence of eight clock pulses. Both master and slave devices must be operated in the same timing mode as controlled by SSCLKPol2 and SSCLKPhas2 signals. Bit 0: Mode12, Read/Write bit. This bit controls the SSIF2 master/slave modes. 0: Master (default) 1: Slave When in the Master Mode, the SSCLK2 pin is configured as an output pin. When in the Slave Mode, SSCLK2 signal is an input to the SSIF2. 19-6 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: SSDiv2 01FF810D Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 Default: (Not Used) Rst. Value xxh Read Value 00h Bit 0 Default: Rst. Value 0xxx0000b Read Value 00h Address: SSDiv2 01FF810C Bit 7 SSInFull2 Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 Bit 2 Bit 1 SSCLK2 Divisor Register Description: This register controls the bits of the SSCLK2 Divisor. Bit 7: SSInFull2, Read bit. This bit indicates the status of the input register. 0: Empty (default) 1: Full This bit allows the Firmware to poll the status of the serial interface when the use of the interrupt is not desired and is cleared by reading the in SSIF2 Data Register. SSInFull2 is active on the falling edge of AUXCLK and is used by Interrupt controller where it masked. Bit 6-4: Bit 3-0: Not used DivReg (Divisor Register), Read/Write bits. The Div Register is the SSCLK2 Divisor Register, which defines the SSCLK frequency. Writing the DivReg register will cause the SSIF logic to load the internal counter. Firmware can transmit data with the right speed immediately after the SSCLK2 setup. The SSCLK2 Divisor Register defines the SSCLK2 frequency, which depends on the AUXCLK frequency. The SSCLK2 Divisor Register is a 5-bit register. The SSCLK2 frequency (fSCK)and Divisor relationship is: TO BE ADDED 19.3 SSIF Timing 19.3.1 SSCLK Timing When SSCLK is on (Figure 19-4), the duty cycle of SSCLK is always 50%. The SSCLK polarity is controlled by the SSIF Command Register SSCLKPol Bit. When the SSCLKPol bit and the phase control is cleared (default), the SSTXD signal transition is on the SSCLK falling edge. External logic can latch the SSTXD signal on the SSCLK rising edge. When the SSCLKPol bit is set, the SSTXD signal transition is on the rising edge of the SSCLK. External logic can latch the SSTXD signal on the SSCLK falling edge. For each write to the empty SSIF Data Register, the SSCLK will be active for eight cycles. When there is no data on the SSTXD pin, the SSCLK will stay in idle state, (logic zero when SSCLKPol bit is clear, and logic one when the SSCLKPol bit is set). 100723A Conexant 19-7 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 19.3.2 Request/Acknowledge Timing Request/Acknowledge handshaking may be used while the SSIF is operating in the slave mode. While in this mode the peripheral (master) may initiate a data transfer by driving the SSACK signal low. The SSACK signal from the external peripheral is connected to any GPIO pin (used as GPI). Firmware will in turn write SSTXD data to the data register. This will cause the SSIF hardware to drive the SSREQ(SSSTAT) signal low. Once the SSREQ is low the peripheral may start the SSCLK to transfer the data. Upon completion of the 8 bit transfer, the peripheral must drive the SSACK high. The IFC will then read the serial data out of the input register which will in turn drive the SSREQ high and complete the transfer. If the IFC wishes to initiate a transfer in this mode it must write to the SSIF output register which will in turn set the SSREQ low. The peripheral must then provide 8 clocks on the SSCLK line to receive the data from the MFC2000's SSIF. P reip h er al In itiated Tran sfer Tr an sfer C om p lete A M F P C In itiate s Tran sfer S SA C K n S SR E Q n 1 7 8 1 S S C LK S er ial in F u ll R ead W r ite Figure 19-4. Timing Diagram 19-8 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 20. Programmable Tone Generators 20.1 Introduction The AMFPC provides three programmable clock generator outputs. Two of the generators are to be used as tone generators and the third as a bell or ring driver. 20.2 Bell/Ringer Generator The frequency of this bell/ringer generator is programmable, ranging from 500 Hz to 15.6 Hz. This frequency is derived from the AMFPC's internal 125s period Clock, and it is calculated based on the following formula: OutputFrequency = 1 , where BellPeriod is ranging from 0 to 31. 125s x ( BellPeriod + 1) x 16 Each bell/ringer period is divided into 16 phases, as shown in the following figure. The phase number may be used by the firmware to determine when to turn off bell signal. period 50% x period 50% x period Phase: 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 F E Hi-Z Bell Mode: Hi-Z Hi-Z Ringer Mode: Modulated by ALTTone Generator Figure 20-1. Bell/Ringer Timing The mode of operation for this bell/ringer generator is selected by RingerEnb bit in BellControl register. Figure 20-2 shows the block diagram of this bell/ringer generator. Table 20-1shows the relationship between BellPeriod value and output frequency. 100723A Conexant 20-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description D [3 :0] 12 5 sC lk resn A [3 :0 ] B ell/R in g er B ell P h a se L o g ic C S ,R /W A d dre ss D eco d er D [4 :0 ] B ellP eriod R eg D [3 :0 ] B ellCtrl R eg A L T To n e A L T T on eE n b T o A L T T on eG en fr om A L T T on e G en Figure 20-2. Bell/Ringer Block Diagram Table 20-1. Bell/Ringer Setting BellPeriod+1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Bell/Ringer Freq(Hz) 500 250 166.7 125 100 83.3 71.4 62.5 55.6 50 45.5 41.7 38.5 35.7 33.3 31.2 BellPeriod+1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Bell/Ringer Freq(Hz) 29.4 27.8 26.3 25 23.8 22.7 21.7 20.8 20 19.2 18.5 17.9 17.2 16.7 16.1 15.6 20-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 20.2.1 Bell Mode Firmware operation The firmware needs to control Bell/Ringer generator to issue the following waveform: ~ 1s B ell H i-Z ... ~ 2s Q u iet Hi-Z ~ 1s B ell ... In order to setup for Bell mode, the following steps must be taken. Initialize: 1. Write the desired frequency of bell in BellPeriod register (see Table 20-1) 2. Allow Hi-Z on output (BellDriveEnb = 0) 3. Disable ringer mode (RingerEnb = 0) Start bell signal: 1. Enable Bell generator (BellEnb = 1) 2. (This setting will start the counter to run) Create "Bell-Quiet-Bell" signal: 1. Once the bell signal has been generated, the firmware will read BellPeriod register. On every Phase A or 9, the off-hook signal is checked. If it is detected, then the bell signal is disabled by having BellEnb = 0. This will ensure the bell signal is terminated on the high to high-Z transition. 2. If after about 1s, the off-hook signal is not detected, then the firmware will disable the bell signal by having BellEnb = 0 when the phase is on 9. When BellEnb is reset to 0, then the bell signal will stop at the Hi-Z, and the phase will be in zero. After about 2 s of quiet, the bell signal can be activated again by setting BellEnb to 1. 20.2.2 Ringer Mode The Ringer mode of operation requires the use of both the Bell/Ringer generator as well as the ALTTone generator. The fundamental frequency of this ringer signal is the same as the bell signal. The ringer signal works in conjunction with the ALTTone Generator to modulated it's output. The active window for the ring pulses (bell period high), will automatically shift so that the modulating waveform is not truncated at the beginning or end. Note: The firmware needs to control Bell/Ringer generator to issue the following waveformn: ~ 1s R in g ~ 2s Q u iet ~ 1s R in g ... Figure 20-3. Bell/Ringer Generator Waveform ... 100723A Conexant 20-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description To setup for Ringer mode, the following steps must be taken: Initialize: 1. 2. 3. 4. 5. Write the desired frequency of bell in BellPeriod register (see Table 20-1) Enable output drive (BellDriveEnb = 1, will over-ride Hi Z control) Enable ringer mode (RingerEnb = 1) Write the desired frequency of tone1 in ALTToneGen register If ALTTone signal is not desired on the ALTTone pin, then disable ALTTone signal to the pin (ALTToneEnb = 0). Note: ALTToneEnb is only to enable the ALTTone signal to the ALTTone pin. If ALTToneEnb = 0, ALTTone signal will be blocked to ALTTone pin, but ALTTone signal is still available to Bell/Ringer generator for modulation purpose. Start ringer signal: 1. Enable Bell generator (BellEnb = 1) 2. (This setting will start the counter to run) Create "Ring-Quiet-Ring" signal: 1. The firmware can generate the signal by switching the BellEnb setting. 20.2.3 Registers Description The following is a description of the registers used to control the Bell/Ringer Function. Address: BellPeriod 01FF80B7 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Rst. Value xxx00000b Read Value 00h Address: BellPeriod 01FF80B6 Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bell Period (0 - 31), bell period = (BellPeriod+1)*2ms Register Description: Bell Period Register Bit 15-5: Bit 4-0: Not Used Writing to this register will set the Bell Period. Reading this register will return that value. 20-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: BellPhase 01FF80B9 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 Default: (Not Used) Rst. Value xxh Read Value 00h Bit 0 Default: Rst. Value xxxx0000b Read Value 00h Address: BellPhase 01FF80B8 (R ) Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 Bell Phase Bit 2 Bit 1 Register Description: Bell Phase Register Bit 15-4: Bit 3-0: Not Used Read only register returns current phase of the bell signal. Address: BellCtrl 01FF80B5 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Rst. Value xxxx0000b Read Value 00h Address: BellCtrl 01FF80B4 Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 Bit 2 Bit 1 Bit 0 ModToneEn RingerEnb b 1=Ring 1 = Enabled Mode 0=Bell Mode BellDrvEnb BellEnb 1 = Enabled 1 = Enabled 0 = Allow Hi Z out Register Description: Bell Control Register Bit 15-4: Bit 3: Bit 2: Bit 1: Not Used Enables the ALTTone output to external pin but has no effect on the Ringer Mode. If this signal is set to 0 the ALTTone output will be at 0. Sets the generator into Bell Mode or Ringer Mode (Ringer Mode overrides bit 1 and does not allow the tristate condition.) In Bell Mode, it Controls weighter the output pin is always driven or tristated during bell phases 0, F, 8, and 7. Enables the Bell/Ringer counters to run. When this bit is set to 0, the counters are held at the start of phase "F". Note: After reset the Bell/Ringer pin will be tristated with the counters held at bell phase "0". Bit 0: 100723A Conexant 20-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 20.3 Tone Generator There are two tone generators which can be operated independently, namely ALTTone and Tone. ALTTone can be used alone or with the bell/ringer generator for modulation purpose. The duty cycle of the tone signal is 50%. Frequency modulation on the tone signal can be controlled by the firmware. While the tone generator is running, the firmware may write a new value to the frequency register which will take effect on the start of the next tone cycle. The tone signal is guaranteed to have a smooth transition to the new frequency Figure 20-4 shows an example of increasing frequency with smooth transition on the tone signal. G litch free T o ne: 255 C o unter O u tp u t: 1 w ritin g a n ew valu e to T on e G en reg ister Figure 20-4. Tone Generator Frequency Change 20.3.1 Tone/AltTone The signal generator called Tone, has the ability to generate a dual-tone output. The output frequency switch time and total cycle time are both programmable from 0 to 104.8mS with a step resolution of 102.4uS. Figure 1-5 is a block diagram of the Tone signal generator. Frequency Register 1 and 2 hold the value of the two alternating frequencies. Switch time specifies the time at which the output frequency stitches from Freq1 to Freq2. The total time register sets the total time of the repeating pattern. Figure 1-6 shows the timing diagram of when the output frequency counter switches between Freq1 and Freq2. Figure 1-7 depicts a waveform of a dual-tone output pattern showing what settings effect what portion of the output. Figure 1-8 is a block diagram of the AltTone frequency generator. 6.4uS Frequency Counter PSF Div 8 Frequency Register1 10 Bits 10 Bits Frequency Register 2 10 Bits 10 ICLK/8 102.4uS IPB_DI Switch Time Register Sw Time Cnter 0 - 104.8mS 10 Bits Select Carry Out Freq Out Div 2 Reset Total Time Register PST Div 16 Tot Time Cnter 0 - 104.8mS 10 Bits Figure 20-5. Dual-Tone Tone Generator Block Diagram 20-6 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Dual-Tone Out Counter Load Counter Use Freq 2 Figure 20-6. Dual-Tone Tone Generator Counter Operation Frequency 1 Frequency 2 Switch Time Total Time Figure 20-7. Dual-Tone Tone Generator output To Bell/Ringer Generator From BellCtrl Register AltTone Enb ICLK/8 PSF Div 8 AltTone Frequency AltTone Figure 20-8. AltTone Generator Block Diagram 100723A Conexant 20-7 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description The frequency of the tone generators can be set according to the following formula: ToneFrequency = AUXCLK ( ToneGenValue) * 8 * 8 * 2 Note: ToneGenValue is the value in ALTToneGen or ToneGen Freq1 and Freq2 registers. When ToneGenValue is zero, then the tone generator is disabled, and the output is low. 20.3.2 Registers Description Address: ALTToneGen 01FF80B3 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 Bit 8 Default: Rst. Value xxxxxx00b Read Value 00h Default: Rst. Value 00h Read Value 00h ALTTone Frequency Register Address: ALTToneGen 01FF80B2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ALTTone Frequency Register Register Description: ALTTone Generator Register. Read/Write register sets the frequency of ModTone. Bit 9-0: ALTTone frequency Note: When ALTToneGen = 0, then ALTTone is disabled and the ALTTone output to pin is 0. Address: ToneGenF1 01FF80B1 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 Bit 9 Bit 8 Default: Rst. Value xxxxxx00b Read Value 00h Default: Rst. Value 00h Read Value 00h (Not Used) Tone Frequency 1 Register Address: ToneGenF1 01FF80B0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Tone Frequency 1 Register Register Description: Tone Generator Register. Read/Write register sets the frequency of Tone Frequency 1. Bit 9-0: Tone frequency 1 Note: When Tone = 0, then tone is disabled and the tone output to pin is 0. 20-8 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: ToneGenF2 01FF80BB Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 Bit 8 Default: Rst. Value xxxxxx00b Read Value 00h Default: Rst. Value 00h Read Value 00h Tone Frequency 2 Register Address: ToneGenF2 01FF80BA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Tone Frequency 2 Register Register Description: Tone Generator Register. Read/Write register sets the frequency of Tone Frequency 2. Bit 9-0: Tone frequency 2 Note: When Tone = 0, then tone is disabled and the tone output to pin is 0. Address: ToneGenSwitch 01FF80BD Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 Bit 8 Default: Rst. Value xxxxxx00b Read Value 00h Default: Rst. Value 00h Read Value 00h Tone Frequency Switch Time Address: ToneGenSwitch 01FF80BC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Tone Frequency Switch Time Register Description: Tone Generator Frequency Switch Register. Read/Write register sets the time of Frequency 1 duration. Bit 9-0: Tone Frequency Switch Time (0 to 104.8 mS in 102.4 uS steps) If this register is set to 000h, the output frequency will = Freq2 for the Total Time. If the register value is >= the Total Time, the output frequency will = Freq1 for the Total Time. 100723A Conexant 20-9 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: ToneGenTotal 01FF80BF Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 Bit 8 Default: Rst. Value xxxxxx00b Read Value 00h Default: Rst. Value 00h Read Value 00h Tone Frequency Total Time Address: ToneGenTotal 01FF80BE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Tone Frequency Total Time Register Description: Tone Generator Total Time Register. Read/Write register sets the time of Frequency 1 plus Frequency 2 duration. When set to 000'h, The tone output will remain low or will be held low once the output switches to it's low state, and all counters will be held in reset (000'h). When this register is set to a non zero value, the counters will be released alowing generation of the tone signal. The the end of the total time will not take effect until the output of the tone is low, preventing truncation of the ouput signal when high. Bit 9-0: Tone Frequency Total Time (0 to 104.8 mS in 102.4 uS steps) 20-10 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 21. Pwm Logic 21.1 Functional Description There are five PWM channels, each channel having separate logic and control. PWM channel 0 outputs from the GPIO[11]/CPCIN pin. There is a PWMCh0 select bit in the PWMCh0Duty Register. The PWMCh0 select bit goes to the GPIO block where the signal selection and the prioritization for the GPIO[11]/CPCIN/PWM0 pin is done. PWM channel 1 and PWM channel 2 share pins with FCS[0]n and FCS[1]n. There is a PWMCh1 select bit in the PWMCh1Duty Register. There is a PWMCh2 select bit in the PWMCh2Duty Register. PWM channel 3 shares the pin with GPIO[5]/CS[3]n. There is a PWMCh3 select bit in the PWMCh3Duty Register. The PWMCh3 select bit goes to the GPIO block where the signal selection and the prioritization for the GPIO[5]/CS[3]n/PWM3 pin is done. PWM channel 4 shares the pin with GPIO[10]/P80_PB3. There is a PWMCh4 select bit in the PWMCh4Duty Register. The PWMCh4 select bit goes to the GPIO block. The GPIO logic does the signal selection and the prioritization for the GPIO[10]/P80_PB3/PWM4 pin. The PWM function requirements are as follows. * * * Signal frequency range " AUXCLK/256 or AUXCLK/(2*256) Duty cycle " high level: 1/256 to 256/256 8-bit counter for duty cycle programmability 100723A Conexant 21-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 21.2 Register Description Name/Address PWM Channel 0 Control (PWMCh0Ctrl) 01FF80C1h Bit 15 ALTTONE/ PWMCh0 Output Select 0=ALTTONE 1=PWMCh0 Bit 7 Bit 7 of PWMCh0 Duty Cycle Control Bit 14 (not used) Bit 13 (not used) Bit 12 (not used) Bit 11 (not used) Bit 10 (not used) Bit 9 (not used) Bit 8 Default PWMCh0 Rst. Value Clock 0xxxxxx0b Divider Read Value 0xxxxxx0b Name/Address PWM Channel 0 Control (PWMCh0Ctrl) 01FF80C0h Bit 6 Bit 6 of PWMCh0 Duty Cycle Control Bit 5 Bit 5 of PWMCh0 Duty Cycle Control Bit 4 Bit 4 of PWMCh0 Duty Cycle Control Bit 3 Bit 3 of PWMCh0 Duty Cycle Control Bit 2 Bit 2 of PWMCh0 Duty Cycle Control Bit 1 Bit 1 of PWMCh0 Duty Cycle Control Bit 0 Bit 0 of PWMCh0 Duty Cycle Control Default Rst. Value 00h Read Value 00h Bit 15 Controls which signal is output to the GPIO[11]/CPCIN/GPIO[11] pin (PWM channel 0 output signal, CPCIN input signal, or GPIO input/output signal). Bit 8/GPIOConfig1 Register 0 0 1 1 Bit 15/PWMCh0Ctrl Register 0 1 0 1 GPIO[11]/CPCIN/PWM0 Pin GPIO[11] GPIO[11] CPCIN PWM0 Bit 8 PWMCh0 clock divider (n = 0-1) PWMCh0 clock = AUXCLK (n + 1) Bits 7-0 Duty cycle control (n = 0 - 255) PWMCh0 signal frequency = PWMCh0clock 256 n +1 * PWMCh0 signal cycle time 256 256 - (n + 1) * PWMCh0 signal 256 PWMCh0 signal `high' period = PWMCh0 signal `low' period = cycle time 21-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Name/Address PWM Channel 1 Control (PWMCh1Ctrl) 01FF80C3h Name/Address PWM Channel 1 Control (PWMCh1Ctrl) 01FF80C2h Bit 15 PWMCh1 Output Select Bit 14 (not used) Bit 13 (not used) Bit 12 (not used) Bit 11 (not used) Bit 10 (not used) Bit 9 (not used) Bit 8 Default PWMCh1 Rst. Value Clock 0xxxxxx0b Divider Read Value 0xxxxxx0b Bit 0 Bit 0 of PWMCh1 Duty Cycle Control Default Rst. Value 00h Read Value 00h Bit 7 Bit 7 of PWMCh1 Duty Cycle Control Bit 6 Bit 6 of PWMCh1 Duty Cycle Control Bit 5 Bit 5 of PWMCh1 Duty Cycle Control Bit 4 Bit 4 of PWMCh1 Duty Cycle Control Bit 3 Bit 3 of PWMCh1 Duty Cycle Control Bit 2 Bit 2 of PWMCh1 Duty Cycle Control Bit 1 Bit 1 of PWMCh1 Duty Cycle Control Bit 15 Controls which signal is output to the FCS[0]n pin (PWM channel 1 output signal or the other output signal). Bit 8/FlashCtrl Register 0 0 1 1 Bit 15/PWMCh1Ctrl Register 0 1 0 1 FCS[0]n/PWM1 Pin FCS[0] FCS[0] FCS[0] for NAND-type Flash Mem PWM1 Bit 8 PWMCh1 clock divider (n = 0-1) PWMCh1 clock = AUXCLK (n + 1) Bits 7-0 Duty cycle control (n = 0 - 255) PWMCh1 signal frequency = PWMCh1clock 256 n +1 * PWMCh1 signal cycle time 256 256 - (n + 1) * PWMCh1 signal 256 PWMCh1 signal `high' period = PWMCh1 signal `low' period = cycle time 100723A Conexant 21-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Name/Address PWM Channel 2 Control (PWMCh2Ctrl) 01FF80C5h Name/Address PWM Channel 2 Control (PWMCh2Ctrl) 01FF80C4h Bit 15 PWMCh2 Output Select Bit 14 (not used) Bit 13 (not used) Bit 12 (not used) Bit 11 (not used) Bit 10 (not used) Bit 9 (not used) Bit 8 Default PWMCh2 Rst. Value Clock 0xxxxxx0b Divider Read Value 0xxxxxx0b Bit 0 Bit 0 of PWMCh2 Duty Cycle Control Default Rst. Value 00h Read Value 00h Bit 7 Bit 7 of PWMCh2 Duty Cycle Control Bit 6 Bit 6 of PWMCh2 Duty Cycle Control Bit 5 Bit 5 of PWMCh2 Duty Cycle Control Bit 4 Bit 4 of PWMCh2 Duty Cycle Control Bit 3 Bit 3 of PWMCh2 Duty Cycle Control Bit 2 Bit 2 of PWMCh2 Duty Cycle Control Bit 1 Bit 1 of PWMCh2 Duty Cycle Control Bit 15 Controls which signal is output to the FCS[1]n pin (PWM channel 2 output signal or the other output signal). Bit 9/FlashCtrl Register 0 0 1 1 Bit 15/PWMCh2Ctrl Register 0 1 0 1 FCS[1]n/PWM2 Pin FCS[1] FCS[1] FCS[1] for NAND-type Flash Mem PWM2 Bit 8 PWMCh2 clock divider (n = 0-1) PWMCh2 clock = AUXCLK (n + 1) Bits 7-0 Duty cycle control (n = 0 - 255) PWMCh2 signal frequency = PWMCh2clock 256 n +1 * PWMCh2 signal cycle time 256 256 - (n + 1) * PWMCh2 signal 256 PWMCh2 signal `high' period = PWMCh2 signal `low' period = cycle time 21-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Name/Address PWM Channel 3 Control (PWMCh3Ctrl) 01FF80C7h Name/Address PWM Channel 3 Control (PWMCh3Ctrl) 01FF80C6h Bit 15 PWMCh3 Output Select Bit 14 (not used) Bit 13 (not used) Bit 12 (not used) Bit 11 (not used) Bit 10 (not used) Bit 9 (not used) Bit 8 Default PWMCh3 Rst. Value Clock 0xxxxxx0b Divider Read Value 0xxxxxx0b Bit 0 Bit 0 of PWMCh3 Duty Cycle Control Default Rst. Value 00h Read Value 00h Bit 7 Bit 7 of PWMCh3 Duty Cycle Control Bit 6 Bit 6 of PWMCh3 Duty Cycle Control Bit 5 Bit 5 of PWMCh3 Duty Cycle Control Bit 4 Bit 4 of PWMCh3 Duty Cycle Control Bit 3 Bit 3 of PWMCh3 Duty Cycle Control Bit 2 Bit 2 of PWMCh3 Duty Cycle Control Bit 1 Bit 1 of PWMCh3 Duty Cycle Control Bit 15 Controls which signal is output to the GPIO[5] pin (PWM channel 3 output signal or the other output signal). Bit 4/GPIOConfig1 Register 0 0 1 1 Bit 15/PWMCh3Ctrl Register 0 1 0 1 GPIO[5]/CS[3]n/PWM3 Pin GPIO[5] GPIO[5] CS[3]n PWM3 Bit 8 PWMCh3 clock divider (n = 0-1) PWMCh3 clock = AUXCLK (n + 1) Bits 7-0 Duty cycle control (n = 0 - 255) PWMCh3 signal frequency = PWMCh3clock 256 n +1 * PWMCh3 signal cycle time 256 256 - (n + 1) * PWMCh3 signal 256 PWMCh3 signal `high' period = PWMCh3 signal `low' period = cycle time 100723A Conexant 21-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Name/Address PWM Channel 4 Control (PWMCh4Ctrl) 01FF80C9h Name/Address PWM Channel 4 Control (PWMCh4Ctrl) 01FF80C8h Bit 15 PWMCh4 Output Select Bit 14 (not used) Bit 13 (not used) Bit 12 (not used) Bit 11 (not used) Bit 10 (not used) Bit 9 (not used) Bit 8 Default PWMCh4 Rst. Value Clock 0xxxxxx0b Divider Read Value 0xxxxxx0b Bit 0 Bit 0 of PWMCh4 Duty Cycle Control Default Rst. Value 00h Read Value 00h Bit 7 Bit 7 of PWMCh4 Duty Cycle Control Bit 6 Bit 6 of PWMCh4 Duty Cycle Control Bit 5 Bit 5 of PWMCh4 Duty Cycle Control Bit 4 Bit 4 of PWMCh4 Duty Cycle Control Bit 3 Bit 3 of PWMCh4 Duty Cycle Control Bit 2 Bit 2 of PWMCh4 Duty Cycle Control Bit 1 Bit 1 of PWMCh4 Duty Cycle Control Bit 15 Controls which signal is output to the GPIO[10] pin (PWM channel 4 output signal or the other output signal). Bit 7/GPIOConfig1 Register 0 0 1 1 Bit 15/PWMCh4Ctrl Register 0 1 0 1 GPIO[10]/P80_PB3/PWM4 Pin GPIO[10] GPIO[10] P80_PB3 PWM4 Bit 8 PWMCh4 clock divider (n = 0-1) PWMCh4 clock = AUXCLK (n + 1) Bits 7-0 Duty cycle control (n = 0 - 255) PWMCh4 signal frequency = PWMCh 4clock 256 n +1 * PWMCh4 signal cycle time 256 256 - (n + 1) * PWMCh4 signal 256 PWMCh4 signal `high' period = PWMCh4 signal `low' period = cycle time 21-6 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 22. Calling Party Control (CPC) In some countries, after the called party is on hook, a pulse is sent to the caller party by stopping the line current of the caller party for a short time to indicate that the called party is on hook, as seen in Figure 22-1. The duration of this pulse varies widely for different countries. The purpose of having Calling Party Control (CPC) circuit is to detect the on-hook signal by sampling CPC signal. . O ff-H ook C aller P arty C alled P arty L in e C u rr en t (o f C aller P arty ) O n -H o ok O ff-H ook O n -H o ok O n -H o ok S ign al C P C S ign al . Figure 22-1: CPC Signal Firmware Note: In order to setup CPC circuit, the following initialization procedure must be done in the given order after both parties are off hook: 1. Write the desired threshold in CPCThreshold register 2. Select the sampling period in CPCStatCtrl register (This will clear the CPCflag and reset CPC counter to zero) Once CPC has been set up, the firmware can periodically check CPCflag by reading CPCStatCtrl register. 100723A Conexant 22-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Tthe following flowchart illustrates the CPC operation: C hec k C P C signal on ev e ry sa m pling c lock C P C signal lev el ? Increm en t c ounter F la g ? F lag ? Is there write sig nal to CP CStatCtrl ? C om pare count v alu e with thresh old F lag = L ow R eset co unter C ou nt = threshold ? F lag = H ig h Figure 22-2. CPC Operation Flowchart 22-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Figure 22-3 illustrates an example of the CPC operation with CPCThreshold containing a value of 4. T h is n oise w ill b e filtered ou t. F a ls e O n -H o o k S ig n a l C PC sign al Sam p lin g C PC C PC cou n t C ou n tE Q T h r C PC Flag C PC S tatC trlR D n C PC S tatC trlW R n 1 0 1 2 0 2 1 2 3 3 4 4 0 Figure 22-3: CPC Operation (with CPCThreshold = 4) Note: 1. Writing to CPCStatCtrl register will clear CPC Flag. 2. Whenever both CPC signal and CPC Flag are low, the counter is reset in order to restart the counting sequence. The previous counter value is regarded as the result from a noise signal. This condition is only checked at every sampling time. In other words, if it happens between the sampling time, then the noise will be filtered out. 3. As soon as the counter value is equal to the threshold value, CPC Flag is raised. 4. Once CPC Flag has been raised, the counter will be clear on the next sampling clock. Figure 22-4 illustrates the CPC block diagram. 100723A Conexant 22-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description C P C S ta tC trlR d n A [3 :0 ] C S ,R /W A d dre ss D ec ode r C PC StatC trl R eg ister C P C S ta tC trlW rn 1 25 sC lk C PC Th reshold R eg ister C lock D ivide r 8 -bit C ou n te r B A C om p ara tor A= B Figure 22-4: CPC Block Diagram C on trol L og ic C P C S ig n al 22-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 22.1 Registers Description Name/Address CPC Threshold (CPCThreshold) 01FF80A9 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default Rst Value xxh Read Value 00h Name/Address CPC Threshold (CPCThreshold) 01FF80A8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Rst Value FFh Read Value FFh (Not Used) CPC Threshold Bit 15-8 Bit 7-0 CPC Threshold Not Used Name/Address CPC Status & Control (CPCStatCtrl) 01FF80AB Name/Address CPC Status & Control (CPCStatCtrl) 01FF80AA Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default Rst Value xxh Read Value 00h Bit 7 CPC Flag (R) Bit 6 Bit 5 Bit 4 (Not Used) Bit 3 (Not Used) Bit 2 (Not Used) Bit 1 Bit 0 Default Rst Value xxxxxx11b Read Value 00000011b CPC Signal (Not Used) (R) Sampling Clock Select: 0: 125 s 1: 500 s 2: 2 ms 3: 8 ms Bit 15-8 Bit 7 Bit 6 Bit 5-2 Bit 1-0 Sampling Clock Selection CPC Flag CPC Signal Not Used Not Used 100723A Conexant 22-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description This page is intentionally blank 22-6 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 23. SSD_P80 23.1 Function Description A 56K/33.6K data/fax modem core is integrated into the MFC2000 chip. It is called the P80 core. Furthermore, Conexant's SmartDAA technology is put into the MFC2000 chip. The P80 core can be connected to the phone line through either the modem IA/traditional DAA or the SmartDAA System Side Device (SSD) logic/the SmartDAA Line Side Device (LSD). The SSD logic is integrated into the MFC2000 chip. The SSD_P80 block includes the SSD logic, P80 core, and interface logic to the internal ARM bus system. 23.1.1 System Configurations The SSD_P80 can be configured in the following ways. * * * Configuration one: data acquisition is done only via SSD. Configuration two: data acquisition is done via SSD and voice acquisition is done via External IA. Configuration three: data acquisition is done only via External IA. MFC2000 EXTERNAL SIU Interface P80 CORE IA interface m_strobe m_rxssd m_txssd m_clk LSD SSD LSD_REG. CONFIGURATION ONE Figure 23-1. System Configuration One 100723A Conexant 23-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description MFC2000 EXTERNAL P80 CORE SIU Interface IA interface External IA iaclk ia1clk m_control m_strobe m_tx m_rx CONFIGURATION TWO Figure 23-2. System Configuration Two MFC2000 P80 CORE Secondary IA interface EXTERNAL v_sclk SIU Interface v_ctrl v_strobe v_txsin v_rx External IA Primary IA interface m_strobe m_txssd m_rxssd m_clk LSD SSD LSD_REG. CONFIGURATION THREE Figure 23-3. System Configuration Three 23-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 23.2 Register Description Address: P80CONTROL Bit 15 (not used) Bit 14 (not used) Bit 13 (not used) Bit 12 (not used) Bit 11 (not used) Bit 10 (not used) Bit 9 (not used) Bit 8 (not used) Default: Rst Value xxh Read Value 00h Bit 7 (not used) Bit 6 SSD Ringwaken Bit 5 SSD Raw_ringn Bit 4 Ext Raw_ringn Bit 3 Ring_Sel[1:0] Bit 2 Bit 1 EXTIA_ MODE Bit 0 IA_SEL Default: Rst Value xxxx0000b Read Value 00h 0x01FF88E1 Address: P80CONTROL 0x01FF88E0 Bit 15:7 Bit 6 Bit 5 Bit 4 Bit 3:2 Not used This is read only bit which indicates status of ring envelope from SSD. This is a read only bit which indicates raw ring signals from SSD. This is a read only bit which indicates raw ring signals from external DAA. This control bits are used to select types of ring signals to be connected to P80_CORE to perform ring detection. "00" : No selection, logic `high' will be driven to PB[3]_C of P80_CORE. "01" : SSD Raw_ringn is selected. "10" : SSD Ringwaken is selected. "11" : External DAA Raw_ringn is selected. Bit 1 Bit 0 This bit controls muxing of output I/O pins. When asserted to high, selected P80 core pins will be directed to external pin. This bit controls muxing of primary and secondary I/O pins in P80 core. When asserted to high, secondary I/O will be selected. 100723A Conexant 23-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 23.2.1 SSD Registers Note: For detailed desciption on register contents, refer to SSD Spec. Table 23-1. SSD Registers Register Name SSD Register 00 SSD Register 01 SSD Register 02 SSD Register 03 SSD Register 04 SSD Register 05 SSD Register 06 SSD Register 07 SSD Register 08 SSD Register 09 SSD Register 0A SSD Register 0B SSD Register 0C SSD Register 0D SSD Register 0E SSD Register 0F SSD Register 10 SSD Register 11 SSD Register 12 SSD Register 13 SSD Register 14 SSD Register 15 SSD Register 16 SSD Register 17 SSD Register 18 SSD Register 19 SSD Register 1A SSD Register 1B SSD Register 1C MFC2K Address 00C30050 00C30052 00C30054 00C30056 00C30058 00C3005A 00C3005C 00C3005E 00C30060 00C30062 00C30064 00C30066 00C30068 00C3006A 00C3006C 00C3006E 00C30070 00C30072 00C30074 00C30076 00C30078 00C3007A 00C3007C 00C3007E 00C30080 00C30082 00C30084 00C30086 00C3008E 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 Bit Positions R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 # Bits 23-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 23.2.2 P80 CORE Registers Note: For detailed description on register contents, refer to FM336 hardware spec. Table 23-2. P80 CORE Registers Register Name P80 Register 00 P80 Register 01 P80 Register 02 P80 Register 03 P80 Register 04 P80 Register 05 P80 Register 06 P80 Register 07 P80 Register 08 P80 Register 09 P80 Register 0A P80 Register 0B P80 Register 0C P80 Register 0D P80 Register 0E P80 Register 0F P80 Register 10 P80 Register 11 P80 Register 12 P80 Register 13 P80 Register 14 P80 Register 15 P80 Register 16 P80 Register 17 P80 Register 18 P80 Register 19 P80 Register 1A P80 Register 1B P80 Register 1C P80 Register 1D P80 Register 1E P80 Register 1F MFC2K Address 00C30000 00C30002 00C30004 00C30006 00C30008 00C3000A 00C3000C 00C3000E 00C30010 00C30012 00C30014 00C30016 00C30018 00C3001A 00C3001C 00C3001E 00C30020 00C30022 00C30024 00C30026 00C30028 00C3002A 00C3002C 00C3002E 00C30030 00C30032 00C30034 00C30036 00C30038 00C3003A 00C3003C 00C3003E 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 Bit Positions R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 # Bits 100723A Conexant 23-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 23.3 Firmware Operation Note: ALL SSD and P80 CORE registers are 8-Bit registers. 23-6 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 24. Countach Imaging DSP Bus Subsystem The Countach Imaging DSP Bus Subsystem contains the Countach Imaging DSP subsystem for video/scan image signal processing and all peripherals/memory needed for the whole operations. The main memory for image data storage is the external DRAM/SDRAM. These peripherals are Countach Subsystem Interface, Scan IA, Video/Scan Controller, SDRAM Controller, Video/Scan Interface, ARM Bus Interface, CDMA Controller, and Countach Bus Unit. The Countach Imaging DSP subsystem should operate at 100 MHz or 85.7MHz. This is the separate bus system from the ARM bus system and runs in parallel with the ARM bus system to get maximum performance out of the MFC2000. ARM Bus Interface logic is the bridge between the ARM bus system and the Countach Imaging DSP Bus Subsystem. Both CPU access and DMA access mastered by the ARM side are supported to coordinate the entire system operation. Several blocks are used to complete the connection between these peripherals: 1. 2. 3. 4. ARM Bus Interfaceconnects the ARM subsystem to the internal busses. Countach Subsystem Interfaceconnects the Countach core to the internal busses. Sync. DRAM Controllerconnects the external DRAM/SDRAM to the internal busses. Video/Scan Interfaceconnects the Video/Scan Controller to the internal busses. Several blocks are used for internal functions: 1. Countach Bus Unitconnects all internal blocks in the Countach Bus Subsystem together. 2. Countach DMA Controllerpaces all DMA transaction between the Video/Scan Interface for video capture and scanner, ARM Bus Interface for ARM bus system, and the Countach Subsystem Interface for the Countach subsystem to and from the SDRAM. Several I/O accesses on the Countach Bus Subsystem are planned: 1. ARM accesses the scratch pad of the Countach subsystem through ARM Bus Interface, Countach Bus Unit, and Countach Subsystem IF. Note: ARM will be able to access all registers in the sub-block of the Countach Bus Subsystem through the IPB bus of the ARM bus system. The ARM must not access the scratchpad while DMA to or from the Countach Imaging DSP Subsystem is in progress. Failure to do so can result in corruption and/or loss of DMA data. The ARM may access the scratchpad during all other DMA transfers, including video/scanner data to SDRAM and SDRAM to and from ARM DRAM. 2. Put the DMA setting data to the Countach DMA Controller from the scratch pad of the Countach subsystem through Countach Bus Unit, and Countach Subsystem IF after the Countach Bus Unit is informed by the GPO signal from Countach Subsystem. Several DMA accesses on the Countach Bus Subsystem are planned: 1. The DMA operation to send video and scan image data to the external SDRAM/DRAM from the Video/Scan Controller through the Video/Scan Interface. 2. The DMA operation to send/receive data from/to memory on the ARM bus system through ARM Bus Interface. 3. The DMA operation to send/receive data from/to the scratch pad of the Countach subsystem through Countach Subsystem Interface. 100723A Conexant 24-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Countach Subsystem Scan Integrated Analog Scanner Countach Subsystem IF Video Capture Chip Video/ Scan Controller Video/ Scan IF Countach Bus Unit Video DMA Controller ARM Bus IF ARM Bus System Sync. DRAM Controller (S)DRAM device Figure 24-1. The ARM Bus System Block Diagram 24-2 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 24.1 Countach Imaging DSP Subsystem 24.1.1 Description The Countach Imaging DSP Subsystem is mainly responsible for monochrome and color image processing and JPEG compression and decompression. The Countach Imaging DSP subsystem contains the Countach core, data RAM and ROM, program RAM and program ROM, scratch pad, and DMA channels. 24.1.2 Countach Imaging DSP Subsystem Memory Program Memory: * * 2K x 40 RAM ROM for program initialization Data RAM: * * * * 1K x 16 register file RAM 4K x 16 DMA-accessible RAM 4K x 16 RAM 8K x 16 ROM 24.1.3 Countach Imaging DSP Subsystem DMA Data DMA: * * * * 4 channels DMA accesses are made via the scratch pad interface Countach Imaging DSP controls which bank DMA transfers occur in - DMA channel does not automatically switch after completion of a block transfer Consecutive DMA cycles must be able to occur at a minimum rate of 6 Countach clocks per transfer Program DMA: * * * * Minimum of 1 channel DMA accesses are made via the scratch pad interface Consecutive DMA cycles must be able to occur at a minimum rate of 6 Countach clocks per transfer An entire instruction is formed by transferring it in three 16-bit segments to scratch pad addresses 0x1b0, 0x1b1, and 0x1b2 24.1.4 Running Frequency The Countach Imaging DSP Subsystem operates at either 87.5MHz or 100 MHz. It is configurable through the CLK_CONFIG[2] signal which is muxed on the ROMCSn pin. 100723A Conexant 24-3 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 24.2 COUNTACH IMAGING DSP BUS UNIT 24.2.1 Function Description The Countach Bus Unit is the conduit for all data and address between the various block of the Countach Bus System. It also decides which blocks become master of these busses. There are four busses in the Countach Bus System: * * * * CPBaddress and data to and from the Countach Subsystem Interface DPBaddress and data to and from the Synchronous DRAM Interface IPBaddress and data to and from the ARM Bus Interface VPBdata from the Video/Scan Interface Because of these separate busses (as opposed to a single tri-state muxed bus), it is possible to have multiple bus masters. The possible connections between these busses are: * * * IPB CPB, VPB DPB: ARM Bus Interface makes discrete I/O accesses to Countach Subsystem scratch pad while Video/Scan Interface makes DMA accesses to Synchronous DRAM Interface. CPB DPB: Countach Subsystem Interface makes DMA accesses to Synchronous DRAM Interface. IPB DPB, {Countach DMA Controller} cpb: ARM Bus Interface makes either discrete I/O accesses or DMA accesses to Synchronous DRAM Interface while Countach DMA Controller fetches DMA parameters from Countach Subsystem scratch pad. 24.2.2 Register Description Address: Deferred Read High Address (DefRdHiAddr) $01FF82A9 Address: Deferred Read High Address (DefRdHiAddr) $01FF82A8 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Bit 7 (Not Used) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Deferred Deferred Deferred Deferred Deferred Deferred Deferred Rst Value Read Read Read Read Read Read Read x0000000b Address [22] Address [21] Address [20] Address [19] Address [18] Address [17] Address [16] Read Value 00h Bit 15-7 Bit 6-0 Not used Deferred Read Address [22:16] These seven bits, in conjunction with the sixteen bits of the Deferred Read Low Address register, make up the deferred read address. It is a halfword address, not a byte address. 24-4 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: Deferred Read Low Address (DefRdLoAddr) $01FF82AB Address: Deferred Read Low Address (DefRdLoAddr) $01FF82AA Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Deferred Read Address [8] Bit 0 Deferred Read Address [0] Default: Rst. Value 00h Read Value 00h Default: Rst Value 00h Read Value 00h Deferred Deferred Deferred Deferred Deferred Deferred Deferred Read Read Read Read Read Read Read Address [15] Address [14] Address [13] Address [12] Address [11] Address [10] Address [9] Bit 7 Deferred Read Address [7] Bit 6 Deferred Read Address [6] Bit 5 Deferred Read Address [5] Bit 4 Deferred Read Address [4] Bit 3 Deferred Read Address [3] Bit 2 Deferred Read Address [2] Bit 1 Deferred Read Address [1] Bit 15-0 Deferred Read Address [15:0] These sixteen bits, in conjunction with the seven bits of the Deferred Read High Address register, make up the deferred read address. It is a halfword address, not a byte address. Notes: 1. The deferred read address is a halfword address in the Countach Bus Subsystem address space. Countach DRAM address space is $000000-$3FFFFF and Countach Subsystem scratch pad address space is $400000-$4001FF. 2. Writing this register begins the deferred access operation. This register must be the last one written when initiating a deferred read access. 3. During a deferred read access, all deferred registers are locked out from ARM writes. 4. When the deferred read access completes, an interrupt is generated via the Countach DMA Done bit in the ARM Bus Interface Interrupt Status register. Address: Deferred Write High Address (DefWrHiAddr) $01FF82AD Address: Deferred Write High Address (DefWrHiAddr) $01FF82AC Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Bit 7 (Not Used) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Deferred Deferred Deferred Deferred Deferred Deferred Deferred Rst Value Write Write Write Write Write Write Write x0000000b Address [22] Address [21] Address [20] Address [19] Address [18] Address [17] Address [16] Read Value 00h Bit 15-7 Bit 6-0 Not used Deferred Write Address [22:16] These seven bits, in conjunction with the sixteen bits of the Deferred Write Low Address register, make up the deferred write address. It is a halfword address, not a byte address. 100723A Conexant 24-5 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: Deferred Write Low Address (DefWrLoAddr) $01FF82AF Address: Deferred Write Low Address (DefWrLoAddr) $01FF82AE Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Deferred Write Address [8] Bit 0 Deferred Write Address [0] Default: Rst. Value 00h Read Value 00h Default: Rst Value 00h Read Value 00h Deferred Deferred Deferred Deferred Deferred Deferred Deferred Write Write Write Write Write Write Write Address [15] Address [14] Address [13] Address [12] Address [11] Address [10] Address [9] Bit 7 Deferred Write Address [7] Bit 6 Deferred Write Address [6] Bit 5 Deferred Write Address [5] Bit 4 Deferred Write Address [4] Bit 3 Deferred Write Address [3] Bit 2 Deferred Write Address [2] Bit 1 Deferred Write Address [1] Bit 15-0 Deferred Write Address [15:0] These sixteen bits, in conjunction with the seven bits of the Deferred Write High Address register, make up the deferred write address. It is a halfword address, not a byte address. Notes: 3. The deferred write address is a halfword address in the Countach Bus Subsystem address space. Countach DRAM address space is $000000-$3FFFFF and Countach Subsystem scratch pad address space is $400000-$4001FF. 4. Writing this register begins the deferred access operation. This register must be the last one written when initiating a deferred write access. 5. During a deferred write access, all deferred registers are locked out from ARM writes. 6. When the deferred write access completes, an interrupt is generated via the Countach DMA Done bit in the ARM Bus Interface Interrupt Status register. Address: Deferred Read Data (R) (DefRdData) $01FF82B1 Address: Deferred Read Data (R) (DefRdData) $01FF82B0 Bit 15 Deferred Read Data [15] (R) Bit 7 Deferred Read Data [7] (R) Bit 14 Deferred Read Data [14] (R) Bit 6 Deferred Read Data [6] (R) Bit 13 Deferred Read Data [13] (R) Bit 5 Deferred Read Data [5] (R) Bit 12 Deferred Read Data [12] (R) Bit 4 Deferred Read Data [4] (R) Bit 11 Deferred Read Data [11] (R) Bit 3 Deferred Read Data [3] (R) Bit 10 Deferred Read Data [10] (R) Bit 2 Deferred Read Data [2] (R) Bit 9 Deferred Read Data [9] (R) Bit 1 Deferred Read Data [1] (R) Bit 8 Deferred Read Data [8] (R) Bit 0 Deferred Read Data [0] (R) Default: Rst. Value 00h Read Value 00h Default: Rst Value 00h Read Value 00h Bit 15-0 Deferred Read Data This read-only register contains the deferred read data at the completion of a deferred read access operation. Its contents are valid when the Countach DMA Done bit in the ARM Bus Interface Interrupt Status register is set. 24-6 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: Deferred Write Data (DefWrData) $01FF82B3 Address: Deferred Write Data (DefWrData) $01FF82B2 Bit 15 Deferred Write Data [15] Bit 7 Deferred Write Data [7] Bit 14 Deferred Write Data [14] Bit 6 Deferred Write Data [6] Bit 13 Deferred Write Data [13] Bit 5 Deferred Write Data [5] Bit 12 Deferred Write Data [12] Bit 4 Deferred Write Data [4] Bit 11 Deferred Write Data [11] Bit 3 Deferred Write Data [3] Bit 10 Deferred Write Data [10] Bit 2 Deferred Write Data [2] Bit 9 Deferred Write Data [9] Bit 1 Deferred Write Data [1] Bit 8 Deferred Write Data [8] Bit 0 Deferred Write Data [0] Default: Rst. Value 00h Read Value 00h Default: Rst Value 00h Read Value 00h Bit 15-0 Deferred Write Data This register contains the data to be written during a deferred write access operation. Notes: This register must be written before beginning the deferred write access via a write to the Deferred Write Low Address register. During a deferred write access, all deferred registers are locked out from ARM writes. 100723A Conexant 24-7 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 24.3 ARM BUS INTERFACE 24.3.1 Function Description The Arm Bus interface block attaches the Countach Bus Subsystem to the ARM Bus System. The ARM can directly access the various registers of the Countach Bus Subsystem. It can access the Countach Bus Subsystem's SDRAM and the Countach Imaging DSP subsystem's scratch pad memory and the SDRAM with discrete I/O accesses with some wait state penalty. It can also access the SDRAM via DMA accesses. To accommodate the ARM DMA interchange, two channels are provided: one for transfers into the SDRAM and one for transfers out of the SDRAM. In addition, two handshaking signals are provided for interrupting of each processor and allow the ARM to interrupt the Countach core. It is implemented through a register in the Countach Subsystem Interface. The arm_attn signal comes directly from the Countach core and is an input to the ARM interrupt controller. 24.3.2 Register Description Address: ARM Bus Interface Interrupt Status (ABIIrqStat) $01FF8283 Address: ARM Bus Interface Interrupt Status (ABIIrqStat) $01FF8282 00h Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Rst Value xx000000b Read Value Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 Countach Subsystem Interrupt Bit 4 VSI Overrrun Bit 3 Deferred Access Done Bit 2 C2A DMA Done Bit 1 Countach Bit 0 Video/ Scan DMA Done DMA Done Bit 15-6 Bit 5 Not used Countach Subsystem Interrupt Countach Subsystem has interrupted the ARM either in IRQP or IRQP2, depending on the setting of the Countach Interrupt Source bit of the ABICountachCtrl register. VSI Overrun Deferred Access Done The second VSI ping-pong buffer has been filled before the first has been emptied, resulting in loss of data. A deferred access to/from scratch pad or SDRAM has completed. If a deferred read was requested, the data in the Deferred Read Access Data register is now valid. C2A (SDRAM to Arm Bus System) block size has been reached. DMA operation specified by Countach scratch pad parameters has completed. Two-dimensional DMA from Video/Scan Interface to SDRAM has completed (two fields) or one scan line has completed. Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C2A DMA Done Countach DMA Done Video/Scan DMA Done Note: Each of these bits are cleared by writing it to a one. This allows individual interrupts to be cleared without affecting the others. 24-8 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: ARM Bus Interface Interrupt Enable (ABIIrqEnable) $01FF8285 Address: ARM Bus Interface Interrupt Enable (ABIIrqEnable) $01FF8284 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 Countach Bit 4 VSI Overrrun Interrupt Enable Bit 3 Deferred Access Interrupt Enable Bit 2 C2A DMA Interrupt Enable Bit 1 Countach Bit 0 Interrupt Enable DMA Interrupt Enable Video/ Scan Rst Value DMA xx000000b Interrupt Read Value Enable 00h Bit 15-6 Bit 5 Bit 4 Bit 3 Countach Interrupt Enable VSI Overrun Interrupt Enable Not used Enables interrupt when the Countach has interrupted the ARM Bus via the IRQP or IRQP2 signals. Enables interrupt when the second VSI ping-pong buffer has been filled before the first has been emptied, indicating in loss of data. Deferred Access Interrupt Enable Enables interrupt when a deferred access to/from scratch pad or SDRAM has completed. Bit 2 Bit 1 C2A DMA Interrupt Enable Countach DMA Interrupt Enable Enables interrupt when C2A (SDRAM to Arm Bus System) block size has been reached. Enables interrupt when DMA operation specified by Countach scratch pad parameters has completed. Bit 0 Video/Scan DMA Interrupt Enables interrupt when two-dimensional DMA from Video/Scan Interface to SDRAM has completed (two fields) or one scan line has been completed. Address: Bit 15 Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Rst Value xxxx0000b Read Value 00h ARM Bus Interface (Not Used) Countach Control (W) (ABICountachCtrl) $01FF8287 Address: Bit 7 ARM Bus Interface (Not Used) Countach Control (W) (ABICountachCtrl) $01FF8286 Bit 6 (Not Used) Bit 5 Countach Bit 4 Reset Countach Bus Subsystem (W) Bit 3 Start Countach DMA (W) Bit 2 Abort Countach DMA (W) Bit 1 Reset Countach Subsystem (W) Bit 0 Interrupt Countach Subsystem (W) Interrupt Source Bit 15-6 Bit 5 Countach Interrupt Source Not used This bit selects which interrupt output from the Countach DSP Subsystem is used to interrupt the ARM via the Countach Interrupt bit in the ARM Bus Interface Interrupt Status Register. A value of 0 selects the IRQP signal and a value of 1 selects the IRQP2 signal. Bit 4 Reset Countach Bus Subsystem Writing a one to this bit resets the entire Countach Bus Subsystem (CBSS.) 100723A Conexant 24-9 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Bit 3 Bit 2 Start Countach DMA Abort Countach DMA Writing a one to this bit causes the Countach DMA controller to fetch parameters from scratch pad and begin a DMA transfer. Writing a one to this bit causes any Countach DMA operation (CDMA channel 1) to be aborted. The Countach receives the Countach DMA Done interrupt after the DMA has aborted (EXTIRQ2). Writing a one to this bit resets the Countach Subsystem and the Countach Subsystem Interface which contains the DMA FIFOs. Bit 1 Bit 0 Reset Countach Subsystem Interrupt Countach Subsystem Writing a one to this bit generates an interrupt to the Countach Subsystem (EXTIRQ). 24.3.3 Internal Memory The ARM Bus Interface contains two 4 x 16 buffers for DMA transfers between memory attached to the ARM Bus Subsystem and the Countach SDRAM. These buffers can be accessed by the ARM as either bytes or halfwords. The two buffers are located at the following addresses: Address: ARM to Countach DMA Buffer (A2CDmaBuf) $01FF830x Address: ARM to Countach DMA Buffer (A2CDmaBuf) $01FF830x Bit 15 A2C Buffer Data [15] Bit 14 A2C Buffer Data [14] Bit 13 A2C Buffer Data [13] Bit 12 A2C Buffer Data [12] Bit 11 A2C Buffer Data [11] Bit 10 A2C Buffer Data [10] Bit 9 A2C Buffer Data [9] Bit 8 A2C Buffer Data [8] Default: Rst. Value 00h Read Value 00h Default: Rst Value 00h Read Value 00h Bit 7 A2C Buffer Data [7] Bit 6 A2C Buffer Data [6] Bit 5 A2C Buffer Data [5] Bit 4 A2C Buffer Data [4] Bit 3 A2C Buffer Data [3] Bit 2 A2C Buffer Data [2] Bit 1 A2C Buffer Data [1] Bit 0 A2C Buffer Data [0] $01FF8300-01 $01FF8302-03 $01FF8304-05 $01FF8306-07 A2C DMA Buffer halfword 0 A2C DMA Buffer halfword 1 A2C DMA Buffer halfword 2 A2C DMA Buffer halfword 3 Address: Countach to ARM DMA Buffer (C2ADmaBuf) $01FF830x Address: Countach to ARM DMA Buffer (C2ADmaBuf) $01FF830x Bit 15 C2A Buffer Data [15] Bit 14 C2A Buffer Data [14] Bit 13 C2A Buffer Data [13] Bit 12 C2A Buffer Data [12] Bit 11 C2A Buffer Data [11] Bit 10 C2A Buffer Data [10] Bit 9 C2A Buffer Data [9] Bit 8 C2A Buffer Data [8] Default: Rst. Value 00h Read Value 00h Default: Rst Value 00h Read Value 00h Bit 7 C2A Buffer Data [7] Bit 6 C2A Buffer Data [6] Bit 5 C2A Buffer Data [5] Bit 4 C2A Buffer Data [4] Bit 3 C2A Buffer Data [3] Bit 2 C2A Buffer Data [2] Bit 1 C2A Buffer Data [1] Bit 0 C2A Buffer Data [0] $01FF8308-09 $01FF830A-0B $01FF830C-0D $01FF830E-0F C2A DMA Buffer halfword 0 C2A DMA Buffer halfword 1 C2A DMA Buffer halfword 2 C2A DMA Buffer halfword 3 24-10 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 ARM access to the ABI buffers are provided for diagnostic purposes only and should not be used as part of normal operation. When the ARM makes an access to these buffers, the ARM is held off and clock domain synchronization occurs before the access is completed. As a result, a significant wait state penalty is incurred. This penalty will be even longer if a local DMA operation is in progress when the access is made as the ARM is held off for both the clock domain synchronization and the completion of the local DMA transfer. There is a risk of data corruption when the ARM makes write accesses to these buffers while a DMA transfer is in progress. This can occur because the buffers alternate betweeen a DMA transfer sequence in the ARM Bus Subsystem domain and a DMA transfer sequence in the Countach Bus Subsystem domain. If the write operation occurs between these DMA transfers, the DMA data in the buffer will be replaced with the ARM data. 24.4 Countach Imaging DSP Subsystem Interface ARM as either bytes or halfwords. The buffer is located at the following addresses: Address: Countach DMA Buffer (CSIDmaBuf) $01FF830x Address: Countach DMA Buffer (CSIDmaBuf) $01FF830x Bit 7 CSI Buffer Data [7] Bit 6 CSI Buffer Data [6] Bit 5 CSI Buffer Data [5] Bit 4 CSI Buffer Data [4] Bit 3 CSI Buffer Data [3] Bit 2 CSI Buffer Data [2] Bit 1 CSI Buffer Data [1] Bit 0 CSI Buffer Data [0] Bit 15 CSI Buffer Data [15] Bit 14 CSI Buffer Data [14] Bit 13 CSI Buffer Data [13] Bit 12 CSI Buffer Data [12] Bit 11 CSI Buffer Data [11] Bit 10 CSI Buffer Data [10] Bit 9 CSI Buffer Data [9] Bit 8 CSI Buffer Data [8] Default: Rst. Value 00h Read Value 00h Default: Rst Value 00h Read Value 00h Table 24-1. Needs a title $01FF8300-01 $01FF8302-03 $01FF8304-05 $01FF8306-07 $01FF8306-07 $01FF8306-07 $01FF8306-07 $01FF8306-07 CSI DMA Buffer halfword 0 CSI DMA Buffer halfword 1 CSI DMA Buffer halfword 2 CSI DMA Buffer halfword 3 CSI DMA Buffer halfword 4 CSI DMA Buffer halfword 5 CSI DMA Buffer halfword 6 CSI DMA Buffer halfword 7 ARM access to the CSI buffers are provided for diagnostic purposes only and should not be used as part of normal operation. When the ARM makes an access to these buffers, the ARM is held off and clock domain synchronization occurs before the access is completed. As a result, a significant wait state penalty is incurred. This penalty will be even longer if a local DMA operation is in progress when the access is made as the ARM is held off for both the clock domain synchronization and the completion of the local DMA transfer. There is a risk of data corruption when the ARM makes write accesses to this buffer while a DMA transfer is in progress. It is also possible that an access to this buffer can cause spurious writes to the scratchpad space while a DMA transfer is in progress. 100723A Conexant 24-11 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 24.5 COUNTACH DMA CONTROLLER 24.5.1 Function Description This block handles data transfers between several of the blocks of the Countach subsystem. It has three potential bus masters: the Video/Scan Interface, the Arm Bus interface, and the Countach subsystem. The VDMA employs a hierarchical round-robin arbitration scheme, with the Video/Scan Interface block at the highest priority and the Countach subsystem and Arm Bus interface in a round-robin scheme at the lowest priority. A round-robin arbitration scheme is one in which no requestor can be serviced until all other requestors at the same priority have been serviced if they are also requesting. A hierarchical arbitration scheme is one in which if a higher priority group is requesting service it is given priority over a lower priority group, after which the lower priority group is handled in its predetermined manner. Below is a table of the four DMA channels, their functionality, and priorities. Table 24-2. DMA Channels: Functionality and Priorities Chan 0 1 2 3 Legend: Chan VSI CSI ABI ++ -- 2D Th ! Notes: (1) To be supplied. DMA channel Video/Scanner Interface Countach Subsystem Interface ARM Bus Interface Incrementing address Decrementing address Address Jumping at boundaries. Burst cycles Throttle: Limits number of DMA Cycles per CBSS clocks Block limit Usage VSI CSI I/O ABI in ABI out ++ " " " " " -- 2D " " " " " " " " " " Th ! Priority A-1 B-1 B-2 B-3 Description Scan/video data to (S)DRAM Countach scratch pad data to/from (S)DRAM ARM data to (S)DRAM ARM data from (S)DRAM Channels 0,2, and 3 operate in a similar fashion as existing channels in the ARM DMA logic. These channels are programmed by ARM-accessible registers and contain address registers and, for channel 3, a block limit and enable register. Channel 1 is very different in its operation. It contains no ARM-accessible registers. It is controlled by the Countach Subsystem. However, since the Countach Subsystem cannot be a bus master and program the registers directly, the Countach DMA logic must fetch the register values from the Countach Subsystem scratch pad. The Countach Subsystem has no DMA handshaking signals as it is able to accept data at a fixed rate. DMA data is transferred to and from the Countach Subsystem via the scratch pad at fixed addresses. Thus, it appears as memory (SDRAM) to I/O (scratch pad) transfers. Channel 1 is shared by five logical DMA channels within the Countach Subsystem, but they operate consecutively, not concurrently (i.e., DMA for one logical channel is completely before DMA for another logical channel is begun. Finally, logical DMA channel 4 (of physical DMA channel 1) is used for program DMA. Because 24-12 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Countach instructions are 40 bits wide, they must be transferred in sections. This is accomplished by DMA transfers to three consecutive scratch pad addresses. Each of the five logical channels is started by the Countach Subsystem by a high-going pulse on the Countach GPIO signal sp_gpio[0]. When the pulse is detected, the Countach DMA Controller fetches the parameters from the scratch pad, executes the desired DMA operation, and interrupts the Countach Subsystem at the completion. The scratch pad addresses for the various DMA parameters are shown below: Table 24-3. DMA Parameters Scratch Pad Addresses Scratch pad address Parameter Countach Subsystem DMA Channel Parameters 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE Scratch pad address 0x100 0x101 0x102 0x103 0x1B0 0x1B1 0x1B2 ENB - Enables the DMA operation BAH - most significant bits of base address and DMA control bits BAL - least significant bits of base address SZ - number of halfwords to transfer NSR - number of sub ranges AST - address step between sub ranges Function Countach Subsystem DMA channel 0 data port Countach Subsystem DMA channel 1 data port Countach Subsystem DMA channel 2 data port Countach Subsystem DMA channel 3 data port Countach Subsystem DMA channel 4 program data port (bits 15:0) Countach Subsystem DMA channel 4 program data port (bits 31:16) Countach Subsystem DMA channel 4 program data port (bits 39:32) To program and initiate a DMA transfer, firmware must first setup the parameter registers shown above. The process of reading the ENB register will cause hardware to generate either an ARM IRQ or start a DMA transfer. If the LSB of the ENB Register is 1 an ARM IRQ is generated. If the value of the LSB is 0, a DMA transfer is initiated. Block Size Sub Range Value Memory This diagram depicts how the SZ, NSR and AST register all work together. The block size is controlled by the SZ register and defines the number of DMA accesses before the Sub Range Jump occurs. At the end of the block, the last DMA address + one is added to the AST register, and is used as the starting address for the next block. This process continues for the number of cycles specified by the NSR register. Once the NSR value is met, an IRQ is generated. 100723A Conexant 24-13 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description The meaning of the ENB, BAH, BAL, SZ, NSR, and AST parameters are shown below: Bit 15 Bit 14 Not used Bit 13 Bit 12 Program /Data Bit 7 Not used Bit 6 Bit 5 Bit 4 Bit 11 Bit 10 Bit 9 Address direction Bit 1 Bit 8 Data direction Bit 0 Logical Data Channel Number Bit 3 Bit 2 Base address (21:16) Parameter Description: BAH parameter Bit 15-13 Bit 12 Not used When high, logical channel 4 is requested (program DMA.) When low, one of logical channels 0-3 is requested as specified by the Logical Channel Number field (data DMA.) When bit 12 is low, this field indicates which logical channel of 0-3 is to be used (data DMA.) When bit 12 is high, this field is not used. When low, the DMA address should be incremented after each halfword is transferred. When high, the DMA address should be decremented after each halfword is transferred. When low, DMA data is read from Countach scratch pad space. When high, DMA data is written to Countach scratch pad space. Not used Upper bits of DMA base address Bit 11-10 Logical Data Channel Number Bit 9 Address direction Bit 8 Bit 7-6 Bit 5-0 Data direction Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Base address (15:8) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Base address (7:0) Parameter Description: BAL parameter Bit 15-8 Lower bits of DMA base address This parameter should only be fetched if the Enable channel bit of the BAH parameter is high. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Block size (15:8) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Block size (7:0) Parameter Description: SZ parameter (Refer to the above diagram) 24-14 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Bit 15-0 Block size in halfwords Block size = Block Size Register + 1. If this parameter is zero, the channel should be considered improperly configured and not enabled. Also, no further parameters need to be fetched in this circumstance. This register programs the data block size (number of DMA accesses) between address steps, AST. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Number of sub ranges (15:8) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Number of sub ranges (7:0) Parameter Description: NSR parameter (Refer to the above diagram) Bit 15-0 Number of sub ranges Total number of sub ranges = register value + 1; When this register is set to $0000, one block will be transferred before the IRQ occurs. This register controls the number of number of sub ranges (NSR), or address steps that occur in the complete DMA transfer. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Address step between sub ranges (15:8) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address step between sub ranges (7:0) Parameter Description: AST parameter (Refer to the above diagram) Bit 15-0 Address step between sub ranges This parameter should only be fetched if the Enable channel bit of the BAH parameter is high. This register controls the address step size between data blocks. The register value is added to the last DMA address accessed in a block plus 1. 100723A Conexant 24-15 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 24.5.2 Register Description Address: Video/Scan High Address One (VsHiAddr1) $01FF828D Address: Video/Scan High Address One (VsHiAddr1) $01FF828C Bit 7 (Not Used) Bit 6 Video /Scan Addr[22] Bit 5 Video /Scan Addr[21] Bit 4 Video /Scan Addr[20] Bit 3 Video /Scan Addr[19] Bit 2 Video /Scan Addr[18] Bit 1 Video /Scan Addr[17] Bit 0 Video /Scan Addr[16] Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Rst Value x0000000b Read Value 00h * * The value written to this register will not take effect until the lower address value is written. Therefore this value should be set first. Reading this register will return the Address Counter status, not the value written to this register. Not Used Video/Scan Interface High Address One [22:16] Bit 15 Video /Scan Addr[15] Bit 7 Video /Scan Addr[7] Bit 14 Video /Scan Addr[14] Bit 6 Video /Scan Addr[6] Bit 13 Video /Scan Addr[13] Bit 5 Video /Scan Addr[5] Bit 12 Video /Scan Addr[12] Bit 4 Video /Scan Addr[4] Bit 11 Video /Scan Addr[11] Bit 3 Video /Scan Addr[3] Bit 10 Video /Scan Addr[10] Bit 2 Video /Scan Addr[2] Bit 9 Video /Scan Addr[9] Bit 1 Video /Scan Addr[1] Bit 8 Video /Scan Addr[8] Bit 0 (Not Used) Default: Rst. Value 00h Read Value 00h Default: Rst Value 0000000xb Read Value 00h Bit 15-7 Bit 6-0 Address: Video/Scan Low Address One (VsLoAddr1) $01FF828F Address: Video/Scan Low Address One (VsLoAddr1) $01FF828E * * Writing to the Video/Scan Low Address Register will load the address counter. Therefore the upper address value should be set first. Reading this register will return the Address Counter status, and not the value written to this register. Video/Scan Interface Low Address One [15:1] Not Used Bit 15-1 Bit 0 24-16 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: Video/Scan High Address Two (VsHiAddr2) $01FF8291 Address: Video/Scan High Address Two (VsHiAddr2) $01FF8290 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Rst Value x0000000b Read Value 00h Bit 7 (Not Used) Bit 6 Video /Scan Addr[22] Bit 5 Video /Scan Addr[21] Bit 4 Video /Scan Addr[20] Bit 3 Video /Scan Addr[19] Bit 2 Video /Scan Addr[18] Bit 1 Video /Scan Addr[17] Bit 0 Video /Scan Addr[16] Bit 15-7 Bit 6-0 Not Used Video/Scan Interface High Address Two [22:16] Address: Video/Scan Low Address Two (VsLoAddr2) $01FF8293 Address: Video/Scan Low Address Two (VsLoAddr2) $01FF8292 Bit 15 Video /Scan Addr[15] Bit 7 Video /Scan Addr[7] Bit 14 Video /Scan Addr[14] Bit 6 Video /Scan Addr[6] Bit 13 Video /Scan Addr[13] Bit 5 Video /Scan Addr[5] Bit 12 Video /Scan Addr[12] Bit 4 Video /Scan Addr[4] Bit 11 Video /Scan Addr[11] Bit 3 Video /Scan Addr[3] Bit 10 Video /Scan Addr[10] Bit 2 Video /Scan Addr[2] Bit 9 Video /Scan Addr[9] Bit 1 Video /Scan Addr[1] Bit 8 Video /Scan Addr[8] Bit 0 (Not Used) Default: Rst. Value 00h Read Value 00h Default: Rst Value 0000000xb Read Value 00h Address: Video/Scan High Address Step (VSHiAddrStep) $01FF8295 Address: Video/Scan High Address Step (VSHiAddrStep) $01FF8294 Bit 15 (Not used) Bit 14 (Not used) Bit 13 (Not used) Bit 12 (Not used) Bit 11 (Not used) Bit 10 (Not used) Bit 9 (Not used) Bit 8 (Not used) Default: Rst. Value xxh Read Value 00h Default: Rst Value x0000000b Read Value 00h Bit 7 (Not used) Bit 6 Video /Scan Step [22] Bit 5 Video /Scan Step [21] Bit 4 Video /Scan Step [20] Bit 3 Video /Scan Step [19] Bit 2 Video /Scan Step [18] Bit 1 Video /Scan Step [17] Bit 0 Video /Scan Step [16] Bit 15-5 Bit 6-0 Not Used Video/Scan Interface High Address Step [22:16] 100723A Conexant 24-17 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: Video/Scan Low Address Step (VSLoAddrStep) $01FF8297 Address: Video/Scan Low Address Step (VSLoAddrStep) $01FF8296 Bit 15 Video /Scan Step[15] Bit 7 Video /Scan Step [7] Bit 14 Video /Scan Step[14] Bit 6 Video /Scan Step [6] Bit 13 Video /Scan Step [13] Bit 5 Video /Scan Step [5] Bit 12 Video /Scan Step [12] Bit 4 Video /Scan Step [4] Bit 11 Video /Scan Step [11] Bit 3 Video /Scan Step [3] Bit 10 Video /Scan Step [10] Bit 2 Video /Scan Step [2] Bit 9 Video /Scan Step [9] Bit 1 Video /Scan Step [1] Bit 8 Video /Scan Step [8] Bit 0 (Not used) Default: Rst. Value 00h Read Value 00h Default: Rst Value 0000000xb Read Value 00h Bit 15-1 Bit 0 Video/Scan Interface Low Address Step [15:1] Not Used Address: Video/Scan Mode (VSMode) $01FF8299 Address: Video/Scan Mode (VSMode) $01FF8298 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Rst Value xxxxxxx0b Read Value 00h Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 (Not Used) Bit 2 (Not Used) Bit 1 (Not Used) Bit 0 Video /Scan Select Bit 15-1 Bit 0 Video/Scan select Not Used A zero selects video capture mode and a one selects scan mode. Address: Bit 15 Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Rst Value x0000000b Read Value 00h ARM Bus A2C High (Not Used) Address (Aba2cHiAddr) $01FF829D Address: Bit 7 ARM Bus A2C High (Not Used) Address (Aba2cHiAddr) $01FF829C Bit 6 ARM Bus Input Addr[22] Bit 5 ARM Bus Input Addr[21] Bit 4 ARM Bus Input Addr[20] Bit 3 ARM Bus Input Addr[19] Bit 2 ARM Bus Input Addr[18] Bit 1 ARM Bus Input Addr[17] Bit 0 ARM Bus Input Addr[16] Bit 15-7 Bit 6-0 Not Used ARM Bus Interface Input (A2C) Data High Address [22:16] 24-18 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: ARM Bus A2C Low Address (Aba2cLoAddr) $01FF829F Address: ARM Bus A2C Low Address (Aba2cLoAddr) $01FF829E Bit 15 ARM Bus Input Addr[15] Bit 7 ARM Bus Input Addr[7] Bit 14 ARM Bus Input Addr[14] Bit 6 ARM Bus Input Addr[6] Bit 13 ARM Bus Input Addr[13] Bit 5 ARM Bus Input Addr[5] Bit 12 ARM Bus Input Addr[12] Bit 4 ARM Bus Input Addr[4] Bit 11 ARM Bus Input Addr[11] Bit 3 ARM Bus Input Addr[3] Bit 10 ARM Bus Input Addr[10] Bit 2 ARM Bus Input Addr[2] Bit 9 ARM Bus Input Addr[9] Bit 1 ARM Bus Input Addr[1] Bit 8 ARM Bus Input Addr[8] Bit 0 (Not Used) Default: Rst. Value 00h Read Value 00h Default: Rst Value 0000000xb Read Value 00h Bit 15-1 Bit 0 ARM Bus Interface Input (A2C) Data Low Address [15:1]. Not Used Address: Bit 15 Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Rst Value x0000000b Read Value 00h ARM Bus C2A High (Not Used) Address (Abc2aHiAddr) $01FF82A1 Address: Bit 7 ARM Bus C2A High (Not Used) Address (Abc2aHiAddr) $01FF82A0 Bit 6 ARM Bus Output Addr[22] Bit 5 ARM Bus Output Addr[21] Bit 4 ARM Bus Output Addr[20] Bit 3 ARM Bus Output Addr[19] Bit 2 ARM Bus Output Addr[18] Bit 1 ARM Bus Output Addr[17] Bit 0 ARM Bus Output Addr[16] Bit 15-7 Bit 6-0 Not Used ARM Bus Interface Output (C2A) Data High Address [22:16] Address: ARM Bus C2A Low Address (Abc2aLoAddr) $01FF82A3 Address: ARM Bus C2A Low Address (Abc2aLoAddr) $01FF82A2 Bit 15 ARM Bus Output Addr[15] Bit 7 ARM Bus Output Addr[7] Bit 14 ARM Bus Output Addr[14] Bit 6 ARM Bus Output Addr[6] Bit 13 ARM Bus Output Addr[13] Bit 5 ARM Bus Output Addr[5] Bit 12 ARM Bus Output Addr[12] Bit 4 ARM Bus Output Addr[4] Bit 11 ARM Bus Output Addr[11] Bit 3 ARM Bus Output Addr[3] Bit 10 ARM Bus Output Addr[10] Bit 2 ARM Bus Output Addr[2] Bit 9 ARM Bus Output Addr[9] Bit 1 ARM Bus Output Addr[1] Bit 8 ARM Bus Output Addr[8] Bit 0 (Not Used) Default: Rst. Value 00h Read Value 00h Default: Rst Value 0000000xb Read Value 00h Bit 15-1 Bit 0 ARM Bus Interface Output (C2A) Data Low Address [15:1] Not Used 100723A Conexant 24-19 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Address: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: ARM Bus C2A Block ARM Bus Size Output (Abc2aBlkSiz) Enable $01FF829B Address: Bit 7 ARM Bus ARM Bus ARM Bus ARM Bus ARM Bus ARM Bus ARM Bus Rst. Value Output Block Output Block Output Block Output Block Output Block Output Block Output Block 00h Size [14] Size [13] Size [12] Size [11] Size [10] Size [9] Size [8] Read Value 00h Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: ARM Bus C2A Block ARM Bus ARM Bus ARM Bus ARM Bus ARM Bus ARM Bus ARM Bus ARM Bus Rst. Value Size (Abc2aBlkSiz) Output Block Output Block Output Block Output Block Output Block Output Block Output Block Output Block 00h Size [7] Size [6] Size [5] Size [4] Size [3] Size [2] Size [1] Size [0] $01FF829A Read Value 00h Bit 15 Bit 14-0 ARM Bus Interface Output (C2A) Data DMA Enable (1 = enabled) ARM Bus Interface Output Data Block Size Note: Writes to bits 14-0 are ignored when the channel is enabled. To write a new block size, the channel must first be disabled by writing a "0" to bit 15 of this register. Address: ARM Bus A2C Throttle (Aba2cThrottle) $01FF82A5 Address: ARM Bus A2C Throttle (Aba2cThrottle) $01FF82A4 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 ARM Bus Input Throttle[10] Bit 2 ARM Bus Input Throttle[2] Bit 9 ARM Bus Input Throttle[9] Bit 1 ARM Bus Input Throttle[1] Bit 8 ARM Bus Input Throttle[8] Bit 0 ARM Bus Input Throttle[0] Default: Rst. Value xxxxx000b Read Value 00h Default: Rst Value 00h Read Value 00h Bit 7 ARM Bus Input Throttle[7] Bit 6 ARM Bus Input Throttle[6] Bit 5 ARM Bus Input Throttle[5] Bit 4 ARM Bus Input Throttle[4] Bit 3 ARM Bus Input Throttle[3] Bit 15-11 Bit 10-0 Not used ARM Bus Interface Input (A2C) DMA Throttle value A value of zero indicates no throttle. A value of 3FFh indicates 2047 Countach Bus Subsystem clocks (25 MHz) between successive DMA acknowledges. 24-20 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Address: ARM Bus C2A Throttle (Abc2aThrottle) $01FF82A7 Address: ARM Bus C2A Throttle (Abc2aThrottle) $01FF82A6 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 ARM Bus Output Throttle[10] Bit 2 ARM Bus Output Throttle[2] Bit 9 ARM Bus Output Throttle[9] Bit 1 ARM Bus Output Throttle[1] Bit 8 ARM Bus Output Throttle[8] Bit 0 ARM Bus Output Throttle[0] Default: Rst. Value xxxxx000b Read Value 00h Default: Rst Value 00h Read Value 00h Bit 7 ARM Bus Output Throttle[7] Bit 6 ARM Bus Output Throttle[6] Bit 5 ARM Bus Output Throttle[5] Bit 4 ARM Bus Output Throttle[4] Bit 3 ARM Bus Output Throttle[3] Bit 15-11 Bit 10-0 Not used ARM Bus Interface Output (C2A) DMA Throttle value A value of zero indicates no throttle. A value of 3FFh indicates 2047 Countach Bus Subsystem clocks (25 MHz) between successive DMA acknowledges. 24.5.3 Firmware Operation CDMA Channel 0 Setup and Operation 1. Program the DMA Controller * * * * Select Mode For Video Mode set up Address Register 2 Write Jump Value Write Address Register 1. This will also initialize the channel by setting up the Address Holder and Address Counter. 2. Operation * * * At the end of each line of data the vsi_eol will pulse, causing the holder value to be added to the jump value and placed back into the Address Holder. st For Video Mode, multiple vsi_eols will occur, then a vsi_eof. Upon the 1 vsi_eof, the Address Register2 will be loaded into the holder and counter. nd st Additional vsi_eols will occur and then a 2 vsi_eof. Upon the 2 vsi_eof the IRQ will be asserted. 100723A Conexant 24-21 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 24.6 VIDEO/SCANNER INTERFACE 24.6.1 Function Description The Video/Scan Interface connects the Video/Scan Controller to the SDRAM via DMA cycles. This interface has a unidirectional data flow: Video/Scan Controller to SDRAM. It consists of two 64 halfword buffers that ping-pong, address counters for Video/Scan Controller input, and CDRAM output and byte to halfword assembly. The Video/Scan Controller transmits a single line when attached to the scanner input or a single frame when attached to the video input. In either case, the Video/Scan Controller data flow is as follows: 1. The Video/Scan Controller initiates a transfer by a single high-going pulse on the start signal to VSI . 2. As each analog sample becomes available, it is placed on the VSC output bus and the data ready signal is pulsed high to VSI. In the case of video capture, it is expected that the data ready signal will remain high for long periods of time as video data is available at each rising edge of the data clock. In the case of scanner capture, it is expected that the data ready signal will be inactive for several data clocks between successive pixels. 3. As the Video/Scan Interface receives data from the Video/Scan Controller, it is assembled into halfwords and then stored into one of the two ping-pong buffers. When the buffer is filled, data storing is switched to the remaining buffer and a signal is passed to the opposite side of the interface indicating a buffer is available for transfer. 4. The Video/Scan Controller terminates the transfer by a single high-going pulse on the stop signal. 5. On the Countach Bus Subsystem side of the Video/Scan Interface, the data flow is as follows: 6. A pulse is received from the Video/Scan Controller side of the Video/Scan Interface indicating a buffer is available for transfer. 7. VSI asserts the DMA request signal to CBU. The sequencial DMA signal is also asserted if the buffer contains more than one halfword of data. 8. Once the DMA acknowledge signal is detected, transfer begins, one data being transferred for each SDRAM ready pulse. 24.6.2 Register Description Address: Video/Scanner Interface Mode (VSIMode) $01FF8289 Address: Video/Scanner Interface Mode (VSIMode) $01FF8288 Bit 15 (Not Used) Bit 14 (Not Used) Bit 13 (Not Used) Bit 12 (Not Used) Bit 11 (Not Used) Bit 10 (Not Used) Bit 9 (Not Used) Bit 8 (Not Used) Default: Rst. Value xxh Read Value 00h Default: Bit 7 (Not Used) Bit 6 (Not Used) Bit 5 (Not Used) Bit 4 (Not Used) Bit 3 (Not Used) Bit 2 (Not Used) Bit 1 Bit 0 Video/Scanner Video/Scanner Rst Value DMA Hog DMA Hog xxxxxx00b Mode[1] Mode[0] Read Value 00h Bit 15-2 Bit 1-0 Not used The Video/Scanner DMA Hog Mode field is used to throttle and/or disable other DMA masters during video capture. It has the following settings: Hog Mode 0 1 2 3 Countach Subsystem Interface Burst and single DMA allowed No burst - single DMA only No DMA allowed No DMA allowed Arm Bus Interface Burst and single DMA allowed No burst - single DMA only No burst - single DMA only No DMA allowed 24-22 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 24.6.3 Internal Memory The Video/Scanner Interface contains two 64x16 buffers for DMA transfers from the Video/Scanner Controller and the Countach SDRAM. The buffers can be accessed by the ARM as halfwords only. The two buffers are located at the following address: Ping pong buffer 1: $01FFA400$01FFA47F Ping pong buffer 2: $01FFA480$01FFA4FF ARM access to the VSI buffers is provided for diagnostic purposes only and should not be used as part of normal operation. When the ARM makes an access to the buffers, the ARM is held off and clock domain synchronization occurs before the access is completed. As a result, a significant wait state penalty is incurred. 24.7 (S)DRAM Controller ((S)DRAMC) 24.7.1 Function Description The (S)DRAM Controller is used to communicate between the Countach Bus Unit (CBU) and external FPDRAM or SDRAM memory. This memory will primarily be used for reading and writing large amounts of sequential data necessary for carrying out the programs running on the Countach Imaging DSP core. Whether DRAM or SDRAM is used is an option, but only one memory unit is accessible to the memory controller. The (S)DRAMC state machine uses a 100Mhz or 87.5Mhz clock to control the SDRAM and DRAM. The CBU will communicate with (S)DRAMC at 25 Mhz or 21.875Mhz, so all data received from either RAM type must be synchronized to this speed before sent to the CBU. A third clock, an inverted version of the 100Mhz or 87.5Mhz clock, will be sent to the SDRAM memory. In this document, 100Mhz clock will be used for all descriptions. From the timing point of view, 87.5Mhz will be covered if it meets 100Mhz requirements. The supported DRAM characteristics are listed in the following table: Table 24-4: Supported FPDRAM Chip Characteristics Addressing Size: Organization: Access Speed: 2 MB, 8 MB 16 bits 50 ns, 60 ns Table 24-5: Supported SDRAM Chip Characteristics Addressing Size: Organization: Access Speed: 2 MB, 8 MB 8 bits or 16 bits 10 ns The maximum memory size that is supported for either memory type is 8MB. Six possible row/column pinouts types are supported. A more detailed description can be found in the address multiplexing table. SDRAM will always be used in burst mode, with one access per burst. The CAS latency will be set to 3 cycles which is normal for SDRAM running at 100MHz. The two possible sizes and two possible organizations are programmable in the (S)DRAMC control register. Fast page mode DRAMs (50ns and 60ns) are supported. The speed requirement is due to the bandwidth requirements of the Countach Imaging DSP. The DRAMS will be used in both fast page burst mode and single access mode. The two possible densities which are supported are programmable in the (S)DRAMC control register. 100723A Conexant 24-23 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 24.7.1.1 Memory Bank Structure There will only be one bank of memory allowed. Accesses to those banks must be done as halfword (16 bit) accesses. SDRAM with 8-bit data bus will not be byte addressable as far as the system in concerned. Instead, each 16-bit access will write or read two consecutive bytes of data to/from the 8-bit SDRAM. For instance, a request to access to byte location 0x100 or 0x101 in 8-bit SDRAM will both access the same halfword (16-bit) location. Hardware does NOT support byte access to external memory connected to (S)DRAM. 24.7.1.2 Wait State Profile 50 ns FPDRAM read requests will have two 25Mhz wait states for the first read access and zero wait states for each successive read. So the FPDRAM read wait state profile is considered to be 2-0-0-0. For example, a burst of four reads will take six cycles to complete; three for the first read, and three total for the next three reads. For 60ns FPDRAM, the read wait state profile is 2-0-1-0-1-0, etc. The write wait state profile for 50ns FPDRAM is 1-0-0-0. The write wait state profile for 60 ns FPDRAM is 1-0-1-0-, etc. SDRAMs will have an identical wait state profile regardless of whether they use a 16 bit data bus or 8 bit data bus. Writes will have a profile of 1-0-0-0. Reads will have a wait state profile of 2-0-0-0. In either case when the burst or single access is finished, there will be a 1 cycle penalty in order to satisfy Trc. 24.7.1.3 Address Multiplexing When reading chart, note that the address bits and data bit on the leftmost column correspond to the actual bits which are output of the (S)DRAMC block (also outputs of ASIC), whereas the address bits in the row/col columns correspond to the input addresses to the (S)DRAMC block (which are aligned to halfword boundary). In other words, the address requested by CBU will be a halfword address, not a byte address. As a result, the CBU and (S)DRAMC will communicate via a 22-bit address bus. In the following charts, MA[x] refers to the memory address pin located on the MFC2000 ASIC (i.e.,. cdao[x]). MD[x] refers to the memory data pin located on the MFC2000 ASIC (i.e.,cddo[x]). BA[x] refers to the bank pin on the SDRAM part. EA[x] refers to the external address pin located on the RAM part. So the External address column of the chart shows the actual connection between the MFC2000 and the RAM. (i.e., looking at the first row of the chart, there will be a wire connecting MA[12] of the MFC2000 to the BA1 of the SDRAM). A[x], within the ROW/COL columns of the chart, refers to the 22-bit address bus within the chip 24-24 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 24-6. Untitled table Address Multiplexing Register External Address MA[12]/BA[1] MA[11]/BA[0] MA[10]/EA[11] MA[9]/EA[10] MD[0]/EA[9] MA[8]/EA[8] MA[7]/EA[7] MA[6]/EA[6] MA[5]/EA[5] MA[4]/EA[4] MA[3]/EA[3] MA[2]/EA[2] MA[1]/EA[1] MA[0]/EA[0] SDRAM 64 Mb (16 bit data bus) (14 x 8) ROW A[21] A[20] A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] COL. A[21] A[20] 0 01 NC 0 A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] 3 SDRAM 64 Mb (8-bit data bus) (14 x 9) ROW A[21] A[20] A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] COL. A[21] A[20] 0 01 NC 3 SDRAM 16 Mb (16 bit data bus) (12 x 8) ROW 0 0 A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] COL. 0 0 A[19] 01 NC 0 A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] 3 SDRAM 16 Mb (8 bit data bus) (12 x 9) ROW 0 0 A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] COL. 0 0 A[19] 01 NC3 (0 or 1)2 A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] (0 or 1)2 A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] 1. EA[10] is used on SDRAMs for auto-precharge during column access. Auto-precharge will not be utilized by CDRAM so EA[10] will always be set to 0 during column access. 2. EA[8] will be used as the byte control bit for 8-bit SDRAMs. Addresses sent to CDRAM from the CBU will always be halfword addressable. In order to communicate with 8-bit SDRAMs, CDRAM toggles EA[8] and obtains two sequential pieces of 8-bit data and sends it back to the system as one 16-bit data chunk. 3. Since MD[0] is used both as a data pin and an address pin, during the column portion of a SDRAM access, the SDRAM will not read from the EA[9] pin. So EA[9] is no-care [NC] during this time. Although at that time, MD[0] may very well be carrying valid data to the data bus. 100723A Conexant 24-25 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Table 24-7. Untitled table Address Multiplexing Register Physical Address MA[12]/EA[11] MA[11]/EA[10] MA[10]/EA[9] MA[8]/EA[8] MA[7]/EA[7] MA[6]/EA[6] MA[5]/EA[5] MA[4]/EA[4] MA[3]/EA[3] MA[2]/EA[2] MA[1]/EA[1] MA[0]/EA[0] 1. DRAM 16 or 64 Mb (16 bit data bus) 12 x 10 or 10 x 101 ROW A[21] A[20] A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] COL. 0 0 A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] DRAM 16 Mb (16 bit data bus) 12 x 8 ROW A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] COL. 0 0 0 0 A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] In the 10x10 version, MA[11] and MA[12] will be left unconnected Table 24-8. Untitled table Memory Size/Type Supported/Not Supported Row 512K x 16 x 2 bank SDRAM (16 Mb) 1M x 8 x 2 bank SDRAM (16 Mb) 1M x 16 x 4 bank SDRAM (64 Mb) 2M x 8 x 4 bank SDRAM (64 Mb) 2M x 16 x 2 bank SDRAM (64 Mb) 4M x 8 x 2 bank SDRAM (64 Mb) 1M x 16 DRAM (16 Mb) 4M x 16 DRAM (64 Mb) Supported Supported Supported Not Supported Supported Supported Supported Supported 11 2 banks (1 bit) Supported 11 2 banks (1 bit) Supported 12 4 banks (2 bits) 12 4 banks (2 bits) 13 2 banks (1 bit) 13 2 banks (1 bit) 12 10 12 13 8 10 10 9 9 8 9 8 9 Row/Column Configuration Column 8 24-26 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 As seen in the preceding tables, special care must be taken when connecting a FPDRAM or SDRAM to the MFC2000 for use with (S)DRAMC. In summary, when using FPDRAMs, A[8:0] of the DRAM should be connected to MA[8:0] of the (S)DRAMC. A[11:9] of the DRAM should be connected to MA[12:10] of the (S)DRAMC. When using SDRAMs, for 64 Mb type, A[8:0] of the SDRAM should be connected to MA[8:0] of the (S)DRAMC. A[9] of the SDRAM should be connected to MD0 of the (S)DRAMC. A[13:10] of the SDRAM should be connected to MA[12:9] of the (S)DRAMC. Consequently, the MD0 pin out of the (S)DRAMC is time multiplexed with address information during the row address portion of a SDRAM access and contains data information during the column address portion of a SDRAM access. This was done to conserve pin usage of the MFC2000. For the same reason, any DQM pins of an SDRAM should be connected to ground. The CKE pin of the SDRAM should be connected high. Also, if two bank 64Mb SDRAM is being used (the chart describes four bank), MA[11] should be connected to EA[12] since there will only be one bank pin (as compared to the four bank SDRAM in which there are two bank pins). For board layout: In order to maintain low delay and minimized crosstalk, the SDRAM should be placed no farther than 0.5 inch from the MFC2000. 100723A Conexant 24-27 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 24.8 Register Description Name/Address DRAM Configuration 0x01FF8281 Bit 15 NA NA Bit 14 NA Bit 13 NA Bit 12 NA Bit 11 NA Bit 10 NA Bit 9 NA Bit 8 Default Rst. Value `h00 Read Value `h00 Bit 0 Default Rst. Value `h00 Read Value `h00 Name/Address DRAM Configuration 0x01FF8280 NA Bit 7 NA Bit 6 NA Bit 5 Bit 4 CDRAM Clock Enable Bit 3 Bit 2 Bit 1 Configuration Code This register contains the information necessary to decide whether DRAM or SDRAM is being used, the size of memory being used, and whether an 8- or 16-bit DRAM is being used. This register should be written to ONCE and only once as the CDRAM may not work properly if this is written to a second or more times. In addition, most RAMs require a minimum of 100us delay before use in order for the RAM to stabilize, but some others require more time. To properly use the RAM, this register should be written to ONLY after the appropriate delay for that particular RAM is met. Writing to this register will cause the CDRAM to perform the proper ammount of refreshes, the precharge, and mode set necessary for correct startup of DRAM or SDRAM. Bit 15-5 Bit 4 CDRAM Clock Enable This bit enables or disables the CDRAM external clock. When using FPDRAM, the clock does not need to be enabled. 0: Enable 1: Disable Bit 3-0 DRAM Type SDRAM 8-bit 16 Mb SDRAM 8-bit 64 Mb SDRAM 16-bit 16 Mb SDRAM 16-bit 64 Mb FPDRAM 60ns 16 Mb (10x10) FPDRAM 60ns 16 Mb (12x8) FPDRAM 60ns 64 Mb (12x10) FPDRAM 50ns 16 Mb (10x10) FPDRAM 50ns 16 Mb (12x8) FPDRAM 50ns 64 Mb (12x10) Configuration Code 0010 0110 0000 0100 0111 0011 0111 1111 1011 1111 24-28 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 24.8.1 Timing 24.8.1.1 Detailed Timing Measurements sdclk100 sdrasn, sdcasn, sdcsn, sdrwn tC M H sdaddr tC M S tA S tD S tA H sddata tD H Figure 24-2. SDRAM Setup and Hold Timing Table 24-9. SDRAM Setup and Hold Timing Parameter Command setup time (includes rasn, casn, wen, csn) Command hold time Address setup time Address hold time Data setup time Data hold time Symbol tCMS tCMH tAS tAH tDS tDH Min. 4 3 4 3 4 3 Max. Units ns ns ns ns ns ns 100723A Conexant 24-29 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description sdclk100 Command ACT RD/WR Trcd RD/WR Trc RD/WR PRE Tdpl Trp ACT Addr R Row address C Column address C Column address C Column Bank address Row address Figure 24-3. SDRAM Read or Write Timing sdclk100 Trp Trsc MODE REF Command sdaddr PRE Figure 24-4. SDRAM Mode Timing Note: In the above SDRAM timing waveforms "Command" is a combination of rasn, casn, wen, and csn. sdclk100 sdcsn sdrasn sdcasn sdwrn REFRESH ACTIVE Trc sdaddr sddata ROW Figure 24-5. SDRAM Refresh Timing 24-30 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 Table 24-10. Timing Parameters for 16-bit SDRAM Read and Write Parameter Clock Period Ras precharge time Mode register set to Active delay Ras cycle time Ras-to-cas delay Data-in to Pre command period Symbol TCLK TRP TRSC TRC TRCD TDPL Min. 10 3 (5 for single access) 4 12 3 2 (4 for single access) Max. Units ns TCLK TCLK TCLK TCLK TCLK Table 24-11. Timing Parameters for 8-bit SDRAM Read and Write Parameter Clock Period Ras precharge time Mode register set to Active delay Ras cycle time Ras-to-cas delay Data-in to Pre command period Symbol TCLK TRP TRSC TRC TRCD TDPL Min. 10 5 (5 for single access) 4 12 3 3 (3 for single access) Max. Units ns TCLK TCLK TCLK TCLK TCLK sdrasn Tras Trc Trcd Trp sdcasn Tcas Tcp Tpc sdwrn (write cycle) Tasr Trah Tasc Tcah sdaddr[12:0] ROW Tds COL1 COL2 COL3 COL4 Tdh sddata[15:0] (write cycle) D1 D2 D3 D4 Figure 24-6. FPDRAM Timing (Read or Write) 100723A Conexant 24-31 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description Table 24-12. 60ns Timing Parameter Ras pulse width Cas pulse width Ras-to-cas delay Ras precharge Cas precharge Column address setup Column address hold Row address setup Row address hold Fast page mode cycle Ras-to-ras delay Data setup time Data hold time Symbol TRAS TCAS TRCD TRP TCP TASC TCAH TASR TRAH TPC TRC TDS TDH Min. 70 20(30 for read) 40 50 40 10 30 10 20 60 120 20 30 Max. Units ns ns ns ns ns ns ns ns ns ns ns ns ns Table 24-13. 50ns Timing Parameter Ras pulse width Cas pulse width Ras-to-cas delay Ras precharge Cas precharge Column address setup Column address hold Row address setup Row address hold Fast page mode cycle Ras-to-ras delay Data setup time Data hold time Symbol TRAS TCAS TRCD TRP TCP TASC TCAH TASR TRAH TPC TRC TDS TDH Min. 70 20(30 for read) 30 50 20(10 for read) 10 20(30 for read) 10 20 40 120 20 30 Max. Units ns ns ns ns ns ns ns ns ns ns ns ns ns Note: The most notable difference between the 50ns and 60ns timing is the Tpc parameter. During bursts, 50ns is able to perform much faster. 24-32 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 sdclk100 t RRAS sdrasn t CRD sdcasn t RCAS sdwrn Figure 24-7. FPDRAM Timing (Refresh) Table 24-14. FPDRAM Timing (Refresh) Parameter OE delay CASN pulse width RASN pulse width CASN to RASN delay Symbol tOED tRCAS tRRAS tCRD 28 60 9 Min. Max. 6 Units ns ns ns ns 100723A Conexant 24-33 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 24.8.2 Firmware Operation There is only one operation in which firmware need be concerned with the CDRAM block. That operation is the powerup operation. During startup, DRAM and SDRAM both have a specific sequence which needs to be performed on them in order for them to function properly. In order to assure that this sequence is properly performed the following must be done: 1. Wait a minumum of 200us. Some memories require as little as 100us, while a few others require as great as 500us. Waiting 200us will assure that MOST memories will work correctly. 2. Write to the CDRAM configuration register. This register should be written to ONCE and ONLY ONCE. Unless this register is written to, CDRAM will not know what type of RAM is being used. 3. That's it. After about a 1 us delay the startup procedure should be finished and the memory ready to be accessed. An access request can be made after the startup procedure is done and before it is finished, but the access will not occur until the complete startup procedure is finished. 24-34 Conexant 100723A Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 This page is intentionally blank 100723A Conexant 24-35 Multifunctional Peripheral Controller 2000 MFC2000 25. Configuration 25.1 Hardware Version Address Hardware Version (HWVer) $01FF8045 (R) Address Hardware Version (HWVer) $01FF8044 (R) Bit 15 (Not Used) Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default Rst. Value xxh Read Value 00h Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Rst. Value 00h Read Value 00h Bit 7 0:= First release 1-FF:= other releases This register is used to content the hardware version number. The value in this register is 0 for first release of a product. Whenever the hardware design is modified, this register value is incremented. This register is not effected by any reset. 00hMFC2000_x1 (the PQFP package) 25.2 Product Code Address Product Code (ProductCode) $01FF8047 (R) Address Product Code (ProductCode) $01FF8046 (R) Bit 15 (Not Used) Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default Rst. Value xxh Read Value 00h Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Rst. Value (must match with the product code) Bit 7 Product Code: BFh: 11626-11, with Data Modem Function, with Voice Codec/Speaker Phone Function, and with SmartDAA support BDh: 11626-12, with Data Modem Function, without Voice Codec/Speaker Phone Function, and with SmartDAA support BBh: 11626-13, without Data Modem Function, with Voice Codec/Speaker Phone Function, and with SmartDAA support B9h: 11626-14, without Data Modem Function, without Voice Codec/Speaker Phone Function, and with SmartDAA support B8h: 11626-15, without Data Modem Function, without Voice Codec/Speaker Phone Function, and without SmartDAA support This register is not affected by any reset. 100723A Conexant 25-1 MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description This page is intentionally blank 25-2 Conexant 100723A Multifunctional Peripheral Controller 2000 MFC2000 INSIDE BACK COVER NOTES Doc. No. 100723A Conexant 0.0 Sales Offices Further Information literature@conexant.com (800) 854-8099 (North America) (949) 483-6996 (International) Printed in USA World Headquarters Conexant Systems, Inc. 4311 Jamboree Road Newport Beach, CA 92660-3007 Phone: (949) 483-4600 Fax 1: (949) 483-4078 Fax 2: (949) 483-4391 Americas U.S. Northwest/ Pacific Northwest - Santa Clara Phone: (408) 249-9696 Fax: (408) 249-7113 U.S. Southwest - Los Angeles Phone: (805) 376-0559 Fax: (805) 376-8180 U.S. Southwest - Orange County Phone: (949) 483-9119 Fax: (949) 483-9090 U.S. Southwest - San Diego Phone: (858) 713-3374 Fax: (858) 713-4001 U.S. North Central - Illinois Phone: (630) 773-3454 Fax: (630) 773-3907 U.S. South Central - Texas Phone: (972) 733-0723 Fax: (972) 407-0639 U.S. Northeast - Massachusetts Phone: (978) 367-3200 Fax: (978) 256-6868 U.S. Southeast - North Carolina Phone: (919) 858-9110 Fax: (919) 858-8669 U.S. Southeast - Florida/ South America Phone: (727) 799-8406 Fax: (727) 799-8306 U.S. Mid-Atlantic - Pennsylvania Phone: (215) 244-6784 Fax: (215) 244-9292 Canada - Ontario Phone: (613) 271-2358 Fax: (613) 271-2359 Europe Europe Central - Germany Phone: +49 89 829-1320 Fax: +49 89 834-2734 Europe North - England Phone: +44 1344 486444 Fax: +44 1344 486555 Europe - Israel/Greece Phone: +972 9 9524000 Fax: +972 9 9573732 Europe South - France Phone: +33 1 41 44 36 51 Fax: +33 1 41 44 36 90 Europe Mediterranean - Italy Phone: +39 02 93179911 Fax: +39 02 93179913 Europe - Sweden Phone: +46 (0) 8 5091 4319 Fax: +46 (0) 8 590 041 10 Europe - Finland Phone: +358 (0) 9 85 666 435 Fax: +358 (0) 9 85 666 220 Asia - Pacific Taiwan Phone: (886-2) 2-720-0282 Fax: (886-2) 2-757-6760 Australia Phone: (61-2) 9869 4088 Fax: (61-2) 9869 4077 China - Central Phone: 86-21-6361-2515 Fax: 86-21-6361-2516 China - South Phone: (852) 2 827-0181 Fax: (852) 2 827-6488 China - South (Satellite) Phone: (86) 755-518-2495 China - North Phone: (86-10) 8529-9777 Fax: (86-10) 8529-9778 India Phone: (91-11) 692-4789 Fax: (91-11) 692-4712 Korea Phone: (82-2) 565-2880 Fax: (82-2) 565-1440 Korea (Satellite) Phone: (82-53) 745-2880 Fax: (82-53) 745-1440 Singapore Phone: (65) 737 7355 Fax: (65) 737 9077 Japan Phone: (81-3) 5371 1520 Fax: (81-3) 5371 1501 www.conexant.com |
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