View AM188ES-25KIW_782204.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY
Am186TMES/ESLV and Am188TM ES/ESLV
High Performance, 80C186-/80C188-Compatible and 80L186-/80L188-Compatible, 16-Bit Embedded Microcontrollers
DISTINCTIVE CHARACTERISTICS
n E86TM family 80C186-/188- and 80L186-/188compatible microcontrollers with enhanced bus interface -- Lower system cost with higher performance -- 3.3-V 0.3-V operation (Am186ESLV and Am188ESLV microcontrollers) n High performance -- 20-, 25-, 33-, and 40-MHz operating frequencies -- Supports zero-wait-state operation at 25 MHz with 100-ns static memory (Am186ESLV and Am188ESLV microcontrollers) and 40 MHz with 70-ns static memory (Am186ES and Am188ES microcontrollers) -- 1-Mbyte memory address space -- 64-Kbyte I/O space n Enhanced features provide improved memory access and remove the requirement for a 2x clock input -- Nonmultiplexed address bus -- Processor operates at the clock input frequency -- On the Am186ES/ESLV microcontroller, 8-bit or 16-bit memory and I/O static bus option n Enhanced integrated peripherals provide increased functionality, while reducing system cost -- Thirty-two programmable I/O (PIO) pins -- Two full-featured asynchronous serial ports allow full-duplex, 7-bit, 8-bit, or 9-bit data transfers -- Serial port hardware handshaking with CTS, RTS, ENRX, and RTR selectable for each port Multidrop 9-bit serial port protocol Independent serial port baud rate generators DMA to and from the serial ports Watchdog timer can generate NMI or reset A pulse-width demodulation option A data strobe, true asynchronous bus interface option included for DEN -- Pseudo static RAM (PSRAM) controller includes auto refresh capability -- Reset configuration register n Familiar 80C186/80L186 peripherals -- Two independent DMA channels -- Programmable interrupt controller with up to eight external and eight internal interrupts -- Three programmable 16-bit timers -- Programmable memory and peripheral chip-select logic -- Programmable wait state generator -- Power-save clock divider n Software-compatible with the 80C186/80L186 and 80C188/80L188 microcontrollers with widely available native development tools, applications, and system software n A compatible evolution of the Am186TMEM and Am188TMEM microcontrollers n Available in the following packages: -- 100-pin, thin quad flat pack (TQFP) -- 100-pin, plastic quad flat pack (PQFP) -- -- -- -- -- --
GENERAL DESCRIPTION
T h e A m 1 8 6 TMES/ESLV and Am188TMES /ESLV microcontrollers are an ideal upgrade for 80C186/188 and 80L186/188 microcontroller designs requiring 80C186/188 and 80L186/188 compatibility, increased performance, serial communications, and a direct bus interface. The Am186ES/ESLV and Am188ES/ESLV microcontrollers ar e p ar t o f th e A MD E 8 6 fa mi l y o f em be dd e d microcontrollers and microprocessors based on the x86 architecture. The E86 family includes the 16- and 32-bit microcontrollers and microprocessors described on page 8. The Am186ES/ESLV and Am188ES/ESLV microcontrollers have been designed to meet the most c om mo n r eq ui r e me nt s of e mb ed de d pr o du c ts developed for the office automation, mass storage, and communications markets. Specific applications include disk drives, hand-held and desktop terminals, set-top controllers, fax machines, printers, photocopiers, feature phones, cellular phones, PBXs, multiplexers, modems, and industrial controls.
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 20002 Rev: B Amendment/0 Issue Date: February 1997
PRELIMINARY
Am186ES MICROCONTROLLER BLOCK DIAGRAM
INT2/INTA0** INT3/INTA1/IRQ CLKOUTA INT6-INT4** INT1/SELECT INT0 TMROUT0 TMROUT1 PWD** TMRIN0 TMRIN1 DRQ0** NMI
CLKOUTB
DRQ1**
X2 X1 VCC GND
Clock and Power Management Unit Watchdog Timer (WDT) Control Registers
Interrupt Control Unit
Pulse Width Demodulator (PWD)
Control Registers
Timer Control Unit 0 1 2 Max Count B Registers Max Count A Registers 16-Bit Count Registers Control Registers
DMA Unit 0 1 20-Bit Source Pointers 20-Bit Destination Pointers 16-Bit Count Registers Control Registers Control Registers
RES
PIO Unit
PIO31- PIO0*
ARDY SRDY S2-S0 DT/R DEN/DS HOLD HLDA S6/LOCK/ CLKDIV2 UZI
Control Registers
Refresh Control Unit
PSRAM Control Unit
Control Registers
Control Registers Asynchronous Serial Port 0
TXD0 RXD0 RTS0/RTR0 CTS0/ENRX0 TXD1 RXD1 RTS1/RTR1** CTS1/ENRX1**
Bus Interface Unit
Execution Unit
Chip-Select Unit Asynchronous Serial Port 1
RD WHB A19-A0 AD15-AD0 WLB WR BHE/ADEN ALE LCS/ONCE0 MCS3/RFSH MCS2-MCS0 PCS6/A2 PCS5/A1 PCS3-PCS0**
UCS/ONCE1
Notes: *All PIO signals are shared with other physical pins. See the pin descriptions beginning on page 27 and Table 2 on page 34 for information on shared functions. ** PWD, INT5, INT6, RTS1/RTR1, and CTS1/ENRX1 are multiplexed with INT2/INTA0, DRQ0, DRQ1, PCS3, and PCS2 respectively. See the pin descriptions beginning on page 27.
2
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Am188ES MICROCONTROLLER BLOCK DIAGRAM
INT2/INTA0** INT3/INTA1/IRQ INT1/SELECT CLKOUTA INT6-INT4** INT0 TMROUT0 TMROUT1 PWD** TMRIN0 TMRIN1 DRQ0** NMI
CLKOUTB
DRQ1**
X2 X1 VCC GND
Clock and Power Management Unit Watchdog Timer (WDT) Control Registers
Interrupt Control Unit
Pulse Width Demodulator (PWD)
Control Registers
Timer Control Unit 0 1 2 Max Count B Registers Max Count A Registers 16-Bit Count Registers Control Registers
DMA Unit 0 1 20-Bit Source Pointers 20-Bit Destination Pointers 16-Bit Count Registers Control Registers Control Registers
RES
PIO Unit
PIO31- PIO0*
Control Registers
ARDY SRDY S2-S0 DT/R DEN/DS HOLD HLDA S6/LOCK/ CLKDIV2 UZI
Refresh Control Unit
PSRAM Control Unit
Control Registers
Control Registers
TXD0 RXD0 RTS0/RTR0 CTS0/ENRX0 TXD1 RXD1 RTS1/RTR1** CTS1/ENRX1**
Asynchronous Serial Port 0 Bus Interface Unit Execution Unit Chip-Select Unit Asynchronous Serial Port 1
RD WB A19-A0 MCS3/RFSH AO15-AO8 AD7-AD0 WR RFSH2/ADEN MCS2-MCS0 PCS5/A1 PCS3-PCS0** LCS/ONCE0 PCS6/A2
UCS/ONCE1
ALE
Notes: *All PIO signals are shared with other physical pins. See the pin descriptions beginning on page 27 and Table 2 on page 34 for information on shared functions. ** PWD, INT5, INT6, RTS1/RTR1, and CTS1/ENRX1 are multiplexed with INT2/INTA0, DRQ0, DRQ1, PCS3, and PCS2 respectively. See the pin descriptions beginning on page 27.
Am186/188ES and Am186/188ESLV Microcontrollers
3
PRELIMINARY
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below. Am186ES -40 V C \W LEAD FORMING \W=Trimmed and Formed TEMPERATURE RANGE C=ES Commercial (TC =0C to +100C) C=ESLV Commercial (TA =0C to +70C) I=ES Industrial (TA =-40C to +85C) where: TC = case temperature TA = ambient temperature PACKAGE TYPE V=100-Pin Thin Quad Flat Pack (TQFP) K=100-Pin Plastic Quad Flat Pack (PQFP) SPEED OPTION -20 = 20 MHz -25 = 25 MHz -33 = 33 MHz -40 = 40 MHz DEVICE NUMBER/DESCRIPTION Am186ES High-Performance, 80C186-Compatible, 16-Bit Embedded Microcontroller Am188ES High-Performance, 80C188-Compatible, 16-Bit Embedded Microcontroller Am186ESLV High-Performance, 80L186-Compatible, Low-Voltage, 16-Bit Embedded Microcontroller Am188ESLV High-Performance, 80L188-Compatible, Low-Voltage, 16-Bit Embedded Microcontroller Valid Combinations Valid combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Valid Combinations Am186ES-20 Am186ES-25 Am186ES-33 Am186ES-40 Am188ES-20 Am188ES-25 Am188ES-33 Am188ES-40 Am186ES-20 Am186ES-25 Am188ES-20 Am188ES-25 Am186ESLV-20 Am186ESLV-25 Am188ESLV-20 Am188ESLV-25 VC\W or KC\W
VC\W or KC\W
Note: The industrial version of the Am186ES and Am188ES microcontrollers, as well as the Am186ESLV and Am188ESLV, are available in 20 and 25 MHz operating frequencies only. The Am186ES, Am188ES, Am186ESLV, and Am188ESLV microcontrollers are all functionally the same except for their DC characteristics and available frequencies.
KI\W KI\W VC\W or KC\W VC\W or KC\W
4
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
TABLE OF CONTENTS
Distinctive Characteristics ............................................................................................................ 1 General Description ..................................................................................................................... 1 Am186ES Microcontroller Block Diagram..................................................................................... 2 Am188ES Microcontroller Block Diagram..................................................................................... 3 Ordering Information .................................................................................................................... 4 Related AMD Products ................................................................................................................ 8 Key Features and Benefits ........................................................................................................ 10 Comparing the ES to the 80C186 .............................................................................................. 11 Comparing the ES to the EM ..................................................................................................... 11 TQFP Connection Diagrams and Pinouts .................................................................................. 13 PQFP Connection Diagrams and Pinouts ................................................................................. 19 Logic Symbol--Am186ES Microcontroller ................................................................................. 25 Logic Symbol--Am188ES Microcontroller ................................................................................. 26 Pin Descriptions ......................................................................................................................... 27 Pins That Are Used by Emulators .................................................................................. 27 Pin Terminology ............................................................................................................. 27 A19-A0 .......................................................................................................................... 27 AD15-AD8 (Am186ES Microcontroller) .......................................................................... 27 AO15-AO8 (Am188ES Microcontroller) ........................................................................ 27 AD7-AD0 ....................................................................................................................... 27 ALE ................................................................................................................................ 27 ARDY ............................................................................................................................. 27 BHE/ADEN (Am186ES Microcontroller Only) ................................................................ 28 CLKOUTA ...................................................................................................................... 28 CLKOUTB ...................................................................................................................... 28 CTS0/ENRX0/PIO21 ...................................................................................................... 28 DEN/DS/PIO5 ................................................................................................................ 29 DRQ0/INT5/PIO12 ......................................................................................................... 29 DRQ1/INT6/PIO13 ......................................................................................................... 29 DT/R/PIO4 ..................................................................................................................... 29 GND ............................................................................................................................... 29 HLDA ............................................................................................................................. 29 HOLD ............................................................................................................................. 29 INT0 ............................................................................................................................... 30 INT1/SELECT ................................................................................................................ 30 INT2/INTA0/PWD/PIO31 ............................................................................................... 30 INT3/INTA1/IRQ ............................................................................................................. 30 INT4/PIO30 .................................................................................................................... 31 LCS/ONCE0 ................................................................................................................... 31 MCS0 (MCS0/PIO14) .................................................................................................... 31 MCS2-MCS1 (MCS2/PIO24, MCS1/PIO15) ................................................................. 31 MCS3/RFSH/PIO25 ....................................................................................................... 31 NMI ................................................................................................................................ 32 PCS1-PCS0 (PCS1/PIO17, PCS0/PIO16) .................................................................... 32 PCS2/CTS1/ENRX1/PIO18 ........................................................................................... 32 PCS3/RTS1/RTR1/PIO19 .............................................................................................. 32 PCS5/A1/PIO3 ............................................................................................................... 33 PCS6/A2/PIO2 ............................................................................................................... 33 PIO31-PIO0 (Shared) .................................................................................................... 33 RD .................................................................................................................................. 35 RES ................................................................................................................................ 35 RFSH2/ADEN (Am188ES Microcontroller Only) ............................................................ 35
Am186/188ES and Am186/188ESLV Microcontrollers
5
PRELIMINARY
RTS0/RTR0/PIO20 ........................................................................................................ 35 RXD0/PIO23 .................................................................................................................. 35 RXD1/PIO28 .................................................................................................................. 35 S2-S0 ............................................................................................................................ 35 S6/LOCK/CLKDIV2/PIO29 ............................................................................................. 36 SRDY/PIO6 .................................................................................................................... 36 TMRIN0/PIO11 .............................................................................................................. 36 TMRIN1/PIO0 ................................................................................................................ 36 TMROUT0/PIO10 .......................................................................................................... 36 TMROUT1/PIO1 ............................................................................................................ 36 TXD0/PIO22 ................................................................................................................... 36 TXD1/PIO27 ................................................................................................................... 36 UCS/ONCE1 .................................................................................................................. 36 UZI/PIO26 ...................................................................................................................... 37 VCC ................................................................................................................................ 37 WHB (Am186ES Microcontroller Only) .......................................................................... 37 WLB (Am186ES Microcontroller Only) ........................................................................... 37 WB (Am188ES Microcontroller Only) ............................................................................. 37 WR ................................................................................................................................. 37 X1 ................................................................................................................................... 37 X2 ................................................................................................................................... 37 Functional Description ................................................................................................................ 38 Bus Operation ............................................................................................................................ 39 Bus Interface Unit ...................................................................................................................... 41 Peripheral Control Block (PCB) ................................................................................................. 42 Clock and Power Management .................................................................................................. 44 Chip-Select Unit ......................................................................................................................... 46 Refresh Control Unit .................................................................................................................. 47 Interrupt Control Unit ................................................................................................................. 48 Timer Control Unit ...................................................................................................................... 48 Direct Memory Access (DMA) ................................................................................................... 49 Pulse Width Demodulation ........................................................................................................ 51 Asynchronous Serial Ports ........................................................................................................ 51 Programmable I/O (PIO) Pins .................................................................................................... 52 Absolute Maximum Ratings ....................................................................................................... 53 Operating Ranges ...................................................................................................................... 53 DC Characteristics Over Commercial Operating Ranges .......................................................... 53 Commercial Switching Characteristics and Waveforms ............................................................ 61 TQFP Physical Dimensions ........................................................................................................ 98 PQFP Physical Dimensions ...................................................................................................... 100
6
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
LIST OF FIGURES
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Am186ES Microcontroller Example System Design .............................................. 10 80C186 Microcontroller Example System Design ................................................. 11 Two-Component Address ...................................................................................... 38 Am186ES Microcontroller Address Bus -- Normal Operation................................ 39 Am186ES Microcontroller--Address Bus Disable In Effect ................................... 40 Am188ES Microcontroller Address Bus -- Normal Operation ............................... 40 Am188ES Microcontroller-- Address Bus Disable In Effect................................... 41 Am186ES and Am188ES Microcontrollers Oscillator Configurations .................... 44 Clock Organization ................................................................................................ 45 DMA Unit Block Diagram ....................................................................................... 50 Typical Icc Versus Frequency for the Am186ESLV and Am188ESLV ................... 54 Typical Icc Versus Frequency for the Am186ES and Am188ES............................. 54 Thermal Resistance(C/Watt) ................................................................................ 55 Thermal Characteristics Equations ........................................................................ 55 Typical Ambient Temperatures for PQFP with a 2-Layer Board ............................ 57 Typical Ambient Temperatures for TQFP with a 2-Layer Board ............................ 58 Typical Ambient Temperatures for PQFP with a 4-Layer to 6-Layer Board .......... 59 Typical Ambient Temperatures for TQFP with a 4-Layer to 6-Layer Board ........... 60
LIST OF TABLES
Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Data Byte Encoding ............................................................................................... 28 Numeric PIO Pin Designations .............................................................................. 34 Alphabetic PIO Pin Designations ........................................................................... 34 Bus Cycle Encoding ............................................................................................... 35 Segment Register Selection Rules ........................................................................ 38 Programming Am186ES Microcontroller Bus Width .............................................. 42 Peripheral Control Block Register Map .................................................................. 43 Am186ES Microcontroller Maximum DMA Transfer Rates .................................... 49 Typical Power Consumption for the Am186ESLV and Am188ESLV...................... 54 Thermal Characteristics (C/Watt) ......................................................................... 55 Typical Power Consumption Calculation ............................................................... 56 Junction Temperature Calculation ......................................................................... 56 Typical Ambient Temperatures for PQFP with a 2-Layer Board ............................ 57 Typical Ambient Temperatures for TQFP with a 2-Layer Board ............................ 58 Typical Ambient Temperatures for PQFP with a 4-Layer to 6-Layer Board .......... 59 Typical Ambient Temperatures for TQFP with a 4-Layer to 6-Layer Board ........... 60
Am186/188ES and Am186/188ESLV Microcontrollers
7
PRELIMINARY
Microprocessors AT Peripheral Microcontrollers 186 Peripheral Microcontrollers Am386SX/DX Microprocessors ElanSC310 Microcontroller ElanSC300 Microcontroller Am186EM and Am188EM Microcontrollers Am186EMLV & Am188EMLV Microcontrollers Am486DX Microprocessor AMD-K5TM Microprocessor
K86TM Future Am486 Future 32-bit Future Am186ER and Am188ER Microcontrollers Am186ES and Am188ES Microcontrollers Am186ESLV & Am188ESLV Microcontrollers
ElanSC400 Microcontroller
Am186 and Am188 Future
80C186 and 80C188 Microcontrollers 80L186 and 80L188 Microcontrollers
Time The E86 Family of Embedded Microprocessors and Microcontrollers
RELATED AMD PRODUCTS E86TM Family Devices
Device 80C186 80C188 80L186 80L188 Am186EM Am188EM Am186EMLV Am188EMLV Description 16-bit microcontroller 16-bit microcontroller with 8-bit external data bus Low-voltage, 16-bit microcontroller Low-voltage, 16-bit microcontroller with 8-bit external data bus High-performance, 80C186-compatible, 16-bit embedded microcontroller High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus Am186ES High-performance, 80C186-compatible, 16-bit embedded microcontroller Am188ES High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus Am186ESLV High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller Am188ESLV High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus Am186ER High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller with 32 Kbyte of internal RAM Am188ER High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus and 32 Kbyte of internal RAM ElanTMSC300 ElanSC310 ElanSC400 Am386(R)DX Am386(R)SX Am486(R)DX 8 High-performance, highly integrated, low-voltage, 32-bit embedded microcontroller High-performance, single-chip, 32-bit embedded PC/AT microcontroller Single-chip, low-power, PC/AT-compatible microcontroller High-performance, 32-bit embedded microprocessor with 32-bit external data bus High-performance, 32-bit embedded microprocessor with 16-bit external data bus High-performance, 32-bit embedded microprocessor with 32-bit external data bus Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Related Documents
The following documents provide additional information regarding the Am186ES and Am188ES microcontrollers: n The Am186ES and Am188ES Microcontrollers User's Manual, order# 21096 n The FusionE86
SM
Corporate Applications Hotline (800) 222-9323 44-(0) 1276-803-299 Toll-free for U.S. and Canada U.K. and Europe hotline
World Wide Web Home Page and FTP Site To a c c e s s t h e A M D h o m e pa g e g o t o h tt p : / / www.amd.com. To downl oad d ocu ments and s oftwar e, ftp t o ftp.amd.com and log on as anonymous using your E-mail address as a password. Or via your web browser, go to ftp://ftp.amd.com. Questions, requests, and input concerning AMD's WWW pages can be sent via E-mail to webmaster@amd.com. Documentation and Literature Free E86 family information such as data books, user's man ual s , data sh eets , ap pl ic ati on n otes , th e FusionE86 Partner Solutions Catalog, and other literature is available with a simple phone call. Internationally, contact your local AMD sales office for complete E86 family literature. Literature Ordering (800) 222-9323 (512) 602-5651 (800) 222-9323 Toll-free for U.S. and Canada Direct dial worldwide AMD Facts-On-DemandTM fax information service, toll-free for U.S. and Canada
Catalog, order# 19255
Third-Party Development Support Products
The FusionE86 S M Program of Partnerships for Application Solutions provides the customer with an array of products designed to meet critical time-tomarket needs. Products and solutions available from the AMD FusionE86 partners include emulators, hardware and software debuggers, board-level products, and software development tools, among others. In addition, mature development tools and applications for the x86 platform are widely available in the general marketplace.
Customer Service
The AMD customer service network includes U.S. offices, international offices, and a customer training center. Expert technical assistance is available from the AMD worldwide staff of field application engineers and factory support staff who can answer E86 family hardware and software development questions. Hotline and World Wide Web Support For answers to technical questions, AMD provides a toll-free number for direct access to our corporate applications hotline. Also available is the AMD World Wide Web home page and FTP site, which provides the latest E86 family product information, including technical information and data on upcoming product releases. For technical support questions on all E86 products, send E-mail to lpd.support@amd.com.
Am186/188ES and Am186/188ESLV Microcontrollers
9
PRELIMINARY
KEY FEATURES AND BENEFITS
The Am186ES and Am188ES microcontrollers extend the AMD family of microcontrollers based on the industry-standard x86 architecture. The Am186ES and Am188ES microcontrollers are higher-performance, mo r e i n te g r a te d v e r s i on s of t he 8 0 C1 8 6/ 1 88 microprocessors, offering an attractive migration path. In addition, the Am186ES and Am188ES microcontrollers offer application-specific features that can enhance the system functionality of the Am186EM and Am188EM microcontrollers. Upgrading to the Am186ES and Am188ES microcontrollers is an attractive solution for several reasons: n Minimized total system cost--New peripherals and on-chip system interface logic on the Am186ES and Am188ES microcontrollers reduce the cost of existing 80C186/188 designs. n x86 software compatibility--80C186/188-compatible and upward-compatible with the other members of the AMD E86 family. The x86 architecture is the most widely used and supported computer architecture in the world. n Enhanced performance--The Am186ES and Am188ES microcontrollers increase the performance of 80C186/188 systems, and the nonmultiplexed address bus offers faster, unbuffered access to memory. n Enhanced functionality--The new and enhanced on-chip peripherals of the Am186ES and Am188ES microcontrollers include two asynchronous serial ports, 32 PIOs, a watchdog timer, additional interrupt pins, a pulse width demodulation option, DMA directly to and from the serial ports, 8-bit and 16-bit static bus sizing, a PSRAM controller, a 16-bit reset configuration register, and enhanced chip-select functionality.
shown in Figure 1 achieves 40-MHz CPU operation, while using a 40-MHz crystal. Memory Interface The integrated memory controller logic of the Am186ES and Am188ES microcontrollers provides a direct address bus interface to memory devices. It is not necessary to use an external address latch controlled by the address latch enable (ALE) signal. Individual byte-write-enable signals eliminate the need for external high/low byte-write-enable circuitry. The maximum bank size that is programmable for the memory chip-select signals has been increased to facilitate the use of high-density memory devices. The improved memory timing specifications for the Am186ES and Am188ES microcontrollers allow nowait-state operation with 70-ns memory access times at a 40-MHz CPU clock speed. This reduces overall system cost significantly by allowing the use of a more commonly available memory speed and technology. Figure 1 also shows an implementation of an RS-232 console or modem communications port. The RS-232to-CMOS voltage-level converter is required for the electrical interface with the external device.
Am186ES Microcontroller
X2 X1 WHB WLB
Flash PROM
WE WE Address Data OE CS
40-MHz Crystal
A19-A0
AD15-AD0 RD UCS
Application Considerations
The integration enhancements of the Am186ES and Am188ES microcontrollers provide a highperformance, low-system-cost solution for 16-bit embedded microcontroller designs. The nonmultiplexed address bus eliminates the need for system-support logic to interface memory devices, while the multiplexed address/data bus maintains the value of previously engineered, customer-specific peripherals and circuits within the upgraded design. Figure 1 illustrates an example system design that uses the integrated peripheral set to achieve high performance with reduced system cost. Clock Generation The integrated clock generation circuitry of the Am186ES and Am188ES microcontrollers allows the use of a times-one crystal frequency. The design
PWD Input
Static RAM
PW
WE WE
RS-232 Level Converter
Serial Port 0 Serial Port 1
Address Data OE
LCS
CS
Figure 1. Am186ES Microcontroller Example System Design Direct Memory Interface Example Figure 1 illustrates the Am186ES microcontroller's direct memory interface. The processor A19-A0 bus connects to the memory address inputs, the AD bus
10
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY connects to the data inputs and outputs, and the chip selects connect to the memory chip-select inputs. The RD output connects to the SRAM Output Enable (OE) pin for read operations. Write operations use the byte-write enables connected to the SRAM Write Enable (WE) pins. The example design uses 2-Mbit memory technology (256 Kbytes) to fully populate the available address space. Two flash PROM devices provide 512 Kbytes of nonvolatile program storage, and two static RAM devices provide 512 Kbytes of data storage area.
COMPARING THE ES TO THE 80C186
Figure 1 shows an example system using a 40-MHz A m1 86 ES m i cr o c on tr o ll er . Fi gu r e 2 s ho ws a comparable system implementation with an 80C186. Because of its superior integration, the Am186ES microcontroller system does not require the support devices that are required on the 80C186 example system. In addition, the Am186ES microcontroller provides significantly better performance with its 40MHz clock rate.
40-MHz Crystal
X1
PAL
X2
BHE A0
Am29F200 Flash
WR
LATCH
SRAM
WE WE Address Data OE CS
WE Address Data OE CS
LATCH
ALE AD15-AD0 RD UCS LCS
PIOs Serial Port
RS-232 Level Converter
PCS0 Timer 0-2 INT3 INT2-INT0 DMA 0-1 CLKOUT
20 MHz
Figure 2. 80C186 Microcontroller Example System Design
COMPARING THE ES TO THE EMTABLE1
Compared to the Am186EM and Am188EM microcontrollers, the Am186ES and Am188ES microcontrollers have the following additional features: n Two full-featured asynchronous serial ports n The ability to use DMA to and from the serial ports n Two additional external interrupt signals n Enhancements to the watchdog timer to improve its security and functionality n A pulse width demodulation option n A data strobe bus interface option for DEN n ARDY functionality is changed to allow both edges of ARDY to be asynchronous to the clock
n An option to have all MCS space asserted through MCS0 n On the Am186ES microcontroller, static bus sizing allows UCS space to use a 16-bit data bus, while LCS space can be either 8-bit or 16-bit. All nonUCS and non-LCS memory and I/O accesses can be 8-bit or 16-bit. This capability is available only on the Am186ES microcontroller; the Am188ES microcontroller has a uniform 8-bit access width. n The synchronous serial interface is removed n On the ES, row addresses are not driven on DRAM refreshes
Two Asynchronous Serial Ports
The Am186ES and Am188ES microcontrollers have two identical asynchronous serial ports. Each serial
Am186/188ES and Am186/188ESLV Microcontrollers
11
PRELIMINARY port operates independently and has the following features: n Full-duplex operation n 7-bit, 8-bit, or 9-bit operation n Even, odd, or no parity n One stop bit n Long or short break character recognition n Parity error, framing error, overrun error, and break character detection n Configurable hardware handshaking with CTS, RTS, ENRX, and RTR n DMA to and from the serial ports n Separate maskable interrupts for each port n Multiprocessor 9-bit protocol n Independent baud rates for each port n Maximum baud rate of 1/16th of the CPU clock rate n Double-buffered transmit and receive n Programmable interrupt generation for transmit, receive, and/or error detection
Pulse Width Demodulation Option
The Am186ES and Am188ES microcontrollers provide pulse width demodulation by adding a Schmitt trigger buffer to the INT2 pin. If pulse width demodulation mode is enabled, timer 0 and timer 1 are used to determine the pulse width of the signal period. Separate maskable interrupts are generated on the rising and falling edge of the pulse input. In pulse width demodulation mode, the external pins INT4, TIMERIN0, and TIMERIN1 are available as PIOs, but not as their normal functionality.
Data Strobe Bus Interface Option
The Am186ES and Am188ES microcontrollers provide a truly asynchronous bus interface that allows the use of 68K-type peripher als . This implementation combines a new DS data strobe signal (multiplexed with DEN) with a truly asynchronous ARDY ready input. When DS is asserted, the data and address signals are valid. A chip-select signal, ARDY, DS, and other control signals (RD/WR) can control the interface of 68K-type external peripherals to the AD bus.
DMA and the Serial Ports
The Am186ES and Am188ES microcontrollers can DMA directly to and from the serial ports. DMA and serial port transfer is accomplished by programming the DMA controller to perform transfers between a data source in memory or I/O space and a serial port transmit or receive register. The two DMA channels can support one serial port in full-duplex mode or two serial ports in half-duplex mode.
MCS0 Asserted for All MCS Option
When the MCS0- onl y mode is enabl ed in the Am186ES and Am188ES microcontrollers, the entire middle chip-select range is selected through MCS0. The remaining MCS pins are available as PIOs or alternate functions.
ARDY Functionality Change
In the Am186ES and Am188ES microcontrollers, the ARDY signal is changed to allow both edges of ARDY to be asynchronous to the clock. On the Am186EM and Am188EM microcontrollers, proper operation was not guaranteed if ARDY did not meet the specification relative to the clock for all edges except the falling edge of a normally-ready system (relative to the rising edge of CLKOUTA). To guarantee the number of wait states inserted, ARDY or SRDY must be synchronized to CLKOUTA. If the falling edge of ARDY is not synchronized to CLKOUTA as specified, an additional clock period can be added.
Two Additional External Interrupts
Two new interrupts, INT5 and INT6, are multiplexed with the DMA request signals, DRQ0 and DRQ1. If a DMA channel is not enabled, or if it is not using external synchronization, then the associated pin can be used as an external interrupt. INT5 and INT6 can also be used in conjunction with the DMA terminal count interrupts.
Enhanced Watchdog Timer
The Am186ES and Am188ES microcontrollers provide a true watchdog timer that can be configured to generate either an NMI interrupt or a system reset upon timeout. The watchdog timer supports up to a 1.67-second timeout period in a 40-MHz system. After reset, the watchdog timer defaults to enabled and can be modified or disabled only one time. If the timer is not disabled, the application program must periodically reset the timer by writing a specific key sequence to the watchdog timer control register. If the timer is not reset before it counts down, either an NMI or a system reset is issued, depending on the configuration of the timer.
8-Bit and 16-Bit Bus Sizing Option
The Am186ES microcontroller allows switchable 8-bit and 16-bit bus sizing based on chip selects for three chip-select regions. The Am188ES microcontroller supports only 8-bit data widths. On the Am186ES microcontroller, the upper chip select (UCS) region is always 16 bits, so memory used for boot code at power-on reset must be 16-bit memory. However, the LCS memory region, memory that is not UCS or LCS (including memory mapped to MCS and PCS), and I/O space can be independently configured as 8-bit or 16-bit.
12
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
TQFP CONNECTION DIAGRAMS AND PINOUTS Am186ES Microcontroller Top Side View--100-Pin Thin Quad Flat Pack (TQFP)
PCS2/CTS1/ENRX1 PCS3 /RTS1/RTR1
MCS3/ RFSH MCS2/PIO24 VCC
DRQ0/INT5 DRQ1/INT6
100 99
98 97
96 95
94 93
92 91
90 89
88 87
86 85
84 83
VCC PCS 5/A1
82 81
80 79
UCS / ONCE1 INT0
PCS 6/A2 LCS / ONCE 0
PCS0
PCS1 GND
RES GND
78
77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
INT2/INTA0/PWD INT3/INTA1/IRQ
INT1/ SELECT
TMROUT1 TMRIN1/PIO0
TMRIN0 TMROUT0
AD0 AD8 AD1 AD9 AD2 AD10 AD3 AD11 AD4 AD12 AD5 GND AD13 AD6 V CC AD14 AD7 AD15 S6/LOCK/CLKDIV2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 30 31 36 37 38 39 28 29 32 33 34 35 40 41 44 45 42 43 46 47 48 49 50
INT4 MCS1 MCS0 DEN/DS DT/R NMI SRDY HOLD HLDA WLB WHB GND A0 A1 VCC A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
Am186ES Microcontroller
UZI
TXD1 RXD1 CTS0/ENRX0 RXD0 TXD0
GND X1 X2
CLKOUTB GND A19 A18
VCC A17
A16 A15
A14 A13
RTS0/RTR0
BHE/ADEN
Note: Pin 1 is marked for orientation.
Am186/188ES and Am186/188ESLV Microcontrollers
VCC CLKOUTA
WR RD ALE ARDY
A12
S2 S1
S0
13
PRELIMINARY
TQFP PIN ASSIGNMENTS--Am186ES Microcontroller (Sorted by Pin Number)
Pin No. 1 2 3 4 5 6 7 8 9 10 Name AD0 AD8 AD1 AD9 AD2 AD10 AD3 AD11 AD4 AD12 Pin No. 26 27 28 29 30 31 32 33 34 35 Name RTS0/RTR0/ PIO20 BHE/ADEN WR RD ALE ARDY S2 S1 S0 GND Pin No. 51 52 53 54 55 56 57 58 59 60 Name A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 Pin No. 76 77 78 79 80 81 82 83 84 85 Name INT3/INTA1/IRQ INT2/INTA0/PWD/ PIO31 INT1/SELECT INT0 UCS/ONCE1 LCS/ONCE0 PCS6/A2/PIO2 PCS5/A1/PIO3 VCC PCS3/RTS1/ RTR1/ PIO19 PCS2/CTS1/ ENRX1/PIO18 GND PCS1/PIO17 PCS0/PIO16 VCC MCS2/PIO24 MCS3/RFSH/ PIO25 GND RES TMRIN1/PIO0 TMROUT1/PIO1 TMROUT0/PIO10 TMRIN0/PIO11 DRQ1/INT6/PIO13 DRQ0/INT5/PIO12
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
AD5 GND AD13 AD6 VCC AD14 AD7 AD15 S6/LOCK/CLKDIV2/ PIO29 UZI/PIO26 TXD1/PIO27 RXD1/PIO28 CTS0/ENRX0/PIO21 RXD0/PIO23 TXD0/PIO22
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
X1 X2 VCC CLKOUTA CLKOUTB GND A19/PIO9 A18/PIO8 VCC A17/PIO7 A16 A15 A14 A13 A12
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
VCC A1 A0 GND WHB WLB HLDA HOLD SRDY/PIO6 NMI DT/R/PIO4 DEN/DS/PIO5 MCS0/PIO14 MCS1/PIO15 INT4/PIO30
86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
14
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
TQFP PIN DESIGNATIONS--Am186ES Microcontroller (Sorted by Pin Name)
Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17/PIO7 A18/PIO8 A19/PIO9 AD0 AD1 AD2 AD3 AD4 No. 63 62 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 43 42 1 3 5 7 9 Pin Name AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 ALE ARDY BHE/ADEN CLKOUTA CLKOUTB CTS0/ENRX0/ PIO21 DEN/DS/PIO5 DRQ0/INT5/PIO12 DRQ1/INT6/PIO13 DT/R/PIO4 GND GND GND GND No. 11 14 17 2 4 6 8 10 13 16 18 30 31 27 39 40 23 72 100 99 71 12 35 41 64 Pin Name GND GND HLDA HOLD INT0 INT1/SELECT INT2/INTA0/ PWD/PIO31 INT3/INTA1/IRQ INT4/PIO30 LCS/ONCE0 MCS0/PIO14 MCS1/PIO15 MCS2/PIO24 MCS3/RFSH/PIO25 NMI PCS0/PIO16 PCS1/PIO17 PCS2/CTS1/ ENRX1/PIO18 PCS3/RTS1/RTR1/ PIO19 PCS5/A1/PIO3 PCS6/A2/PIO2 RD RES RTS0/RTR0/PIO20 RXD0/PIO23 No. 87 93 67 68 79 78 77 76 75 81 73 74 91 92 70 89 88 86 85 83 82 29 94 26 24 Pin Name RXD1 S0 S1 S2 S6/LOCK/ CLKDIV2/PIO29 SRDY/PIO6 TMRIN0/PIO11 TMRIN1/PIO0 TMROUT0/ PIO10 TMROUT1/PIO1 TXD0/PIO22 TXD1 UCS/ONCE1 UZI/PIO26 VCC VCC VCC VCC VCC VCC WHB WLB WR X1 X2 No. 22 34 33 32 19 69 98 95 97 96 25 21 80 20 15 38 44 61 84 90 65 66 28 36 37
Am186/188ES and Am186/188ESLV Microcontrollers
15
PRELIMINARY
CONNECTION DIAGRAM Am188ES Microcontroller Top Side View--100-Pin Thin Quad Flat Pack (TQFP)
PCS 2/CTS1/ENRX1 PCS 3 /RTS1/RTR1 INT1/ SELECT INT2/INTA0/PWD 78 77 INT3/INTA1/IRQ 76 75 74 73 72 71 70 69 68 67 66 65 64
DRQ1/INT6 TMRIN0
MCS2 VCC PCS 0
100
94
93 92
91 90 89
88 87
86 85
84 83
VCC PCS 5/A1
82 81
80 79
99 98
97 96 95
UCS / ONCE1 INT0
TMROUT0 TMROUT1 TMRIN1
PCS 6/A2 LCS / ONCE 0
GND MCS3/ RFSH
DRQ0/INT5
PCS 1 GND
RES
AD0 AO8 AD1 AO9 AD2 AO10 AD3 AO11 AD4 AO12 AD5 GND AO13 AD6 VCC AO14 AD7 AO15 S6/LOCK/CLKDIV2 UZI TXD1 RXD1 CTS0/ENRX0 RXD0 TXD0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 29 30 41 42 43 44 45 46 47 48 27 28 31 32 33 34 35 36 37 38 39 40 49 50
INT4 MCS1
MCS0 DEN/DS DT/R
NMI SRDY HOLD HLDA WB
GND
GND A0 A1 VCC A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
Am188ES Microcontroller
63 62 61 60 59 58 57 56 55 54 53 52 51
RFSH2/ADEN WR
RD ALE
RTS0/RTR0
CLKOUTB GND A19
ARDY
VCC CLKOUTA
A18
VCC A17 A16
A15 A14
Note: Pin 1 is marked for orientation.
16
Am186/188ES and Am186/188ESLV Microcontrollers
GND X1 X2
A13 A12
S2
S1 S0
PRELIMINARY
TQFP PIN DESIGNATIONS--Am188ES Microcontroller (Sorted by Pin Number)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name AD0 AO8 AD1 AO9 AD2 AO10 AD3 AO11 AD4 AO12 AD5 GND AO13 AD6 VCC AO14 AD7 AO15 S6/LOCK/ CLKDIV2/PIO29 UZI/PIO26 TXD1/PIO27 RXD1/PIO28 CTS0/ENRX0/ PIO21 RXD0/PIO23 TXD0/PIO22 Pin No. Name 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 RTS0/RTR0/ PIO20 RFSH2/ADEN WR RD ALE ARDY S2 S1 S0 GND X1 X2 VCC CLKOUTA CLKOUTB GND A19/PIO9 A18/PIO8 VCC A17/PIO7 A16 A15 A14 A13 A12 Pin No. Name 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 VCC A1 A0 GND GND WB HLDA HOLD SRDY/PIO6 NMI DT/R/PIO4 DEN/DS/PIO5 MCS0/PIO14 MCS1/PIO15 INT4/PIO30 Pin No. Name 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 INT3/INTA1/IRQ INT2/INTA0/ PWD/PIO31 INT1/SELECT INT0 UCS/ONCE1 LCS/ONCE0 PCS6/A2/PIO2 PCS5/A1/PIO3 VCC PCS3/RTS1/RTR1/ PIO19 PCS2/CTS1/ENRX1/ PIO18 GND PCS1/PIO17 PCS0/PIO16 VCC MCS2/PIO24 MCS3/RFSH/PIO25 GND RES TMRIN1/PIO0 TMROUT1/PIO1 TMROUT0/PIO10 TMRIN0/PIO11 DRQ1/INT6/PIO13 DRQ0/INT5/PIO12
Am186/188ES and Am186/188ESLV Microcontrollers
17
PRELIMINARY
TQFP PIN DESIGNATIONS--Am188ES Microcontroller (Sorted by Pin Name)
Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17/PIO7 No. 63 62 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 Pin Name AD5 AD6 AD7 ALE AO8 AO9 AO10 AO11 AO12 AO13 AO14 AO15 ARDY CLKOUTA CLKOUTB CTS0/ENRX0/ PIO21 DEN/DS/PIO5 DRQ0/INT5/ PIO12 DRQ1/INT6/ PIO13 DT/R/PIO4 GND GND GND GND GND No. 11 14 17 30 2 4 6 8 10 13 16 18 31 39 40 23 72 100 Pin Name GND GND HLDA HOLD INT0 INT1/SELECT INT2/INTA0/ PWD/PIO31 INT3/INTA1/IRQ INT4/PIO30 LCS/ONCE0 MCS0/PIO14 MCS1/PIO15 MCS2/PIO24 MCS3/RFSH/ PIO25 NMI PCS0/PIO16 PCS1/PIO17 PCS2/CTS1/ ENRX1/PIO18 PCS3/RTS1/ RTR1/ PIO19 PCS5/A1/PIO3 PCS6/A2/PIO2 RD RES RFSH2/ADEN RTS0/RTR0/ PIO20 No. 87 93 67 68 79 78 77 76 75 81 73 74 91 92 70 89 88 86 Pin Name RXD0/PIO23 RXD1/PIO28 S0 S1 S2 S6/LOCK/ CLKDIV2/PIO29 SRDY/PIO6 TMRIN0/PIO11 TMRIN1/PIO0 TMROUT0/PIO10 TMROUT1/PIO1 TXD0/PIO22 TXD1/PIO27 UCS/ONCE1 UZI/PIO26 VCC VCC VCC No. 24 22 34 33 32 19 69 98 95 97 96 25 21 80 20 15 38 44
A18/PIO8 A19/PIO9 AD0 AD1 AD2 AD3 AD4
43 42 1 3 5 7 9
99 71 12 35 41 64 65
85 83 82 29 94 27 26
VCC VCC VCC WB WR X1 X2
61 84 90 66 28 36 37
18
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
PQFP CONNECTION DIAGRAMS AND PINOUTS Am186ES Microcontroller Top Side View--100-Pin Plastic Quad Flat Pack (PQFP)
S6/LOCK/CLKDIV2
CTS0/ENRX0 RXD1 TXD1 UZI
AD12 AD4
AD7 AD14
AD15
AD13
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
AD11 AD3
GND AD5
VCC AD6
83
82
81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
RXD0 TXD0 RTS0/RTR0 BHE/ADEN WR
RD ALE
ARDY S2 S1
S0
GND X1 X2 VCC CLKOUTA CLKOUTB GND A19 A18 VCC A17 A16 A15 A14 A13 A12 A11 A10 A9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
SRDY
Note: Pin 1 is marked for orientation.
Am186/188ES and Am186/188ESLV Microcontrollers
DEN/DS MCS0
HOLD
HLDA
NMI DT/R
VCC A1 A0 GND
WHB WLB
A8 A7
A6
A5
A4
A3
A2
50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
AD10 AD2 AD9
AD1 AD8 AD0 DRQ0/INT5 DRQ1/INT6 TMRIN0 TMROUT0 TMROUT1 TMRIN1 RES GND MCS3/RFSH
Am186ES Microcontroller
MCS2 VCC PCS0 PCS1 GND PCS2/CTS1/ENRX1 PCS3/RTS1/RTR1
VCC PCS5/A1 PCS6/A2 LCS/ONCE0 UCS/ONCE1 INT0 INT1/SELECT INT2/INTA0/PWD INT3/INTA1/IRQ INT4 MCS1
19
PRELIMINARY
PQFP PIN DESIGNATIONS--Am186ES Microcontroller (Sorted by Pin Number)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name RXD0/PIO23 TXD0/PIO22 RTS0/RTR0/ PIO20 BHE/ADEN WR RD ALE ARDY S2 S1 S0 GND X1 X2 VCC CLKOUTA CLKOUTB GND A19/PIO9 A18/PIO8 VCC A17/PIO7 A16 A15 A14 Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 VCC A1 A0 GND WHB WLB HLDA HOLD SRDY/PIO6 NMI DT/R/PIO4 DEN/DS/PIO5 MCS0/PIO14 Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Name MCS1/PIO15 INT4/PIO30 INT3/INTA1/IRQ INT2/INTA0/ PWD/PIO31 INT1/SELECT INT0 UCS/ONCE1 LCS/ONCE0 PCS6/A2/PIO2 PCS5/A1/PIO3 VCC PCS3/RTS1/RTR1/ PIO19 PCS2/CTS1/ ENRX1/PIO18 GND PCS1/PIO17 PCS0/PIO16 VCC MCS2/PIO24 MCS3/RFSH/PIO25 GND RES TMRIN1/PIO0 TMROUT1/PIO1 TMROUT0/PIO10 TMRIN0/PIO11 Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name DRQ1/INT6/PIO13 DRQ0/INT5/PIO12 AD0 AD8 AD1 AD9 AD2 AD10 AD3 AD11 AD4 AD12 AD5 GND AD13 AD6 VCC AD14 AD7 AD15 S6/LOCK/ CLKDIV2/PIO29 UZI/PIO26 TXD1/PIO27 RXD1/PIO28 CTS0/ENRX0/PIO21
20
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
PQFP PIN DESIGNATIONS--Am186ES Microcontroller (Sorted by Pin Name)
Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17/PIO7 A18/PIO8 A19/PIO9 AD0 AD1 AD2 AD3 AD4 No. 40 39 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 20 19 78 80 82 84 86 Pin Name AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 ALE ARDY BHE/ADEN CLKOUTA CLKOUTB CTS0/ENRX0/ PIO21 DEN/DS/PIO5 DRQ0/INT5/PIO12 DRQ1/INT6/PIO13 DT/R/PIO4 GND GND GND GND No. 88 91 94 79 81 83 85 87 90 93 95 7 8 4 16 17 100 49 77 76 48 12 18 41 64 Pin Name GND GND HLDA HOLD INT0 INT1/SELECT INT2/INTA0/ PWD/PIO31 INT3/INTA1/IRQ INT4/PIO30 LCS/ONCE0 MCS0/PIO14 MCS1/PIO15 MCS2/PIO24 MCS3/RFSH/PIO25 NMI PCS0/PIO16 PCS1/PIO17 PCS2/CTS1/ENRX1/ PIO18 PCS3/RTS1/RTR1/ PIO19 PCS5/A1/PIO3 PCS6/A2/PIO2 RD RES RTS0/RTR0/PIO20 RXD0/PIO23 No. 70 89 44 45 56 55 54 53 52 58 50 51 68 69 47 66 65 63 62 60 59 6 71 3 1 Pin Name RXD1/PIO28 S0 S1 S2 S6/LOCK/ CLKDIV2/PIO29 SRDY/PIO6 TMRIN0/PIO11 TMRIN1/PIO0 TMROUT0/ PIO10 TMROUT1/PIO1 TXD0/PIO22 TXD1/PIO27 UCS/ONCE1 UZI/PIO26 VCC VCC VCC VCC VCC VCC WHB WLB WR X1 X2 No. 99 11 10 9 96 46 75 72 74 73 2 98 57 97 15 21 38 61 67 92 42 43 5 13 14
Am186/188ES and Am186/188ESLV Microcontrollers
21
PRELIMINARY
CONNECTION DIAGRAM Am188ES Microcontroller Top Side View--100-Pin Plastic Quad Flat Pack (PQFP)
S6/LOCK/CLKDIV2
CTS0/ENRX0 RXD1 TXD1
AO12 AD4
AD7 AO14
AO15
AO13
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
AO11 AD3
GND AD5
83
82
81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
RXD0 TXD0 RTS0/RTR0
RFSH2/ADEN WR RD
ALE ARDY S2 S1
S0
GND X1 X2 VCC CLKOUTA CLKOUTB GND A19 A18 VCC A17 A16 A15 A14 A13 A12 A11 A10 A9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
SRDY
Note: Pin 1 is marked for orientation.
22
Am186/188ES and Am186/188ESLV Microcontrollers
DEN/DS MCS0
HLDA
HOLD
NMI DT/R
VCC A1
A0 GND
GND WB
A8 A7
A6
A5
A4
A3 A2
50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
AO10 AD2 AO9
AD6
UZI
VCC
AD1 AO8 AD0 DRQ0/INT5 DRQ1/INT6 TMRIN0 TMROUT0 TMROUT1 TMRIN1 RES GND MCS3/RFSH
Am188ES Microcontroller
MCS2 VCC PCS0 PCS1 GND PCS2/CTS1/ENRX1 PCS3/RTS1/RTR1
VCC PCS5/A1 PCS6/A2 LCS/ONCE0 UCS/ONCE1 INT0 INT1/SELECT INT2/INTA0/PWD
INT3/INTA1/IRQ
INT4 MCS1
PRELIMINARY
PQFP PIN DESIGNATIONS--Am188ES Microcontroller (Sorted by Pin Number)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name RXD0/PIO23 TXD0/PIO22 RTS0/RTR0/ PIO20 RFSH2/ADEN WR RD ALE ARDY S2 S1 S0 GND X1 X2 VCC CLKOUTA CLKOUTB GND A19/PIO9 A18/PIO8 VCC A17/PIO7 A16 A15 A14 Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 VCC A1 A0 GND GND WB HLDA HOLD SRDY/PIO6 NMI DT/R/PIO4 DEN/DS/PIO5 MCS0/PIO14 Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Name MCS1/PIO15 INT4/PIO30 INT3/INTA1/IRQ INT2/INTA0/ PWD/PIO31 INT1/SELECT INT0 UCS/ONCE1 LCS/ONCE0 PCS6/A2/PIO2 PCS5/A1/PIO3 VCC PCS3/RTS1/RTR1/ PIO19 PCS2/CTS1/ENRX1/ PIO18 GND PCS1/PIO17 PCS0/PIO16 VCC MCS2/PIO24 MCS3/RFSH/PIO25 GND RES TMRIN1/PIO0 TMROUT1/PIO1 TMROUT0/PIO10 TMRIN0/PIO11 Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name DRQ1/INT6/PIO13 DRQ0/INT5/PIO12 AD0 AO8 AD1 AO9 AD2 AO10 AD3 AO11 AD4 AO12 AD5 GND AO13 AD6 VCC AO14 AD7 AO15 S6/LOCK/ CLKDIV2/PIO29 UZI/PIO26 TXD1/PIO27 RXD1/PIO28 CTS0/ENRX0/PIO21
Am186/188ES and Am186/188ESLV Microcontrollers
23
PRELIMINARY
PQFP PIN DESIGNATIONS--Am188ES Microcontroller (Sorted by Pin Name)
Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17/PIO7 A18/PIO8 A19/PIO9 AD0 AD1 AD2 AD3 AD4 No. 40 39 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 20 19 78 80 82 84 86 Pin Name AD5 AD6 AD7 ALE AO8 AO9 AO10 AO11 AO12 AO13 AO14 AO15 ARDY CLKOUTA CLKOUTB CTS0/ENRX0/ PIO21 DEN/DS/PIO5 DRQ0/INT5/PIO12 DRQ1/INT6/PIO13 DT/R/PIO4 GND GND GND GND GND No. 88 91 94 7 79 81 83 85 87 90 93 95 8 16 17 100 49 77 76 48 12 18 41 42 64 Pin Name GND GND HLDA HOLD INT0 INT1/SELECT INT2/INTA0/ PWD/PIO31 INT3/INTA1/IRQ INT4/PIO30 LCS/ONCE0 MCS0/PIO14 MCS1/PIO15 MCS2/PIO24 MCS3/RFSH/PIO25 NMI PCS0/PIO16 PCS1/PIO17 PCS2/CTS1/ENRX1/ PIO18 PCS3/RTS1/RTR1/ PIO19 PCS5/A1/PIO3 PCS6/A2/PIO2 RD RES RFSH2/ADEN RTS0/RTR0/PIO20 No. 70 89 44 45 56 55 54 53 52 58 50 51 68 69 47 66 65 63 62 60 59 6 71 4 3 Pin Name RXD0/PIO23 RXD1/PIO28 S0 S1 S2 S6/LOCK/ CLKDIV2/PIO29 SRDY/PIO6 TMRIN0/PIO11 TMRIN1/PIO0 TMROUT0/ PIO10 TMROUT1/PIO1 TXD0/PIO22 TXD1/PIO27 UCS/ONCE1 UZI/PIO26 VCC VCC VCC VCC VCC VCC WB WR X1 X2 No. 1 99 11 10 9 96 46 75 72 74 73 2 98 57 97 15 21 38 61 67 92 43 5 13 14
24
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
LOGIC SYMBOL--Am186ES MICROCONTROLLER
X1 Clocks X2 CLKOUTA CLKOUTB RES DRQ1/INT6 DRQ0/INT5 INT4 INT3/INTA1/IRQ INT2/INTA0/PWD
*
Reset Control and Interrupt Service
*
*
Address and Address/Data Buses
20 16
A19-A0 AD15-AD0 S6/LOCK/CLKDIV2 UZI
INT1/SELECT INT0 NMI
* *
PCS6/A2 ALE 3 S2-S0 HOLD HLDA RD WR Bus Control PCS5/A1 PCS3/RTS1/RTR1 PCS2/CTS1/ENRX1 PCS1-PCS0 LCS/ONCE0 MCS3/RFSH MCS2-MCS0 UCS/ONCE1 3 2
* * * * *
Memory and Peripheral Control
* *
* *
DT/R DEN/DS ARDY
*
SRDY BHE/ADEN WHB WLB TXD0 DRQ1/INT6 DRQ0/INT5
* *
DMA Control
* * * * * * * *
Asynchronous Serial Port Control
*
Timer Control
TMRIN0 TMROUT0 TMRIN1 TMROUT1 32 shared
RXD0
* * *
CTS0/ENRX0 RTS0/RTR0
TXD1 RXD1
Programmable I/O Control
PCS2/CTS1/ENRX1
PIO32-PIO0
**
PCS3/RTS1/RTR1
Notes: * These signals are the normal function of a pin that can be used as a PIO. See Pin Descriptions beginning on page 27 and Table 2 on page 34 for information on shared function. ** All PIO signals are shared with other physical pins.
Am186/188ES and Am186/188ESLV Microcontrollers
25
PRELIMINARY
LOGIC SYMBOL--Am188ES MICROCONTROLLER
X1 Clocks X2 CLKOUTA CLKOUTB RES DRQ1/INT6 DRQ0/INT5 INT4 INT3/INTA1/IRQ INT2/INTA0/PWD
*
Reset Control and Interrupt Service
*
*
20 8
A19-A0 AO15-AO8 AD7-AD0 S6/LOCK/CLKDIV2 UZI
INT1/SELECT INT0 NMI
Address and Address/Data Buses
8
* *
PCS6/A2 PCS5/A1
* * * *
2
ALE 3 S2-S0 HOLD HLDA RD Bus Control WR
PCS3/RTS1/RTR1 PCS2/CTS1/ENRX1 PCS1-PCS0 LCS/ONCE0 MCS3/RFSH MCS2-MCS0 UCS/ONCE1 3
*
Memory and Peripheral Control
* *
* *
DT/R DEN/DS ARDY
*
SRDY RFSH2/ADEN WB
DRQ1/INT6 DRQ0/INT5
* *
DMA Control
TXD0
* * * * * * * *
Asynchronous Serial Port Control
*
Timer Control
TMRIN0 TMROUT0 TMRIN1 TMROUT1
RXD0
* * *
CTS0/ENRX0 RTS0/RTR0
TXD1 RXD1
Programmable I/O Control
**
32 shared
PCS2/CTS1/ENRX1
PIO32-PIO0
PCS3/RTS1/RTR1
Notes: * These signals are the normal function of a pin that can be used as a PIO. See Pin Descriptions beginning on page 27 and Table 2 on page 34 for information on shared function. ** All PIO signals are shared with other physical pins.
26
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
PIN DESCRIPTIONS Pins That Are Used by Emulators
The following pins are used by emulators: A19-A0, AO15-AO8, AD7-AD0, ALE, BHE/ADEN (on the 186), CLKOUTA, RFSH2/ADEN (on the 188), RD, S2-S0, S6/LOCK/CLKDIV2, and UZI. Emulators require S6/LOCK/CLKDIV2 and UZI to be configured in their normal functionality as S6 and UZI, not as PIOs. If BHE/ADEN (on the 186) or RFSH2/ ADEN (on the 188) is held Low during the rising edge of RES, S6 and UZI are configured in their normal functionality.
During a power-on reset, the address and data bus pins (AD15-AD0 for the 186, AO15-AO8 and AD7- AD0 for the 188) can also be used to load system configuration information into the internal reset configuration register. AO15-AO8--When the address bus is enabled on the Am188ES microcontroller, via the AD bit in the UMCS and LMCS registers, the address-only bus (AO15- AO8) contains valid high-order address bits from bus cycles t1-t4. These outputs are floated during a bus hold or reset. On the Am188ES microcontroller, AO15-AO 8 combine with AD7-AD0 to form a complete multiplexed address bus while AD7-AD0 is the 8-bit data bus.
Pin Terminology
The following terms are used to describe the pins: Input--An input-only pin. Output--An output-only pin. Input/Output--A pin that can be either input or output. Synchronous--Synchronous inputs must meet setup and hold times in relation to CLKOUTA. Synchronous outputs are synchronous to CLKOUTA. Asynchronous--Inputs or outputs that are asynchronous to CLKOUTA.
AD7-AD0
Address and Data Bus (input/output, three-state, synchronous, level-sensitive) These time-multiplexed pins supply partial memory or I/O addresses, as well as data, to the system. This bus supplies the low-order 8 bits of an address to the system during the first period of a bus cycle (t1), and it supplies data to the system during the remaining periods of that cycle (t2, t3, and t4). In 8-bit mode on the Am188ES microcontroller, AD7-AD0 supplies the data. The address phase of these pins can be disabled. See the ADEN description with the BHE/ADEN pin. When WLB is deasserted, these pins are three-stated during t2, t3, and t4. During a bus hold or reset condition, the address and data bus is in a high-impedance state. During a power-on reset, the address and data bus pins (AD15-AD0 for the 186, AO15-AO8 and AD7- AD0 for the 188) can also be used to load system configuration information into the internal reset configuration register.
A19-A0 (A19/PIO9, A18/PIO8, A17/PIO7)
Address Bus (output, three-state, synchronous) These pins supply nonmultiplexed memory or I/O addresses to the system one half of a CLKOUTA period earlier than the multiplexed address and data bus (AD15-AD0 on the 186 or AO15-AO8 and AD7- AD0 on the 188). During a bus hold or reset condition, the address bus is in a high-impedance state.
AD15-AD8 (Am186ES Microcontroller) AO15-AO8 (Am188ES Microcontroller)
Address and Data Bus (input/output, three-state, synchronous, level-sensitive) Address-Only Bus (output, three-state, synchronous, level-sensitive) AD15-AD8--On the Am186ES microcontroller, these time-multiplexed pins supply memory or I/O addresses and data to the system. This bus can supply an address to the system during the first period of a bus cycle (t1). It supplies data to the system during the remaining periods of that cycle (t2, t3, and t4). The address phase of these pins can be disabled. See the ADEN description with the BHE/ADEN pin. When WHB is deasserted, these pins are three-stated during t2, t3, and t4. During a bus hold or reset condition, the address and data bus is in a high-impedance state.
ALE
Address Latch Enable (output, synchronous) This pin indicates to the system that an address appears on the address and data bus (AD15-AD0 for the 186 or AO15-AO8 and AD7-AD0 for the 188). The address is guaranteed to be valid on the trailing edge of ALE. This pin is three-stated during ONCE mode. This pin is not three-stated during a bus hold or reset.
ARDY
Asynchronous Ready (input, asynchronous, level-sensitive) This pin is a true asynchronous ready that indicates to the microcontroller that the addressed memory space or I/O device will complete a data transfer. The ARDY
Am186/188ES and Am186/188ESLV Microcontrollers
27
PRELIMINARY pin is asynchronous to CLKOUTA and is active High. To guarantee the number of wait states inserted, ARDY or SRDY must be synchronized to CLKOUTA. If the falling edge of ARDY is not synchronized to CLKOUTA as specified, an additional clock period can be added. To always assert the ready condition to the microcontroller, tie ARDY High. If the system does not use ARDY, tie the pin Low to yield control to SRDY. pullup resistor on BHE/ADEN so no external pullup is required. This mode of operation reduces power consumption. If BHE/ADEN is held Low on power-on reset, the AD bus drives both addresses and data, regardless of the DA bit setting. The pin is sampled on the rising edge of RE S . ( S 6 an d U Z I a l s o a s s u me th e i r n o r m al functionality in this instance. See Table 2 on page 34.)
BHE/ADEN (Am186ES Microcontroller Only)
Bus High Enable (three-state, output, synchronous) Address Enable (input, internal pullup) BHE--During a memory access, this pin and the leastsignificant address bit (AD0 or A0) indicate to the system which bytes of the data bus (upper, lower, or both) participate in a bus cycle. The BHE/ADEN and AD0 pins are encoded as shown in Table 1.
Note: On the Am188ES microcontroller, AO15-AO8 are driven during the t2-t4 bus cycle, regardless of the setting of the DA bit in the UMCS and LMCS registers.
CLKOUTA
Clock Output A (output, synchronous) This pin supplies the internal clock to the system. Depending on the value of the system configuration register (SYSCON), CLKOUTA operates at either the PLL frequency, the power-save frequency, or is threestated. CLKOUTA remains active during reset and bus hold conditions. All AC timing specs that use a clock relate to CLKOUTA.
Table 1. Data Byte Encoding
BHE 0 0 1 1 AD0 0 1 0 1 Type of Bus Cycle Word Transfer High Byte Transfer (Bits 15-8) Low Byte Transfer (Bits 7-0) Refresh
CLKOUTB
Clock Output B (output, synchronous) This pin supplies an additional clock with a delayed output compared to CLKOUTA. Depending upon the value of the system configuration register (SYSCON), CLKOUTB operates at either the PLL frequency, the power-save frequency, or is three-stated. CLKOUTB remains active during reset and bus hold conditions. CLKOUTB is not used for AC timing specs.
BHE is asserted during t 1 and remains asserted through t3 and tW. BHE does not need to be latched. BHE floats during bus hold and reset. On the Am186ES microcontroller, WLB and WHB implement the functionality of BHE and AD0 for high and low byte-write enables. BHE/ADEN also signals DRAM refresh cycles when using the multiplexed address and data (AD) bus. A refresh cycle is indicated when both BHE/ADEN and AD0 are High. During refresh cycles, the A bus and the AD bus are not guaranteed to provide the same address during the address phase of the AD bus cycle. For this reason, the A0 signal cannot be used in place of the AD0 signal to determine refresh cycles. PSRAM refreshes also provide an additional RFSH signal (see the MCS3/RFSH pin description on page 31). ADEN--If BHE/ADEN is held High or left floating during power-on reset, the address portion of the AD bus (AD15-AD0 for the 186 or AO15-AO8 and AD7- AD0 for the 188) is enabled or disabled during LCS and UCS bus cycles based on the DA bit in the LMCS and UMCS registers. In this case, the memory address is accessed on the A19-A0 pins. There is a weak internal
CTS0/ENRX0/PIO21
Clear-to-Send 0 (input, asynchronous) Enable-Receiver-Request 0 (input, asynchronous) CTS0--This pin provides the Clear to Send signal for asynchronous serial port 0 when the ENRX0 bit in the AUXCON register is 0 and hardware flow control is enabled for the port (FC bit in the serial port 0 control register is set). The CTS0 signal gates the transmission of data from the associated serial port transmit register. When CTS0 is asserted, the transmitter begins transmission of a frame of data, if any is available. If CTS0 is deasserted, the transmitter holds the data in the serial port transmit register. The value of CTS0 is checked only at the beginning of the transmission of the frame. ENRX0--This pin provides the Enable Receiver Request for asynchronous serial port 0 when the ENRX0 bit in the AUXCON register is 1 and hardware flow control is enabled for the port (FC bit in the serial port 0 control register is set). The ENRX0 signal enables the receiver for the associated serial port.
28
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
DEN/DS/PIO5
Data Enable (output, three-state, synchronous) Data Strobe (output, three-state, synchronous) DEN--This pin supplies an output enable to an external data-bus transceiver. DEN is asserted during memory, I/O, and interrupt acknowledge cycles. DEN is deasserted when DT/R changes state. DEN floats during a bus hold or reset condition. DS--The data strobe provides a signal where the write cycle timing is identical to the read cycle timing. When used with other control signals, DS provides an interface for 68K-type peripherals without the need for additional system interface logic. When DS is asserted, addresses are valid. When DS is asserted on writes, data is valid. When DS is asserted on reads, data can be asserted on the AD bus.
DT/R/PIO4
Data Transmit or Receive (output, three-state, synchronous) This pin indicates in which direction data should flow through an external data-bus transceiver. When DT/R is asserted High, the microcontroller transmits data. When this pin is deasserted Low, the microcontroller receives data. DT/R floats during a bus hold or reset condition.
GND
Ground Ground pins connect the microcontroller to the system ground.
HLDA
Bus Hold Acknowledge (output, synchronous) This pin is asserted High to indicate to an external bus master that the microcontroller has released control of the local bus. When an external bus master requests control of the local bus (by asserting HOLD), the microcontroller completes the bus cycle in progress. It then relinquishes control of the bus to the external bus master by asserting HLDA and floating DEN, RD, WR, S2-S0, AD15-AD0, S6, A19-A0, BHE, WHB, WLB, and DT/R, and then driving the chip selects UCS, LCS, MCS3-MCS0, PCS6-PCS5, and PCS3-PCS0 High. When the external bus master has finished using the local bus, it indicates this to the microcontroller by deasserting HOLD. The microcontroller responds by deasserting HLDA. If the microcontroller requires access to the bus (for example, to refresh), it will deassert HLDA before the external bus master deasserts HOLD. The external bus master must be able to deassert HOLD and allow the microcontroller access to the bus. See the timing diagrams for bus hold on page 97.
Note: This pin resets to DEN.
DRQ0/INT5/PIO12
DMA Request 0 (input, synchronous, level-sensitive) Maskable Interrupt Request 5 (input, asynchronous, edge-triggered) DRQ0--This pin indicates to the microcontroller that an external device is ready for DMA channel 0 to perform a transfer. DRQ0 is level-triggered and internally synchronized. DRQ0 is not latched and must remain active until serviced. INT5--If DMA 0 is not enabled or DMA 0 is not being used with external synchronization, INT5 can be used as an additional external interrupt request. INT5 shares the DMA 0 interrupt type (0Ah) and register control bits. INT5 is edge-triggered only and must be held until the interrupt is acknowledged.
DRQ1/INT6/PIO13
DMA Request 1 (input, synchronous, level-sensitive) Maskable Interrupt Request 6 (input, asynchronous, edge-triggered) DRQ1--This pin indicates to the microcontroller that an external device is ready for DMA channel 1 to perform a transfer. DRQ1 is level-triggered and internally synchronized. DRQ1 is not latched and must remain active until serviced. INT6--If DMA 1 is not enabled or DMA 1 is not being used with external synchronization, INT6 can be used as an additional external interrupt request. INT6 shares the DMA 1 interrupt type (0Bh) and register control bits. INT6 is edge-triggered only and must be held until the interrupt is acknowledged.
HOLD
Bus Hold Request (input, synchronous, level-sensitive) This pin indicates to the microcontroller that an external bus master needs control of the local bus. The Am186ES and Am188ES microcontrollers' HOLD latency time is a function of the activity occurring in the processor when the HOLD request is received. A DRAM request will delay a HOLD request when both requests are made at the same time. In addition, if locked transfers are performed, the HOLD latency time is increased by the length of the locked transfer. For more information, see the HLDA pin description on page 29.
Am186/188ES and Am186/188ESLV Microcontrollers
29
PRELIMINARY
INT0
Maskable Interrupt Request 0 (input, asynchronous) This pin indicates to the microcontroller that an interrupt request has occurred. If the INT0 pin is not masked, the microcontroller transfers program execution to the location specified by the INT0 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT0 until the request is acknowledged.
INTA0--When the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on INT0. The peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type. PWD--If pulse width demodulation is enabled, PWD processes a signal through the Schmitt trigger. PWD is used internally to drive TIMERIN0 and INT2, and PWD is inverted internally to drive TIMERIN1 and INT4. If INT2 and INT4 are enabled and timer 0 and timer 1 are properly configured, the pulse width of the alternating PWD signal can be calculated by comparing the values in timer 0 and timer 1. In P WD m ode , the si gna ls TIME RIN0/ PIO 11 , TIMERIN1/PIO0, and INT4/PIO30 can be used as PIOs. If they are not used as PIOs they are ignored internally. The level of INT2/INTA0/PWD/PIO31 is reflected in the PIO data register for PIO 31 as if it was a PIO.
INT1/SELECT
Maskable Interrupt Request 1 (input, asynchronous) Slave Select (input, asynchronous) INT1--This pin indicates to the microcontroller that an interrupt request has occurred. If INT1 is not masked, the microcontroller transfers program execution to the location specified by the INT1 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT1 until the request is acknowledged. SELECT--When the microcontroller interrupt control unit is operating as a slave to an external interrupt controller, this pin indicates to the microcontroller that an interrupt type appears on the address and data bus. The INT0 pin must indicate to the microcontroller that an interrupt has occurred before the SELECT pin indicates to the microcontroller that the interrupt type appears on the bus.
INT3/INTA1/IRQ
Maskable Interrupt Request 3 (input, asynchronous) Interrupt Acknowledge 1 (output, synchronous) Slave Interrupt Request (output, synchronous) INT3--This pin indicates to the microcontroller that an interrupt request has occurred. If the INT3 pin is not masked, the microcontroller then transfers program execution to the location specified by the INT3 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT3 until the request is acknowledged. INT3 becomes INTA1 when INT1 is configured in cascade mode. INTA1--When the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on INT1. The peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type. IRQ--When the microcontroller interrupt control unit is operating as a slave to an external master interrupt controller, this pin lets the microcontroller issue an interrupt request to the external master interrupt controller.
INT2/INTA0/PWD/PIO31
Maskable Interrupt Request 2 (input, asynchronous) Interrupt Acknowledge 0 (output, synchronous) Pulse Width Demodulator (input, Schmitt trigger) INT2--This pin indicates to the microcontroller that an interrupt request has occurred. If the INT2 pin is not masked, the microcontroller transfers program execution to the location specified by the INT2 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT2 until the request is acknowledged. INT2 becomes INTA0 when INT0 is configured in cascade mode.
30
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
INT4/PIO30
Maskable Interrupt Request 4 (input, asynchronous) This pin indicates to the microcontroller that an interrupt request has occurred. If the INT4 pin is not masked, the microcontroller then transfers program execution to the location specified by the INT4 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT4 until the request is acknowledged. When pulse width demodulation mode is enabled, the INT4 signal is used internally to indicate a High-to-Low transition on the PWD signal. When pulse width demodulation mode is enabled, INT4/PIO30 can be used as a PIO.
addition, it has weak internal pullup resistors that are active during reset. This signal functions like the corresponding signal in the Am186EM and Am188EM microcontrollers except that MCS0 can be programmed as the chip select for the entire middle chip select address range.
MCS2-MCS1 (MCS2/PIO24, MCS1/PIO15)
Midrange Memory Chip Selects (output, synchronous, internal pullup) These pins indicate to the system that a memory access is in progress to the corresponding region of the midrange memory block. The base address and size of the midrange memory block are programmable. On the Am186ES microcontroller, MCS2-MCS1 are configured for 8-bit or 16-bit bus size by the auxiliary configuration register. MCS2-MCS1 are held High during a bus hold condition. In addition, they have weak internal pullup resistors that are active during reset. These signals function like the signals in the Am186EM and Am188EM microcontrollers except that if MCS0 is programmed to be active for the entire middle chipselect range, then these signals are available as PIOs. If they are not programmed as PIOs and if MCS0 is programmed for the whole middle chip-select range, then these signals operate normally.
LCS/ONCE0
Lower Memory Chip Select (output, synchronous, internal pullup) ONCE Mode Request 0 (input) LCS--This pin indicates to the system that a memory access is in progress to the lower memory block. The base address and size of the lower memory block are programmable up to 512 Kbytes. On the Am186ES microcontroller, LCS is configured for 8-bit or 16-bit bus size by the auxiliary configuration register. LCS is held High during a bus hold condition. ONCE0--During reset, this pin and ONCE1 indicate to the microcontroller the mode in which it should operate. ONCE0 and ONCE1 are sampled on the rising edge of RES. If both pins are asserted Low, the microcontroller enters ONCE mode; otherwise, it operates normally. In ONCE mode, all pins assume a high-impedance state and remain in that state until a subsequent reset occurs. To guarantee that the microcontroller does not inadvertently enter ONCE mode, ONCE0 has a weak internal pullup resistor that is active only during reset. This pin is not three-stated during a bus hold condition.
MCS3/RFSH/PIO25
Midrange Memory Chip Select 3 (output, synchronous, internal pullup) Automatic Refresh (output, synchronous) MCS3--This pin indicates to the system that a memory access is in progress to the fourth region of the midrange memory block. The base address and size of the midrange memory block are programmable. On the Am186ES microcontroller, MCS3 is configured for 8-bit or 16-bit bus size by the auxiliary configuration register. MCS3 is held High during a bus hold condition. In addition, this pin has a weak internal pullup resistor that is active during reset. This signal functions like the corresponding signal in the Am186EM and Am188EM microcontrollers except that if MCS0 is programmed for the entire middle chipselect range, then this signal is available as a PIO. If MCS3 is not programmed as a PIO and if MCS0 is programmed for the entire middle chip-select range, then this signal operates normally. Depending on the chip configuration, this signal can serve as a memory RFSH. RFSH--This pin provides a signal timed for auto refresh to PSRAM or DRAM devices. It is only enabled to function as a refresh pulse when the PSRAM or DRAM mode bit is set. An active Low pulse is
MCS0 (MCS0/PIO14)
Midrange Memory Chip Select 0 (output, synchronous, internal pullup) This pin indicates to the system that a memory access is in progress to the corresponding region of the midrange memory block. The base address and size of the midrange memory block are programmable. On the Am186ES microcontroller, MCS0 is configured for 8-bit or 16-bit bus size by the auxiliary configuration register. MCS0 is held High during a bus hold condition. In
Am186/188ES and Am186/188ESLV Microcontrollers
31
PRELIMINARY generated for 1.5 clock cycles with an adequate deassertion period to ensure that overall auto refresh cycle time is met. This signal functions like the RFSH signal in the Am186EM and Am188EM microcontrollers except that the DRAM row address is not driven on DRAM refreshes. This pin is not three-stated during a bus hold condition. byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers.
PCS2/CTS1/ENRX1/PIO18
Peripheral Chip Select 2 (output, synchronous) Clear-to-Send 1 (input, asynchronous) Enable-Receiver-Request 1 (input, asynchronous) PCS2--This pin provides the Peripheral Chip Select 2 signal to the system when hardware flow control is not enabled for asynchronous serial port 1. The PCS2 signal indicates to the system that a memory access is in progress to the corresponding region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. PCS2 is held High during a bus hold or reset condition. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. CTS1--This pin provides the Clear to Send signal for asynchronous serial port 1 when the ENRX1 bit in the AUXCON register is 0 and hardware flow control is enabled for the port (FC bit in the serial port 1 control register is set). The CTS1 signal gates the transmission of data from the associated serial port transmit register. When CTS1 is asserted, the transmitter begins transmission of a frame of data, if any is available. If CTS1 is deasserted, the transmitter holds the data in the serial port transmit register. The value of CTS1 is checked only at the beginning of the transmission of the frame. ENRX1--This pin provides the Enable Receiver Request for asynchronous serial port 1 when the ENRX1 bit in the AUXCON register is 1 and hardware flow control is enabled for the port (FC bit in the serial port 1 control register is set). The ENRX1 signal enables the receiver for the associated serial port.
NMI
Nonmaskable Interrupt (input, synchronous, edge-sensitive) This pin indicates to the microcontroller that an interrupt request has occurred. The NMI signal is the highest priority hardware interrupt and, unlike the INT6-INT0 pins, cannot be masked. The microcontroller always transfers program execution to the location specified by the nonmaskable interrupt vector in the microcontroller interrupt vector table when NMI is asserted. Although NMI is the highest priority interrupt source, it does not participate in the priority resolution process of the maskable interrupts. There is no bit associated with NMI in the interrupt in-service or interrupt request registers. This means that a new NMI request can interrupt an executing NMI interrupt service routine. As with all hardware interrupts, the IF (interrupt flag) is cleared when the processor takes the interrupt, disabling the maskable interrupt sources. However, if maskable interrupts are re-enabled by software in the NMI interrupt service routine, via the STI instruction for example, the fact that an NMI is currently in service does not have any effect on the priority resolution of maskable interrupt requests. For this reason, it is strongly advised that the interrupt service routine for NMI should not enable the maskable interrupts. An NMI transition from Low to High is latched and synchronized internally, and it initiates the interrupt at the next instruction boundary. To guarantee that the interrupt is recognized, the NMI pin must be asserted for at least one CLKOUTA period.
PCS1-PCS0 (PCS1/PIO17, PCS0/PIO16)
Peripheral Chip Selects (output, synchronous) These pins indicate to the system that a memory access is in progress to the corresponding region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. PCS3-PCS0 are held High during a bus hold condition. They are also held High during reset. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256-
PCS3/RTS1/RTR1/PIO19
Peripheral Chip Select 3 (output, synchronous) Ready-to-Send 1 (output, asynchronous) Ready-to-Receive 1 (output, asynchronous) PCS3--This pin provides the Peripheral Chip Select 3 signal to the system when hardware flow control is not enabled for asynchronous serial port 1. The PCS3 signal indicates to the system that a memory access is in progress to the corresponding region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. PCS3 is held High during a bus hold or reset condition.
32
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. RTS1--This pin provides the Ready to Send signal for asynchronous serial port 1 when the RTS1 bit in the AUXCON register is 1 and hardware flow control is enabled for the port (FC bit in the serial port 1 control register is set). The RTS1 signal is asserted when the associated serial port transmit register contains data which has not been transmitted. RTR1--This pin provides the Ready to Receive signal for asynchronous serial port 1 when the RTS1 bit in the AUXCON register is 0 and hardware flow control is enabled for the port (FC bit in the serial port 1 control register is set). The RTR1 signal is asserted when the associated serial port receive register does not contain valid, unread data. covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. A2--When the EX bit in the MCS and PCS auxiliary register is 0, this pin supplies an internally latched address bit 2 to the system. During a bus hold condition, A2 retains its previously latched value.
PIO31-PIO0 (Shared)
Programmable I/O Pins (input/output, asynchronous, open-drain) The Am186ES and Am188ES microcontrollers provide 32 individually programmable I/O pins. Each PIO can be programmed with the following attributes: PIO function (enabled/disabled), direction (input/output), and weak pullup or pulldown. The pins that are multiplexed with PIO31-PIO0 are listed in Table 2 and Table 3. After power-on reset, the PIO pins default to various configurations. The column titled Power-On Reset Status in Table 2 and Table 3 lists the defaults for the PIOs. Most of the PIO pins are configured as PIO inputs with pullup after power-on reset. The system initialization code must reconfigure any PIO pins as required. The A19-A17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address FFFF0h. The DT/R, DEN, and SRDY pins also default to normal operation on power-on reset.
PCS5/A1/PIO3
Peripheral Chip Select 5 (output, synchronous) Latched Address Bit 1 (output, synchronous) PCS5--This pin indicates to the system that a memory access is in progress to the sixth region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. PCS5 is held High during a bus hold condition. It is also held High during reset. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. A1--When the EX bit in the MCS and PCS auxiliary register is 0, this pin supplies an internally latched address bit 1 to the system. During a bus hold condition, A1 retains its previously latched value.
PCS6/A2/PIO2
Peripheral Chip Select 6 (output, synchronous) Latched Address Bit 2 (output, synchronous) PCS6--This pin indicates to the system that a memory access is in progress to the seventh region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. PCS6 is held High during a bus hold condition or reset. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256byte address range, which is twice the address range Am186/188ES and Am186/188ESLV Microcontrollers 33
PRELIMINARY Table 2. Numeric PIO Pin Designations
PIO No 0 1 2 3 4 5 6 7(1) 8(1) 9(1) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26(1,2) 27 28 29
(1,2)
Table 3.
Associated Pin A17
(1)
Alphabetic PIO Pin Designations
PIO No Power-On Reset Status 7 8 9 21 5 12 13 4 31 30 14 15 24 25 16 17 18 19 3 2 20 23 28
(1,2)
Associated Pin TMRIN1 TMROUT1 PCS6/A2 PCS5/A1 DT/R DEN/DS SRDY A17 A18 A19 TMROUT0 TMRIN0 DRQ0/INT5 DRQ1/INT6 MCS0 MCS1 PCS0 PCS1 PCS3/RTS1/RTR1 RTS0/RTR0 CTS0/ENRX0 TXD0 RXD0 MCS2 MCS3/RFSH UZI TXD1 RXD1 S6/LOCK/CLKDIV2 INT4 INT2/INTA0/PWD
Power-On Reset Status Input with pullup Input with pulldown Input with pullup Input with pullup Normal operation(3) Normal operation(3) Normal operation(4) Normal Normal operation(3) operation(3) Normal operation(3) Input with pulldown Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup
Normal operation(3) Normal operation(3) Normal operation(3) Input with pullup Normal operation(3) Input with pullup Input with pullup Normal operation(3) Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Normal operation(4) Input with pullup Input with pullup Input with pulldown Input with pulldown Input with pullup Input with pullup Input with pullup
A18(1) A19(1) CTS0/ENRX0 DEN/DS DRQ0/INT5 DRQ1/INT6 DT/R INT2/INTA0/PWD INT4 MCS0 MCS1 MCS2 MCS3/RFSH PCS0 PCS1 PCS2/CTS1/ENRX1 PCS3/RTS1/RTR1 PCS5/A1 PCS6/A2 RTS0/RTR0 RXD0 RXD1 S6/LOCK/CLKDIV2 SRDY TMRIN0 TMRIN1 TMROUT0 TMROUT1 TXD0 TXD1 UZI
(1,2)
PCS2/CTS1/ENRX1 Input with pullup
29 6 11 0 10 1 22 27 26
30 31
Notes: The following notes apply to both tables. 1. These pins are used by emulators. (Emulators also use S2-S0, RES, NMI, CLKOUTA, BHE, ALE, AD15-AD0, and A16-A0.) 2. These pins revert to normal operation if BHE/ADEN (186) or RFSH2/ADEN (188) is held Low during power-on reset. 3. When used as a PIO, input with pullup option available. 4. When used as a PIO, input with pulldown option available.
34
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
RD
Read Strobe (output, synchronous, three-state) RD--This pin indicates to the system that the microcontroller is performing a memory or I/O read cycle. RD is guaranteed to not be asserted before the address and data bus is floated during the address-todata transition. RD floats during a bus hold condition.
RTS0/RTR0/PIO20
Ready-to-Send 0 (output, asynchronous) Ready-to-Receive 0 (output, asynchronous) RTS0--This pin provides the Ready to Send signal for asynchronous serial port 0 when the RTS0 bit in the AUXCON register is 1 and hardware flow control is enabled for the port (FC bit in the serial port 0 control register is set). The RTS0 signal is asserted when the associated serial port transmit register contains data that has not been transmitted. RTR0--This pin provides the Ready to Receive signal for asynchronous serial port 0 when the RTS0 bit in the AUXCON register is 0 and hardware flow control is enabled for the port (FC bit in the serial port 0 control register is set). The RTR0 signal is asserted when the associated serial port receive register does not contain valid, unread data.
RES
Reset (input, asynchronous, level-sensitive) This pin requires the microcontroller to perform a reset. When RES is asserted, the microcontroller immediately terminates its present activity, clears its internal logic, and transfers CPU control to the reset address, FFFF0h. RES must be held Low for at least 1 ms. RES can be asserted asynchronously to CLKOUTA because RES is synchronized internally. For proper initialization, VCC must be within specifications, and CLKO UTA mus t be stab le for m ore th an four CLKOUTA periods during which RES is asserted. The microcontroller begins fetching instructions approximately 6.5 CLKOUTA periods after RES is deasserted. This input is provided with a Schmitt trigger to facilitate power-on RES generation via an RC network.
RXD0/PIO23
Receive Data 0 (input, asynchronous) This pin supplies asynchronous serial receive data from the system to asynchronous serial port 0.
RXD1/PIO28
Receive Data 1 (input, asynchronous) This pin supplies asynchronous serial receive data from the system to asynchronous serial port 1.
RFSH2/ADEN (Am188ES Microcontroller Only)
Refresh 2 (three-state, output, synchronous) Address Enable (input, internal pullup) RFSH2--Asserted Low to signify a DRAM refresh bus cycle. The use of RFSH2/ADEN to signal a refresh is not valid when PSRAM mode is selected. Instead, the MCS3/RFSH signal is provided to the PSRAM. ADEN--If RFSH2/ADEN is held High or left floating on power-on reset, the AD bus (AO15-AO8 and AD7- AD0) is enabled or disabled during the address portion of LCS and UCS bus cycles based on the DA bit in the LMCS and UMCS registers. If the DA bit is set, the memory address is accessed on the A19-A0 pins. This mode of operation reduces power consumption. For more information, see the "Bus Operation" section on page 39. There is a weak internal pullup resistor on RFSH2/ADEN so no external pullup is required. If RFSH2/ADEN is held Low on power-on reset, the AD bus drives both addresses and data, regardless of the DA bit setting. The pin is sampled one crystal clock cycle after the rising edge of RES. RFSH2/ADEN is three-stated during bus holds and ONCE mode.
S2-S0
Bus Cycle Status (output, three-state, synchronous) These pins indicate to the system the type of bus cycle in progress. S2 can be used as a logical memory or I/ O indicator, and S1 can be used as a data transmit or receive indicator. S2-S0 float during bus hold and hold acknowledge conditions. The S2-S0 pins are encoded as shown in Table 4.
Table 4.
S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1
Bus Cycle Encoding
Bus Cycle Interrupt acknowledge Read data from I/O Write data to I/O Halt Instruction fetch Read data from memory Write data to memory None (passive)
S0 0 1 0 1 0 1 0 1
Am186/188ES and Am186/188ESLV Microcontrollers
35
PRELIMINARY
S6/LOCK/CLKDIV2/PIO29
Bus Cycle Status Bit 6 (output, synchronous) Bus Lock (output, synchronous) Clock Divide by 2 (input, internal pullup) S6--During the second and remaining periods of a cycle (t2, t3, and t4), this pin is asserted High to indicate a DMA-initiated bus cycle. During a bus hold or reset condition, S6 floats. LOCK--This signal is asserted Low to indicate to other system bus masters that they are not to gain control of the system bus. This signal is only available during t1. LOCK on the Am186ES and Am188ES microcontrollers does not conform to the timing of the LOCK signal on the 80C186/188 microcontrollers. This signal is primarily intended for use by emulators. CLKDIV2--If S6/CLKDIV2/PIO29 is held Low during power-on reset, the chip enters clock divided by 2 mode where the processor clock is derived by dividing the external clock input by 2. If this mode is selected, the PLL is disabled. The pin is sampled on the rising edge of RES. If S6 is to be used as PIO29 in input mode, the device driving PIO29 must not drive the pin Low during poweron reset. S6/CLKDIV2/PIO29 defaults to a PIO input with pullup, so the pin does not need to be driven High externally.
TMRIN1/PIO0
Timer Input 1 (input, synchronous, edge-sensitive) This pin supplies a clock or control signal to the internal microcontroller timer 1. After internally synchronizing a Low-to-High transition on TMRIN1, the microcontroller increments the timer. TMRIN1 must be tied High if not being used. When PIO0 is enabled, TMRIN1 is pulled High internally. TMRIN1 is driven internally by INT2/INTA0/PWD when pulse width demodulation mode is enabled. The TMRIN1/PIO0 pin can be used as a PIO when pulse width demodulation mode is enabled.
TMROUT0/PIO10
Timer Output 0 (output, synchronous) This pin supplies the system with either a single pulse or a continuous waveform with a programmable duty cycle. TMROUT0 is floated during a bus hold or reset.
TMROUT1/PIO1
Timer Output 1 (output, synchronous) This pin supplies the system with either a single pulse or a continuous waveform with a programmable duty cycle. TMROUT1 floats during a bus hold or reset.
TXD0/PIO22
Transmit Data 0 (output, asynchronous) This pin supplies asynchronous serial transmit data to the system from serial port 0.
SRDY/PIO6
Synchronous Ready (input, synchronous, level-sensitive) This pin indicates to the microcontroller that the addressed memory space or I/O device will complete a data transfer. The SRDY pin accepts an active High input synchronized to CLKOUTA. Using SRDY instead of ARDY allows a relaxed system timing because of the elimination of the one-half clock period required to internally synchronize ARDY. To always assert the ready condition to the microcontroller, tie SRDY High. If the system does not use SRDY, tie the pin Low to yield control to ARDY.
TXD1/PIO27
Transmit Data 1 (output, asynchronous) This pin supplies asynchronous serial transmit data to the system from serial port 1.
UCS/ONCE1
Upper Memory Chip Select (output, synchronous) ONCE Mode Request 1 (input, internal pullup) UCS--This pin indicates to the system that a memory access is in progress to the upper memory block. The base address and size of the upper memory block are programmable up to 512 Kbytes. UCS is held High during a bus hold condition. After reset, UCS is active for the 64 Kbyte memory range from F0000h to FFFFFh, including the reset address of FFFF0h. ONCE1--During reset, this pin and LCS/ONCE0 indicate to the microcontroller the mode in which it should operate. ONCE0 and ONCE1 are sampled on the rising edge of RES. If both pins are asserted Low, the microcontroller enters ONCE mode. Otherwise, it operates normally. In ONCE mode, all pins assume a high-impedance state and remain in that state until a subsequent reset occurs. To guarantee that the micro-
TMRIN0/PIO11
Timer Input 0 (input, synchronous, edge-sensitive) This pin supplies a clock or control signal to the internal microcontroller timer 0. After internally synchronizing a Low-to-High transition on TMRIN0, the microcontroller increments the timer. TMRIN0 must be tied High if not being used. When PIO11 is enabled, TMRIN0 is pulled High internally. TMRIN0 is driven internally by INT2/INTA0/PWD when pulse width demodulation mode is enabled. The TMRIN0/PIO11 pin can be used as a PIO when pulse width demodulation mode is enabled.
36
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY controller does not inadvertently enter ONCE mode, ONCE1 has a weak internal pullup resistor that is active only during a reset. This pin is not three-stated during a bus hold condition.
WR
Write Strobe (output, synchronous) WR--This pin indicates to the system that the data on the bus is to be written to a memory or I/O device. WR floats during a bus hold or reset condition.
UZI/PIO26
Upper Zero Indicate (output, synchronous) This pin lets the designer determine if an access to the interrupt vector table is in progress by ORing it with bits 15-10 of the address and data bus (AD15-AD10 on the 186 and AO15-AO10 on the 188). UZI is the logical OR of the inverted A19-A16 bits. It asserts in the first period of a bus cycle and is held throughout the cycle. This pin should be allowed to float or it should be pulled High at reset. This pin has an internal pullup. If this pin is Low at the negation of reset, the Am186ES and Am188ES microcontrollers will enter a reserved clock test mode.
X1
Crystal Input (input) This pin and the X2 pin provide connections for a fundamental mode or third-overtone, parallel-resonant crystal used by the internal oscillator circuit. To provide the microcontroller with an external clock source, connect the source to the X1 pin and leave the X2 pin unconnected.
X2
Crystal Output (output) This pin and the X1 pin provide connections for a fundamental mode or third-overtone, parallel-resonant crystal used by the internal oscillator circuit. To provide the microcontroller with an external clock source, leave the X2 pin unconnected and connect the source to the X1 pin.
VCC
Power Supply (input) These pins supply power (+5 V) to the microcontroller.
WHB (Am186ES Microcontroller Only)
Write High Byte (output, three-state, synchronous) This pin and WLB indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. In 80C186 microcontroller designs, this information is provided by BHE, AD0, and WR. However, by using WHB and WLB, the standard system interface logic and external address latch that were required are eliminated. WHB is asserted with AD15-AD8. WHB is the logical OR of BHE and WR. This pin floats during reset.
WLB (Am186ES Microcontroller Only) WB (Am188ES Microcontroller Only)
Write Low Byte (output, three-state, synchronous) Write Byte (output, three-state, synchronous) WLB--This pin and WHB indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. In 80C186 microcontroller designs, this information is provided by BHE, AD0, and WR. However, by using WHB and WLB, the standard system interface logic and external address latch that were required are eliminated. WLB is asserted with AD7-AD0. WLB is the logical OR of AD0 and WR. This pin floats during reset. WB--On the Am188ES microcontroller, this pin indicates a write to the bus. WB uses the same early timing as the nonmultiplexed address bus. WB is associated with AD7-AD0. This pin floats during reset.
Am186/188ES and Am186/188ESLV Microcontrollers
37
PRELIMINARY
FUNCTIONAL DESCRIPTION
The Am186ES and Am188ES microcontrollers are based on the architecture of the original Am186 and Am188 microcontrollers--the 80C186 and 80C188 microcontrollers. The Am186ES and Am188ES microcontrollers function in the enhanced mode of earlier generations of Am186 and Am188 microcontrollers. Enhanced mode includes system features such as power-save control. Each of the 8086, 8088, 80186, and 80188 microcontrollers contains the same basic set of registers, instructions, and addressing modes. The Am186ES and Am188ES microcontrollers are backward compatible with the 80C186 and 80C188 microcontrollers. A full description of all the Am186ES and Am188ES microcontroller registers and instructions is included in the Am186ES and Am188ES Microcontrollers User's Manual, order# 21096. ment register used for physical address generation is implied by the addressing mode used (see Table 5).
Shift Left 4 Bits
1 15 0 15
2
A
0
2
4 Segment Logical 0 Base Address 2 Offset 0
1 19 0
2
A
4
0 0
0 15 2
0
2
2 0 2 0 Physical Address
1 19
A
6
Memory Organization
Memory is organized in sets of segments. Each segment is a linear contiguous sequence of 64K (216) 8-bit bytes. Memory is addressed using a two-component address that consists of a 16-bit segment value and a 16-bit offset. The 16-bit segment values are contained in one of four internal segment registers (CS, DS, SS, or ES). The physical address is calculated by shifting the segment value left by 4 bits and adding the 16-bit offset value to yield a 20-bit physical address (see Figure 3). This allows for a 1-Mbyte physical address size. All instructions that address operands in memory must specify the segment value and the 16-bit offset value. For speed and compact instruction encoding, the seg-
To Memory
Figure 3. Two-Component Address
I/O Space
The I/O space consists of 64K 8-bit or 32K 16-bit ports. Separate instructions (IN, INS and OUT, OUTS) address the I/O space with either an 8-bit port address specified in the instruction, or a 16-bit port address in the DX register. Eight-bit port addresses are zero-extended such that A15-A8 are Low. I/O port addresses 00F8h through 00FFh are reserved.
Table 5.
Memory Reference Needed Instructions Local Data Stack External Data (Global)
Segment Register Selection Rules
Implicit Segment Selection Rule Instructions (including immediate data) All data references All stack pushes and pops; any memory references that use BP Register All string instruction references that use the DI Register as an index
Segment Register Used Code (CS) Data (DS) Stack (SS) Extra (ES)
38
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
BUS OPERATION
The industry-standard 80C186 and 80C188 microcontrollers use a multiplexed address and data (AD) bus. The address is present on the AD bus only during the t1 clock phase. The Am186ES and Am188ES microcontrollers continue to provide the multiplexed AD bus and, in addition, provide a nonmultiplexed address (A) bus. The A bus provides an address to the system for the complete bus cycle (t1-t4). For systems where power consumption is a concern, it is possible to disable the address from being driven on the AD bus on the Am186ES microcontroller and on the AD and AO buses on the Am188ES microcontroller during the normal address portion of the bus cycle for accesses to UCS and/or LCS address spaces. In this mode, the affected bus is placed in a high-impedance state during the address portion of the bus cycle. This feature is enabled through the DA bits in the UMCS and LMCS registers. When address disable is in effect, the number of signals that assert on the bus during all normal bus cycles to the associated address space is reduced, decreasing power consumption and reducing processor switching noise. On the Am188ES microcontroller, the address is driven on A015-A08 during the data portion of the bus cycle regardless of the setting of the DA bits. If the ADEN pin is pulled Low during processor reset, the value of the DA bits in the UMCS and LMCS registers is ignored and the address is driven on the AD bus for all accesses, thus preserving the industry-standard 80C186 and 80C188 microcontrollers' multiplexed address bus and providing support for existing emulation tools. The following diagrams show the Am186ES and AM188ES microcontroller bus cycles when the address bus disable feature is in effect: n Figure 4 shows the affected signals during a normal read or write operation for an Am186ES microcontroller. The address and data are multiplexed onto the AD bus. n Figure 5 shows an Am186ES microcontroller bus cycle when address bus disable is in effect. This results in the AD bus operating in a nonmultiplexed address/data mode. The A bus has the address during a read or write operation. n Figure 6 shows the affected signals during a normal read or write operation for an Am188ES microcontroller. The multiplexed address/data mode is compatible with the 80C186 and 80C188 microcontrollers and might be used to take advantage of existing logic or peripherals. n Figure 7 shows an Am188ES microcontroller bus cycle when address bus disable is in effect. The address and data is not multiplexed. The AD7-AD0 signals have only data on the bus, while the AO bus has the address during a read or write operation.
t1 Address Phase
t2
t3 Data Phase
t4
CLKOUTA A19-A0 Address
AD15-AD0 (Read)
Address
Data
AD15-AD0 (Write) LCS or UCS
Address
Data
MCSx, PCSx
Figure 4.
Am186ES Microcontroller Address Bus--Normal Read and Write Operation
Am186/188ES and Am186/188ESLV Microcontrollers
39
PRELIMINARY
t1 Address Phase CLKOUTA A19-A0 AD15-AD0 (Read) AD15-AD0 (Write) LCS, UCS
t2
t3 Data Phase
t4
Address
Data
Data
MCSx, PCSx
Figure 5.
Am186ES Microcontroller--Read and Write with Address Bus Disable In Effect
t1 Address Phase
t2
t3 Data Phase
t4
CLKOUTA A19-A0 Address
AD7-AD0 (Read)
Address
Data
AO15-AO8 (Read or Write) AD7-AD0 (Write) LCS or UCS
Address
Address
Data
MCSx, PCSx
Figure 6.
Am188ES Microcontroller Address Bus--Normal Read and Write Operation
40
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
t1 Address Phase CLKOUTA A19-A0 AD7-AD0 (Read)
t2
t3 Data Phase
t4
Address
Data
AO15-AO8 AD7-AD0 (Write) LCS, UCS MCSx, PCSx
Address
Data
Figure 7.
Am188ES Microcontroller--Read and Write with Address Bus Disable In Effect
BUS INTERFACE UNIT
The bus interface unit controls all accesses to external peripherals and memory devices. External accesses include those to memory devices, as well as those to memory-mapped and I/O-mapped peripherals and the peripheral control block. The Am186ES and Am188ES microcontrollers provide an enhanced bus interface unit with the following features: n A nonmultiplexed address bus n On the Am186ES microcontroller, a static bus-sizing option for 8-bit and 16-bit memory and I/O n Separate byte write enables for high and low bytes in the Am186ES microcontroller only n Pseudo Static RAM (PSRAM) support The standard 80C186/188 microcontroller multiplexed address and data bus requires system interface logic and an external address latch. On the Am186ES and Am188ES microcontrollers, new byte write enables, PSRAM control logic, and a new nonmultiplexed address bus can reduce design costs by eliminating this external logic.
Nonmultiplexed Address Bus
The nonmultiplexed address bus (A19-A0) is valid onehalf CLKOUTA cycle in advance of the address on the AD bus. When used in conjunction with the modified UCS and LCS outputs and the byte-write enable signals, the A19-A0 bus provides a seamless interface to SRAM, PSRAM, and Flash EPROM memory systems.
Static Bus Sizing
The 80C186 microcontroller provided a 16-bit wide data bus over its entire address range, memory, and I/O, but did not allow accesses to an 8-bit wide bus. The 80C188 microcontroller provided a lower-cost interface by reducing the data bus width to 8 bits, again over the entire address range. The Am188ES microcontroller follows the 80C188 microcontroller in providing an 8-bit data bus to all memory and peripherals. However, the Am186ES microcontroller differs from the 80C186 microcontroller in allowing programmability for data bus widths through fields in the auxiliary configuration (AUXCON) register, as shown in Table 6. The width of the data access should not be modified while the processor is fetching instructions from the associated address space.
Am186/188ES and Am186/188ESLV Microcontrollers
41
PRELIMINARY Table 6. Programming Am186ES Microcontroller Bus Width
AUXCON Field - LSIZ Value - 0 1 I/O IOSIZ 0 1 Other MSIZ 0 1 Bus Width 16 bits 16 bits 8 bits 16 bits 8 bits 16 bits 8 bits default default Comments not configurable default
Space UCS LCS
when PSRAM mode and the refresh control unit are enabled. No refresh address is required by the PSRAM when using the auto refresh mechanism. The RFSH signal is multiplexed with the MCS3 signal pin. When PSRAM mode is enabled, MCS3 is not available for use as a chip-select signal. The refresh control unit must be programmed before accessing PSRAM in LCS space. The refresh counter in the clock prescaler (CDRAM) register must be configured with the required refresh interval value. The ending address of LCS space and the ready and waitstate generation in the LMCS register must also be programmed. The refresh counter reload value in the CDRAM register should not be set to less than 18 (12h) in order to provide time for processor cycles within refresh. The refresh address counter must be set to 000000h to prevent another chip select from asserting. LCS is held High during a refresh cycle. The A bus is not used during refresh cycles. The LMCS register must be configured to external ready ignored (R2=1) with one wait state (R1-R0=01b), and the PSRAM mode enable bit (PSE) must be set to 1.
Byte-Write Enables
The Am186ES microcontroller provides the WHB (Write High Byte) and WLB (Write Low Byte) signals, which act as byte-write enables. WHB is the logical OR of BHE and WR. WHB is Low when BHE and WR are both Low. WLB is the logical OR of A0 and WR. WLB is Low when A0 and WR are both Low. WB is Low whenever a byte is written on the Am188ES microcontroller. On the Am188ES microcontroller, the WB (Write Byte) pin indicates a write to the bus. WB uses the same early timing as the nonmulitplexed address bus. WB is associated with AD7--AD0. This pin floats during reset. The byte-write enables are driven in conjunction with the nonmultiplexed address bus as required for the write timing requirements of common SRAMs.
PERIPHERAL CONTROL BLOCK (PCB)
The integrated peripherals of the Am186ES and Am188ES microcontrollers are controlled by 16-bit read/write registers. The peripheral registers are contained within an internal 256-byte control block. The registers are physically located in the peripheral devices they control, but they are addressed as a single 256-byte block. Table 7 shows a map of these registers.
Reading and Writing the PCB
Code that is intended to execute on the Am188ES microcontroller should perform all writes to the PCB registers as byte writes. These writes transfer 16 bits of data to the PCB register even if an 8-bit register is named in the instruction. For example, out dx, al results in the value of ax being written to the port address in dx. Reads to the PCB should be done as word reads. Code written in this manner runs correctly on the Am188ES microcontroller and on the Am186ES microcontroller. Unaligned reads and writes to the PCB result in unpredictable behavior on both the Am186ES and Am188ES microcontrollers. For a complete description of all the registers in the PCB, see the Am186ES and Am188ES Microcontrollers User's Manual, order# 21096.
Pseudo Static RAM (PSRAM) Support
The Am186ES and Am188ES microcontrollers support the use of PSRAM devices in low memory chip-select (LCS) space only. When PSRAM mode is enabled, the timing for the LCS signal is modified by the chip-select control unit to provide a CS precharge period during PS RA M a cc e ss es . T h e 4 0- MH z t im in g o f the Am186ES and Am188ES microcontrollers is appropriate to allow 70-ns PSRAM to run with one wait state. PSRAM mode is enabled through a bit in the Low Memory Chip-Select (LMCS) register. The PSRAM feature is disabled on CPU reset. In addition to the LCS timing changes for PSRAM precharge, the PSRAM devices also require periodic refresh of all internal row addresses to retain their data. Although refresh of PSRAM can be accomplished several ways, the Am186ES and Am188ES microcontrollers implement auto refresh only. The Am186ES and Am188ES microcontrollers generate a refresh signal, RFSH, to the PSRAM devices
42
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY Table 7. Peripheral Control Block Register Map
Register Name Processor Control Registers: Peripheral control block relocation register Reset configuration register Processor release level register Auxiliary configuration register 2 System configuration register 1 Watchdog timer control register Enable RCU register
1 2 1
Register Name Timer 2 max count compare A register Timer 2 count register Timer 1 mode/control register Timer 1 max count compare B register Timer 1 max count compare A register Timer 1 count register Timer 0 mode/control register Timer 0 max count compare B register Timer 0 max count compare A register Timer 0 count register Interrupt Registers: Serial port 0 interrupt control register 1
Offset 62h 60h 5Eh 5Ch 5Ah 58h 56h 54h 52h 50h 44h 42h 40h 3Eh 3Ch 3Ah 38h 36h 34h 32h 30h 2Eh 2Ch 2Ah 28h 26h 24h 22h 20h 18h 16h 14h 12h 10h
1
Offset FEh F6h F4h F2h F0h E6h E4h E2h E0h DAh D8h D6h D4h D2h D0h CAh C8h C6h C4h C2h C0h A8h A6h A4h
1
Clock prescaler register Memory partition register DMA Registers: DMA 1 control register
1
Serial port 1 interrupt control register INT4 interrupt control register INT3 control register INT2 control register INT1 control register INT0 control register
2
DMA 1 transfer count register DMA 1 destination address high register DMA 1 destination address low register DMA 1 source address high register DMA 1 source address low register DMA 0 control register 1 DMA 0 transfer count register DMA 0 destination address high register DMA 0 destination address low register DMA 0 source address high register DMA 0 source address low register Chip-Select Registers: PCS and MCS auxiliary register Midrange memory chip-select register Peripheral chip-select register Low memory chip-select register Serial Port 0 Registers: Serial port 0 baud rate divisor register 1 Serial port 0 receive register Serial port 0 status register 1 Serial port 0 control register PIO Registers: PIO data 1 register PIO direction 1 register PIO mode 1 register PIO data 0 register PIO direction 0 register PIO mode 0 register Timer Registers: Timer 2 mode/control register
1 1
DMA1/INT6 interrupt control register 1 DMA0/INT5 interrupt control register Timer interrupt control register Interrupt status register Interrupt request register 1 Interrupt in-service register 1 Interrupt priority mask register Interrupt mask register Interrupt poll register End-of-interrupt register Interrupt vector register Serial Port 1 Registers: Serial port 1 baud rate divisor register 2 Serial port 1 receive register Serial port 1 status register 2 Serial port 1 control register
2 2 2 1
Interrupt poll status register
A2h A0h 88h 86h 84h 82h 80h 7Ah 78h 76h 74h 72h 70h 66h
Upper memory chip-select register
Serial port 0 transmit register 1
Serial port 1 transmit register
Notes: 1. The register has been changed from the Am186EM and Am188EM microcontrollers. 2. The register is new. Note: All unused addresses are reserved and should not be accessed.
Am186/188ES and Am186/188ESLV Microcontrollers
43
PRELIMINARY
CLOCK AND POWER MANAGEMENT
The clock and power management unit of the Am186ES and Am188ES microcontrollers includes a phase-locked loop (PLL) and a second programmable system clock output (CLKOUTB). the output of the amplifier and negatively affects the operation of the clock generator. Values for the loading on X1 and X2 must be chosen to provide the necessary phase shift and crystal operation. Selecting a Crystal When selecting a crystal, the load capacitance should always be specified (CL). This value can cause variance in the oscillation frequency from the desired specified value (resonance). The load capacitance and the loading of the feedback network have the following relationship: (C1 C2) CL = + CS (C1 + C2) where CS is the stray capacitance of the circuit. Placing the crystal and CL in series across the inverting amplifier and tuning these values (C1, C2) allows the crystal to oscillate at resonance. This relationship is true for both fundamental and third-overtone operation. Finally, there is a relationship between C1 and C2. To enhance the oscillation of the inverting amplifier, these values need to be offset with the larger load on the output (X2). Equal values of these loads tend to balance the poles of the inverting amplifier. The characteristics of the inverting amplifier set limits on the following parameters for crystals: ESR (Equivalent Series Resistance) ......40 max Drive Level ..............................................1 mW max The recommended range of values for C1 and C2 are as follows: C1 ..................................................................15 pF 20% C2 ..................................................................22 pF 20% The specific values for C1 and C2 must be determined by the designer and are dependent on the characteristics of the chosen crystal and board design.
Phase-Locked Loop (PLL)
In a traditional 80C186/188 microcontroller design, the crystal frequency is twice that of the desired internal clock. Because of the internal PLL on the Am186ES and Am188ES microcontrollers, the internal clock generated by the Am186ES and Am188ES microcontrollers (CLKOUTA) is the same frequency as the crystal. The PLL takes the crystal inputs (X1 and X2) and generates a 45-55% (worst case) duty cycle intermediate system clock of the same frequency. This removes the need for an external 2x oscillator, reducing system cost. The PLL is reset during power-on reset by an onchip power-on reset (POR) circuit.
Crystal-Driven Clock Source
The internal oscillator circuit of the Am186ES and Am188ES microcontrollers is designed to function with a parallel resonant fundamental or third overtone crystal. Because of the PLL, the crystal frequency should be equal to the processor frequency. Do not replace a crystal with an LC or RC equivalent. The signals X1 and X2 are connected to an internal inverting amplifier (oscillator) that provides, along with the external feedback loading, the necessary phase shift (Figure 8). In such a positive feedback circuit, the inverting amplifier has an output signal (X2) 180 degrees out of phase of the input signal (X1). The external feedback network provides an additional 180-degree phase shift. In an ideal system, the input to X1 will have 360 or zero degrees of phase shift. The external feedback network is designed to be as close to ideal as possible. If the feedback network is not providing necessary phase shift, negative feedback dampens
C1 X1 Crystal Crystal C1 C2 X2 C2 Note 1 Am186ES Microcontroller
a. Inverting Amplifier Configuration
Note 1: Use for Third Overtone Mode XTAL Frequency L1 Value (Max) 20 MHz 12 H 20% 25 MHz 8.2 H 20% 33 MHz 4.7 H 20% 40 MHz 3.0 H 20%
200 pF b. Crystal Configuration
Figure 8. Am186ES and Am188ES Microcontrollers Oscillator Configurations
44
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
External Source Clock
Alternately, the internal oscillator can be driven from an external clock source. This source should be connected to the input of the inverting amplifier (X1), with the output (X2) not connected.
Initialization and Processor Reset
Processor initialization or startup is accomplished by driving the RES input pin Low. RES must be held Low for 1 ms during power-up to ensure proper device initialization. RES forces the Am186ES and Am188ES microcontrollers to terminate all execution and local bus activity. No instruction or bus activity occurs as long as RES is active. After RES becomes inactive and an internal processing interval elapses, the microcontroller begins execution with the instruction at physical location FFFF0h, with UCS asserted with three wait states. RES also sets some registers to predefined values and resets the watchdog timer.
System Clocks
The base system clock of AMD's original 80C186 and 80C188 microcontrollers is renamed CLKOUTA and the additional output is called CLKOUTB. CLKOUTA and CLKOUTB operate at either the processor frequency or the PLL frequency. The output drivers for both clocks are individually programmable for disable. Figure 9 shows the organization of the clocks. The second clock output (CLKOUTB) allows one clock to run at the PLL frequency and the other clock to run at the power-save frequency. Individual drive enable bits allow selective enabling of just one or both of these clock outputs.
The Reset Configuration Register
When the RES input is asserted Low, the contents of the address/data bus (AD15-AD0) are written into the reset configuration register. The system can place configuration information on the address/data bus using weak external pullup or pulldown resistors, or using an external driver that is enabled during reset. The processor does not drive the address/data bus during reset. For example, the reset configuration register could be used to provide the software with the position of a configuration switch in the system. Using weak external pullup and pulldown resistors on the address and data bus, the system can provide the microcontroller with a value corresponding to the position of the jumper during a reset.
Power-Save Operation
The power-save mode of the Am186ES and Am188ES microcontrollers reduces power consumption and heat dissipation, thereby extending battery life in portable systems. In power-save mode, operation of the CPU and internal peripherals continues at a slower clock frequency. When an interrupt occurs, the microcontroller automatically returns to its normal operating frequency on the internal clock's next rising edge of t3.
Note: Power-save operation requires that clock-dependent devices be reprogrammed for clock frequency changes. Software drivers must be aware of clock frequency.
Processor Internal Clock PLL X1, X2 Power-Save Divisor (/2 to /128)
Mux Drive Enable Time Delay 6 2.5ns Drive Enable
CLKOUTA
Mux
CLKOUTB
Figure 9. Clock Organization
Am186/188ES and Am186/188ESLV Microcontrollers
45
PRELIMINARY
CHIP-SELECT UNIT
The Am186ES and Am188ES microcontrollers contain logic that provides programmable chip-select generation for both memories and peripherals. The logic can be programmed to provide ready and wait-state generation and latched address bits A1 and A2. The chip-select lines are active for all memory and I/O cycles in their programmed areas, whether they are generated by the CPU or by the integrated DMA unit. The Am186ES and Am188ES microcontrollers provide six chip-select outputs for use with memory devices and six more for use with peripherals in either memory space or I/O space. The six memory chip selects can be used to address three memory ranges. Each peripheral chip select addresses a 256-byte block that is offset from a programmable base address. A write to a chip select register will enable the corresponding chip select logic even if the actual pin has another function (e.g., PIO). The ARDY signal on the Am186ES and Am188ES microcontrollers is a true asynchronous ready signal. The ARDY pin accepts a rising edge that is asynchronous to CLKOUTA and is active High. If the falling edge of ARDY is not synchronized to CLKOUTA as specified, an additional clock period may be added.
Chip-Select Overlap
Although programming the various chip selects on the Am186ES microcontroller so that multiple chip select signals are asserted for the same physical address is not recommended, it may be unavoidable in some systems. In such systems, the chip selects whose assertions overlap must have the same configuration for ready (external ready required or not required) and the number of wait states to be inserted into the cycle by the processor. The peripheral control block (PCB) is accessed using internal signals. These internal signals function as chip selects configured with zero wait states and no external ready. Therefore, the PCB can be programmed to addresses that overlap external chip-select signals only if those external chip selects are programmed to zero wait states with no external ready required. When overlapping an additional chip select with either the LCS or UCS chip selects, it must be noted that setting the Disable Address (DA) bit in the LMCS or UMCS register disables the address from being driven on the AD bus for all accesses for which the associated chip select is asserted, including any accesses for which multiple chip selects assert. The MCS and PCS chip-select pins can be configured as either chip selects (normal function) or as PIO inputs or outputs. It should be noted; however, that the ready and wait state generation logic for these chip selects is in effect regardless of their configurations as chip selects or PIOs. This means that if these chip selects are enabled (by a write to the MMCS and MPCS for the MCS chip selects, or by a write to the PACS and MPCS registers for the PCS chip selects), the ready and wait state programming for these signals must agree with the programming for any other chip selects with which their assertion would overlap if they were configured as chip selects. Although the PCS4 signal is not available on an external pin, the ready and wait state logic for this signal still exists internal to the part. For this reason, the PCS4 address space must follow the rules for overlapping chip selects. The ready and wait-state logic for PCS6- PCS5 is disabled when these signals are configured as address bits A2-A1. Failure to configure overlapping chip selects with the same ready and wait state requirements may cause the processor to hang with the appearance of waiting
Chip-Select Timing
The timing for the UCS and LCS outputs is modified from the original 80C186 microcontroller. These outputs now assert in conjunction with the nonmultiplexed address bus for normal memory timing. To allow these outputs to be available earlier in the bus cycle, the number of programmable memory size selections has been reduced.
Ready and Wait-State Programming
The Am186ES and Am188ES microcontrollers can be programmed to sense a ready signal for each of the peripheral or memory chip-select lines. The ready signal can be either the ARDY or SRDY signal. Each chipselect control register (UMCS, LMCS, MMCS, PACS, and MPCS) contains a single-bit field that determines whether the external ready signal is required or ignored. The number of wait states to be inserted for each access to a peripheral or memory region is programmable. The chip-select control registers for UCS, LCS, MCS3-MCS0, PCS6, and PCS5 contain a two-bit field that determines the number of wait states from zero to three to be inserted. PCS3-PCS0 use three bits to provide additional values of 5, 7, 9, and 15 wait states. When external ready is required, internally programmed wait states will always complete before external ready can terminate or extend a bus cycle. For example, if the internal wait states are set to insert two wait states, the processor samples the external ready pin during the first wait cycle. If external ready is asserted at that time, the access completes after six cycles (four cycles plus two wait states). If external ready is not asserted during the first wait cycle, the access is extended until ready is asserted, and one more wait state occurs followed by t4. 46
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY for a ready signal. This behavior may occur even in a system in which ready is always asserted (ARDY or SRDY tied High). Configuring PCS in I/O space with LCS or any other chip select configured for memory address 0 is not considered overlapping of the chip selects. Overlapping chip selects refers to configurations where more than one chip select asserts for the same physical address.
Peripheral Chip Selects
The Am186ES and Am188ES microcontrollers provide six chip selects, PCS6-PCS5 and PCS3-PCS0, for use within a user-configured memory or I/O block. PCS4 is not available on the Am186ES and Am188ES microcontrollers. The base address of the memory block can be located anywhere within the 1-Mbyte memory address space, exclusive of the areas associated with the UCS, LCS, and MCS chip selects, or they can be configured to access the 64-Kbyte I/O space. The PCS pins are not active on reset. PCS6-PCS5 can be programmed for zero to three wait states. PCS3- PCS0 can be programmed for four additional wait-state values: 5, 7, 9, and 15. The AUXCON register can be used to configure PCS for 8-bit or 16-bit accesses. The bus width of the PCS range is determined by the width of the non-UCS/nonLCS memory range or by the width of the I/O area. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80C186/188 microcontrollers.
Upper Memory Chip Select
The Am186ES and Am188ES microcontrollers provide a UCS chip select for the top of memory. On reset the Am186ES and Am188ES microcontrollers begin fetching and executing instructions at memory location FFFF0h. Therefore, upper memory is usually used as instruction memory. To facilitate this usage, UCS defaults to active on reset, with a default memory range of 64 Kbytes from F0000h to FFFFFh, with external ready required and three wait states automatically inserted. The UCS memory range always ends at FFFFFh. The UCS lower boundary is programmable.
Low Memory Chip Select
The Am186ES and Am188ES microcontrollers provide an LCS chip select for lower memory. The AUXCON register can be used to configure LCS for 8-bit or 16-bit accesses. Since the interrupt vector table is located at the bottom of memory starting at 00000h, the LCS pin is usually used to control data memory. The LCS pin is not active on reset.
REFRESH CONTROL UNIT
The Refresh Control Unit (RCU) automatically generates refresh bus cycles. After a programmable period of time, the RCU generates a memory read request to the bus interface unit. The RCU is fixed to three wait states for the PSRAM auto refresh mode. In the Am186ES and Am188ES microcontrollers, refresh is enabled when the ENA bit is set in the enable RCU register, offset E4h. This is different from the Am186EM and Am188EM microcontrollers where the PSRAM enable bit in the low memory chip-select register, offset A2h, enables refresh. The refresh function is the same as on the Am186EM and Am188EM microcontrollers, except that the DRAM address is not driven on DRAM refreshes. If the HLDA pin is active when a refresh request is generated (indicating a bus hold condition), the Am186ES and Am188ES microcontrollers deactivate the HLDA pin in order to perform a refresh cycle. The external bus master must remove the HOLD signal for at least one clock in order to allow the refresh cycle to execute.
Midrange Memory Chip Selects
The Am186ES and Am188ES microcontrollers provide four chip selects, MCS3-MCS0, for use in a user-locatable memory block. With some exceptions, the base address of the memory block can be located anywhere within the 1-Mbyte memory address space of the Am186ES and Am188ES microcontrollers. The areas associated with the UCS and LCS chip selects are excluded. If they are mapped to memory, the address range of the peripheral chip selects, PCS6, PCS5, and PCS3-PCS0, are also excluded. The MCS address range can overlap the PCS address range if the PCS chip selects are mapped to I/O space. MCS0 can be configured to be asserted for the entire MCS range. When configured in this mode, the MCS3- MCS1 pins can be used as PIOs. The AUXCON register can be used to configure MCS for 8-bit or 16-bit accesses. The bus width of the MCS range is determined by the width of the non-UCS/nonLCS memory range. Unlike the UCS and LCS chip selects, the MCS outputs assert with the same timing as the multiplexed AD address bus.
Am186/188ES and Am186/188ESLV Microcontrollers
47
PRELIMINARY
INTERRUPT CONTROL UNIT
The Am186ES and Am188ES microcontrollers can receive interrupt requests from a variety of sources, both internal and external. The internal interrupt controller arranges these requests by priority and presents them one at a time to the CPU. There are up to eight external interrupt sources on the Am186ES and Am188ES microcontrollers--seven maskable interrupt pins and one nonmaskable interrupt (NMI) pin. In addition, there are eight internal interrupt sources (three timers, two DMA channels, the two asynchronous serial ports, and the Watchdog Timer NMI) that are not connected to external pins. INT5 and INT6 are multiplexed with DRQ0 and DRQ1. These two interrupts are available if the associated DMA is not enabled or is being used with internal synchronization. The Am186ES and Am188ES microcontrollers provide up to six interrupt sources not present on the 80C186 and 80C188 microcontrollers. There are up to three additional external interrupt pins--INT4, INT5, and INT6. These pins operate much like the INT3-INT0 interrupt pins on the 80C186 and 80C188 microcontrollers. There are also two internal interrupts from the serial ports and the watchdog timer can generate interrupts. The seven maskable interrupt request pins can be used as direct interrupt requests. INT4-INT0 can be either edge triggered or level triggered. INT6 and INT5 are edge triggered only. In addition, INT0 and INT1 can be configured in cascade mode for use with an external 82C59A-compatible interrupt controller. When INT0 is configured in cascade mode, the INT2 pin is automatically configured in its INTA0 function. When INT1 is configured in cascade mode, the INT3 pin is automatically configured in its INTA1 function. An external interrupt controller can be used as the system master by programming the internal interrupt controller to operate in slave mode. INT6-INT4 are not available in slave mode. Interrupts are automatically disabled when an interrupt is taken. Interrupt-service routines (ISRs) may re-enable interrupts by setting the IF flag. This allows interrupts of greater or equal priority to interrupt the currently executing ISR. Interrupts from the same source are disabled as long as the corresponding bit in the interrupt in-service register is set. INT1 and INT0 provide a special bit to enable special fully nested mode. When configured in special fully nested mode, the interrupt source may generate a new interrupt regardless of the setting of the in-service bit.
TIMER CONTROL UNIT
There are three 16-bit programmable timers and a watchdog timer on the Am186ES and Am188ES microcontrollers. Timer 0 and timer 1 are connected to four external pins (each one has an input and an output). These two timers can be used to count or time external events, or to generate nonrepetitive or variable-duty-cycle waveforms. When pulse width demodulation is enabled, timer 0 and timer 1 are used to measure the width of the High and Low pulses on the PWD pin. (See the Pulse Width Demodulation section on page 51.) Timer 2 is not connected to any external pins. It can be used for real-time coding and time-delay applications. It can also be used as a prescaler to timers 0 and 1 or to synchronize DMA transfers. The programmable timers are controlled by eleven 16bit registers in the peripheral control block. A timer's timer-count register contains the current value of that timer. The timer-count register can be read or written with a value at any time, whether the timer is running or not. The microcontroller increments the value of the timer-count register each time a timer event occurs. Each timer also has a maximum-count register that defines the maximum value the timer can reach. When the timer reaches the maximum value, it resets to 0 during the same clock cycle. The value in the maximum-count register is never stored in the timer-count register. Also, timers 0 and 1 have a secondary maximum-count register. Using both the primary and secondary maximum-count registers lets the timer alternate between two maximum values. If the timer is programmed to use only the primary maximum-count register, the timer output pin switches Low for one clock cycle after the maximum value is reached. If the timer is programmed to use both of its maximum-count registers, the output pin indicates which maximum-count register is currently in control, thereby creating a waveform. The duty cycle of the waveform depends on the values in the maximumcount registers. Each timer is serviced every fourth clock cycle, so a timer can operate at a speed of up to one-quarter of the internal clock frequency. A timer can be clocked externally at this same frequency; however, because of internal synchronization and pipelining of the timer circuitry, the timer output can take up to six clock cycles to respond to the clock or gate input.
48
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Watchdog Timer
The Am186ES and Am188ES microcontrollers provide a true watchdog timer function. The Watchdog Timer (WDT) can be used to regain control of the system when software fails to respond as expected. The WDT is active after reset. It can only be modified a single time by a keyed sequence of writes to the watchdog timer control register (WDTCON) following reset. This single write can either disable the timer or modify the timeout period and the action taken upon timeout. A keyed sequence is also required to reset the current WDT count. This behavior ensures that randomly executing code will not prevent a WDT event from occurring. The WDT supports up to a 1.67-second timeout period in a 40-MHz system. After reset, the WDT is enabled and the timeout period is set to its maximum value. The WDT can be configured to cause either an NMI interrupt or a system reset upon timeout. If the WDT is configured for NMI, the NMIFLAG in the WDTCON register is set when the NMI is generated. The NMI interrupt service routine (ISR) should examine this flag to determine if the interrupt was generated by the WDT or by an external source. If the NMIFLAG is set, the ISR should clear the flag by writing the correct keyed sequence to the WDTCON register. If the NMIFLAG is set when a second WDT timeout occurs, a WDT system reset is generated rather than a second NMI event. When the processor takes a WDT reset, either due to a single WDT event with the WDT configured to generate resets or due to a WDT event with the NMIFLAG set, the RSTFLAG in the WDTCON register is set. This allows system initialization code to differentiate between a hardware reset and a WDT reset and take appropriate action. The RSTFLAG is cleared when the WDTCON register is read or written. The processor does not resample external pins during a WDT reset. This means that the clocking, the reset configuration register, and any other features that are user-selectable during reset do not change when a WDT system reset occurs. All other activities are identical to those of a normal system reset.
DIRECT MEMORY ACCESS (DMA)
Direct memory access (DMA) permits transfer of data between memory and peripherals without CPU involvement. The DMA unit in the Am186ES and Am188ES microcontrollers, shown in Figure 10, provides two high-speed DMA channels. Data transfers can occur between memory and I/O spaces (e.g., memory to I/O) or within the same space (e.g., memory to memory or I/O to I/O). The DMA channels can be directly connected to the asynchronous serial ports. Either bytes or words can be transferred to or from even or odd addresses on the Am186ES microcontroller. However, the Am186ES microcontroller does not support word DMA transfers to or from memory configured for 8-bit accesses. The Am188ES microcontroller does not support word transfers. Only two bus cycles (a minimum of eight clocks) are necessary for each data transfer. Each channel accepts a DMA request from one of four sources: the channel request pin (DRQ1-DRQ0), Timer 2, a serial port, or the system software. The channels can be programmed with different priorities in the event of a simultaneous DMA request or if there is a need to interrupt transfers on the other channel.
DMA Operation
Each channel has six registers in the peripheral control block that define specific channel operations. The DMA registers consist of a 20-bit source address (two registers), a 20-bit destination address (two registers), a 16bit transfer count register, and a 16-bit control register. The DMA transfer count register (DTC) specifies the number of DMA transfers to be performed. Up to 64K of byte or word transfers can be performed with automatic termination. The DMA control registers define the channel operation. All registers can be modified during any DMA activity. Any changes made to the DMA registers are reflected immediately in DMA operation. Table 8. Am186ES Microcontroller Maximum DMA Transfer Rates
Maximum DMA Transfer Rate (Mbytes) Type of Synchronization Selected Unsynchronized Source Synch Destination Synch (CPU needs bus) Destination Synch (CPU does not need bus) 40 MHz 10 10 6.6 8 33 MHz 8.25 8.25 5.5 6.6 25 MHz 6.25 6.25 4.16 5 20 MHz 5 5 3.3 4
Note: The Watchdog Timer (WDT) is active after reset.
Am186/188ES and Am186/188ESLV Microcontrollers
49
PRELIMINARY
20-bit Adder/Subtractor
Adder Control Logic
Timer Request DRQ1/Serial Port Request Selection Logic
20
DRQ0/Serial Port
Transfer Counter Ch. 1 Destination Address Ch. 1 Source Address Ch. 1 Transfer Counter Ch. 0 Destination Address Ch. 0 Source Address Ch. 0 DMA Control Logic
Interrupt Request
Channel Control Register 1 Channel Control Register 0 20 16
Internal Address/Data Bus
Figure 10.
DMA Unit Block Diagram
DMA Channel Control Registers
Each DMA control register determines the mode of operation for the particular DMA channel. The DMA control registers specify the following: n The mode of synchronization n Whether bytes or words are transferred n Whether an interrupt is generated after the last transfer n Whether the DRQ pins are configured as INT pins n Whether DMA activity ceases after a programmed number of DMA cycles n The relative priority of the DMA channel with respect to the other DMA channel n Whether the source address is incremented, decremented, or maintained constant after each transfer n Whether the source address addresses memory or I/O space n Whether the destination address is incremented, decremented, or maintained constant after transfers n Whether the destination address addresses memory or I/O space
DMA Priority
The DMA channels can be programmed so that one channel is always given priority over the other, or they can be programmed to alternate cycles when both have DMA requests pending. DMA cycles always have priority over internal CPU cycles except between locked memory accesses or word accesses to odd memory locations. However, an external bus hold takes priority over an internal DMA cycle. Because an interrupt request cannot suspend a DMA operation and the CPU cannot access memory during a DMA cycle, interrupt latency time suffers during sequences of continuous DMA cycles. An NMI request, however, causes all internal DMA activity to halt. This allows the CPU to respond quickly to the NMI request.
50
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
PULSE WIDTH DEMODULATION
For many applications, such as bar-code reading, it is necessary to measure the width of a signal in both its High and Low phases. The Am186ES and Am188ES microcontrollers provide a pulse-width demodulation (PWD) option to fulfill this need. The PWD bit in the system configuration register (SYSCON) enables the PWD option. Please note that the Am186ES and Am188ES microcontrollers do not support analog-todigital conversion. In PWD mode, TMRIN0, TMRIN1, INT2, and INT4 are configured internal to the microcontroller to support the detection of rising and falling edges on the PWD input pin (INT2/INTA0/PWD) and to enable either timer 0 when the signal is High or timer 1 when the signal is Low. The INT4, TMRIN0, and TMRIN1 pins are not used in PWD mode and so are available for use as PIOs. The following diagram shows the behavior of a system for a typical waveform.
ASYNCHRONOUS SERIAL PORTS
The Am186ES and Am188ES microcontrollers provide two independent asynchronous serial ports. These ports provide full-duplex, bidirectional data transfer using several industry-standard communications protocols. The serial ports can be used as sources or destinations of DMA transfers. The asynchronous serial ports support the following features: n Full-duplex operation n 7-bit, 8-bit, or 9-bit data transfers n Odd, even, or no parity n One stop bit n Two lengths of break characters n Error detection -- Parity errors -- Framing errors -- Overrun errors n Hardware handshaking with the following selectable control signals: -- Clear-to-send (CTS)
INT2
INT4
INT2 Ints generated TMR1 enabled TMR0 enabled
-- Enable-receiver-request (ENRX) -- Ready-to-send (RTS) -- Ready-to-receive (RTR) n DMA to and from the serial ports n Separate maskable interrupts for each port n Multidrop protocol (9-bit) support n Independent baud rate generators n Maximum baud rate of 1/16th of the CPU clock n Double-buffered transmit and receive
The interrupt service routine (ISR) for the INT2 and INT4 interrupts should examine the current count of the associated timer, timer 1 for INT2 and timer 0 for INT4, in order to determine the pulse width. The ISR should then reset the timer count register in preparation for the next pulse. Since the timers count at one quarter of the processor clock rate, this determines the maximum resolution that can be obtained. Further, in applications where the pulse width may be short, it may be necessary to poll the INT2 and INT4 request bits in the interrupt request register in order to avoid the overhead involved in taking and returning from an interrupt. Overflow conditions, where the pulse width is greater than the maximum count of the timer, can be detected by monitoring the Maximum Count (MC) bit in the associated timer or by setting the INT bit to enable timer interrupt requests.
DMA Transfers through the Serial Port
The Am186ES and Am188ES microcontrollers support DMA transfers both to and from the serial port. Either or both DMA channels and either or both serial ports can be used for DMA transmits or receives. See the DMA Control register descriptions in the Am186ES and Am188ES Microcontrollers User's Manual for more information.
Am186/188ES and Am186/188ESLV Microcontrollers
51
PRELIMINARY
PROGRAMMABLE I/O (PIO) PINS
There are 32 pins on the Am186ES and Am188ES microcontrollers that are available as user-programmable I/O signals. Table 2 on page 34 and Table 3 on page 34 list the PIO pins. Each of these pins can be used as a user-programmable input or output signal if the normal shared function is not needed. If a pin is enabled to function as a PIO signal, the preassigned signal function is disabled and does not affect the level on the pin. A PIO signal can be configured to operate as an input or output with or without a weak pullup or pulldown, or as an open-drain output. After power-on reset, the PIO pins default to various configurations. The column titled Power-On Reset Status in Table 2 on page 34 and Table 3 on page 34 lists
the defaults for the PIOs. The system initialization code must reconfigure the PIOs as required. The A19-A17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address FFFF0h. The DT/R, DEN, and SRDY pins also default to normal operation on power-on reset. Note that emulators use A19, A18, A17, S6, and UZI. In environments where an emulator is needed, these pins must be configured for normal function--not as PIOs. If the AD15-AD0 bus override is enabled on power-on reset, then S6/CLKDIV2 and UZI revert to normal operation instead of PIO input with pullup. If BHE/ADEN (186) or RFSH2/ADEN (188) is held Low during poweron reset, the AD15-AD0 bus override is enabled.
52
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Storage temperature Am186ES/Am188ES....................... -65C to +125C Am186ESLV/Am188ESLV .............. -65C to +125C Voltage on any pin with respect to ground Am186/188ES ............................ -0.5 V to Vcc +0.5 V Am186/188ESLV ....................... -0.5 V to V cc +0.5 V
the functionality of the device is guaranteed. Am186ES/Am188ES Microcontrollers Commercial (TC) .................................0C to +100C Industrial* (TA) ..................................-40C to +85C VCC up to 33 MHz......................................5 V 10% VCC greater than 33 MHz ............................5 V 5% Am186ESLV/Am188ESLV Microcontrollers Commercial (TA) ................................... 0C to +70C VCC up to 25 MHz................................. 3.3 V 0.3 V Where: TC = case temperature TA = ambient temperature
Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
OPERATING RANGES
Operating Ranges define those limits between which
*Industrial versions of Am186ES and Am188ES microcontrollers are available in 20 and 25 MHz operating frequencies only.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Preliminary Symbol Parameter Description Input Low Voltage (Except X1) Clock Input Low Voltage (X1) Input High Voltage (Except RES and X1) Input High Voltage (RES) Clock Input High Voltage (X1) Output Low Voltage Am186ES and Am188ES VOL Am186ESLV and Am188ESLV Output High Voltage(a) VOH Am186ES and Am188ES IOH = -2.4 mA @ 2.4 V IOH = -200 A @ VCC -0.5 Am186ESLV and Am188ESLV Power Supply Current @ 0C ICC ILI ILO VCLO VCHO Am186ES and Am188ES Am186ESLV and Am188ESLV Input Leakage Current @ 0.5 MHz Output Leakage Current @ 0.5 MHz Clock Output Low Clock Output High VCC = 5.5 V (b) VCC = 3.6 V (b)
(c)
Test Conditions
Min -0.5 -0.5 2.0 2.4 VCC -0.8
Max 0.8 0.8 VCC +0.5 VCC +0.5 VCC +0.5 0.45 0.45
Unit V V V V V
VIL VIL1 VIH VIH 1 VIH 2
IOL = 2.5 mA (S2-S0) IOL = 2.0 mA (others) IOL = 1.5 mA (S2-S0) IOL = 1.0 mA (others) 2.4 VCC -0.5 VCC -0.5
V V
VCC +0.5 VCC VCC 5.9 2.75 10 10 0.45
V V V
IOH = -200 A @ VCC -0.5
mA/MHz mA/MHz A A V V
0.45 VVIN VCC 0.45 VVOUT VCC ICLO = 4.0 mA ICHO = -500 A VCC -0.5
Notes: a The LCS/ONCE0, MCS3-MCS0, UCS/ONCE1, and RD pins have weak internal pullup resistors. Loading the LCS/ONCE0 and UCS/ONCE1 pins in excess of IOH = -200 A during reset can cause the device to go into ONCE mode. b c d Current is measured with the device in RESET with X1 and X2 driven and all other non-power pins open but held High or Low. Testing is performed with the pins floating, either during HOLD or by invoking the ONCE mode. Power supply current for the Am186ESLV and Am188ESLV microcontrollers, which are available in 20 and 25 MHz operating frequencies only.
Am186/188ES and Am186/188ESLV Microcontrollers
53
PRELIMINARY
Capacitance
Symbol Parameter Description CIN Input Capacitance CIO Output or I/O Capacitance Test Conditions @ 1 MHz @ 1 MHz Preliminary Min Max 10 20 Unit pF pF
Note: Capacitance limits are guaranteed by characterization.
Power Supply Current
For the following typical system specification shown in Figure 11, ICC has been measured at 4.0 mA per MHz of system clock. For the following typical system specification shown in Figure 12, I CC has been measured at 5.9 mA per MHz of system clock. The typical system is measured while the system is executing code in a typical application with maximum voltage and maximum case temperature. Actual power supply current is dependent on system design and may be greater or less than the typical ICC figure presented here. Typical current in Figure 11 is given by: ICC = 4.0 mA freq(MHz) Typical current in Figure 12 is given by: ICC = 5.9 mA freq(MHz) Please note that dynamic ICC measurements are dependent upon chip activity, operating frequency, output buffer logic, and capacitive/resistive loading of the outputs. For these ICC measurements, the devices were set to the following modes: n No DC loads on the output buffers n Output capacitive load set to 35 pF n AD bus set to data only n PIOs are disabled n Timer, serial port, refresh, and DMA are enabled
ICC (mA)
140 120 100 80 60 40 20 0 10 20 30 25 MHz 20 MHz
Table 9 shows the variables that are used to calculate the typical power consumption value for each version of the Am186ESLV and Am188ESLV microcontrollers. Table 9. Typical Power Consumption Calculation for the Am186ESLV and Am188ESLV
MHz ICC Volts / 1000 = P MHz Typical ICC Volts 20 4.0 3.6 25 4.0 3.6 Typical Power in Watts 0.288 0.360
Clock Frequency (MHz)
Figure 11. Typical ICC Versus Frequency for the Am186ESLV and Am188ESLV
280 240 200 160 25 MHz 20 MHz 33 MHz 40 MHz
ICC (mA)
120 80 40 0 10
20
30
40
50
Clock Frequency (MHz)
Figure 12.
Typical Icc Versus Frequency for Am186ES and Am188ES
54
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
THERMAL CHARACTERISTICS TQFP Package
The Am186ES and Am188ES microcontrollers are specified for operation with case temperature ranges from 0C to +100C for a commercial device. Case temperature is measured at the top center of the pack age as shown in Figure 13. The various temperatures and thermal resistances can be determined using the equations in Figure 14 with information given in Table 10. JA is the total thermal resistance. JA is the sum of JC, the internal thermal resistance of the assembly, and CA, the case to ambient thermal resistance.
The variable P is power in watts. Typical power supply current (ICC) is TBD mA per MHz of clock frequency. JA TC JC CA
JA = JC + CA Figure 13. Thermal Resistance(C/Watt)
JA = JC + CA P=ICC freq (MHz) VCC TJ =TC +( PJC ) TJ =TA + ( PJA ) TC =TJ -( PJC ) TC =TA +( PCA ) TA =TJ -( PJA ) TA =TC -( PCA ) Figure 14. Thermal Characteristics Equations
Table 10. Thermal Characteristics (C/Watt)
Airflow (Linear Feet per Minute) 0 fpm 200 fpm 400 fpm 600 fpm TQFP/2-Layer 0 fpm 200 fpm 400 fpm 600 fpm PQFP/4-Layer to 6-Layer 0 fpm 200 fpm 400 fpm 600 fpm TQFP/4-Layer to 6-Layer 0 fpm 200 fpm 400 fpm 600 fpm
Package/Board PQFP/2-Layer
JA 45 39 35 33 56 46 40 38 23 21 19 17 30 28 26 24
JC 7 7 7 7 10 10 10 10 5 5 5 5 6 6 6 6
CA 38 32 28 26 46 36 30 28 18 16 14 12 24 22 20 18
Am186/188ES and Am186/188ESLV Microcontrollers
55
PRELIMINARY
Typical Ambient Temperatures
The typical ambient temperature specifications are based on the following assumptions and calculations: The commercial operating range of the Am186ES and Am188ES microcontrollers is a case temperature TC of 0 to 100 degrees Centigrade. TC is measured at the top center of the package. An increase in the ambient temperature causes a proportional increase in TC. The 40-MHz microcontroller is specified as 5.0 V plus or minus 5%. Therefore, 5.25 V is used for calculating typical power consumption on the 40-MHz microcontroller. Microcontrollers up to 33 MHz are specified as 5.0 V plus or minus 10%. Therefore, 5.5 V is used for calculating typical power consumption up to 33 MHz. Typical power supply current (ICC) in normal usage is estimated at 5.9 mA per MHz of microcontroller clock rate. Typical power consumption (watts) = (5.9 mA/MHz) times microcontroller clock rate times voltage divided by 1000. Table 11 shows the variables that are used to calculate the typical power consumption value for each version of the Am186ES and Am188ES microcontrollers.
column titled Speed/Pkg/Board in Table 12 indicates the clock speed in MHz, the type of package (P for PQFP and T for TQFP), and the type of board (2 for 2layer and 4-6 for 4-layer to 6-layer).
Table 12. Junction Temperature Calculation
Speed/ Pkg/ Board 40/P2 40/T2 40/P4-6 40/T4-6 33/P2 33/T2 33/P4-6 33/T4-6 25/P2 25/T2 25/P4-6 25/T4-6 20/P2 20/T2 20/P4-6 20/T4-6 TJ = TC + (P JC) TJ 108.673 112.39 106.195 107.434 107.49595 110.7085 105.35425 106.4251 105.67875 108.1125 104.05625 104.8675 104.543 106.49 103.245 103.894 TC 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 P 1.239 1.239 1.239 1.239 1.07085 1.07085 1.07085 1.07085 0.81125 0.81125 0.81125 0.81125 0.649 0.649 0.649 0.649 JC 7 10 5 6 7 10 5 6 7 10 5 6 7 10 5 6
Table 11.
Typical Power Consumption Calculation
Typical Power (P) in Watts 1.239 1.07085 0.81125 0.649
P = MHz ICC Volts / 1000 MHz 40 33 25 20 Typical ICC 5.9 5.9 5.9 5.9 Volts 5.25 5.5 5.5 5.5
By using T J from Table 12, the typical power consumption value from Table 11, and a JA value from Table 10, the typical ambient temperature TA can be calculated using the following formula from Figure 14: TA = TJ - (P JA) For example, TA for a 40-MHz PQFP design with a 2layer board and 0 fpm airflow is calculated as follows: TA = 108.673 - (1.239 45) TA = 52.918 In this calculation, TJ comes from Table 12, P comes from Table 11, and JA comes from Table 10. See Table 13. TA for a 33-MHz TQFP design with a 4-layer to 6-layer board and 200 fpm airflow is calculated as follows: TA = 106.4251 - (1.07085 28) TA = 76.4413 See Table 16 for the result of this calculation. Table 13 through Table 16 and Figure 15 through Figure 18 show TA based on the preceding assumptions and calculations for a range of JA values with airflow from 0 linear feet per minute to 600 linear feet per minute.
Thermal resistance is a measure of the ability of a package to remove heat from a semiconductor device. A safe operating range for the device can be calculated using the formulas from Figure 14 and the variables in Table 10. By using the maximum case rating T C , the typical power consumption value from Table 11, and JC from Table 10, the junction temperature T J can be calculated by using the following formula from Figure 14. TJ = TC + (P JC) Table 12 shows TJ values for the various versions of the Am186ES and Am188ES microcontrollers. The
56
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY Table 13 shows typical maximum ambient temperatures in degrees Centigrade for a PQFP package used on a 2layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 15 graphically illustrates the typical temperatures in Table 13. Table 13. Typical Ambient Temperatures for PQFP with a 2-Layer Board
Linear Feet per Minute Airflow Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz Typical Power (Watts) 1.239 1.07085 0.81125 0.649 0 fpm 52.918 59.3077 69.1725 75.338 200 fpm 60.352 65.7328 74.04 79.232 400 fpm 65.308 70.0162 77.285 81.828 600 fpm 67.786 72.1579 78.9075 83.126
90
Typical Ambient Temperature (Degrees C)
s 80 s 70 s x x
s x
I
x
I
q
I
60 q
q
I
q
Legend: q 40 MHz H 33 MHz x 25 Mhz s 20 MHz
50
40
0 fpm 200 fpm 400 fpm 600 fpm
Airflow (Linear Feet Per Minute)
Figure 15. Typical Ambient Temperatures for PQFP with a 2-Layer Board
Am186/188ES and Am186/188ESLV Microcontrollers
57
PRELIMINARY Table 14 shows typical maximum ambient temperatures in degrees Centigrade for a TQFP package used on a 2layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 16 graphically illustrates the typical temperatures in Table 14. Table 14. Typical Ambient Temperatures for TQFP with a 2-Layer Board
Linear Feet per Minute Airflow Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz Typical Power (Watts) 1.239 1.07085 0.81125 0.649 0 fpm 43.006 50.7409 62.6825 70.146 200 fpm 55.396 61.4494 70.795 76.636 400 fpm 62.83 67.8745 75.6625 80.53 600 fpm 65.308 70.0162 77.285 81.828
90 Typical Ambient Temperature (Degrees C)
s 80 s s x x
70
s
x
I I
q
x 60
I
q
q
I
Legend: q 40 MHz H 33 MHz x 25 Mhz s 20 MHz 40
0 fpm 200 fpm 400 fpm 600 fpm
50
q
Airflow (Linear Feet Per Minute)
Figure 16.
Typical Ambient Temperatures for TQFP with a 2-Layer Board
58
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY Table 15 shows typical maximum ambient temperatures in degrees Centigrade for a PQFP package used on a 4layer to 6-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 17 graphically illustrates the typical temperatures in Table 15. Table 15. Typical Ambient Temperatures for PQFP with a 4-Layer to 6-Layer Board
Linear Feet per Minute Airflow Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz Typical Power (Watts) 1.239 1.07085 0.81125 0.649 0 fpm 77.698 80.7247 85.3975 88.318 200 fpm 80.176 82.8664 87.02 89.616 400 fpm 82.654 85.0081 88.6425 90.914 600 fpm 85.132 87.1498 90.265 92.212
95 s Typical Ambient Temperature (Degrees C) s 90 s x 85 x s x x
I I
q
I I
80 q q
q
Legend: q 40 MHz H 33 MHz x 25 Mhz s 20 MHz
75
70
0 fpm 200 fpm 400 fpm 600 fpm
Airflow (Linear Feet Per Minute)
Figure 17.
Typical Ambient Temperatures for PQFP with a 4-Layer to 6-Layer Board
Am186/188ES and Am186/188ESLV Microcontrollers
59
PRELIMINARY Table 16 shows typical maximum ambient temperatures in degrees Centigrade for a TQFP package used on a 4layer to 6-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 18 graphically illustrates the typical temperatures in Table 16. Table 16. Typical Ambient Temperatures for TQFP with a 4-Layer to 6-Layer Board
Linear Feet per Minute Airflow Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz Typical Power (Watts) 1.239 1.07085 0.81125 0.649 0 fpm 70.264 74.2996 80.53 84.424 200 fpm 72.742 76.4413 82.1525 85.722 400 fpm 75.22 78.583 83.775 87.02 600 fpm 77.698 80.7247 85.3975 88.318
95
Typical Ambient Temperature (Degrees C)
90 s s s 85 s x x 80 x x
I I I
q q
Legend: q 40 MHz H 33 MHz x 25 Mhz s 20 MHz
75
I
q 70 q
0 fpm 200 fpm 400 fpm 600 fpm
Airflow (Linear Feet Per Minute)
Figure 18.
Typical Ambient Temperatures for TQFP with a 4-Layer to 6-Layer Board
60
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
COMMERCIAL SWITCHING CHARACTERISTICS AND WAVEFORMS
In the switching waveforms that follow, several abbreviations are used to indicate the specific periods of a bus cycle. These periods are referred to as time states. A typical bus cycle is composed of four consecutive time states: t1, t2, t3, and t4. Wait states, which represent multiple t3 states, are referred to as tw states. When no bus cycle is pending, an idle (ti) state occurs. In t h e s w i tc h i n g pa r a m e te r de s c r i p t i on s , t h e multiplexed address is referred to as the AD address bus; the demultiplexed address is referred to as the A address bus.
Key to Switching Waveforms
WAVEFORM INPUT Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUT Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance Off State Invalid
Invalid
Am186/188ES and Am186/188ESLV Microcontrollers
61
PRELIMINARY
Alphabetical Key to Switching Parameter Symbols
Parameter Symbol tARYCH tARYCHL tARYHDSH tARYHDV tARYLCL tARYLDSH tAVBL tAVCH tAVLL tAVRL tAVWL tAZRL tCH1CH2 tCHAV tCHCK tCHCL tCHCSV tCHCSX tCHCTV tCHCV tCHCZ tCHDX tCHLH tCHLL tCHRFD tCHSV tCICOA tCICOB tCKHL tCKIN tCKLH tCL2CL1 tCLARX tCLAV tCLAX tCLAZ tCLCH tCLCK tCLCL tCLCLX tCLCSL No. 49 51 95 89 52 96 87 14 12 66 65 24 45 68 38 44 67 18 22 64 63 8 9 11 79 3 69 70 39 36 40 46 50 5 6 15 43 37 42 80 81 Description ARDY Resolution Transition Setup Time ARDY Inactive Holding Time ARDY High to DS High ARDY Assert to Data Valid ARDY Setup Time ARDY Low to DS High A Address Valid to WHB, WLB Low AD Address Valid to Clock High AD Address Valid to ALE Low A Address Valid to RD Low A Address Valid to WR Low AD Address Float to RD Active CLKOUTA Rise Time CLKOUTA High to A Address Valid X1 High Time CLKOUTA High Time CLKOUTA High to LCS/UCS Valid MCS/PCS Inactive Delay Control Active Delay 2 Command Lines Valid Delay (after Float) Command Lines Float Delay Status Hold Time ALE Active Delay ALE Inactive Delay CLKOUTA High to RFSH Valid Status Active Delay X1 to CLKOUTA Skew X1 to CLKOUTB Skew X1 Fall Time X1 Period X1 Rise Time CLKOUTA Fall Time ARDY Active Hold Time AD Address Valid Delay Address Hold AD Address Float Delay CLKOUTA Low Time X1 Low Time CLKOUTA Period LCS Inactive Delay LCS Active Delay
62
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Alphabetical Key to Switching Parameter Symbols (continued)
Parameter Symbol tCLCSV tCLDOX tCLDV tCLDX tCLHAV tCLRF tCLRH tCLRL tCLSH tCLSRY tCLTMV tCOAOB tCSHARYL tCVCTV tCVCTX tCVDEX tCXCSX tDSHDIR tDSHDIW tDSHDX tDSHLH tDSLDD tDSLDV tDVCL tDVDSL tDXDL tHVCL tINVCH tINVCL tLCRF tLHAV tLHLL tLLAX tLOCK tLRLL tRESIN tRFCY tRHAV tRHDX tRHDZ tRHLH No. 16 30 7 2 62 82 27 25 4 48 55 83 88 20 31 21 17 92 98 93 41 90 91 1 97 19 58 53 54 86 23 10 13 61 84 57 85 29 59 94 28 Data Hold Time Data Valid Delay Data in Hold HLDA Valid Delay CLKOUTA High to RFSH Invalid RD Inactive Delay RD Active Delay Status Inactive Delay SRDY Transition Hold Time Timer Output Delay CLKOUTA to CLKOUTB Skew Chip Select to ARDY Low Control Active Delay 1 Control Inactive Delay DEN Inactive Delay MCS/PCS Hold from Command Inactive DS High to Data Invalid--Read DS High to Data Invalid--Write DS High to Data Bus Turn-off Time DS Inactive to ALE Inactive DS Low to Data Driven DS Low to Data Valid Data in Setup Data Valid to DS Low DEN Inactive to DT/R Low HOLD Setup Peripheral Setup Time DRQ Setup Time LCS Inactive to RFSH Active Delay ALE High to Address Valid ALE Width AD Address Hold from ALE Inactive Maximum PLL Lock Time LCS Precharge Pulse Width RES Setup Time RFSH Cycle Time RD Inactive to AD Address Active RD High to Data Hold on AD Bus RD High to Data Bus Turn-off Time RD Inactive to ALE High Description MCS/PCS Active Delay
Am186/188ES and Am186/188ESLV Microcontrollers
63
PRELIMINARY
Alphabetical Key to Switching Parameter Symbols (continued)
Parameter Symbol tRLRH tSRYCL tWHDEX tWHDX tWHLH tWLWH No. 26 47 35 34 33 32 RD Pulse Width SRDY Transition Setup Time WR Inactive to DEN Inactive Data Hold after WR WR Inactive to ALE High WR Pulse Width Description
Note: The following parameters are not defined or used as this time: 56, 60, 71-78.
64
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Numerical Key to Switching Parameter Symbols
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Parameter Symbol tDVCL tCLDX tCHSV tCLSH tCLAV tCLAX tCLDV tCHDX tCHLH tLHLL tCHLL tAVLL tLLAX tAVCH tCLAZ tCLCSV tCXCSX tCHCSX tDXDL tCVCTV tCVDEX tCHCTV tLHAV tAZRL tCLRL tRLRH tCLRH tRHLH tRHAV tCLDOX tCVCTX tWLWH tWHLH tWHDX tWHDEX tCKIN tCLCK tCHCK tCKHL tCKLH tDSHLH tCLCL Data in Setup Data in Hold Status Active Delay Status Inactive Delay AD Address Valid Delay Address Hold Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay AD Address Valid to ALE Low AD Address Hold from ALE Inactive AD Address Valid to Clock High AD Address Float Delay MCS/PCS Active Delay MCS/PCS Hold from Command Inactive MCS/PCS Inactive Delay DEN Inactive to DT/R Low Control Active Delay 1 DEN Inactive Delay Control Active Delay 2 ALE High to Address Valid AD Address Float to RD Active RD Active Delay RD Pulse Width RD Inactive Delay RD Inactive to ALE High RD Inactive to AD Address Active Data Hold Time Control Inactive Delay WR Pulse Width WR Inactive to ALE High Data Hold after WR WR Inactive to DEN Inactive X1 Period X1 Low Time X1 High Time X1 Fall Time X1 Rise Time DS Inactive to ALE Inactive CLKOUTA Period Description
Am186/188ES and Am186/188ESLV Microcontrollers
65
PRELIMINARY
Numerical Key to Switching Parameter Symbols (continued)
No. 43 44 45 46 47 48 49 50 51 52 53 54 55 57 58 59 61 62 63 64 65 66 67 68 69 70 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 Parameter Symbol tCLCH tCHCL tCH1CH2 tCL2CL1 tSRYCL tCLSRY tARYCH tCLARX tARYCHL tARYLCL tINVCH tINVCL tCLTMV tRESIN tHVCL tRHDX tLOCK tCLHAV tCHCZ tCHCV tAVWL tAVRL tCHCSV tCHAV tCICOA tCICOB tCHRFD tCLCLX tCLCSL tCLRF tCOAOB tLRLL tRFCY tLCRF tAVBL tCSHARYL tARYHDV tDSLDD tDSLDV tDSHDIR tDSHDX Description CLKOUTA Low Time CLKOUTA High Time CLKOUTA Rise Time CLKOUTA Fall Time SRDY Transition Setup Time SRDY Transition Hold Time ARDY Resolution Transition Setup Time ARDY Active Hold Time ARDY Inactive Holding Time ARDY Setup Time Peripheral Setup Time DRQ Setup Time Timer Output Delay RES Setup Time HOLD Setup RD High to Data Hold on AD Bus Maximum PLL Lock Time HLDA Valid Delay Command Lines Float Delay Command Lines Valid Delay (after Float) A Address Valid to WR Low A Address Valid to RD Low CLKOUTA High to LCS/UCS Valid CLKOUTA High to A Address Valid X1 to CLKOUTA Skew X1 to CLKOUTB Skew CLKOUTA High to RFSH Valid LCS Inactive Delay LCS Active Delay CLKOUTA High to RFSH Invalid CLKOUTA to CLKOUTB Skew LCS Precharge Pulse Width RFSH Cycle Time LCS Inactive to RFSH Active Delay A Address Valid to WHB, WLB Low Chip Select to ARDY Low ARDY Assert to Data Valid DS Low to Data Driven DS Low to Data Valid DS High to Data Invalid--Read DS High to Data Bus Turn-off Time
66
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Numerical Key to Switching Parameter Symbols (continued)
No. 94 95 96 97 98 Parameter Symbol tRHDZ tARYHDSH tARYLDSH tDVDSL tDSHDIW Description RD High to Data Bus Turn-off Time ARDY High to DS High ARDY Low to DS High Data Valid to DS Low DS High to Data Invalid--Write
Note: The following parameters are not defined or used as this time: 56, 60, 71-78.
Am186/188ES and Am186/188ESLV Microcontrollers
67
PRELIMINARY
SWITCHING CHARACTERISTICS over Commercial operating ranges Read Cycle (20 MHz and 25 MHz)
Parameter No. Symbol Description General Timing Requirements Data in Setup 1 tDVCL Data in Hold(c) 2 tCLDX General Timing Responses Status Active Delay 3 tCHSV 4 tCLSH Status Inactive Delay AD Address Valid Delay and BHE 5 tCLAV Address Hold 6 tCLAX Status Hold Time 8 tCHDX ALE Active Delay 9 tCHLH ALE Width 10 tLHLL ALE Inactive Delay AD Address Valid to ALE Low(a) AD Address Hold from ALE Inactive(a) 14 tAVCH AD Address Valid to Clock High AD Address Float Delay 15 tCLAZ 16 tCLCSV MCS/PCS Active Delay 17 tCXCSX MCS/PCS Hold from Command Inactive(a) 18 tCHCSX MCS/PCS Inactive Delay DEN Inactive to DT/R Low(a) 19 tDXDL 20 tCVCTV Control Active Delay 1(b) 21 tCVDEX DEN Inactive Delay 22 tCHCTV Control Active Delay 2(b) ALE High to Address Valid 23 tLHAV PCS Low to ALE Low 99 tPLAL Read Cycle Timing Responses AD Address Float to RD Active 24 tAZRL RD Active Delay 25 tCLRL 26 tRLRH RD Pulse Width 27 tCLRH RD Inactive Delay 28 tRHLH RD Inactive to ALE High(a) RD Inactive to AD Address 29 tRHAV Active(a) 41 tDSHLH DS Inactive to ALE High 59 66 67 68 tRHDX tAVRL tCHCSV tCHAV 11 12 13 tCHLL tAVLL tLLAX Preliminary 20 MHz 25 MHz Min Max Min Max 10 3 0 0 0 0 0 tCLCL -10= 40 25 tCLCHL -2 tCHCL -2 0 tCLAX =0 0 tCLCH -2 0 0 0 0 0 20 15 tCLCH -2 tCHCL -2 0 tCLAX =0 0 tCLCH -2 0 0 0 0 0 15 15 0 0 2tCLCL -15= 65 0 tCLCH -3 tCLCL -10= 30 tCLCH -2= 16 0 tCLCL + tCHCL-3 0 0 25 25 25 25 25 tCLCL -10= 30 20 10 3 0 0 0 0 0 20 20 20 20 20
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
25 25
20 20
25 25 12 25 28
20 20 12 20 24
0 0 2tCLCL -15= 85 0 tCLCH -3 tCLCL -10= 40 tCLCH -2= 21 RD High to Data Hold on AD Bus(c) 0 A Address Valid to RD Low(a) tCLCL + tCHCL-3 CLKOUTA High to LCS/UCS Valid 0 CLKOUTA High to A Address 0 Valid
25
20
25
20
ns ns 20 20 ns ns
25 25
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a Equal loading on referenced pins. b This parameter applies to the DEN, DS, INTA1-INTA0, WR, WHB, and WLB signals. c If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
68
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Read Cycle (33 MHz and 40 MHz)
Preliminary Parameter No. Symbol Description General Timing Requirements Data in Setup 1 tDVCL Data in Hold(c) 2 tCLDX General Timing Responses Status Active Delay 3 tCHSV 4 tCLSH Status Inactive Delay AD Address Valid Delay and BHE 5 tCLAV Address Hold 6 tCLAX Status Hold Time 8 tCHDX ALE Active Delay 9 tCHLH ALE Width 10 tLHLL 11 tCHLL ALE Inactive Delay AD Address Valid to ALE Low(a) 12 tAVLL AD Address Hold from ALE 13 tLLAX Inactive(a) 14 tAVCH AD Address Valid to Clock High AD Address Float Delay 15 tCLAZ 16 tCLCSV MCS/PCS Active Delay 17 tCXCSX MCS/PCS Hold from Command Inactive(a) 18 tCHCSX MCS/PCS Inactive Delay DEN Inactive to DT/R Low(a) 19 tDXDL 20 tCVCTV Control Active Delay 1(b) 21 tCVDEX DEN Inactive Delay 22 tCHCTV Control Active Delay 2(b) ALE High to Address Valid 23 tLHAV PCS Low to ALE Low 99 tPLAL Read Cycle Timing Responses AD Address Float to RD Active 24 tAZRL RD Active Delay 25 tCLRL RD Pulse Width 26 tRLRH RD Inactive Delay 27 tCLRH RD Inactive to ALE High(a) 28 tRHLH RD Inactive to AD Address 29 tRHAV Active(a) 41 tDSHLH DS Inactive to ALE Inactive RD High to Data Hold on AD Bus(c) 59 tRHDX 66 tAVRL A Address Valid to RD Low(a) 67 68 tCHCSV tCHAV CLKOUTA High to LCS/UCS Valid CLKOUTA High to A Address Valid 33 MHz Min 8 3 0 0 0 0 0 tCLCL -10=20 15 tCLCH -2 tCHCL -2 0 tCLAX =0 0 tCLCH -2 0 0 0 0 0 10 12 0 0 2tCLCL -15=45 0 tCLCH -3 tCLCL -10=20 tCLCH -2=11.5 0 tCLCL + tCHCL-3 0 0 15 15 tCLCH -2 tCHCL -2 0 tCLAX =0 0 tCLCH -2 0 0 0 0 0 7.5 10 0 0 2tCLCL -10=40 0 tCLCH -2 tCLCL -5=20 tCLCH -2=9.25 0 tCLCL + tCHCL- 1.125 0 0 15 15 15 15 15 tCLCL -5=20 12 Max 40 MHz Min 5 2 0 0 0 0 0 12 12 12 12 12 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
15 15
12 12
15 15 12 15 20
12 12 12 12 18
15 15
10 12
ns ns 10 10 ns ns
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b c Equal loading on referenced pins. This parameter applies to the DEN, DS, INTA1-INTA0, WR, WHB, and WLB signals. If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
Am186/188ES and Am186/188ESLV Microcontrollers
69
PRELIMINARY
Read Cycle Waveforms
t1 t2 t3 tW CLKOUTA
66
t4
A19-A0
68
Address
8
S6/LOCK
S6
14
LOCK
6 1
S6
AD15-AD0*, AD7-AD0**
Address
Data
2
AO15-AO8**
23 9 11 15 10 24
Address
29 59 28 26 25 27
ALE
RD
5
12
BHE*
67 13
BHE
18
LCS, UCS
16
MCS1-MCS0, PCS6-PCS5, PCS3-PCS0 DEN, DS
19
99
17
20
21
41
DT/R
22 *** 4
*** 22
S2-S0
3
Status
UZI
Notes: * Am186ES microcontroller only
**
***
Am188ES microcontroller only Changes in t phase preceding next bus cycle if followed by read, INTA, or halt.
70
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Write Cycle (20 MHz and 25 MHz)
Preliminary Parameter No. Symbol Description General Timing Responses Status Active Delay 3 tCHSV 4 tCLSH Status Inactive Delay AD Address Valid Delay and BHE 5 tCLAV Address Hold 6 tCLAX 7 tCLDV Data Valid Delay Status Hold Time 8 tCHDX 9 tCHLH ALE Active Delay ALE Width 10 tLHLL 11 tCHLL ALE Inactive Delay AD Address Valid to ALE Low(a) 12 tAVLL 13 tLLAX AD Address Hold from ALE Inactive(a) 14 tAVCH AD Address Valid to Clock High 16 tCLCSV MCS/PCS Active Delay 17 tCXCSX MCS/PCS Hold from Command Inactive(a) 18 tCHCSX MCS/PCS Inactive Delay 19 tDXDL DEN Inactive to DT/R Low(a) 20 tCVCTV Control Active Delay 1(b) 21 tCVDEX DS Inactive Delay 22 tCHCTV Control Active Delay 2 23 tLHAV ALE High to Address Valid Write Cycle Timing Responses 30 tCLDOX Data Hold Time 31 tCVCTX Control Inactive Delay(b) 32 tWLWH WR Pulse Width 33 tWHLH WR Inactive to ALE High(a) 34 tWHDX Data Hold after WR(a) 35 tWHDEX WR Inactive to DEN Inactive(a) 41 tDSHLH DS Inactive to ALE High 65 67 68 87 98 tAVWL tCHCSV tCHAV tAVBL tDSHDIW A Address Valid to WR Low CLKOUTA High to LCS/UCS Valid CLKOUTA High to A Address Valid A Address Valid to WHB, WLB Low DS High to Data Invalid--Write 20 MHz Min 0 0 0 0 0 0 tCLCL -10=40 25 tCLCH -2 tCHCL-2 0 0 tCLCH -2 0 0 0 0 0 20 0 0 2tCLCL -10=90 tCLCH -2 tCLCL -10=40 tCLCH -3 tCLCH -2= 21 tCLCL+tCHCL -3 0 0 tCHCL -3 35 25 15 25 25 tCLCH -2 tCHCL-2 0 0 tCLCH -2 0 0 0 0 0 15 0 0 2tCLCL -10=70 tCLCH -2 tCLCL -10=30 tCLCH -3 tCLCH -2= 16 tCLCL +tCHCL -3 0 0 tCHCL -3 0 20 20 20 20 Max 25 25 25 25 15 25 tCLCL -10=30 20 25 MHz Min 0 0 0 0 0 0 Max 20 20 20 20 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
25
20
25
20
25 25 25
20 20 20 30
ns ns ns ns ns
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b Testing is performed with equal loading on referenced pins. This parameter applies to the DEN, DS, INTA1-INTA0, WR, WHB, and WLB signals.
Am186/188ES and Am186/188ESLV Microcontrollers
71
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Write Cycle (33 MHz and 40 MHz)
Preliminary Parameter No. Symbol Description General Timing Responses Status Active Delay 3 tCHSV 4 tCLSH Status Inactive Delay AD Address Valid Delay and BHE 5 tCLAV Address Hold 6 tCLAX 7 tCLDV Data Valid Delay Status Hold Time 8 tCHDX 9 tCHLH ALE Active Delay ALE Width 10 tLHLL 11 tCHLL ALE Inactive Delay AD Address Valid to ALE Low(a) 12 tAVLL 13 tLLAX AD Address Hold from ALE Inactive(a) 14 tAVCH AD Address Valid to Clock High 16 tCLCSV MCS/PCS Active Delay 17 tCXCSX MCS/PCS Hold from Command Inactive(a) 18 tCHCSX MCS/PCS Inactive Delay 19 tDXDL DEN Inactive to DT/R Low(a) 20 tCVCTV Control Active Delay 1(b) 21 tCVDEX DS Inactive Delay 22 tCHCTV Control Active Delay 2 23 tLHAV ALE High to Address Valid Write Cycle Timing Responses 30 tCLDOX Data Hold Time 31 tCVCTX Control Inactive Delay(b) 32 tWLWH WR Pulse Width 33 tWHLH WR Inactive to ALE High(a) 34 tWHDX Data Hold after WR(a) 35 tWHDEX WR Inactive to DEN Inactive(a) 65 tAVWL A Address Valid to WR Low 67 68 87 98 tCHCSV tCHAV tAVBL tDSHDIW CLKOUTA High to LCS/UCS Valid CLKOUTA High to A Address Valid A Address Valid to WHB, WLB Low DS High to Data Invalid--Write 33 MHz Min 0 0 0 0 0 0 tCLCL -10=20 15 tCLCH -2 tCHCL-2 0 0 tCLCH -2 0 0 0 0 0 10 0 0 2tCLCL -10=50 tCLCH -2 tCLCL -10=20 tCLCH -5 tCLCL +tCHCL -3 0 0 tCHCL -3 0 15 15 15 15 tCLCH -2 tCHCL-2 0 0 tCLCH -2 0 0 0 0 0 7.5 0 0 2tCLCL -10=40 tCLCH -2 tCLCL -10=15 tCLCH tCLCL +tCHCL - 1.25 0 0 tCHCL -1.25 0 12 12 12 12 Max 15 15 15 25 15 15 tCLCL -5=20 12 40 MHz Min 0 0 0 0 0 0 Max 12 12 12 20 12 12 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
15
12
15
12
15 15 15 20
10 10 12 15
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b Testing is performed with equal loading on referenced pins. This parameter applies to the DEN, DS, INTA1-INTA0, WR, WHB, and WLB signals.
72
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Write Cycle Waveforms
t1 t2 t3 tW CLKOUTA
65
t4
A19-A0
68
Address
8
S6/LOCK
S6
14
LOCK
7
S6
30
AD15-AD0*, AD7-AD0** AO15-AO8**
23 9
Address
6
Data
Address
11 13 10 32 31 33 12 20 20 87 5 31 34
ALE
WR
WHB*, WLB* WB** BHE*
67
BHE
41
LCS, UCS
16 99 17 20 35 31 98 20 21 19 18
MCS3-MCS0, PCS6-PCS5, PCS3-PCS0 DEN
DS DT/R
22 *** 22
***
S2-S0 Status
3 4
UZI
Notes: * Am186ES microcontroller only
**
Am188ES microcontroller only Changes in t phase preceding next bus cycle if followed by read, INTA, or halt.
***
Am186/188ES and Am186/188ESLV Microcontrollers
73
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges PSRAM Read Cycle (20 MHz and 25 MHz)
Preliminary Parameter No. Symbol Description General Timing Requirements 1 2 tDVCL tCLDX Data in Setup Data in Hold(b) 20 MHz Min 10 3 0 0 0 tCLCL -10=40 25 20 0 0 tCLCL+ tCLCH-3 0 0 2tCLCL -15=85 0 tCLCH -3 0 tCLCL + tCHCL-3 0 25 25 25 15 0 0 tCLCL + tCLCH -3 0 0 2tCLCL -15=65 0 tCLCH -3 0 tCLCL + tCHCL-3 0 20 20 20 25 25 25 tCLCL -10=30 20 Max 25 MHz Min 10 3 0 0 0 20 20 20 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
General Timing Responses 5 tCLAV AD Address Valid Delay and BHE 7 8 9 10 11 23 80 81 tCLDV tCHDX tCHLH tLHLL tCHLL tLHAV tCLCLX tCLCSL Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay ALE High to Address Valid LCS Inactive Delay LCS Active Delay
LCS Precharge Pulse Width 84 tLRLL Read Cycle Timing Responses 24 25 26 27 28 59 66 68 tAZRL tCLRL tRLRH tCLRH tRHLH tRHDX tAVRL tCHAV AD Address Float to RD Active RD Active Delay RD Pulse Width RD Inactive Delay RD Inactive to ALE High(a) RD High to Data Hold on AD Bus(b) A Address Valid to RD Low CLKOUTA High to A Address Valid
25 25
20 20
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC -0.5 V. a b Testing is performed with equal loading on referenced pins. If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
74
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges PSRAM Read Cycle (33 MHz and 40 MHz)
Preliminary Parameter No. Symbol Description General Timing Requirements 1 2 tDVCL tCLDX Data in Setup Data in Hold(b) 33 MHz Min 8 3 0 0 0 tCLCL -10=20 15 10 0 0 tCLCL + tCLCH -3 15 15 7.5 0 0 tCLCL + tCLCH - 1.25 0 15 15 0 2tCLCL -10=40 0 tCLCH -1.25 0 tCLCL + tCHCL- 1.25 0 10 12 12 12 15 15 15 tCLCL -5=20 12 Max 40 MHz Min 5 2 0 0 0 12 12 12 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns
General Timing Responses 5 tCLAV AD Address Valid Delay and BHE 7 8 9 10 11 23 80 81 84 tCLDV tCHDX tCHLH tLHLL tCHLL tLHAV tCLCLX tCLCSL tLRLL Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay ALE High to Address Valid LCS Inactive Delay LCS Active Delay LCS Precharge Pulse Width
Read Cycle Timing Responses 24 tAZRL AD Address Float to RD Active 25 26 27 28 59 66 68 tCLRL tRLRH tCLRH tRHLH tRHDX tAVRL tCHAV RD Active Delay RD Pulse Width RD Inactive Delay RD Inactive to ALE High(a) RD High to Data Hold on AD Bus(b) A Address Valid to RD Low CLKOUTA High to A Address Valid
0 0 2tCLCL -15=45 0 tCLCH -3 0 tCLCL + tCHCL-3 0 15
ns ns ns ns ns ns ns 10 ns
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC -0.5 V. a b Testing is performed with equal loading on referenced pins. If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
Am186/188ES and Am186/188ESLV Microcontrollers
75
PRELIMINARY
PSRAM Read Cycle Waveforms
t1
t2
t3
t4
t1
tW CLKOUTA
66
A19-A0
68
Address
8
S6/LOCK
S6
LOCK
7 1
S6
AD15-AD0*, AD7-AD0**
Address
Data
2
Address
AO15-AO8**
23 9 11
Address
59
ALE
10 24 26 27 5 25 27 28
RD
LCS
80 84 81 80
Notes:
* **
Am186ES microcontroller only Am188ES microcontroller only
76
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges PSRAM Write Cycle (20 MHz and 25 MHz)
Preliminary Parameter No. Symbol Description General Timing Responses 5 7 8 9 10 11 20 23 80 81 tCLAV tCLDV tCHDX tCHLH tLHLL tCHLL tCVCTV tLHAV tCLCLX tCLCSL AD Address Valid Delay and BHE Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay Control Active Delay 1(b) ALE High to Address Valid LCS Inactive Delay LCS Active Delay 20 MHz Min 0 0 0 25 tCLCL -10=40 25 0 20 0 0 tCLCL + tCLCH -3 0 0 2tCLCL -10=90 tCLCH -2 tCLCL -10=40 tCLCL +tCHCL -3 0 tCHCL -3 25 25 25 0 15 0 0 tCLCL + tCLCH -3 0 0 2tCLCL -10=70 tCLCH -2 tCLCL -10=30 tCLCL +tCHCL -3 0 tCHCL -3 ns ns ns ns ns ns 20 20 ns ns tCLCL -10=30 20 20 20 20 Max 25 25 25 MHz Min 0 0 0 20 Max 20 20 Unit ns ns ns ns ns ns ns ns ns ns
LCS Precharge Pulse Width 84 tLRLL Write Cycle Timing Responses 30 31 32 33 34 65 68 87 tCLDOX tCVCTX tWLWH tWHLH tWHDX tAVWL tCHAV tAVBL Data Hold Time Control Inactive Delay(b) WR Pulse Width WR Inactive to ALE High(a) Data Hold after WR(a) A Address Valid to WR Low CLKOUTA High to A Address Valid A Address Valid to WHB, WLB Low
25
20
25 25
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b Testing is performed with equal loading on referenced pins. This parameter applies to the DEN, WR, WHB, and WLB signals.
Am186/188ES and Am186/188ESLV Microcontrollers
77
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges PSRAM Write Cycle (33 MHz and 40 MHz)
Preliminary Parameter No. Symbol Description General Timing Responses 5 7 8 9 10 11 20 23 80 81 84 tCLAV tCLDV tCHDX tCHLH tLHLL tCHLL tCVCTV tLHAV tCLCLX tCLCSL tLRLL AD Address Valid Delay and BHE Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay Control Active Delay 1(b) ALE High to Address Valid LCS Inactive Delay LCS Active Delay LCS Precharge Pulse Width 33 MHz Min 0 0 0 15 tCLCL -10=20 15 0 10 0 0 tCLCL + tCLCH - 3 0 0 2tCLCL -10=50 tCLCH -2 tCLCL -10=20 tCLCL +tCHCL -3 0 tCHCL -3 15 15 15 15 0 7.5 0 0 tCLCL + tCLCH - 1.25 0 0 2tCLCL -10=40 tCLCH -2 tCLCL -10=15 tCLCL +tCHCL -1.25 0 tCHCL -1.25 12 ns ns ns ns ns ns 10 12 ns ns tCLCL -5=20 12 12 12 12 Max 15 15 40 MHz Min 0 0 0 12 Max 12 12 Unit ns ns ns ns ns ns ns ns ns ns
Write Cycle Timing Responses 30 tCLDOX Data Hold Time 31 32 33 34 65 68 87 tCVCTX tWLWH tWHLH tWHDX tAVWL tCHAV tAVBL Control Inactive Delay(b) WR Pulse Width WR Inactive to ALE High(a) Data Hold after WR(a) A Address Valid to WR Low CLKOUTA High to A Address Valid A Address Valid to WHB, WLB Low
15 15
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b Testing is performed with equal loading on referenced pins. This parameter applies to the DEN, WR, WHB, and WLB signals.
78
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
PSRAM Write Cycle Waveforms
t1 t2 t1
t3 tW
t4
CLKOUTA
65
A19-A0
68
Address
8
S6/LOCK AD15-AD0*, AD7-AD0**
S6
LOCK
7
S6
30
Address
Data
AO15-AO8**
23 9 11
Address
34
ALE
10 32
33
WR
31
5 20
20
31
WHB*, WLB* WB** LCS
87
80 84 81
80
Notes:
* **
Am186ES microcontroller only Am188ES microcontroller only
Am186/188ES and Am186/188ESLV Microcontrollers
79
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges PSRAM Refresh Cycle (20 MHz and 25 MHz)
Preliminary Parameter No. Symbol Description General Timing Responses 9 10 tCHLH tLHLL ALE Active Delay ALE Width 20 MHz Min Max 25 tCLCL -10=40 25 0 2tCLCL -15=85 0 tCLCH -3 0 0 0 0 6 * tCLCL 2tCLCL -3 25 25 25 25 25 25 0 2tCLCL -15=65 0 tCLCH -3 0 0 0 0 6 * tCLCL 2tCLCL -3 tCLCL -10=30 20 20 20 20 20 20 20 25 MHz Min Max 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns
ALE Inactive Delay 11 tCHLL Read/Write Cycle Timing Responses 25 26 27 28 80 81 tCLRL tRLRH tCLRH tRHLH tCLCLX tCLCSL RD Active Delay RD Pulse Width RD Inactive Delay RD Inactive to ALE High(a) LCS Inactive Delay LCS Active Delay
Refresh Timing Cycle Parameters 79 tCLRFD CLKOUTA Low to RFSH Valid 82 85 86 tCLRF tRFCY tLCRF CLKOUTA High to RFSH Invalid RFSH Cycle Time LCS Inactive to RFSH Active Delay
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a Testing is performed with equal loading on referenced pins.
80
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges PSRAM Refresh Cycle (33 MHz and 40 MHz)
Preliminary Parameter No. Symbol Description General Timing Responses 9 10 tCHLH tLHLL ALE Active Delay ALE Width 33 MHz Min Max 15 tCLCL -10=20 15 0 2tCLCL -15=45 0 tCLCH -3 0 0 0 0 6 * tCLCL 2tCLCL -3 15 15 15 15 15 15 0 2tCLCL -10=40 0 tCLCH -2 0 0 0 0 6 * tCLCL 2tCLCL -1.25 tCLCL -5=20 12 10 12 12 12 12 12 40 MHz Min Max 12 Unit ns ns ns ns ns ns ns ns ns ns ns ns
ALE Inactive Delay 11 tCHLL Read/Write Cycle Timing Responses 25 26 27 28 80 81 tCLRL tRLRH tCLRH tRHLH tCLCLX tCLCSL RD Active Delay RD Pulse Width RD Inactive Delay RD Inactive to ALE High(a) LCS Inactive Delay LCS Active Delay
Refresh Timing Cycle Parameters 79 tCLRFD CLKOUTA Low to RFSH Valid 82 85 86 tCLRF tRFCY tLCRF CLKOUTA High to RFSH Invalid RFSH Cycle Time LCS Inactive to RFSH Active Delay
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a Testing is performed with equal loading on referenced pins.
Am186/188ES and Am186/188ESLV Microcontrollers
81
PRELIMINARY
PSRAM Refresh Cycle Waveforms
t1 t2 t3 tW * CLKOUTA t4 t1
A19-A0
9 11
Address
ALE
27 10 26 80 25 27 81 28
RD
LCS
79
RFSH
82
85 86
Notes:
* The period tw is fixed at 3 wait states for PSRAM auto refresh only.
82
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Interrupt Acknowledge Cycle (20 MHz and 25 MHz)
Preliminary Parameter No. Symbol Description General Timing Requirements 1 2 tDVCL tCLDX Data in Setup Data in Hold 20 MHz Min 10 3 0 0 0 0 25 tCLCL -10=40 25 tCLCH tCLAX =0 0 0 0 0 20 0 0 25 25 25 25 25 25 tCLCH tCLAX =0 0 0 0 0 15 0 0 20 20 20 20 20 20 tCLCL -10=30 20 25 25 25 Max 25 MHz Min 10 3 0 0 0 0 20 20 20 20 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
General Timing Responses 3 tCHSV Status Active Delay 4 7 8 9 10 11 12 15 19 20 21 22 23 31 68 tCLSH tCLDV tCHDX tCHLH tLHLL tCHLL tAVLL tCLAZ tDXDL tCVCTV tCVDEX tCHCTV tLHAV tCVCTX tCHAV Status Inactive Delay Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay AD Address Invalid to ALE Low(a) AD Address Float Delay DEN Inactive to DT/R Low(a) Control Active Delay 1(b) DEN Inactive Delay Control Active Delay 2(c) ALE High to Address Valid Control Inactive Delay(b) CLKOUTA High to A Address Valid
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b c Testing is performed with equal loading on referenced pins. This parameter applies to the INTA1-INTA0 signals. This parameter applies to the DEN and DT/R signals.
Am186/188ES and Am186/188ESLV Microcontrollers
83
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Interrupt Acknowledge Cycle (33 MHz and 40 MHz)
Preliminary Parameter No. Symbol Description General Timing Requirements 1 2 tDVCL tCLDX Data in Setup Data in Hold 33 MHz Min 8 3 0 0 0 0 15 tCLCL -10=20 15 tCLCH tCLAX =0 0 0 0 0 10 0 0 15 15 15 15 15 15 tCLCH tCLAX =0 0 0 0 0 7.5 0 0 12 12 12 12 12 10 tCLCL -5=20 12 15 15 15 Max 40 MHz Min 5 2 0 0 0 0 12 12 12 12 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
General Timing Responses 3 tCHSV Status Active Delay 4 7 8 9 10 11 12 15 19 20 21 22 23 31 68 tCLSH tCLDV tCHDX tCHLH tLHLL tCHLL tAVLL tCLAZ tDXDL tCVCTV tCVDEX tCHCTV tLHAV tCVCTX tCHAV Status Inactive Delay Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay AD Address Invalid to ALE Low(a) AD Address Float Delay DEN Inactive to DT/R Low(a) Control Active Delay 1(b) DEN Inactive Delay Control Active Delay 2(c) ALE High to Address Valid Control Inactive Delay(b) CLKOUTA High to A Address Valid
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b c Testing is performed with equal loading on referenced pins. This parameter applies to the INTA1-INTA0 signals. This parameter applies to the DEN and DT/R signals.
84
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Interrupt Acknowledge Cycle Waveforms
t1
t2
t3 tW
t4
CLKOUTA
68
A19-A0
7
Address
8
S6/LOCK AD15-AD0*, AD7-AD0**
S6
LOCK
1 12
S6
2
(b)
Ptr
15
AO15-AO8**
9
Address
23 10 11 4
ALE
BHE*
BHE
31
INTA1-INTA0
20
DEN
22 19 (c) 22 21
DT/R
3 4 (a) 22 (d)
S2-S0
Status
Notes:
* **
Am186ES microcontroller only Am188ES microcontroller only The status bits become inactive in the state preceding t4. The data hold time lasts only until the interrupt acknowledge signal deasserts, even if the interrupt acknowledge transition occurs prior to tCLDX (min). This parameter applies for an interrupt acknowledge cycle that follows a write cycle. If followed by a write cycle, this change occurs in the state preceding that write cycle.
a b c d
Am186/188ES and Am186/188ESLV Microcontrollers
85
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Software Halt Cycle (20 MHz and 25 MHz)
Preliminary Parameter No. Symbol Description General Timing Responses 3 4 5 9 10 11 19 22 68 tCHSV tCLSH tCLAV tCHLH tLHLL tCHLL tDXDL tCHCTV tCHAV Status Active Delay Status Inactive Delay AD Address Invalid Delay and BHE ALE Active Delay ALE Width ALE Inactive Delay DEN Inactive to DT/R Low(a) Control Active Delay 2(b) CLKOUTA High to A Address Invalid 20 MHz Min 0 0 0 tCLCL -10=40 25 0 0 0 25 25 0 0 0 Max 25 25 25 25 25 MHz Min 0 0 0 tCLCL -10=30 20 20 20 Max 20 20 20 20 Unit ns ns ns ns ns ns ns ns ns
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b Testing is performed with equal loading on referenced pins. This parameter applies to the DEN signal.
86
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Software Halt Cycle (33 MHz and 40 MHz)
Preliminary Parameter No. 3 4 5 9 10 11 19 22 68 Symbol tCHSV tCLSH tCLAV tCHLH tLHLL tCHLL tDXDL tCHCTV tCHAV Description Status Active Delay Status Inactive Delay AD Address Invalid Delay and BHE ALE Active Delay ALE Width ALE Inactive Delay DEN Inactive to DT/R Low(a) Control Active Delay 2(b) CLKOUTA High to A Address Invalid General Timing Responses 0 0 0 tCLCL -10=20 15 0 0 0 15 15 0 0 0 15 15 15 15 0 0 0 tCLCL -5=20 12 12 10 12 12 12 12 ns ns ns ns ns ns ns ns ns 33 MHz Min Max 40 MHz Min Max Unit
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b Testing is performed with equal loading on referenced pins. This parameter applies to the DEN signal.
Am186/188ES and Am186/188ESLV Microcontrollers
87
PRELIMINARY
Software Halt Cycle Waveforms
t1
t2
ti
ti
CLKOUTA
68
A19-A0
5
Invalid Address
S6, AD15-AD0*, AD7-AD0**, AO15-AO8** ALE
9
Invalid Address
10
11
DEN
19
DT/R
22 4
S2-S0
3
Status
Notes:
* **
Am186ES microcontroller only Am188ES microcontroller only
88
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Clock (20 MHz and 25 MHz)
Preliminary Parameter No. Symbol CLKIN Requirements 36 37 38 39 tCKIN tCLCK tCHCK tCKHL Description 20 MHz Min 50 15 15 5 5 50 0.5tCLCL -2=23 0.5tCLCL -2=23 3 3 1 15 25 40 0.5tCLCL -2=18 0.5tCLCL -2=18 3 3 1 15 25 Max 60 25 MHz Min 40 15 15 5 5 Max 60 Unit ns ns ns ns ns ns ns ns ns ns ms ns ns
X1 Period(a) X1 Low Time (1.5 V)(a) X1 High Time (1.5 V)(a) X1 Fall Time (3.5 to 1.0 V)(a)
X1 Rise Time (1.0 to 3.5 V)(a) 40 tCKLH CLKOUT Timing 42 43 44 45 46 61 69 70 tCLCL tCLCH tCHCL tCH1CH2 tCL2CL1 tLOCK tCICOA tCICOB CLKOUTA Period CLKOUTA Low Time (CL =50 pF) CLKOUTA High Time (CL =50 pF) CLKOUTA Rise Time (1.0 to 3.5 V) CLKOUTA Fall Time (3.5 to 1.0 V) Maximum PLL Lock Time X1 to CLKOUTA Skew X1 to CLKOUTB Skew
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes. The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2 mode should be used. Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should be used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation.
Am186/188ES and Am186/188ESLV Microcontrollers
89
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Clock (33 MHz and 40 MHz)
Preliminary Parameter No. Symbol CLKIN Requirements 36 37 38 39 tCKIN tCLCK tCHCK tCKHL Description 33 MHz Min 30 10 10 5 5 30 0.5tCLCL -1.5 =13.5 0.5tCLCL -1.5 =13.5 3 3 1 15 25 25 0.5tCLCL -1.25 =11.25 0.5tCLCL -1.25 =11.25 3 3 1 15 25 Max 60 40 MHz Min 25 7.5 7.5 5 5 Max 60 Unit ns ns ns ns ns ns ns ns ns ns ms ns ns
X1 Period(a) X1 Low Time (1.5 V)(a) X1 High Time (1.5 V)(a) X1 Fall Time (3.5 to 1.0 V)(a)
X1 Rise Time (1.0 to 3.5 V)(a) 40 tCKLH CLKOUT Timing 42 43 44 45 46 61 69 70 tCLCL tCLCH tCHCL tCH1CH2 tCL2CL1 tLOCK tCICOA tCICOB CLKOUTA Period CLKOUTA Low Time (CL =50 pF) CLKOUTA High Time (CL =50 pF) CLKOUTA Rise Time (1.0 to 3.5 V) CLKOUTA Fall Time (3.5 to 1.0 V) Maximum PLL Lock Time X1 to CLKOUTA Skew X1 to CLKOUTB Skew
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes. The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2 mode should be used. Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should be used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation.
90
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Clock Waveforms--Active Mode
X2
36 37 38
X1
39 40 45 46
CLKOUTA (Active, F=000)
69 42 43 44
CLKOUTB
70
Clock Waveforms--Power-Save Mode
X2
X1
CLKOUTA (Power-Save, F=010) CLKOUTB (Like X1, CBF=1) CLKOUTB (Like CLKOUTA, CBF=0)
Am186/188ES and Am186/188ESLV Microcontrollers
91
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Ready and Peripheral (20 MHz and 25 MHz)
Parameter No. Symbol Description Ready and Peripheral Timing Requirements 47 48 49 50 51 52 53 tSRYCL tCLSRY tARYCH tCLARX tARYCHL tARYLCL tINVCH SRDY Transition Setup Time(a) SRDY Transition Hold Time(a) ARDY Resolution Transition Setup Time(b) ARDY Active Hold Time(a) ARDY Inactive Holding Time ARDY Setup Time(a) Peripheral Setup Time(b) Preliminary 20 MHz Min 10 3 10 4 6 15 10 10 25 Max Preliminary 25 MHz Min 10 3 10 4 6 15 10 10 20 Max Unit ns ns ns ns ns ns ns ns ns
DRQ Setup Time(b) 54 tINVCL Peripheral Timing Responses 55 tCLTMV Timer Output Delay
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b This timing must be met to guarantee proper operation. This timing must be met to guarantee recognition at the clock edge.
92
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Ready and Peripheral (33 MHz and 40 MHz)
Preliminary Parameter No. 47 48 49 50 51 52 53 54 55 Symbol tSRYCL tCLSRY tARYCH tCLARX tARYCHL tARYLCL tINVCH tINVCL tCLTMV Description SRDY Transition Setup Time(a) SRDY Transition Hold Time(a) ARDY Resolution Transition Setup Time(b) ARDY Active Hold Time(a) ARDY Inactive Holding Time ARDY Setup Time(a) Peripheral Setup Time(b) DRQ Setup Time(b) Timer Output Delay Ready and Peripheral Timing Requirements 8 3 8 4 6 10 8 8 15 5 2 5 3 5 5 5 5 12 ns ns ns ns ns ns ns ns ns 33 MHz Min Max 40 MHz Min Max Unit
Peripheral Timing Responses
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a b This timing must be met to guarantee proper operation. This timing must be met to guarantee recognition at the clock edge.
Synchronous Ready Waveforms
Case 1 Case 2 Case 3 Case 4 tW t3 t2 t1 tW tW t3 t2 tW tW tW t3 t4 t4 t4 t4
CLKOUTA
47
SRDY
48
Am186/188ES and Am186/188ESLV Microcontrollers
93
PRELIMINARY
Asynchronous Ready Waveforms
Case 1 Case 2 Case 3 Case 4 tW t3 t2 t1 tW tW t3 t2 tW tW tW t3 t4 t4 t4 t4
CLKOUTA
49 50
ARDY (Normally NotReady System)
49
ARDY (Normally Ready System)
51
50
52
Peripheral Waveforms
CLKOUTA
53
INT4-INT0, NMI, TMRIN1-TMRIN0
54
DRQ1-DRQ0
55
TMROUT1- TMROUT0
94
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Reset and Bus Hold (20 MHz and 25 MHz)
Parameter No. Symbol Description Reset and Bus Hold Timing Requirements 5 15 57 58 tCLAV tCLAZ tRESIN tHVCL AD Address Valid Delay and BHE AD Address Float Delay RES Setup Time HOLD Setup(a) Preliminary 20 MHz 25 MHz Min 0 0 10 10 0 25 25 25 Max 25 25 Min 0 0 10 10 0 20 20 20 Max 20 20 Unit ns ns ns ns ns ns ns
Reset and Bus Hold Timing Responses 62 tCLHAV HLDA Valid Delay 63 64 tCHCZ tCHCV Command Lines Float Delay Command Lines Valid Delay (after Float)
Reset and Bus Hold (33 MHz and 40 MHz)
Preliminary No. Symbol Parameter Description 33 MHz Min Max 0 0 8 8 0 15 15 15 15 15 40 MHz Min Max 0 0 5 5 0 12 12 12 12 12 Unit ns ns ns ns ns ns ns
Reset and Bus Hold Timing Requirements 5 tCLAV AD Address Valid Delay and BHE 15 57 tCLAZ tRESIN AD Address Float Delay RES Setup Time
HOLD Setup(a) 58 tHVCL Reset and Bus Hold Timing Responses 62 63 64 tCLHAV tCHCZ tCHCV HLDA Valid Delay Command Lines Float Delay Command Lines Valid Delay (after Float)
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC - 0.5 V. a This timing must be met to guarantee recognition at the next clock.
Am186/188ES and Am186/188ESLV Microcontrollers
95
PRELIMINARY
Reset Waveforms
X1
57 57
RES
CLKOUTA
Signals Related to Reset Waveforms
RES
CLKOUTA
BHE/ADEN, RFSH2/ADEN, S6/CLKDIV2, and UZI
three-state
AD15-AD0 (186) AO15-AO8, AD7-AD0 (188)
three-state
96
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Bus Hold Waveforms--Entering
Case 1 Case 2 ti t4 ti ti ti ti
CLKOUTA
58
HOLD
62
HLDA
15
AD15-AD0, DEN A19-A0, S6, RD, WR, BHE, DT/R, S2-S0 WHB, WLB
63
Bus Hold Waveforms--Leaving
Case 1 Case 2 ti ti ti ti ti t4 t1 t1
CLKOUTA
58
HOLD
62
HLDA
5
AD15-AD0, DEN
64
A19-A0, S6, RD, WR, BHE, DT/R, S2-S0 WHB, WLB
Am186/188ES and Am186/188ESLV Microcontrollers
97
PRELIMINARY
TQFP PHYSICAL DIMENSIONS PQL 100, Trimmed and Formed Thin Quad Flat Pack
Pin 100
Pin 75 Pin 1 ID
12.00 Ref
-A-
-B-
13.80 14.20 15.80 16.20
Pin 25
-D-
12.00 Ref 13.80 14.20 15.80 16.20 Top View See Detail X
Pin 50
1.35 1.45 S 0.50 Basic 1.00 Ref Side View
S
1.60 Max
-A- -C-
Seating Plane
Notes: 1. All measurements are in millimeters, unless otherwise noted. 2. Not to scale; for reference only.
pql100 4-15-94
98
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
PQL 100 (continued)
0 Min 1.60 Max Gage Plane 0.13 R 0.20 0.05 0.15
0.25 Seating Plane 0.45 0.75 0.20 0-7 0.17 0.27 Max 0.08 Lead Coplanarity
Detail X
0.17 0.27
0.14 0.18
Section S-S
Notes: 1. All measurements are in millimeters, unless otherwise noted. 2. Not to scale; for reference only.
pql100 4-15-94
Am186/188ES and Am186/188ESLV Microcontrollers
99
PRELIMINARY
PQFP PHYSICAL DIMENSIONS PQR 100, Trimmed and Formed Plastic Quad Flat Pack
17.00 17.40 13.90 14.10 12.35 REF Pin 80
Pin 100
Pin 1 I.D.
-A-
18.85 REF 19.90 20.10 -B- 23.00 23.40
Pin 30 -D-
Pin 50
Top View
See Detail X 0.65 BASIC
2.70 2.90
S 3.35 Max S -A- -C- Seating Plane
0.25 Min
Side View
Notes: 1. All measurements are in millimeters, unless otherwise noted. 2. Not to scale; for reference only.
pqr100 4-15-94
100
Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
PQFP PQR 100 (continued)
0.20 Min. Flat Shoulder 7 Typ.
0 Min. 0.300.05 R 3.35 Max
Gage Plane
0.25 0.73 1.03 0-7 7 Typ. 0.22 0.38
0.15 0.23
Detail X
0.22 0.38
0.15 0.23
Section S-S
Note: Not to scale; for reference only.
pqr100 4-15-94
Trademarks AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am386 and Am486 are registered trademarks of Advanced Micro Devices, Inc. Am186, Am188, E86, K86, Elan, and AMD Facts-on-Demand are trademarks of Advanced Micro Devices, Inc. FusionE86 is a service mark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am186/188ES and Am186/188ESLV Microcontrollers
101
PRELIMINARY
102
Am186/188ES and Am186/188ESLV Microcontrollers
WWW..COM
Copyright (c) Each Manufacturing Company. All Datasheets cannot be modified without permission.
This datasheet has been download from : www..com
100% Free DataSheet Search Site. Free Download. No Register. Fast Search System. www..com

▲Up To Search▲

Price & Availability of AM188ES-25KIW

	To Download AM188ES-25KIW Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .