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CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 4096 x 9
Integrated Device Technology, Inc.
IDT72132 IDT72142
FEATURES:
* 35ns parallel-port access time, 45ns cycle time * 50MHz serial port shift rate * Expandable in depth and width with no external components * Programmable word lengths including 8, 9, 16-18, and 32-36 bit using FlexshiftTM serial input without using any additional components * Multiple status flags: Full, Almost-Full (1/8 from full), Half-Full, Almost Empty (1/8 from empty), and Empty * Asynchronous and simultaneous read and write operations * Dual-Port zero fall-through architecture * Retransmit capability in single device mode * Produced with high-performance, low-power CMOS technology * Available in the 28-pin plastic DIP * Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications
DESCRIPTION:
The IDT72132/72142 are high-speed, low-power serial-toparallel FIFOs. These FIFOs are ideally suited to serial communications applications, tape/disk controllers, and local area networks (LANs). The IDT72132/72142 can be configured with the IDTs parallel-to-serial FIFOs (IDT72131/72141) for bidirectional serial data buffering. The FIFO has a serial input port and a 9-bit parallel output port. Wider and deeper serial-to-parallel data buffers can be built using multiple IDT72132/72142 chips. IDTs unique Flexshift serial expansion logic (SIX, makes width expansion possible with no additional components. These FIFOs will expand to a variety of word widths including 8, 9, 16, and 32 bits. The IDT72132/142 can also be directly connected for depth expansion. Five flags are provided to monitor the FIFO. The full and empty flags prevent any FIFO data overflow or underflow conditions. The Almost-Full (7/8), Half-Full, and Almost Empty (1/8) flags signal memory utilization within the FIFO. The IDT72132/72142 is fabricated using IDTs high-speed submicron CMOS technology.
NW)
FUNCTIONAL BLOCK DIAGRAM
SICP SIX SI D7 D8
PIN CONFIGURATION
NW
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24
Vcc D7 D8 FL/RT RS SI SICP SIX OE EF XO/HF GND Q8 Q7
SERIAL INPUT CIRCUITRY FLAG LOGIC
GND
EF AEF /HF FF
XI AEF FF Q0 Q1 Q2 Q3 Q4 GND R Q5 Q6
NW
NEXT WRITE POINTER
RAM ARRAY 2048 x 9 4096 x 9
READ POINTER
P28-1 & C28-3
23 22 21 20 19 18 17 16 15
R
RS FL/RT
RESET LOGIC
XI
EXPANSION LOGIC
XO/
OE Q0-Q 8
2752 drw 01
DIP TOP VIEW
2752 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-2752/6
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IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
Symbol SI Name Serial Input Reset I/O I I Description Serial data is shifted in least significant bit first. In the serial cascade mode, the Serial Input (SI) pins are tied together and SIX plus D7, D8 determine which device stores the data. When RS is set LOW, internal READ and WRITE pointers are set to the first location of the RAM array. HF and FF go HIGH, and AEF, and EF go LOW. A reset is required before an initial WRITE after power-up. R must be HIGH during an RS cycle. To program the Serial In word width , connect NW with one of the Data Set pins (D7, D8). Serial data is read into the serial input register on the rising edge of SICP. In both Depth and Serial Word Width Expansion modes, all of the SICP pins are tied together. When READ is LOW, data can be read from the RAM array sequentially, independent of SICP. In order for READ to be active, EF must be HIGH. When the FIFO is empty (EF-LOW), the internal READ operation is blocked and Q0-Q8 are in a high impedance condition. This is a dual-purpose input. In the single device configuration (XI grounded), activating retransmit (FL/RT-LOW) will set the internal READ pointer to the first location. There is no effect on the WRITE pointer. R must be HIGH and SICP must be LOW before setting FL/RT LOW. Retransmit is not possible in depth expansion. In the depth expansion configuration, FL/RT grounded indicates the first activated device.
RS NW
SICP
Next Write Serial Input Clock Read
I I I
R FL/RT
First Load/ Retransmit
I
XI
SIX
Expansion In Serial Input Expansion
I I
In the single device configuration, XI is grounded. In depth expansion or daisy chain expansion, XI is connected to XO (expansion out) of the previous device.
In the Expansion mode, the SIX pin of the least significant device is tied HIGH. The SIX pin of all other devices is connected to the D7 or D8 pin of the previous device. For single device operation, SIX is tied HIGH. When OE is set LOW, the parallel output buffers receive data from the RAM array. When OE is set HIGH, parallel three state buffers inhibit data flow. Data outputs for 9-bit wide data. When FF goes LOW, the device is full and data must not be clocked by SICP. When FF is HIGH, the device is not full. See the diagram on page 7 for more details. When EF goes LOW, the device is empty and further READ operations are inhibited. When EF is HIGH, the device is not empty. When AEF is LOW, the device is empty to 1/8 full or 7/8 to completely full. When AEF is HIGH, the device is greater than 1/8 full, but less than 7/8 full.
OE
Q0-Q8
Output Enable Output Data Full Flag Empty Flag Almost-Empty/ Almost-Full Flag Expansion Out/ Half-Full Flag
I O O O O O
FF EF AEF XO/HF
This is a dual-purpose output. In the single device configuration (XI grounded), the device is more than half full when HF is LOW. In the depth expansion configuration (XO connected to XI of the next device), a pulse is sent from XO to XI when the last location in the RAM array is filled. The appropriate Data Set pin (D7, D8 ) is connected to NW to program the Serial In data word width. For example: D7 - NW programs a 8-bit word width, D8 - NW programs a 9-bit word width, etc. Single Power Supply of 5V. Three grounds at 0V.
2752 tbl 01
D7, D8
Data Set
O
VCC GND
Power Supply Ground
STATUS FLAGS
Number of Words in FIFO IDT72132 0 1-255 256-1024 1025-1792 1793-2047 2048 IDT72142 0 1-511 512-2048 2049-3584 3585-4095 4096 FF H H H H H L AEF L L H H L L HF H H H L L L EF L H H H H H
2752 tbl 02
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IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial -0.5 to +7.0 Unit V
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIL(1) Parameter Commercial Supply Voltage Supply Voltage Input High Voltage Commercial Input Low Voltage Min. 4.5 0 2.0 -- Typ. 5.0 0 -- -- Max. Unit 5.5 0 -- 0.8 V V V V
2752 tbl 04
TA TBIAS TSTG IOUT
0 to +70 -55 to +125 -55 to +125 50
C C C mA
NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle.
NOTE: 2752 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 10 12 Unit pF pF
2752 tbl 05
NOTE: 1. This parameter is sampled and not 100% tested.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V 10%, TA = 0C to +70C)
IDT72132/IDT72142 Commercial Symbol IIL
(1)
Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic "1" Voltage, IOUT = -2mA Output Logic "0" Voltage, IOUT = 8mA Power Supply Current Average Standby Current (R = RS = FL/RT = VIH) (SICP = VIL) Power Down Current
Min. -1 -10 2.4 -- -- --
Typ. -- -- -- -- 90 8
Max. 1 10 -- 0.4 140 12
Unit A A V V mA mA
IOL(2) VOH VOL ICC1(3) ICC2
(3)
ICC3(L)(3,4)
--
--
2
mA
2752 tbl 06
NOTES: 1. Measurements with 0.4 VIN VCC. 2. R VIL, 0.4 VOUT VCC. 3. ICC measurements are made with outputs open.
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IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V 10%, TA = 0C to +70C)
Commercial IDT72132L35 IDT72132L50 IDT72142L35 IDT72142L50 Min. Max. Min. Max. -- 22.2 -- 15 -- 50 -- 40 -- 10 35 45 5 -- 5 -- 5 -- 12 0 5 8 -- -- -- 15 -- -- -- 35 45 35 35 10 -- -- 20 5 45 35 35 10 -- -- 35 10 16 35 -- -- -- -- 20 -- 15 -- 20 -- -- -- -- 45 30 45 -- 30 30 45 -- -- -- -- -- 45 45 -- 17 -- -- -- -- 40 40 -- -- -- -- 15 50 65 10 -- 5 -- 5 -- 15 0 5 10 -- -- -- 15 -- -- -- 50 65 50 50 15 -- -- 35 5 65 50 50 15 -- -- 50 10 15 50 -- -- -- -- 30 -- 15 -- 22 -- -- -- -- 65 40 65 -- 45 45 65 -- -- -- -- -- 65 65 -- 20 -- -- -- -- 50 50 -- -- --
Symbol Parameter tS Parallel Shift Frequency tSICP Serial-InShift Frequency PARALLEL OUTPUT TIMINGS tA Access Time tRR Read Recovery Time tRPW Read Pulse Width tRC Read Cycle Time tRLZ Read Pulse LOW to Data Bus at Low-Z(1) tRHZ Read Pulse HIGH to Data Bus at High-Z(1) tDV Data Valid from Read Pulse HIGH tOEHZ Output Enable to High-Z (Disable)(1) tOELZ Output Enable to Low-Z (Enable)(1) tAOE Output Enable to Data Valid (Q0-8) SERIAL INPUT TIMINGS tSIS Serial Data in Set-Up Time to SICP Rising Edge tSIH Serial Data in Hold Time to SICP Rising Edge tSIX SIX Set-Up Time to SICP Rising Edge tSICW Serial-In Clock Width HIGH/LOW FLAG TIMINGS tSICEF SICP Rising Edge (Last Bit - First Word) to EF HIGH tSICFF SICP Rising Edge (Bit 1 - Last Word) to FF LOW tSICF SICP Rising Edge to HF, AEF tRFFSI Recovery Time SICP After FF Goes HIGH tREF Read LOW to EF LOW tRFF Read HIGH to FF HIGH tRF Read HIGH to Transitioning HF and AEF tRPE Read Pulse Width After EF HIGH RESET TIMINGS tRSC Reset Cycle Time tRS Reset Pulse Width tRSS Reset Set-up Time tRSR Reset Recovery Time tRSF1 Reset to EF and AEF LOW tRSF2 Reset to HF and FF HIGH tRSDL Reset to D LOW tPOI SICP Rising Edge to D RETRANSMIT TIMINGS tRTC Retransmit Cycle Time tRT Retransmit Pulse Width tRTS Retransmit Set-up Time tRTR Retransmit Recovery Time DEPTH EXPANSION MODE TIMINGS tXOL Read/Write to XO LOW tXOH Read/Write to XO HIGH tXI XI Pulse Width tXIR XI Recovery Time tXIS XI Set-up Time
NOTE: 1. Guaranteed by design minimum times, not tested
Unit MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2752 tbl 07
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IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V See Figure A
2752 tbl 08
5V
1.1K D.U.T. 680 30pF*
2752 drw 03
or equivalent circuit
Figure A. Output Load *Includies jig and scope capacitances
FUNCTIONAL DESCRIPTION
Serial Data Input The serial data is input on the SI pin. The data is clocked in on the rising edge of SICP providing the Full Flag (FF) is not asserted. If the Full Flag is asserted then the next parallel data word is inhibited from moving into the RAM array. NOTE: SICP should not be clocked once the last bit of the last word has been shifted in, as indicated by NW HIGH and FF LOW. If it is, then the input data will be lost. The serial word is shifted in Least Significant Bit first. Thus, when the FIFO is read, the Least Significant Bit will come out on Q0 and the second bit is on Q1 and so on. The serial word width must be programmed by connecting the appropriate Data Set line (D7, D8) to the NW input. The data set lines are taps off a digital delay line. Selecting one of these taps programs the width of the serial word to be written in. Parallel Data Output A read cycle is initiated on the falling edge of Read (R) provided the Empty Flag is not set. The output data is accessed on a first-in/first-out basis, independent of the ongoing write operations. The data is available tA after the falling edge of R and the output bus Q goes into high impedance after R goes HIGH. Alternately, the user can access the FIFO by keeping R LOW and enabling data on the bus by asserting Output Enable (OE). When R is LOW, the OE signal enables data on the output bus. When R is LOW and OE is HIGH, the output bus is three-stated. When R is HIGH, the output bus is disabled irrespective of OE.
tRSC t RS
RS
tRSS SICP tRSS tRSR
0 n-1 (1)
R
tRSF1
AEF, EF
tRSF2
HF, FF
t RSDL D7 ,D8
2752 drw 04
t PDI
NOTE: 1. Input bits are numbered 0 to n-1. D7 and D8 correspond to n=8 and n=9 respectively Figure 1. Reset
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IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
tSICW
0 1
tSICW
2 n-1
(1)
SICP 1/t SICP SIX tSIX SI t SIS t SIH
Figure 2. Write Operation NOTE: 1. Input bits are numbered 0 to n-1.
2752 drw 05
t RC
R
t RPW Q0-8 tRLZ tA VALID DATA tDV tRHZ
2752 drw 06
tRR
Figure 3. Read Operation
t RC t RR
R
TERMINATE READ CYCLE
OE
Q0-8
tA tRLZ tOEHZ DATA 1
SECOND READ BY CONTROLLINGOE
tAOE tOELZ DATA 1
tDV
2752 drw 07
Figure 4. Output Enable Timings
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IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
LAST WRITE
NO WRITE
FIRST READ
ADDITIONAL READS
FIRST WRITE
R
0 1 n-1 (1) 0 1 n-1
SICP t SICFF
t RFF
FF
NOTE: 1. After FF goes LOW and the last bit of the final word has been clocked in, SICP should not be clocked until FF goes HIGH. Figure 5. Full Flag from Last Write to First Read
2752 drw 08
LAST READ
IGNORED READ
0
FIRST WRITE
1 n-1 0
ADDITIONAL WRITES
1 n-1
FIRST READ
SICP
R
t REF t SICEF
EF
tA DATA OUT VALID
VALID
2752 drw 09
Figure 6. Empty Flag from Last Read to First Write
FIRST SERIAL-IN WORD
0 1 n-1 0
SECOND SERIAL-IN WORD
1 n-1 0
SICP t SICEF
EF
t RPE
R
tA DATA OUT
2752 drw 10
Figure 7. Empty Boundry Condition Timing
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IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
R
tRFF
FF
t RFFSI SICP
(1)
tSICFF
0 1 n-1
t SIS SI tA DATA OUT
NOTE: 1. After FF goes LOW and the last bit of the final word has been clocked in, SICP should not be clocked until FF goes HIGH. Figure 8. Full Boundry Condition Timing
2752 drw 11
0
1
n-2
n-1
SICP
HF R
HALF-FULL tSICF
HALF_FULL + 1 tRF
HALF-FULL
tSICF
tRF ALMOST FULL (7/8 + 1) 7/8 FULL
AEF AEF
7/8 FULL
ALMOST-EMPTY (1/8 FULL-1)
1/8 FULL
ALMOST-EMPTY (1/8 FULL-1)
2752 drw 12
Figure 9. Half Full, Almost Full and Almost Empty Timings
tRTC t RT
RT
tRTS SICP tRTR
0 1
R
tRTS
EF, AEF, HF, FF
NOTE: 1. EF, AEF, HF and FF may change status during Retransmit, but flags will be valid at tRTC. Figure 10. Retransmit
FLAG VALID
2752 drw 13
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IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
WRITE TO LAST PHYSICAL LOCATION
0 1 n-1
SICP
READ FROM LAST PHYSICAL LOCATION
R
t XOL t XOH t XOL t XOH
XO
2752 drw 14
Figure 11. Expansion-Out
t XI
tXIR
XI
t XIS SICP t XIS
0 1 n-1
R
Write to first physical location
Read from physical location
2752 drw 15
Figure 12. Expansion-In
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IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
OPERATING CONFIGURATIONS
Single Device Configuration In the standalone case, the SIX line is tied HIGH and not used. On the first LOW-to-HIGH of the SICP clock, both of the
Data Set lines (D7, D8) go LOW and a new serial word is started. The Data Set lines then go HIGH on the equivalent SICP clock pulse. This continues until the D line connected to NW goes HIGH completing the serial word. The cycle is then repeated with the next LOW-to-HIGH transition of SICP.
SERIAL DATA IN SI SERIAL INPUT CLOCK VCC SICP SIX NW D7 D8 Q0-8 XI PARALLEL DATA OUTPUT GND
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
0
SICP
D7
D8
NW
2752 drw 16
Figure 13. Nine-Bit Word Single Device Configuration
TRUTH TABLES TABLE 1: RESET AND RETRANSMIT SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
Inputs Mode Reset Retransmit Read/Write Internal Status Outputs
RS
0 1 1
FL/RT
X 0 1
XI
0 0 0
Read Pointer Location Zero Location Zero Increment
(1)
Write Pointer Location Zero Unchanged Increment
(1)
AEF, EF
0 X X
FF
1 X X
HF
1 X X
2752 tbl 09
NOTE: 1. Pointer will increment if appropriate flag is HIGH.
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IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
Width Expansion Configuration In the cascaded case, word widths of more than 9 bits can be achieved by using more than one device. By tying the SIX line of the least significant device HIGH and the SIX of the subsequent devices to the appropriate Data Set lines of the
previous devices, a cascaded serial word is achieved. On the first LOW-to-HIGH clock edge of SICP, both the Data Set lines go LOW. Just as in the standalone case, on each corresponding clock cycle, the equivalent Data Set line goes HIGH in order of least to most significant.
SERIAL DATA IN
8
XI
SERIAL-IN CLOCK V CC SICP SIX
SI Q 0-7 FIFO #1 NW D7
8
XI
SICP SIX
SI Q 0-7 FIFO #2 NW D7
PARALLEL DATA OUT
8
0
1
7
8
9
10
14
15
0
SOCP D 7 OF FIFO #1 AND SIX OF FIFO #2 D 7 OF FIFO #2 AND NW TO FIFO #1 AND FIFO #2
2752 drw 17
Figure 14. Serial-In to Parallel-Out Data of 16 Bits
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IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
Depth Expansion (Daisy Chain) Mode The IDT72132/42 can be easily adapted to applications where the requirements are for greater than 2048/4096 words. Figure 15 demonstrates Depth Expansion using three IDT72132/42. Any depth can be attained by adding additional IDT72132/42 operates in the Depth Expansion configuration when the following conditions are met: 1. The first device must be designated by grounding the First Load (FL) control input.
2. All other devices must have FL in the high state. 3. The Expansion Out (XO) pin and Expansion In (XI) pin of each device must be tied together. 4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires the OR-ing of all EFs and OR-ing of all FFs (i.e., all must be set to generate the correct composite (FF) or (EF). 5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth Expansion mode.
Q0-7
V CC
SIX
Q 0-7 FIFO #1 IDT72142 SI SICP
FL/RT
R NW
R
XO XI
D7
SICP VCC FIFO #2 IDT72142 SI SICP
XI
XO
Q 0-7 R D7
FL/RT
SI
SIX
NW
2752 drw 18
Figure 15. An 8K x 8 Serial-In Parallel-Out FIFO
TABLE 2: RESET AND FIRST LOAD TRUTH TABLE -- DEPTH EXPANSION/COMPOUND EXPANSION MODE
Inputs Mode Reset-First Device Reset all Other Devices Read/Write Internal Status Outputs
RS
0 0 1
FL/RT
0 1 X
XI
(1) (1) (1)
Read Pointer Location Zero Location Zero X
Write Pointer Location Zero Location Zero X
EF
0 0 X
FF
1 1 X
2752 tbl 10
NOTES: 1. XI is connected to XO of the previous device. 2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Ouput, FF = Full Flag Output, XI = Expansion Input.
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IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
SERIAL INPUT WITH WIDTH AND DEPTH EXPANSION
SERIAL DATA IN VCC SIX SICP R Q 0-7 XI XO Q 0-7 XI XO SI D7 NW SICP R Q 0-7 XI XO SIX SI D7 NW SICP R SIX SI D7 NW
CC SERIAL INPUT CLOCK
V SIX SI D7 XO XI SICP R Q0-7 Q0-7 NW SIX SI D7 XO XI SICP R Q0-7 NW SIX SI D7 XO XI SICP R READ NW
P0-7
P8-15 PARALLEL DATA OUT
P16-23
2752 drw 19
Figure 16. An 8K x 24 Serial-In, Parallel-Out FIFO Using Six IDT72142s
ORDERING INFORMATION
IDT XXXXX Device Type X Power XXX Speed X Package X Process/ Temperature Range
Blank
Commercial (0C to +70C)
P
Plastic DIP
35 50 L 72132 72142
(50MHz serial shift rate) (40MHz serial shift rate) Low Power
Parallel Access Time (tA)
2048 x 9-Bit Serial-Parallel FIFO 4096 x 9-Bit Serial-Parallel FIFO
2752 drw 20
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