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Micrel, Inc.
3.3V 500MHz DUAL 1:10 HSTL FANOUT BUFFER/TRANSLATOR WITH 2:1 MUX INPUT
Precision Edge(R) SY89827L Precision Edge(R)
SY89827L
FEATURES
s Dual LVPECL or HSTL input, 10 differential 1.5V HSTL compatible outputs s Configurable as dual-channel 10 output or a singlechannel 20 output clock driver s Guaranteed AC parameters over temperature and voltage: * > 500MHz fMAX * < 50ps within device skew * < 1.5ns propagation delay * < 700ps tr / tf time s Low jitter design * < 1psRMS cycle-to-cycle jitter * < 10psPP total jitter s 3.3V core supply, 1.8V output supply s Output enable function s Available in a 64-Pin EPAD-TQFP Precision Edge(R)
DESCRIPTION
The SY89827L is a High Performance Bus Clock Driver with dual 1:10 or single 1:20 HSTL (High Speed Transceiver Logic) output pairs. The part is designed for use in low voltage (3.3V/1.8V) applications which require a large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed from either HSTL or LVPECL (Low Voltage Positive Emitter Coupled Logic) by the CLK_SEL pin. The Output Enables (OE1 & OE2) are synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/ disabled as can happen with an asynchronous control. The SY89827L features extremely low skew performance of <50ps over temperature and voltage - performance previously unachievable in a standard product having such a high number of outputs. The SY89827L is available in a single space saving package, enabling a lower overall cost solution. For applications that require greater HSTL fanout capability, consider the SY89824L.
APPLICATIONS
s s s s s High-performance PCs Workstations Parallel processor-based systems Other high-performance computing Communications
TYPICAL APPLICATION CIRCUIT
Primary Clock Source LVPECL_CLKA /LVPECL_CLKA Redundant Backup Clock Source LVPECL_CLKB /LVPECL_CLKB
10 10
Primary Card
10 10
Redundant Card
SEL1 Primary/Backup Clock Select (Switchover within 2.0ns)
System using SY89827L as a switchover circuit from a Primary Clock to a Redundant Backup Clock in a failsafe application. LVPECL inputs only, shown in this application. Precision Edge is a registered trademark of Micrel, Inc. M9999-011907 hbwhelp@micrel.com or (408) 955-1690
Rev.: E Amendment: /0
1
Issue Date: January 2007
Micrel, Inc.
Precision Edge(R) SY89827L
PACKAGE/ORDERING INFORMATION
VCCO Q0 /Q0 Q1 /Q1 Q2 /Q2 Q3 /Q3 Q4 /Q4 Q5 /Q5 Q6 /Q6 VCCO
Ordering Information(1)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCCO Q7 /Q7 Q8 /Q8 Q9 /Q9 VCCO VCCO Q10 /Q10 Q11 /Q11 Q12 /Q12 VCCO
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SEL2 HSTL_CLKB /HSTL_CLKB VCCI HSTL_CLKA /HSTL_CLKA CLK_SEL1 LVPECL_CLKA /LVPECL_CLKA GND OE1 LVPECL_CLKB /LVPECL_CLKB CLK_SEL2 OE2 SEL1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Part Number SY89827LHI SY89827LHITR(2) SY89827LHY(3) SY89827LHYTR(2, 3)
Package Type H64-1 H64-1 H64-1 H64-1
Operating Range Industrial Industrial Industrial Industrial
Package Marking SY89827LHI SY89827LHI
Lead Finish Sn-Pb Sn-Pb
SY89827LHY with Pb-Free Pb-Free bar-line indicator Matte-Sn SY89827LHY with Pb-Free Pb-Free bar-line indicator Matte-Sn
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC electricals only. 2. Tape and Reel. 3. Pb-Free package recommended for new designs.
64-Pin TQFP (H64-1)
FUNCTIONAL BLOCK DIAGRAM
CLK_SEL1 SEL1 HSTL_CLKA /HSTL_CLKA LVPECL_CLKA /LVPECL_CLKA 0 0 1 1 LEN HSTL_CLKB /HSTL_CLKB LVPECL_CLKB /LVPECL_CLKB 0 D 1 0 CLK_SEL2 1 LEN SEL2 Q D OE2
10 10 10 10
VCCO /Q19 Q19 /Q18 Q18 /Q17 Q17 /Q16 Q16 /Q15 Q15 /Q14 Q14 /Q13 Q13 VCCO
OE1
Q0 - Q9 /Q0 - /Q9
Q
Q10 - Q19 /Q10 - /Q19
M9999-011907 hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precision Edge(R) SY89827L
TRUTH TABLE
OE1(1) OE2(1) SEL1(1) SEL2(1) CLK_SEL1(1) CLK_SEL2(1) 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0
Note 1.
Q0 - Q9
/Q0 - /Q9
Q10 - Q19
/Q10 - /Q19
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0
0 0 0 0 0 0 1 1 1 1 1 1 X X X X 0 0 1 1 X
0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 X X X X X
0 1 0 0 1 1 0 0 1 1 X X 0 1 X X 0 1 X X X
X X 0 1 0 1 0 1 0 1 0 1 X X 0 1 X X 0 1 X
HSTL_CLKA /HSTL_CLKA HSTL_CLKA /HSTL_CLKA LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKA /LVPECL_CLKA HSTL_CLKA /HSTL_CLKA HSTL_CLKB /HSTL_CLKB HSTL_CLKA /HSTL_CLKA LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKA /LVPECL_CLKA HSTL_CLKB /HSTL_CLKB LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKB /LVPECL_CLKB HSTL_CLKB /HSTL_CLKB HSTL_CLKA /HSTL_CLKA LVPECL_CLKB /LVPECL_CLKB HSTL_CLKA /HSTL_CLKA HSTL_CLKB /HSTL_CLKB LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKA /LVPECL_CLKA HSTL_CLKB /HSTL_CLKB HSTL_CLKB /HSTL_CLKB LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKB /LVPECL_CLKB LOW LOW LOW LOW HIGH HIGH HIGH HIGH HSTL_CLKA /HSTL_CLKA LVPECL_CLKA /LVPECL_CLKA HSTL_CLKB /HSTL_CLKB LVPECL_CLKB /LVPECL_CLKB LOW LOW LOW LOW LOW HIGH HIGH HIGH HIGH HIGH
HSTL_CLKA /HSTL_CLKA LVPECL_CLKA /LVPECL_CLKA HSTL_CLKB /HSTL_CLKB LVPECL_CLKB /LVPECL_CLKB LOW HIGH
Input has internal pull-up Floating input = 1.
M9999-011907 hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
Precision Edge(R) SY89827L
PIN DESCRIPTIONS
Pin Number 5, 6 Pin Name HSTL_CLKA /HSTL_CLKA I/O Input Type HSTL Internal P/U Pin Function Differential clock input selected by CLK_SEL1, SEL1 and SEL2. Can be left floating if not selected. Floating input, if selected produces an indeterminate output. HSTL input signal requires external termination 50-to-GND. Differential clock input selected by CLK_SEL1, SEL1 and SEL2. Can be left floating if not selected. Floating input, if selected produces an indeterminate output. HSTL input signal requires external termination 50-to-GND. 75k pull-down 75k pull-down 11k Pull-up 11k Pull-up 11k Pull-up 11k Pull-up 11k Pull-up 11k Pull-up Differential clock input selected by CLK_SEL1, SEL1 and SEL2. Can be left floating. Floating input, if selected produces a LOW at output. Requires external termination. See Figure 1. Differential clock input selected by CLK_SEL2, SEL1 and SEL2. Requires external termination. See Figure 1. Selects HSTL_CLKA input when LOW and LVPECL_CLKA input when HIGH. Selects HSTL_CLKB input when LOW and LVPECL_CLKB input when HIGH. Selects input source CLKA when LOW and CLKB when HIGH for outputs Q0 - Q9 and /Q0 - /Q9. Selects input source CLKA when LOW and CLKB when HIGH for outputs Q10 - Q19 and /Q10 - /Q19. Enable input synchronized internally to prevent glitching of the Q0 - Q9 and /Q0 - /Q9 outputs. Enable input synchronized internally to prevent glitching of the Q10 - Q19 and /Q10 - /Q19 outputs. Core VCC connected to 3.3V supply. Bypass with 0.1F in parallel with 0.01F low ESR capacitors as close to VCC pins as possible. Output buffer VCC connected to 1.8V nominal supply. All VCCO pins should be connected together on the PCB. Bypass with 0.1F in parallel with 0.01F low ESR capacitors as close to VCCO pins as possible. Ground. HSTL Differential clock outputs from CLKA when SEL1 = LOW and from CLKB when SEL1 = HIGH. HSTL outputs (Q and /Q) must be terminated with 50-to-GND. Q outputs are static when OE1 = LOW. Unused output pairs may be left floating. Differential clock outputs (complement) from CLKA when SEL1 = LOW and from CLKB when SEL1 = HIGH. HSTL outputs (Q and /Q) must be terminated with 50-to-GND. /Q outputs are static HIGH when OE1 = LOW. Unused output pairs may be left floating. Differential outputs from CLKA when SEL2 = LOW and from CLKB when SEL2 = HIGH. HSTL outputs (Q and /Q) must be terminated with 50-to-GND. Q outputs are static LOW when OE2 = LOW. Unused output pairs may be left floating. Differential outputs (complement) from CLKA when SEL2 = LOW and from CLKB when SEL2 = HIGH. HSTL outputs (Q and /Q) must be terminated with 50-to-GND. /Q outputs are static HIGH when OE2 = LOW. Unused output pairs may be left floating.
2, 3
HSTL_CLKB /HSTL_CLKB
Input
HSTL
8, 9
LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKB /LVPECL_CLKB CLK_SEL1 CLK_SEL2 SEL1 SEL2 OE1 OE2 VCCI
Input
LVPECL
12, 13 7 14 16 1 11 15 4
Input Input Input Input Input Input Input Power
LVPECL LVTTL/ CMOS LVTTL/ CMOS LVTTL/ CMOS LVTTL/ CMOS LVTTL/ CMOS LVTTL/ CMOS
17, 32, 33, 40, 41, 48, 49, 64
VCCO
Power
10 63, 61, 59, 57, 55 53, 51, 47, 45, 43
GND Q0 - Q9
Power Output
62, 60, 58, 56, 54 52, 50, 46, 44, 42
/Q0 - /Q9
Output
HSTL
39, 37, 35, 31, 29
Q10 - Q19 Output 27, 25, 23, 21, 19
HSTL
38, 36, 34, 30, 28
/Q10 - /Q19 Output 26, 24, 22, 20, 18
HSTL
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Micrel, Inc.
Precision Edge(R) SY89827L
Absolute Maximum Ratings(Note 1)
Power Supply Voltage (VCCI, VCCO) .............. -0.5 to +4.0V Input Voltage (VIN) ........................................... -0.5 to VCCI Output Current (IOUT) ............................................... -50mA Lead Temperature (TLEAD, Soldering, 20sec.) .......... 260C Storage Temperature (TS) ........................... -65 to +150C ESD Rating, Note 3 .................................................... >1kV
Operating Ratings(Note 2)
Supply Voltage (VCCI) .................................................... +3.3V to +3.47V (VCCO) ..................................................... +1.6V to +2.0V Ambient Temperature (TA) ......................... -40C to +85C Package Thermal Resistance TQFP (JA) Exposed pad soldered to GND, Note 4 Still-Air (multi-layer PCB) ................................. 23C/W -200lfpm (multi-layer PCB) ............................. 18C/W -500lfpm (multi-layer PCB) ............................. 15C/W Exposed pad NOT soldered to GND (not recommended) Still-Air (multi-layer PCB) ................................. 44C/W -200lfpm (multi-layer PCB) ............................. 36C/W -500lfpm (multi-layer PCB) ............................. 30C/W TQFP (JC) ......................................................... 4.4C/W
DC ELECTRICAL CHARACTERISTICS
Power Supply: TA = -40C to +85C
Symbol VCCI VCCO ICCI Parameter VCC Core VCC Output ICC Core No Load Condition Min 3.13 1.6 Typ 3.3 1.8 140 Max 3.47 2.0 170 Units V V mA
HSTL Input/Output: VCCI = 3.3V 5%, VCCO = 1.8V 10%, TA = -40C to +85C
Symbol VOH VOL VIH VIL VX IIH IIL
Note 1.
Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Crossover Voltage Input HIGH Current Input LOW Current
Condition Note 5 Note 5
Min 1.0 0.2 VX +0.1 -0.3 0.68 +20
Typ
Max 1.2 0.4 1.6 VX -0.1 0.9 -350 -500
Units V V V V V A A
Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended periods may affect device reliability. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. Devices are ESD sensitive. Handling precautions recommended. It is highly recommended to solder the exposed pad of the EPAD-TQFP package to a ground plane on the PCB for maximum thermal efficiency. Outputs loaded with 50-to-ground.
Note 2. Note 3. Note 4. Note 5.
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Micrel, Inc.
Precision Edge(R) SY89827L
DC ELECTRICAL CHARACTERISTICS
LVPECL Input: VCCI = 3.3V 5%, TA = -40C to +85C
Symbol VIH VIL VPP VCMR IIH IIL
Note 6. Note 7.
Parameter Input HIGH Voltage (Single-Ended) Input LOW Voltage Minimum Input Swing (LVPECL_CLK)
Condition
Min VCCI -1.165 VCCI -1.945
Typ
Max VCCI -0.880 VCCI -1.625 VCCI -0.4 150
Units V V mV V A A
Note 6
300 GNDI +1.8
Common Mode Range (LVPECL_CLK) Note 7 Input HIGH Current Input LOW Current
0.5
The VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The numbers in the table are referenced to VCCI. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP (min.). VCMR range varies 1:1 with VCCI. VCMR (min) is fixed at GNDI +1.8V
CMOS/LVTTL Inputs: VCCI = 3.3V 5%, VCCO = 1.8V 10%, TA = -40C to +85C
Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current +20 Condition Min 2.0 0.8 -250 -600 Typ Max Units V V A A
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Micrel, Inc.
Precision Edge(R) SY89827L
AC ELECTRICAL CHARACTERISTICS(NOTE 1)
VCCI = 3.3V 5%, VCCO = 1.8V 10%, TA = -40C to +85C, all outputs loaded, unless noted. Symbol fMAX tPD VPP tSW tJITTER tS(OE) tH(OE) tskew Parameter Maximum Toggle Frequency Differential Propagation Delay Minimum Input Swing, Note 4 Switchover Time Cycle-to-Cycle Total Jitter Output Enable Set-Up Time Output Enable Hold Time Within Device Skew Part-to-Part Skew tr, tf
Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Note 8. Note 9.
Condition Note 2 Note 3 HSTL PECL CLK_SEL-to-Q SEL-to-Q Note 8 Note 9 Note 5 Note 5 Note 6 Note 7 0C to +85C -40C
Min 500 1.0 200 150
Typ
Max
Units MHz
1.3
1.5
ns mV mV
1.6 1.4
2.0 1.75 <1 <10
ns ns psRMS psPP ns ns
1.0 0.5 25 35 50 75 400 450 700
ps ps ps ps
Output Rise/Fall Times (20% to 80%)
Outputs loaded with 50-t- ground.
fMAX is defined as the maximum toggle frequency, measured with a 750mV LVPECL/HSTL input. HSTL output swing is > 400mV. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential output signals. The VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH-to-LOW transition ensures outputs remain disabled during the next clock cycle. OE LOW-to-HIGH transition enables normal operation of the next input clock. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same voltage and temperature. This parameters includes within bank skew and bank-to-bank skew. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. Cycle-to-cycle jitter definition: The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. TJITTER_CC =Tn-Tn+1 where T is the time between rising edges of the output signal. Total jitter definition: with an ideal clock input, no more than one output edge in 1012 output edges will deviate by more than the specified peakto-peak jitter value.
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Micrel, Inc.
Precision Edge(R) SY89827L
TYPICAL OPERATING CHARACTERISTICS
VCCI = 3.3V, VCCO = 1.8V, TA = 25C, unless otherwise stated.
800 OUTPUT AMPLITUDE (mV) 700 600 500 400 300 200 100 0 0
Output Amplitude vs. Frequency
200 400 600 800 FREQUENCY (MHz)
1000
1400 PROPAGATION DELAY (ns) 1200 1000 800 600 400 200 0 0
Propagation Delay vs. Input Amplitude HSTL INPUT SWITCHOVER TIME (ns)
1800 1600 1400 1200 1000 800 600 400 200 0 -50
CLK_SEL Switchover Time vs. Temperature
PECL INPUT
200 400 600 800 1000 INPUT AMPLITUDE (mV)
-25 0 25 50 75 TEMPERATURE (C)
100
M9999-011907 hbwhelp@micrel.com or (408) 955-1690
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Micrel, Inc.
Precision Edge(R) SY89827L
FUNCTIONAL CHARACTERISTICS
VCCI = 3.3V, VCCO = 1.8V, TA = 25C, unless otherwise stated.
100MHz Output
/Q
250MHz Output
/Q
Output Swing (100mV/div.)
Q
Q
Output Swing (100mV/div.)
TIME (2ns/div.)
TIME (500ps/div.)
500MHz Output
/Q
Output Swing (100mV/div.)
Q
TIME (500ps/div.)
M9999-011907 hbwhelp@micrel.com or (408) 955-1690
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Micrel, Inc.
Precision Edge(R) SY89827L
LVPECL/HSTL INPUTS
VCC
VCC
LVPECL_CLK
HSTL_CLK
75k
75k
/HSTL_CLK Clamp
/LVPECL_CLK
GND
GND
Figure 1. Simplified LVPECL Input Stage
Figure 2. Simplified HSTL Input Stage
HSTL OUTPUTS
QOUT 1.6V QOUT -- /QOUT /QOUT
Figure 3. Output Driver Signal Levels (Single-Ended) Figure 4. Output Driver Signal Levels (Differential)
QOUT
800mV /QOUT
RELATED PRODUCT AND SUPPORT DOCUMENTATION
Part Number SY89809L SY89824L M-0317 MIC3775 Function 3.3V 1:9 High-Performance, Low-Voltage Bus Clock Driver 3.3V 1:22 High-Performance, Low-Voltage Bus Clock Driver Exposed Pad Application Note HBW Solutions 750mA Cap Low-Voltage Low-Dropout Regulator Data Sheet Link www.micrel.com/product-info/products/sy89809l.shtml www.micrel.com/product-info/products/sy89824l.html www.amkor.com/products/notes_papers/epad.pdf www.micrel.com/product-info/products/solutions.shtml www.micrel.com/product-info/products/mic3775.shtml
M9999-011907 hbwhelp@micrel.com or (408) 955-1690
10
Micrel, Inc.
Precision Edge(R) SY89827L
64-PIN EPAD-TQFP (DIE UP) (H64-1)
+0.05 -0.05 +0.002 -0.002
+0.05 -0.05 +0.012 -0.012
+0.03 -0.03 +0.012 -0.012
+0.15 -0.15 +0.006 -0.006
+0.05 -0.05 +0.002 -0.002
Rev. 02
Package EP- Exposed Pad
Die
CompSide Island
Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane
PCB Thermal Consideration for 64-Pin EPAD-TQFP Package (Always solder, or equivalent, the exposed pad to the PCB)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
USA
+ 1 (408) 944-0800
FAX
+ 1 (408) 944-0970
WEB
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated. M9999-011907 hbwhelp@micrel.com or (408) 955-1690
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