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MC74VHC4051, MC74VHC4052, MC74VHC4053 Analog Multiplexers / Demultiplexers
High-Performance Silicon-Gate CMOS
The MC74VHC4051, MC74VHC4052 and MC74VHC4053 utilize silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The VHC4051, VHC4052 and VHC4053 are identical in pinout to the high-speed HC4051A, HC4052A and HC4053A, and the metal- gate MC14051B, MC14052B and MC14053B. The Channel-Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off. The Channel-Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors they are compatible with LSTTL outputs. These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal-gate CMOS analog switches. * Fast Switching and Propagation Speeds * Low Crosstalk Between Switches * Diode Protection on All Inputs/Outputs * Analog Power Supply Range (VCC -- VEE) = 2.0 to 12.0 V * Digital (Control) Power Supply Range (VCC -- GND) = 2.0 to 6.0 V * Improved Linearity and Lower ON Resistance Than Metal--Gate Counterparts * Low Noise * Chip Complexity: VHC4051 -- 184 FETs or 46 Equivalent Gates VHC4052 -- 168 FETs or 42 Equivalent Gates VHC4053 -- 156 FETs or 39 Equivalent Gates
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16
16 1
SO-16 D SUFFIX CASE 751B 1
VHC405x AWLYWW
16
16 1
TSSOP-16 DT SUFFIX CASE 948F 1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week
VHC 405x ALYW
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet.
*
These devices are available in Pb-free package(s). Specifications herein apply to both standard and Pb-free devices. Please see our website at www.onsemi.com for specific Pb-free orderable part numbers, or contact your local ON Semiconductor sales office or representative.
(c) Semiconductor Components Industries, LLC, 2006
March, 2006 - Rev. 5 -
1
Publication Order Number: MC74VHC4051/D
MC74VHC4051, MC74VHC4052, MC74VHC4053
X0 14 X1 15 X2 X3 1 X4 5 X5 2 X6
4 12 13
ANALOG INPUTS/ OUTPUTS
3
MULTIPLEXER/ DEMULTIPLEXER
X
COMMON OUTPUT/ INPUT
CHANNEL SELECT INPUTS
X7 11 A 10 B 9 C
6
ENABLE
PIN 16 = VCC PIN 7 = VEE PIN 8 = GND
MC74VHC4051 Single-Pole, 8-Position Plus Common Off
X0 14 X1 15 X2 11 X3 Y0 5 Y1 2 Y2 Y3 10 A 9 B
6 4 1 12
X SWITCH
13
X COMMON OUTPUTS/INPUTS
ANALOG INPUTS/OUTPUTS
Y SWITCH
3
Y
CHANNEL-SELECT INPUTS
ENABLE
PIN 16 = VCC PIN 7 = VEE PIN 8 = GND
MC74VHC4052 Double-Pole, 4-Position Plus Common Off
12
X0 13 X1 Y0 1 Y1 Z0 3 Z1 CHANNEL-SELECT INPUTS A
11 10 5 2
X SWITCH
14
X
ANALOG INPUTS/OUTPUTS
Y SWITCH
15
Y
COMMON OUTPUTS/INPUTS
Z SWITCH
4
Z
B 9 C 6 ENABLE
PIN 16 = VCC PIN 7 = VEE PIN 8 = GND
NOTE: This device allows independent control of each switch. Channel--Select Input A controls the X--Switch, Input B controls the Y--Switch and Input C controls the Z--Switch
MC74VHC4053 Triple Single-Pole, Double-Position Plus Common Off
Figure 1. Logic Diagrams http://onsemi.com
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MC74VHC4051, MC74VHC4052, MC74VHC4053
FUNCTION TABLE - MC74VHC4051 VCC 16 X2 15 X1 14 X0 13 X3 12 A 11 B 10 C 9 Control Inputs Enable L L L L L L L L H C L L L L H H H H X Select B A L L H H L L H H X L H L H L H L H X ON Channels X0 X1 X2 X3 X4 X5 X6 X7 NONE
1 X4
2 X6
3 X
4 X7
5 X5
6
7
8 GND
Enable VEE
Figure 2. Pinout: MC74VHC4051 (Top View)
X = Don't Care
VCC 16
X2 15
X1 14
X 13
X0 12
X3 11
A 10
B 9
FUNCTION TABLE - MC74VHC4052 Control Inputs Enable L L L L H X = Don't Care B L L H H X Select A L H L H X ON Channels Y0 Y1 Y2 Y3 NONE X0 X1 X2 X3
1 Y0
2 Y2
3 Y
4 Y3
5 Y1
6
7
Enable VEE
8 GND
Figure 3. Pinout: MC74VHC4052 (Top View)
FUNCTION TABLE - MC74VHC4053 VCC 16 Y 15 X 14 X1 13 X0 12 A 11 B 10 C 9 Enable L L L L L L L L H C L L L L H H H H X Control Inputs Select B A L L H H L L H H X L H L H L H L H X ON Channels Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 NONE X0 X1 X0 X1 X0 X1 X0 X1
1 Y1
2 Y0
3 Z1
4 Z
5 Z0
6
7
8 GND
Enable VEE
Figure 4. Pinout: MC74VHC4053 (Top View)
X = Don't Care
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MC74VHC4051, MC74VHC4052, MC74VHC4053
MAXIMUM RATINGS*
Symbol VCC VEE VIS Vin I PD Tstg Parameter Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE) Value - 0.5 to + 7.0 - 0.5 to + 14.0 - 7.0 to + 5.0 VEE -- 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 25 SOIC Package TSSOP Package 500 450 - 65 to + 150 Unit V V V V mA mW _C _C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high--impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
Negative DC Supply Voltage (Referenced to GND) Analog Input Voltage Digital Input Voltage (Referenced to GND) DC Current, Into or Out of Any Pin Power Dissipation in Still Air Storage Temperature Range
TL Lead Temperature, 1 mm from Case for 10 Seconds 260 *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: -- 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VEE VIS Vin VIO* TA tr, tf Positive DC Supply Voltage Parameter (Referenced to GND) (Referenced to VEE) Min 2.0 2.0 -- 6.0 VEE GND Max 6.0 12.0 GND VCC VCC 1.2 - 55 0 0 0 0 + 125 1000 800 500 400 Unit V V V V V _C ns
Negative DC Supply Voltage, Output (Referenced to GND) Analog Input Voltage Digital Input Voltage (Referenced to GND) Static or Dynamic Voltage Across Switch Operating Temperature Range, All Package Types Input Rise/Fall Time (Channel Select or Enable Inputs)
VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V *For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
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MC74VHC4051, MC74VHC4052, MC74VHC4053
DC CHARACTERISTICS -- Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
Symbol VIH Parameter Minimum High--Level Input Voltage, Channel--Select or Enable Inputs Maximum Low--Level Input Voltage, Channel--Select or Enable Inputs Maximum Input Leakage Current, Channel--Select or Enable Inputs Maximum Quiescent Supply Current (per Package) Condition Ron = Per Spec VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 6.0 Guaranteed Limit -55 to 25C 1.50 2.10 3.15 4.20 0.5 0.9 1.35 1.8 0.1 85C 1.50 2.10 3.15 4.20 0.5 0.9 1.35 1.8 1.0 125C 1.50 2.10 3.15 4.20 0.5 0.9 1.35 1.8 1.0 Unit V
VIL
Ron = Per Spec
V
Iin ICC
Vin = VCC or GND, VEE = -- 6.0 V Channel Select, Enable and VIS = VCC or GND; VEE = GND VIO = 0 V VEE = -- 6.0
A A
6.0 6.0
1 4
10 40
40 80
DC ELECTRICAL CHARACTERISTICS Analog Section
Guaranteed Limit Symbol Ron Parameter Maximum "ON" Resistance Test Conditions Vin = VIL or VIH VIS = VCC to VEE IS 2.0 mA (Figures 5 through 11) Vin = VIL or VIH VIS = VCC or VEE (Endpoints) IS 2.0 mA (Figures 5 through11) Ron Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package Maximum Off--Channel Leakage Current, Any One Channel Vin = VIL or VIH VIS = 1/2 (VCC -- VEE) IS 2.0 mA Vin = VIL or VIH; VIO = VCC -- VEE; Switch Off (Figure 12) VCC V 3.0 4.5 4.5 6.0 3.0 4.5 4.5 6.0 3.0 4.5 4.5 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 VEE V 0.0 0.0 - 4.5 - 6.0 0.0 0.0 - 4.5 - 6.0 0.0 0.0 - 4.5 - 6.0 -- 6.0 -- 6.0 -- 6.0 -- 6.0 -- 6.0 -- 6.0 -- 6.0 - 55 to 25_C 200 160 120 100 150 110 90 80 40 20 10 10 0.1 0.2 0.1 0.1 0.2 0.1 0.1 85_C 240 200 150 125 180 140 120 100 50 25 15 12 0.5 2.0 1.0 1.0 2.0 1.0 1.0 125_C 320 280 170 140 230 190 140 115 80 40 18 14 1.0 4.0 2.0 2.0 4.0 2.0 2.0 A Unit
Ioff
A
Maximum Off--Channel VHC4051 Vin = VIL or VIH; Leakage Current, VHC4052 VIO = VCC -- VEE; Common Channel VHC4053 Switch Off (Figure 13) Ion Maximum On--Channel VHC4051 Vin = VIL or VIH; Leakage Current, VHC4052 Switch--to--Switch = Channel--to--Channel VHC4053 VCC -- VEE; (Figure 14)
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MC74VHC4051, MC74VHC4052, MC74VHC4053
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Channel--Select to Analog Output (Figures 18, 19) VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 Guaranteed Limit -55 to 25C 270 90 59 45 40 25 12 10 160 70 48 39 245 115 49 39 10 35 130 80 50 1.0 85C 320 110 79 65 60 30 15 13 200 95 63 55 315 145 69 58 10 35 130 80 50 1.0 125C 350 125 85 75 70 32 18 15 220 110 76 63 345 155 83 67 10 35 130 80 50 1.0 Unit ns
tPLH, tPHL
Maximum Propagation Delay, Analog Input to Analog Output (Figures 20, 21)
ns
tPLZ, tPHZ
Maximum Propagation Delay, Enable to Analog Output (Figures 22, 23)
ns
tPZL, tPZH
Maximum Propagation Delay, Enable to Analog Output (Figures 22, 23)
ns
Cin CI/O
Maximum Input Capacitance, Channel--Select or Enable Inputs Maximum Capacitance (All Switches Off) Analog I/O Common O/I: VHC4051 VHC4052 VHC4053 Feedthrough
pF pF
Typical @ 25C, VCC = 5.0 V, VEE = 0 V CPD Power Dissipation Capacitance (Figure 25)* VHC4051 VHC4052 VHC4053 45 80 45 pF
* Used to determine the no--load dynamic power consumption: P D = CPD V CC 2 f + ICC V CC .
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MC74VHC4051, MC74VHC4052, MC74VHC4053
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Symbol BW Parameter Maximum On--Channel Bandwidth or Minimum Frequency Response (Figure 15) Condition fin = 1MHz Sine Wave; Adjust fin Voltage to Obtain 0dBm at VOS; Increase fin Frequency Until dB Meter Reads --3dB; RL = 50, CL = 10pF fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600, CL = 50pF VCC V VEE V `51 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 --2.25 --4.50 --6.00 --2.25 --4.50 --6.00 --2.25 --4.50 --6.00 --2.25 --4.50 --6.00 --2.25 --4.50 --6.00 --2.25 --4.50 --6.00 --2.25 --4.50 --6.00 80 80 80 Limit* 25C `52 95 95 95 --50 --50 --50 --40 --40 --40 25 105 135 35 145 190 --50 --50 --50 --60 --60 --60 % 2.25 4.50 6.00 --2.25 --4.50 --6.00 0.10 0.08 0.05 dB mVPP `53 120 120 120 dB Unit MHz
--
Off--Channel Feedthrough Isolation (Figure 16)
fin = 1.0MHz, RL = 50, CL = 10pF -- Feedthrough Noise. Channel--Select Input to Common I/O (Figure 17) Vin 1MHz Square Wave (tr = tf = 6ns); Adjust RL at Setup so that IS = 0A; Enable = GND RL = 600, CL = 50pF
RL = 10k, CL = 10pF -- Crosstalk Between Any Two Switches (Figure 24) (Test does not apply to VHC4051) fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600, CL = 50pF
fin = 1.0MHz, RL = 50, CL = 10pF fin = 1kHz, RL = 10k, CL = 50pF THD = THDmeasured -- THDsource VIS = 4.0VPP sine wave VIS = 8.0VPP sine wave VIS = 11.0VPP sine wave *Limits not tested. Determined by design and verified by qualification. 180 160 Ron , ON RESISTANCE (OHMS) 140 120 100 80 60 40 20 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 0 0 THD Total Harmonic Distortion (Figure 26)
300 Ron , ON RESISTANCE (OHMS) 250 200 150 100 50 0
125C 25C --55C
125C 25C --55C
0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 2.75 3.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Figure 5. Typical On Resistance, VCC - VEE = 2.0 V -
Figure 6. Typical On Resistance, VCC - VEE = 3.0 V -
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MC74VHC4051, MC74VHC4052, MC74VHC4053
120 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 100 80 60 25C 40 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 --55C 105 90 75 60 45 30 15 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 125C 25C --55C
125C
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Figure 7. Typical On Resistance, VCC - VEE = 4.5 V -
Figure 8. Typical On Resistance, VCC - VEE = 6.0 V -
80 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 70 60 50 40 30 20 10 0 --4.5 --3.5 --2.5 --1.5 --0.5 0.5 1.5 2.5 3.5 4.5 25C --55C 125C
60 50 40 30 --55C 20 10 0 --6.0 --5.0 --4.0 --3.0 --2.0 --1.0 0 1.0 2.0 3.0 4.0 5.0 6.0
125C 25C
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Figure 9. Typical On Resistance, VCC - VEE = 9.0 V -
Figure 10. Typical On Resistance, VCC - VEE = 12.0 V -
PLOTTER
PROGRAMMABLE POWER SUPPLY -+
MINI COMPUTER VCC DEVICE UNDER TEST
DC ANALYZER
ANALOG IN
COMMON OUT VEE
GND
Figure 11. On Resistance Test Set-Up
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MC74VHC4051, MC74VHC4052, MC74VHC4053
VCC VCC
VEE VCC A NC
16 OFF OFF
VCC
VEE VCC
ANALOG I/O
16 OFF OFF
VCC
COMMON O/I
COMMON O/I
VIH
6 7 8
VIH
6 7 8
VEE
VEE
Figure 12. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up
Figure 13. Maximum Off Channel Leakage Current, Common Channel, Test Set-Up
VCC A ON VEE VCC ANALOG I/O VIL 6 7 8 OFF
16
VCC N/C fin
VCC 0.1F ON 16
VOS dB METER CL* RL
COMMON O/I
6 7 8 VEE *Includes all probe and jig capacitance
VEE
Figure 14. Maximum On Channel Leakage Current, Channel to Channel, Test Set-Up
Figure 15. Maximum On Channel Bandwidth, Test Set-Up
VIS 0.1F fin RL OFF
VCC 16
VOS dB METER CL* RL RL ANALOG I/O RL ON/OFF OFF/ON
VCC 16 COMMON O/I RL CL* TEST POINT
6 7 8 VEE VIL or VIH CHANNEL SELECT *Includes all probe and jig capacitance VCC GND
Vin 1 MHz tr = tf = 6 ns
6 7 8 VEE
VCC 11
CHANNEL SELECT *Includes all probe and jig capacitance
Figure 16. Off Channel Feedthrough Isolation, Test Set-Up
Figure 17. Feedthrough Noise, Channel Select to Common Out, Test Set-Up
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MC74VHC4051, MC74VHC4052, MC74VHC4053
VCC VCC CHANNEL SELECT tPLH ANALOG OUT 50% 50% GND tPHL 6 7 8 CHANNEL SELECT *Includes all probe and jig capacitance ANALOG I/O ON/OFF OFF/ON VCC 16 COMMON O/I CL* TEST POINT
Figure 18. Propagation Delays, Channel Select to Analog Out
Figure 19. Propagation Delay, Test Set-Up Channel Select to Analog Out
VCC 16 ANALOG IN tPLH ANALOG OUT 50% VCC 50% tPHL GND 6 7 8 ANALOG I/O ON COMMON O/I CL* TEST POINT
*Includes all probe and jig capacitance
Figure 20. Propagation Delays, Analog In to Analog Out
Figure 21. Propagation Delay, Test Set-Up Analog In to Analog Out
tf ENABLE tPZL ANALOG OUT 50% tPZH ANALOG OUT 50%
tr 90% 50% 10% tPLZ VCC GND HIGH IMPEDANCE 10% tPHZ 90% VOL VOH HIGH IMPEDANCE VCC
1 2
POSITION 1 WHEN TESTING tPHZ AND tPZH POSITION 2 WHEN TESTING tPLZ AND tPZL VCC 16 ANALOG I/O
1k TEST POINT
1 2
ON/OFF CL*
ENABLE
6 7 8
Figure 22. Propagation Delays, Enable to Analog Out
Figure 23. Propagation Delay, Test Set-Up Enable to Analog Out
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MC74VHC4051, MC74VHC4052, MC74VHC4053
VIS RL 0.1F OFF VEE RL 6 7 8 *Includes all probe and jig capacitance RL CL* RL CL* VEE 6 7 8 VCC 11 16 ON VCC VOS ANALOG I/O ON/OFF OFF/ON VCC A 16 COMMON O/I NC
fin
CHANNEL SELECT
Figure 24. Crosstalk Between Any Two Switches, Test Set-Up
VIS 0.1F fin ON RL CL* 0 VCC 16 VOS TO DISTORTION METER dB --10 --20 --30 --40 --50 --60 --70 --80 *Includes all probe and jig capacitance --90 --100
Figure 25. Power Dissipation Capacitance, Test Set-Up
FUNDAMENTAL FREQUENCY
DEVICE SOURCE
6 7 8 VEE
1.0
2.0 FREQUENCY (kHz)
3.125
Figure 26. Total Harmonic Distortion, Test Set-Up
Figure 27. Plot, Harmonic Distortion
APPLICATIONS INFORMATION The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example: VCC = +5V = logic high GND = 0V = logic low The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In this example, the difference between VCC and VEE is ten volts. Therefore, using the configuration of Figure 28, a maximum analog signal of ten volts peak- -peak can be controlled. Unused -toanalog inputs/outputs may be left floating (i.e., not connected). However, tying unused analog inputs and outputs to VCC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: VCC - GND = 2 to 6 volts VEE - GND = 0 to - volts -6 VCC - VEE = 2 to 12 volts and VEE GND When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 29. These diodes should be able to absorb the maximum anticipated current surges during clipping.
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MC74VHC4051, MC74VHC4052, MC74VHC4053
+5V +5V --5V ANALOG SIGNAL 16 ON ANALOG SIGNAL +5V --5V VCC Dx Dx VEE 6 7 8 --5V 11 10 9 TO EXTERNAL CMOS CIRCUITRY 0 to 5V DIGITAL SIGNALS VEE 7 8 VCC 16 ON/OFF Dx VEE VCC Dx
Figure 28. Application Example
Figure 29. External Germanium or Schottky Clipping Diodes
+5V +5V VEE +5V VEE ANALOG SIGNAL 16 ON/OFF ANALOG SIGNAL +5V VEE +5V LSTTL/NMOS CIRCUITRY VEE 6 7 8 11 10 9 HCT BUFFER LSTTL/NMOS CIRCUITRY
+5V +5V VEE ANALOG SIGNAL 16 ON/OFF ANALOG SIGNAL +5V * R 6 7 8 VEE 11 10 9 * 2K R 10K R R
a. Using Pull-Up Resistors
b. Using HCT Interface
Figure 30. Interfacing LSTTL/NMOS to CMOS Inputs
A 11 LEVEL SHIFTER 13 X0
14
X1
B
10
LEVEL SHIFTER
15
X2
12
X3
C
9
LEVEL SHIFTER
1
X4
5
X5
ENABLE
6
LEVEL SHIFTER
2
X6
4
X7
3
Figure 31. Function Diagram, VHC4051
X
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MC74VHC4051, MC74VHC4052, MC74VHC4053
A 10 LEVEL SHIFTER 12 X0
14
X1
B
9
LEVEL SHIFTER
15
X2
11 13 ENABLE 6 LEVEL SHIFTER 1
X3 X Y0
5
Y1
2
Y2
4
Y3
3
Y
Figure 33. Function Diagram, VHC4052
A
11
LEVEL SHIFTER
13
X1
12 14 B 10 LEVEL SHIFTER 1
X0 X Y1
2 15 C 9 LEVEL SHIFTER 3
Y0 Y Z1
5 4 ENABLE 6 LEVEL SHIFTER
Z0 Z
Figure 32. Function Diagram, VHC4053
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MC74VHC4051, MC74VHC4052, MC74VHC4053
ORDERING & SHIPPING INFORMATION
Device MC74VHC4051D MC74VHC4051DR2 MC74VHC4051DT MC74VHC4051DTR2 MC74VHC4052D MC74VHC4052DR2 MC74VHC4052DT MC74VHC4052DTR2 MC74VHC4053D MC74VHC4053DR2 MC74VHC4053DT MC74VHC4053DTR2 Package SOIC--16 SOIC--16 TSSOP--16 TSSOP--16 SOIC--16 SOIC--16 TSSOP--16 TSSOP--16 SOIC--16 SOIC--16 TSSOP--16 TSSOP--16 Shipping 48 Units / Rail 2500 Units / Tape & Reel 96 Units / Rail 2500 Units / Tape & Reel 48 Units / Rail 2500 Units / Tape & Reel 96 Units / Rail 2500 Units / Tape & Reel 48 Units / Rail 2500 Units / Tape & Reel 96 Units / Rail 2500 Units / Tape & Reel
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MC74VHC4051, MC74VHC4052, MC74VHC4053
PACKAGE DIMENSIONS D SUFFIX SOIC CASE 751B-05 ISSUE J
--A16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
--B1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C --TSEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC74VHC4051, MC74VHC4052, MC74VHC4053
PACKAGE DIMENSIONS DT SUFFIX TSSOP CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE --W--. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 -----1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 -----0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
2X
L/2
J1 B --USECTION N-N J
L
PIN 1 IDENT. 1 8
N 0.15 (0.006) T U
S
0.25 (0.010) M
A --VN F DETAIL E
C 0.10 (0.004) - - SEATING -TPLANE
--W-
D
G
H
DETAIL E
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC74VHC4051/D

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