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MC10EP451, MC100EP451 3.3V / 5V ECL 6-Bit Differential Register with Master Reset
Description
The MC10/100EP451 is a 6-bit fully differential register with common clock and single-ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have a 75 kW pulldown resistor internally. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to < VEE + 1.2 V, the clamp will override and force the output to a default state. When in the default state, and since the flip-flop is edge triggered, the output reaches a determined, but not predicted, valid state. The positive transition of CLK (pin 4) will latch the registers. Master Reset (MR) HIGH will asynchronously reset all registers forcing Q outputs to go LOW. The 100 Series contains temperature compensation.
Features
http://onsemi.com MARKING DIAGRAM*
LQFP-32 FA SUFFIX CASE 873A
MCxxx EP451 AWLYYWWG 32 1
1
1
32
* * * * * * * * *
450 ps Typical Propagation Delay Maximum Frequency > 3.0 GHz Typical Asynchronous Master Reset 20 ps Skew Within Device, 35 ps Skew Device-To-Device PECL Mode Operating Range: VCC = 3.0 V to 5.5 V With VEE = 0 V NECL Mode Operating Range: VCC = 0 V With VEE = -3.0 V to -5.5 V Open Input Default State Safety Clamp on Inputs Pb-Free Packages are Available*
QFN32 MN SUFFIX CASE 488AM xxx A WL, L YY, Y WW, W G
MCxxx EP451 ALYWG
= 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
1
March, 2006 - Rev. 8
Publication Order Number: MC10EP451/D
MC10EP451, MC100EP451
D4 D5 D5 Q5 Q5 VEE Q4 Q4 D1 24 D4 D3 D3 VEE MR D2 D2 D1 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 23 22 21 20 19 18 17 16 15 14 VCC Q3 Q3 VCC Q2 Q2 Q1 Q1 D1 D0 D0 CLK CLK VCC Q0 Q0 1 2 3 4 5 6 7 8 9 Q1 D1 D0 D0 CLK CLK VCC Q0 Q0 10 Q1 11 Q2 12 13 14 15 16 32 D2 31 D2 MR VEE D3 30 29 28 27 D3 26 D4 25 24 D4 23 D5 22 D5
MC10EP451 MC100EP451
13 12 11 10 9
MC10EP451 MC100EP451
21 Q5 20 Q5 19 VEE 18 Q4 17 Q4
Q2 VCC Q3
Q3 VCC
Figure 2. QFN-32 Pinout (Top View)
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. LQFP-32 Pinout (Top View)
D0 D0
D
Q
Q0 Q0
R
Table 1. PIN DESCRIPTION
PIN D [0:5]*, D [0:5]* MR* CLK*, CLK* Q [0:5], Q [0:5] VCC VEE EP for QFN-32, only FUNCTION ECL Differential Data Inputs ECL Master Reset Input ECL Differential Clock Inputs ECL Differential Data Outputs Positive Supply Negative Supply The Exposed Pad (EP) on the QFN-32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat- sinking conduit. The pad is electrically connected to VEE.
D1 D1
D
Q
Q1 Q1
R D2 D2
D
Q
Q2 Q2
R D3 D3
D
Q
Q3 Q3
R
* Pins will default LOW when left open.
D4 D4
D
Q
Q4 Q4
R D5 D5 CLK CLK MR
D
Q
Q5 Q5
R VEE
Figure 3. Logic Diagram http://onsemi.com
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MC10EP451, MC100EP451
Table 2. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Pb Pkg Level 2 Value 75 kW N/A > 2 kV > 200 V > 2 kV Pb-Free Pkg Level 2 Level 1
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) LQFP-32 QFN-32 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in 919 Devices
Table 3. MAXIMUM RATINGS
Symbol VCC VEE VI Iout TA Tstg qJA qJC qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm 2S2P LQFP-32 LQFP-32 LQFP-32 QFN-32 QFN-32 QFN-32 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI v VCC VI w VEE Condition 2 Rating 6 -6 6 -6 50 100 -40 to +85 -65 to +150 80 55 12 to 17 31 27 12 265 265 Unit V V V V mA mA C C C/W C/W C/W C/W C/W C/W C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
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MC10EP451, MC100EP451
Table 4. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) Input HIGH Current Input LOW Current 0.5 Min 80 2165 1365 2090 1365 2.0 Typ 95 2290 1490 Max 125 2415 1615 2415 1690 3.3 Min 80 2230 1430 2155 1430 2.0 25C Typ 95 2355 1555 Max 125 2480 1680 2480 1755 3.3 Min 80 2290 1470 2215 1490 2.0 85C Typ 95 2415 1615 Max 125 2540 1740 2540 1815 3.3 Unit mA mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
Table 5. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) Input HIGH Current Input LOW Current 0.5 Min 80 3865 3065 3790 3065 2.0 Typ 95 3990 3190 Max 125 4115 3315 4115 3390 5.0 Min 80 3930 3130 3855 3130 2.0 25C Typ 95 4055 3255 Max 125 4180 3380 4180 3455 5.0 Min 80 3990 3170 3915 3190 2.0 85C Typ 95 4115 3315 Max 125 4240 3440 4240 3515 5.0 Unit mA mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
Table 6. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 6)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) Input HIGH Current Input LOW Current 0.5 Min 80 -1135 -1935 -1210 -1935 VEE+2.0 Typ 95 -1010 -1810 Max 125 -885 -1685 -885 -1610 0.0 Min 80 -1070 -1870 -1145 -1870 VEE+2.0 25C Typ 95 -945 -1745 Max 125 -820 -1620 -820 -1545 0.0 Min 80 -1010 -1830 -1085 -1810 VEE+2.0 85C Typ 95 -885 -1685 Max 125 -760 -1560 -760 -1485 0.0 Unit mA mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 3. All loading with 50 W to VCC - 2.0 V. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 6. Input and output parameters vary 1:1 with VCC.
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MC10EP451, MC100EP451
Table 7. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 7)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 8) Output LOW Voltage (Note 8) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 9) Input HIGH Current Input LOW Current 0.5 Min 85 2155 1355 2075 1355 2.0 Typ 105 2280 1480 Max 135 2405 1605 2420 1675 3.3 Min 85 2155 1355 2075 1355 2.0 25C Typ 105 2280 1480 Max 135 2405 1605 2420 1675 3.3 Min 85 2155 1355 2075 1355 2.0 85C Typ 105 2280 1480 Max 135 2405 1605 2420 1675 3.3 Unit mA mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 8. All loading with 50 W to VCC - 2.0 V. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 10)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 11) Output LOW Voltage (Note 11) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 12) Input HIGH Current Input LOW Current 0.5 Min 85 3855 3055 3775 3055 2.0 Typ 105 3980 3180 Max 135 4105 3305 4120 3375 5.0 Min 85 3855 3055 3775 3055 2.0 25C Typ 105 3980 3180 Max 135 4105 3305 4120 3375 5.0 Min 85 3855 3055 3775 3055 2.0 85C Typ 105 3980 3180 Max 135 4105 3305 4120 3375 5.0 Unit mA mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 11. All loading with 50 W to VCC - 2.0 V. 12. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP451, MC100EP451
Table 9. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 13)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 14) Output LOW Voltage (Note 14) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 15) Input HIGH Current Input LOW Current 0.5 Min 85 -1145 -1945 -1225 -1945 VEE+2.0 Typ 105 -1020 -1820 Max 135 -895 -1695 -880 -1625 0.0 Min 85 -1145 -1945 -1225 -1945 VEE+2.0 25C Typ 105 -1020 -1820 Max 135 -895 -1695 -880 -1625 0.0 Min 85 -1145 -1945 -1225 -1945 VEE+2.0 85C Typ 105 -1020 -1820 Max 135 -895 -1695 -880 -1625 0.0 Unit mA mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 13. Input and output parameters vary 1:1 with VCC. 14. All loading with 50 W to VCC - 2.0 V. 15. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 10. AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 16)
-40C Symbol VOUTpp tPLH, tPHL tRR tS tH tPW tSKEW tJITTER tr tf Characteristic Output Voltage Amplitude @ 3 GHz (Figure 4) (Note 17) Propagation Delay to Output Differential Reset Recovery Setup Time Hold Time Minimum Pulse Rate Within-Device Skew (Note 18) Device-To-Device Skew (Note 19) CLOCK Random Jitter (RMS) @ v3.0 GHz (Figure 4) Output Rise/Fall Times (20% - 80%) Q, Q 100 100 CLK to Q, Q MR to Q, Q MR to CLK D to CLK CLK to D MR Min 540 330 430 240 80 80 400 20 35 0.2 150 150 40 100 1 250 250 110 110 Typ 670 430 530 145 40 40 530 630 Max Min 520 350 450 250 80 80 400 20 35 0.2 160 160 40 100 1 260 260 130 130 25C Typ 650 450 550 150 40 40 550 650 Max Min 450 390 490 260 80 80 400 20 35 0.2 180 180 40 100 1 280 280 ps ps 85C Typ 580 490 590 160 40 40 590 690 Max Unit GHz ps ps ps ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 16. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. 17. VOL and VOH specifications not guaranteed for Fmax testing. 18. Skew is measured between outputs under identical transitions and conditions on any one device. 19. Device-To-Device skew for identical transitions at identical VCC levels.
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MC10EP451, MC100EP451
900 800 VOUTpp (mV) 700 600 500 400 300 200 100 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 5V 3.3 V
FREQUENCY (MHz)
Figure 4. Fmax Typical
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 5. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
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MC10EP451, MC100EP451
ORDERING INFORMATION
Device MC10EP451FA MC10EP451FAG MC10EP451FAR2 MC10EP451FAR2G MC100EP451FA MC100EP451FAG MC100EP451FAR2 MC100EP451FAR2G MC10EP451MNG MC10EP451MNR4G MC100EP451MNG MC100EP451MNR4G QFN-32 (Pb-Free) Package LQFP-32 LQFP-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) Shipping 250 Units / Tray 250 Units / Tray 2000 / Tape & Reel 2000 / Tape & Reel 250 Units / Tray 250 Units / Tray 2000 / Tape & Reel 2000 / Tape & Reel 72 Units / Tray 1000 / Tape & Reel 72 Units / Tray 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1642/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC10EP451, MC100EP451
PACKAGE DIMENSIONS
LQFP-32 FA SUFFIX CASE 873A-02 ISSUE B
-T-, -U-, -Z- AE -U- V B1
8
A
32
4X 25
A1
0.20 (0.008) AB T-U Z
1
-T- B DETAIL Y
17
P AE DETAIL Y
V1
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC- 0.10 (0.004) AC
BASE METAL
N
F
D
8X
M_ R
J
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
0.20 (0.008)
M
AC T-U Z
CE
SECTION AE-AE
X DETAIL AD
GAUGE PLANE
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0.250 (0.010)
H
W
K
Q_
EE EE EE
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
MC10EP451, MC100EP451
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P CASE 488AM-01 ISSUE O
A B
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 --- --- 0.300 0.400 0.500
D
2X 2X
0.15 C 0.15 C 0.10 C
32 X
0.08 C L
32 X
8
1 32 32 X b 0.10 C A B 25
0.05 C BOTTOM VIEW
32 X
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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EE EE
TOP VIEW SIDE VIEW D2
9 16 17
PIN ONE LOCATION
E
(A3) A A1 C
EXPOSED PAD SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
K
32 X
SOLDERING FOOTPRINT*
5.30
E2 3.20
24 32 X
0.63 e 3.20 5.30
0.28
28 X
0.50 PITCH *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC10EP451/D

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