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MC100EP210S 2.5V 1:5 Dual Differential LVDS Compatible Clock Driver
The MC100EP210S is a low skew 1-to-5 dual differential driver, designed with LVDS clock distribution in mind. The LVDS or LVPECL input signals are differential and the signal is fanned out to five identical differential LVDS outputs. The EP210S specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. Two internal 50 W resistors are provided across the inputs. For LVDS inputs, VTA and VTB pins should be unconnected. For LVPECL inputs, VTA and VTB pins should be connected to the VTT (VCC-2.0 V) supply. Designers can take advantage of the EP210S performance to distribute low skew LVDS clocks across the backplane or the board. Special considerations are required for differential inputs under No Signal conditions to prevent instability.
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MC100 EP210S LQFP-32 FA SUFFIX CASE 873A AWLYYWW 32 1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week
* * * * * * * *
20 ps Typical Output-to-Output Skew 85 ps Typical Device-to-Device Skew 550 ps Typical Propagation Delay The 100 Series Contains Temperature Compensation Maximum Frequency > 1 GHz Typical Operating Range: VCC = 2.375 V to 2.625 V with VEE = 0 V Internal 50 W Input Termination Resistors LVDS Input/Output Compatible
*For additional information, refer to Application Note AND8002/D
ORDERING INFORMATION
Device MC100EP210SFA MC100EP210SFAR2 Package LQFP-32 Shipping 250 Units/Tray
LQFP-32 2000 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2002
1
May, 2002 - Rev. 5
Publication Order Number: MC100EP210S/D
MC100EP210S
Qa3 Qa3 Qa4 Qa4 Qb0 Qb0 Qb1 Qb1
24 VCC Qa2 Qa2 Qa1 Qa1 Qa0 Qa0 VCC 25 26 27 28 29 30 31 32 1
23
22
21
20
19
18
17 16 15 14 VCC
PIN DESCRIPTION
Qb2 Qb2 Qb3 Qb3 Qb4 Qb4 VCC PIN CLKn, CLKn Qn0:4, Qn0:4 VTA VTB VCC VEE FUNCTION LVDS, LVPECL CLK Inputs LVDS Outputs 50 Termination Resistors 50 Termination Resistors Positive Supply Ground
MC100EP210S
13 12 11 10 9
2
3
4
5
6
7
8
CLKa
CLKa
CLKb
VEE VTA
VTB
CLKb
VEE
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. 32-Lead LQFP Pinout (Top View)
VTA 50 W CLKa CLKa 50 W Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 Qa3 Qa3 Qa4 Qa4 CLKb CLKb 50 W VTB 50 W Qb0 Qb0 Qb1 Qb1 Qb2 Qb2 Qb3 Qb3 Qb4 Qb4
Figure 2. Logic Diagram
ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value N/A N/A > 2 kV > 100 V > 2 kV Level 2 UL-94 code V-0 A 1/8 28 to 34 461 Devices
Moisture Sensitivity (Note 1) Flammability Rating Oxygen Index Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer to Application Note AND8003/D.
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MC100EP210S
MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI Iout TA Tstg JA JC Tsol Power Supply Power Supply (GND) LVDS, LVDS LVPECL Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 LFPM 500 LFPM std bd < 2 to 3 sec @ 248C 32 LQFP 32 LQFP 32 LQFP Parameter Condition 1 VEE = 0 V VCC = 2.5 V VEE = 0 V Continuous Surge VI VCC Condition 2 Rating 6 -6 6 50 100 -40 to +85 -65 to +150 80 55 12 to 17 265 Units V V V mA mA C C C/W C/W C/W C
2. Maximum Ratings are those values beyond which device damage may occur.
DC CHARACTERISTICS VCC = 2.5 V, VEE = 0 V (Note 3)
-40C Symbol IEE VOH VOL VIHCMR RT IIH IIL NOTE: Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage Common Mode Range (Differential) (Note 5) Internal Termination Resistor Input HIGH Current Input LOW Current CLK CLK 0.5 -150 1250 800 1.2 43 Min Typ 150 1400 950 Max 200 1550 1100 2.5 57 150 0.5 -150 1250 800 1.2 43 50 Min 25C Typ 150 1400 950 Max 200 1550 1100 2.5 57 150 0.5 -150 1250 800 1.2 43 Min 85C Typ 150 1400 950 Max 200 1550 1100 2.5 57 150 Unit mA mV mV V W A A
100EP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. 4. All loading with 100 across LVDS differential outputs. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
AC CHARACTERISTICS VCC = 2.375 to 2.625 V, VEE = 0 V (Note 6)
-40C Symbol fmaxLVDS/
LVPECL
25C Max Min Typ >1 625 25 160 100 <1 1200 200 150 75 450 550 20 85 80 .2 800 150 650 25 160 100 <1 1200 225 150 80 475 Max Min
85C Typ >1 575 20 85 80 .2 800 160 675 35 160 100 <1 1200 230 Max Unit GHz ps ps
Characteristic Maximum Frequency (See Figure 3. Fmax/JITTER) Propagation Delay Within-Device Skew (Note 7) Device-to-Device Skew (Note 8) Duty Cycle Skew (Note 9) Cycle-to-Cycle Jitter (See Figure 3. Fmax/JITTER) Minimum Input Swing Output Rise/Fall Time (20%-80%)
Min
Typ >1
tPLH tPHL tskew
425
525 20 85 80 .2
tJITTER VPP tr/tf 6. 7. 8. 9.
ps mV ps
150 50
800 130
Measured with 400 mV source, 50% duty cycle clock source. All loading with 100 across differential outputs. Skew is measured between outputs under identical transitions of similar paths through a device. Device-to-Device skew for identical transitions at identical VCC levels. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
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MC100EP210S
450 400 350 VOUTpp (mV) 300 250 200 150 100 50 0 Simulated
9 8 7 6 5 4 3 2 (JITTER) 1 1400 JITTEROUT ps (RMS)
0
200
400
600
800
1000
1200
FREQUENCY (MHz)
Figure 3. Fmax/Jitter
Q Driver Device Q 100
D Recceiver Device D
Figure 4. Typical Termination for Output Driver and Device Evaluation
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EE EE EE
EEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEEEEEEEEEEE
MC100EP210S
PACKAGE DIMENSIONS
LQFP FA SUFFIX 32-LEAD PLASTIC PACKAGE CASE 873A-02 ISSUE A
A
32 4X 25
A1
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V P DETAIL Y
17
AE
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
8X
M_ R
CE
SECTION AE-AE
X DETAIL AD
GAUGE PLANE
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5
0.250 (0.010)
H
W
K
Q_
EE EE EE EE
N
F
D
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
-T-, -U-, -Z-
MC100EP210S
Notes
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MC100EP210S
Notes
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MC100EP210S
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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MC100EP210S/D

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