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IDTCV110L PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
IDTCV110L
FEATURES:
DESCRIPTION:
* One high precision PLL for CPU, SSC, and N programming * One high precision PLL for SRC/PCI/SATA, SSC, and N programming * One high precision PLL for 96MHz/48MHz * Band-gap circuit for differential outputs * Support spread spectrum modulation, down spread 0.5% * Support SMBus block read/write, index read/write * Selectable output strength for REF * Allows for CPU frequency to change to a higher frequency for maximum system computing power * Available in SSOP package
IDTCV110L is a 56 pin clock device. The CPU output buffer is designed to support up to 400MHz processor. This chip has three PLLs inside for CPU/ SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for Serial ATA clock provides high accuracy frequency. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Static PLL frequency divide error can be as low as 36 ppm, worse case 114 ppm, providing high accuracy output clock. Each CPU/SRC/PCI, SATA clock has its own Spread Spectrum selection, which allows for isolated changes instead of affecting other clock groups.
OUTPUTS:
* 2*0.7V current -mode differential CPU CLK pair * 6*0.7V current -mode differential SRC CLK pair, one dedicated for SATA * One CPU_ITP/SRC selectable CLK pair * 9*PCI, 3 free running, 33.3MHz * 1*96MHz, 1*48MHz * 1*REF
KEY SPECIFICATION:
* * * * *
CPU/SRC CLK cycle to cycle jitter < 85ps SATA CLK cycle to cycle jitter < 85ps PCI CLK cycle to cycle jitter < 250ps Static PLL frequency divide error < 114 ppm Static PLL frequency divide error for 48MHz < 5 ppm
FUNCTIONAL BLOCK DIAGRAM
PLL1 SSC N Programmable
CPU CLK Output Buffers Stop Logic
CPU[1:0]
X1
XTAL Osc Amp
CPU_ITP/SRC7 IREF REF ITP_EN
X2
SDATA SCLK SM Bus Controller PLL2 SSC N Programmable SRC CLK Output Buffer Stop Logic SRC[6:1]
PCI[5:0], PCIF[2:0] IREF VTT_PWRGD#/PD Control Logic FSA.B.C PLL3 48MHz/96MHz Output BUffer DOT96
48MHz
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
(c) 2004 Integrated Device Technology, Inc.
IDT CONFIDENTIAL
DECEMBER 2004
DSC-6534/5
IDTCV110L PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
VDD_PCI VSS_PCI
PCI3 PCI4 PCI5
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDDA Description 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage GND - 0.5 Storage Temperature Ambient Operating Temperature Case Temperature Input ESD Protection Human Body Model
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Min
Max 4.6 4.6 +150 +70 +115
Unit V V C C C V
1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8
5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9
PCI2
VDD TSTG TAMBIENT TCASE ESD Prot
PCI1 PCI0 FSC/TEST_SEL REF VSS_REF XTAL_IN XTAL_OUT VDD_REF SDA SCL VSS_CPU
CPU0 CPU0#
-65 0 2000
VSS_PCI VDD_PCI PCIF0/ITP_EN PCIF1
PCIF2
VDD48
USB48
VSS48
DOT96 DOT96#
VDD_CPU
CPU1 CPU1#
FSB/TEST_MODE VTT_PWRGD#/PD
FSA SRC1 SRC1#
IREF VSSA VDDA
CPU2_ITP/SRC7 CPU2_ITP#/SRC7#
VDD_SRC
SRC2 SRC2# SRC3 SRC3# SRC4 SRC4#
VDD_SRC
SRC6 SRC6# SRC5 SRC5#
VDD_SRC
VSS_SRC
SSOP TOP VIEW
FREQUENCY SELECTION TABLE
FSC, B, A 101 001 011 010 000 100 110 111 CPU 100 133 166 200 266 333 400 Reserve SRC[7:1] 100 100 100 100 100 100 100 100 PCI 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 2 USB 48 48 48 48 48 48 48 48 DOT 96 96 96 96 96 96 96 96 REF 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
IDT CONFIDENTIAL
IDTCV110L PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Name VDD_PCI VSS_PCI PCI3 PCI4 PCI5 VSS_PCI VDD_PCI PCIF0/ITP_EN PCIF1 PCIF2 VDD48 USB48 VSS48 DOT96 DOT96# FSB/TEST_MODE VTT_PWRGD#/PD FSA SRC1 SRC1# VDD_SRC SRC2 SRC2# SRC3 SRC3# SRC4 SRC4# VDD_SRC VSS_SRC SRC5# SRC5 SRC6# SRC6 VDD_SRC CPU2_ITP#/SRC7# CPU2_ITP/SRC7 VDDA VSSA IREF CPU1# CPU1 VDD_CPU Type PWR GND OUT OUT OUT GND PWR I/O OUT OUT PWR OUT GND OUT OUT IN IN IN OUT OUT PWR OUT OUT OUT OUT OUT OUT PWR GND OUT OUT OUT OUT PWR OUT OUT PWR GND OUT OUT OUT PWR 3.3V GND PCI clock PCI clock PCI clock GND 3.3V PCI clock, free running. CPU2 select (sampled on VTT_PWRGD# assertion) HIGH = CPU2. PCI clock, free running PCI clock, free running 3.3V 48MHz clock GND 96MHz 0.7 current mode differential clock output 96MHz 0.7 current mode differential clock output CPU frequency selection. Selects REF/N or Hi-Z when in test mode, Hi-Z = 1, REF/N = 0. Level-sensitive strobe used to latch the FSA, FSB, FSC/TEST_SEL, and PCIF0/ITP_EN inputs. After VTT_PWRGD# assertion, becomes a real-time input for asserting power down. (Active HIGH) CPU frequency selection Differential serial reference clock Differential serial reference clock 3.3V Differential serial reference clock Differential serial reference clock Differential serial reference clock Differential serial reference clock Differential serial reference clock Differential serial reference clock 3.3V GND Differential serial reference clock Differential serial reference clock Differential serial reference clock Differential serial reference clock 3.3V Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7#. Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7. 3.3V GND Reference current for differential output buffer Host 0.7 current mode differential clock output Host 0.7 current mode differential clock output 3.3V Description
IDT CONFIDENTIAL
3
IDTCV110L PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONT.)
Pin Number 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Name CPU0# CPU0 VSS_CPU SCL SDA VDD_REF XTAL_OUT XTAL_IN VSS_REF REF FSC/TEST_SEL PCI0 PCI1 PCI2 Type OUT OUT GND IN I/O PWR OUT IN GND OUT IN OUT OUT OUT Host 0.7 current mode differential clock output Host 0.7 current mode differential clock output GND SMBus clock SMBus data 3.3V XTAL output XTAL input GND 14.318 MHz reference clock output CPU frequency selection. Selects test mode if pulled to above 2V when VTT_PWRGD# is asserted LOW. PCI clock PCI clock PCI clock Description
INDEX BLOCK WRITE PROTOCOL
Bit 1 2-9 10 11-18 19 20-27 28 29-36 37 38-45 46 # of bits 1 8 1 8 1 8 1 8 1 8 1 From Master Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Master Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Byte count, N (0 is not valid) Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Nth data byte Acknowledge Stop
INDEX BLOCK READ PROTOCOL
Bit 1 2-9 10 11-18 19 20 21-28 29 30-37 38 39-46 47 48-55 # of bits 1 8 1 8 1 1 8 1 8 1 8 1 8 From Master Master Slave Master Slave Master Master Slave Slave Master Slave Master Slave
Master can stop reading any time by issuing the stop bit without waiting until Nth byte (byte count bit30-37).
Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Repeated Start D3h Ack (Acknowledge) Byte count, N (block read back of N bytes), power on is 8 Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Ack (Acknowledge) Nth data byte Not acknowledge Stop
Master Slave Master
INDEX BYTE WRITE
INDEX BYTE READ
Setting bit[11:18] = starting address, bit[20:27] = 01h.
Setting bit[11:18] = starting address. After reading back the first data byte, master issues Stop bit.
IDT CONFIDENTIAL
4
IDTCV110L PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
CONTROL REGISTERS
N PROGRAMMING PROCEDURE
* *
Use Index byte write. For N programming, the user only needs to access Byte17, Byte 25, and Byte8. 1. 2. 3. Write Byte17 for CPU PLL N, CPU f = N* Resolution, see resolution table below Byte17. Write Byte25 for SRC PLL N, SRC f = N*0.666667, PCI = SRC f /3, SATA f = SRC f. Enable N Programming bit, Byte8 bit1. Once this bit is enabled, any N value will be changed on the fly.
* * *
Center spread only works when the N Programming bit is enabled. Down spread is OK even N Programming bit is disabled It is OK to change N value to any value on the bench test board. In the system, IDT recommends the stepping change. It is unknown how much the system can sustain for each stepping change; the estimate is about 5. If the N changes too much in one step, the system will likely hang. Note that SATA is with SRC PLL. This SATA Hard Drive might not operate during SRC N programming.
Most of the Bytes, from Byte8-Byte31, are used to adjust output waveforms and SSC modulation profiles. The power on setting will be changed according to each power on frequency selection. To avoid mistakes, don't write on those byte (be careful about Block Write). It is suggested to use the Index Byte write to access bytes.
SSC MAGNITUDE CONTROL, SMC
SMC[2:0] 000 001 010 011 100 101 110 111 -0.25 -0.5 -0.75 -1 0.125 0.25 0.375 0.5
FREQUENCY SELECTION TABLE
FS_C, B, A 101 001 011 010 000 100 110 111 CPU 100 133 166 200 266 333 400 RESERVE
RESOLUTION
CPU (MHz) 100 133 166 200 266 333 400 Resolution 0.666667 0.666667 1.333333 1.333333 1.333333 2.666667 2.666667 N= 150 200 125 150 200 125 150
IDT CONFIDENTIAL
5
IDTCV110L PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 0
Bit 0 1 2 3 4 5 6 7 Output(s) Affected Reserve SRC1, SRC1# SRC2, SRC2# SRC3, SRC3# SRC4, SRC4# SRC5, SRC5# SRC6, SRC6# CPU2, CPU2#/ SRC7, SRC7# Output enable Output enable Output enable Output enable Output enable Output enable Output enable Tristate Tristate Tristate Tristate Tristate Tristate Tristate Enable Enable Enable Enable Enable Enable Enable RW RW RW RW RW RW RW 1 1 1 1 1 1 1 Description/Function 0 1 Type Power On
BYTE 1
Bit 0 1 2 3 4 5 6 7 Output(s) Affected CPU[2:0], SRC[7:1], PCI[5:0], PCIF[2:0] CPU0, CPU0# CPU1, CPU1# Reserve REF USB48 DOT96 PCIF0 Output enable Output enable Output enable Output enable Tristate Tristate Tristate Tristate Enable Enable Enable Enable RW RW RW RW Output enable Output enable Tristate Tristate Enable Enable RW RW 1 1 0 1 1 1 1 Description/Function Spread Spectrum mode enable 0 Spread off 1 Spread on Type RW Power On 0
BYTE 2
Bit 0 1 2 3 4 5 6 7 Output(s) Affected PCIF1 PCIF2 PCI0 PCI1 PCI2 PCI3 PCI4 PCI5 Description/Function Output enable Output enable Output enable Output enable Output enable Output enable Output enable Output enable 0 Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate 1 Enable Enable Enable Enable Enable Enable Enable Enable Type RW RW RW RW RW RW RW RW Power On 1 1 1 1 1 1 1 1
IDT CONFIDENTIAL
6
IDTCV110L PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 3
Bit 0 1 2 3 4 5 6 7 Output(s) Affected Reserve SRC1 SRC2 SRC3 SRC4 SRC5 SRC6 SRC7 Allow controlled by software PCI_STOP, byte 6, bit 3, assertion Allow controlled by software PCI_STOP, byte 6, bit 3, assertion Allow controlled by software PCI_STOP, byte 6, bit 3, assertion Allow controlled by software PCI_STOP, byte 6, bit 3, assertion Allow controlled by software PCI_STOP, byte 6, bit 3, assertion Allow controlled by software PCI_STOP, byte 6, bit 3, assertion Allow controlled by software PCI_STOP, byte 6, bit 3, assertion Free running, not affected by PCI_STOP Free running, not affected by PCI_STOP Free running, not affected by PCI_STOP Free running, not affected by PCI_STOP Free running, not affected by PCI_STOP Free running, not affected by PCI_STOP Free running, not affected by PCI_STOP Stopped with PCI_STOP Stopped with PCI_STOP Stopped with PCI_STOP Stopped with PCI_STOP Stopped with PCI_STOP Stopped with PCI_STOP Stopped with PCI_STOP RW RW RW RW RW RW RW 0 0 0 0 0 0 0 Description / Function 0 1 Type Power On
BYTE 4
Bit 0 1 2 3 4 5 6 7 Output(s) Affected Reserve Reserve Reserve PCIF0 PCIF1 PCIF2 DOT96 Reserve Allow controlled by software PCI_STOP, byte 6, bit 3, assertion Allow controlled by software PCI_STOP, byte 6, bit 3, assertion Allow controlled by software PCI_STOP, byte 6, bit 3, assertion DOT96 power down drive mode Not stopped by PCI_STOP Not stopped by PCI_STOP Not stopped by PCI_STOP Driven in power down Stopped with PCI_STOP Stopped with PCI_STOP Stopped with PCI_STOP Tristate RW 0 0 RW 0 RW 0 Description / Function 0 1 Type RW RW RW RW Power On 1 1 1 0
BYTE 5
Bit 0 1 2 3 4 5 6 7 Output(s) Affected CPU0, CPU0# CPU1, CPU1# CPU2, CPU2# SRC[7:1], SRC[7:1]# Reserve Reserve Reserve SRC[7:1], SRC[7:1]# SRC PCI_STOP drive mode 7 Driven in PCI_STOP Tristate when stopped RW Description / Function CPU0 PWRDWN drive mode CPU1 PWRDWN drive mode CPU2 PWRDWN drive mode SRC PWRDWN drive mode 0 Driven in power down Driven in power down Driven in power down Driven in power down 1 Tristate in power down Tristate in power down Tristate in power down Tristate in power down Type RW RW RW RW Power On 0 0 0 0 0 0 0 0
IDT CONFIDENTIAL
IDTCV110L PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 6
Bit 0 1 2 3 Output(s) Affected CPU[2:0] CPU[2:0] CPU[2:0] PCI, SRC Description / Function FSA latched value on power up FSB latched value on power up FSC latched value on power up Software PCI_STOP control for PCI and SRC CLK REF drive strength Test clock mode entry control CPU, SRC, PCI PCIF, REF, USB48, DOT96 Only valid when Byte 6, Bit 7 is HIGH Stop all PCI, PCIF, and SRC which can be stopped by PCI_STOP# 1x drive Normal operation Hi-Z Software STOP Disabled 2x drive Test mode, controlled by Byte 6, Bit 7 7 REF/N 0 RW 0 1 Type R R R RW 1 Power On
4 5 6
REF Reserve
1 0 0
BYTE 7
Bit 0 1 2 3 4 5 6 7 Output(s) Affected Description / Function Vendor ID Vendor ID Vendor ID Vendor ID Revision ID Revision ID Revision ID Revision ID 0 1 Type R R R R R R R R Power On 1 0 1 0 0 1 1 0
BYTE 8
Bit 0 1 2 3 4 5 6 7 Output(s) Affected One cycle read N Programming enable Reserve USB48 USB 48 Strength control USB PLL power down SRC PLL power down CPU PLL power down Only valid when Byte1 bit0 is 1 Description / Function 0 disable Disable 1x normal normal normal disable 1 enable enable 2x Power down Power down Power down enable Type RW RW RW RW RW RW RW RW Power On 0 0 0 0 0 0 0 1
SRC, PLL2, SSC enable
IDT CONFIDENTIAL
8
IDTCV110L PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 9
Bit 0 1 2 3 4 5 6 7 Output(s) Affected SRC SMC0 SRC SMC1 SRC SMC2 Reserve CPU SMC0 CPU SMC1 CPU SMC2 Description / Function SRC/PCI SSC control see SMC table 0 1 Type RW RW RW RW RW RW RW RW Power On 1 0 0 0 1 0 0 0 (Must be 0)
CPU PLL SSC control see SMC table Must be 0 Must be 0
BYTES 10-16: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER.
BYTE 17
Bit 0 1 2 3 4 5 6 7 Output(s) Affected CPU_N0, LSB CPU_N1 CPU_N2 CPU_N3 CPU_N4 CPU_N5 CPU_N6 CPU_N7, MSB Description / Function CPU CLK = N* Resolution see Resolution table 0 1 Type RW RW RW RW RW RW RW RW Power On
BYTES 18-24: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER. BYTE 25
Bit 0 1 2 3 4 5 6 7 Output(s) Affected SRC_N0, LSB SRC_N1 SRC_N2 SRC_N3 SRC_N4 SRC_N5 SRC_N6 SRC_N7, MSB Description / Function SRC f = N*SRC Resolution Resolution = 0.666667 100MHz N= 150 0 1 Type RW RW RW RW RW RW RW RW Power On
BYTES 26-31: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER.
IDT CONFIDENTIAL
9
IDTCV110L PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
APPLICATION NOTE
Bits 111 011 001 000 Strength 0.6x 0.8x 1x 1.2x
Byte 18, bit[2:0] controls PCIF[2:0] strength. Byte 26, bit[2:0] controls PCI[5:0] strength. Byte 27, Byte 28 controls the magnitude of the SRC spread. (1) Byte 30, Byte 31 sets the center of the frequency of the SRC. (1) Byte 23, bit[3:0] controls the CPU PLL spread.
NOTE: 1. Write byte 9 prior to Bytes 27, 28, 30, and 31.
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT PARAMETERS
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%
Symbol VIH VIL VIH_FS VIL_FS IIL IDD3.3OP IDD3.3PD FI LPIN CIN COUT CINX TSTAB Clock Stabilization(2,3) Modulation Frequency(2) TDRIVE_PD(2) TFALL_PD(2) TRISE_PD(3) Input Capacitance(2) Parameter Input HIGH Voltage Input LOW Voltage LOW Voltage, HIGH Threshold LOW Voltage, LOW Threshold Input LeakageCurrent Operating Supply Current Powerdown Current Input Frequency(1) Pin Inductance(2) Logic inputs Output pin capacitance X1 and X2 pins From VDD power-up or de-assertion of PD to first clock Triangular modulation CPU output enable after PD de-assertion Fall time of PD Rise time of PD 3.3V 5% 3.3V 5% For FSA.B.C test_mode For FSA.B.C test_mode 0< VIN < VDD, no internal pull-up or pull-down Full active, CL = full load All differential pairs driven All differential pairs tri-stated VDD = 3.3V Test Conditions Min. 2 VSS - 0.3 0.7 VSS - 0.3 -5 -- -- -- -- -- -- -- -- -- 30 -- -- -- Typ. -- -- -- -- -- -- -- -- 14.31818 -- -- -- -- -- -- -- -- -- Max. VDD + 0.3 0.8 VDD + 0.3 0.35 +5 400 70 12 -- 7 5 6 5 1.8 33 300 5 5 ms KHz us ns ns pF MHz nH Unit V V V V mA mA mA
NOTES: 1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 2. This parameter is guaranteed by design, but not 100% production tested. 3. See TIMING DIAGRAMS for timing requirements.
IDT CONFIDENTIAL
10
IDTCV110L PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE DIFFERENTIAL PAIR(1)
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 2pF
Symbol ZO VOH3 VOL3 VHIGH VLOW VOVS VUDS VCROSS(ABS) d - VCROSS ppm Parameter Current Source Output Impedance(2) Output HIGH Voltage Output LOW Voltage Voltage HIGH(2) Voltage LOW(2) Max Voltage(2) Min Voltage(2) Crossing Voltage (abs)(2) Crossing Voltage (var)(2) Long Accuracy(2,3)
Variation of crossing over all edges
Test Conditions VO = VX IOH = -1mA IOL = 1mA Statistical measurement on single-ended signal using oscilloscope math function Measurement on single-ended signal using absolute value
Min. 3000 2.4 -- 660 -300 -- -300 250 -- -300 2.4993 2.9991 3.7489 4.9985 5.9982 7.4978 9.997 10.4135 2.4143 2.9141 3.6639 4.9135 5.9132 7.4128 9.912 10.1635 175 175 -- --
Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max. -- -- 0.4 1150 150 1150 -- 550 140 300 2.5133 3.016 3.77 5.0266 6.032 7.54 10.0533 10.4198 -- -- -- -- -- -- -- -- 700 700 125 125 55
Unit V V mV mV mV mV ppm
See TPERIOD Min. - Max. values 400MHz nominal / -0.5% spread 333.33MHz nominal / -0.5% spread 266.66MHz nominal / -0.5% spread
TPERIOD
Average Period(3)
200MHz nominal / -0.5% spread 166.66MHz nominal / -0.5% spread 133.33MHz nominal / -0.5% spread 100MHz nominal / -0.5% spread 96MHz nominal 400MHz nominal / -0.5% spread 333.33MHz nominal / -0.5% spread 266.66MHz nominal / -0.5% spread 200MHz nominal / -0.5% spread 166.66MHz nominal / -0.5% spread 133.33MHz nominal / -0.5% spread 100MHz nominal / -0.5% spread 96MHz nominal
ns
TABSMIN
Absolute Min Period(2,3)
ns
tR tF d-tR d-tF dT3
Rise Time(2) Fall Time(2) Rise Time Variation(2) Fall Time Variation(2) Duty Cycle(2)
VOL = 0.175V, VOH = 0.525V VOL = 0.175V, VOH = 0.525V
ps ps ps ps %
Measurement from differential waveform
45
NOTES: 1. SRC clock outputs run only at 100MHz. 2. This parameter is guaranteed by design, but not 100% production tested. 3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
IDT CONFIDENTIAL
11
IDTCV110L PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE DIFFERENTIAL PAIR, CONTINUED(1)
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 2pF
Symbol tSK3 Parameter Skew, CPU[1:0](2) Skew, CPU2(2) Skew, tJCYC-CYC SRC(2) Measurement from differential waveform Jitter, Cycle to Cycle, CPU[1:0](2) Jitter, Cycle to Cycle, CPU2(2) Jitter, Cycle to Cycle, SRC(2) Jitter, Cycle to Cycle, DOT96(2)
NOTES: 1. SRC clock outputs run only at 100MHz. 2. This parameter is guaranteed by design, but not 100% production tested.
Test Conditions VT = 50%
Min. -- -- -- -- -- -- --
Typ. -- -- -- -- -- -- --
Max. 100 250 250 85 100 125 250
Unit ps
ps
ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 10 - 30pF
Symbol ppm TPERIOD VOH VOL IOH IOL Parameter Static Error(1,2) Clock Period(2) Output HIGH Voltage Output LOW Voltage Output HIGH Current Output LOW Current Edge Rate(1) Edge Rate(1) tR1 tF1 dT1 tSK1 tJCYC-CYC Rise Time(1) Fall Time(1) Duty Cycle(1) Cycle(1) Skew(1) Jitter, Cycle to Test Conditions See Tperiod Min. - Max. values 33.33MHz output nominal 33.33MHz output spread IOH = -1mA IOL = 1mA VOH at Min. = 1V VOH at Max. = 3.135V VOL at Min. = 1.95V VOL at Max. = 0.4V Rising edge rate Falling edge rate VOL = 0.8V, VOH = 2V VOL = 0.8V, VOH = 2V VT = 1.5V VT = 1.5V VT = 1.5V Min. -- 29.991 29.991 2.4 -- -33 -- 30 -- 1 1 0.3 0.3 45 -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 0 30.009 30.1598 -- 0.55 -- -33 -- 38 4 4 1.2 1.2 55 500 500 V/ns V/ns ns ns % ps ps mA V V mA Unit ppm ns
NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
IDT CONFIDENTIAL
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IDTCV110L PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS, 48MHZ, USB
Symbol ppm TPERIOD VOH VOL IOH IOL Parameter Static Error(1,2) Clock Period(2) Output HIGH Voltage Output LOW Voltage Output HIGH Current Output LOW Current Edge Rate(1) Edge Rate(1) tR1 tF1 dT1 tJCYC-CYC Rise Time(1) Fall Time(1) Duty Cycle(1) Jitter, Cycle to Cycle Test Conditions See Tperiod Min. - Max. values 48MHz output nominal IOH = -1mA IOL = 1mA VOH at Min. = 1V VOH at Max. = 3.135V VOL at Min. = 1.95V VOL at Max. = 0.4V Rising edge rate Falling edge rate VOL = 0.8V, VOH = 2V VOL = 0.8V, VOH = 2V VT = 1.5V
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 10 - 20pF
Min. -- 20.8257 2.4 -- -29 -- 29 -- 1 1 0.5 0.5 45 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 0 20.834 -- 0.55 -- -23 -- 27 2 2 1.2 1.2 55 350 V/ns V/ns ns ns % ps mA Unit ppm ns V V mA
NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICAL CHARACTERISTICS - REF-14.318MHZ
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 10 - 20pF
Symbol ppm TPERIOD VOH VOL IOH IOL Parameter Long Accuracy(1) Clock Period Output HIGH Voltage(1) Output LOW Voltage(1) Output HIGH Current Output LOW Current Edge Rate(1) Edge Rate(1) tR1 tF1 dT1 tJCYC-CYC Rise Time(1) Fall Time(1) Duty Cycle(1) Cycle(1) Jitter, Cycle to Test Conditions See Tperiod Min. - Max. values 14.318MHz output nominal IOH = -1mA IOL = 1mA VOH at Min. = 1V VOH at Max. = 3.135V VOL at Min. = 1.95V VOL at Max. = 0.4V Rising edge rate Falling edge rate VOL = 0.8V, VOH = 2V VOL = 0.8V, VOH = 2V VT = 1.5V VT = 1.5V Min. -- 69.827 2.4 -- -33 -- 30 -- 1 1 0.3 0.3 45 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 0 69.855 -- 0.4 -- -33 -- 38 4 4 1.2 1.2 55 1000 V/ns V/ns ns ns % ps mA Unit ppm ns V V mA
NOTE: 1. This parameter is guaranteed by design, but not 100% production tested.
IDT CONFIDENTIAL
13
IDTCV110L PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PCI STOP FUNCTIONALITY
PCI_STOP (Byte 6 bit 3) 1 0 CPU Normal Normal CPU# Normal Normal
If PCIF (2:0) and SRC clocks are set to be free-running through SMBus programming, they will ignore the PCI_STOP register bit.
SRC Normal IREF * 6 or float SRC# Normal Low PCIF/PCI 33MHz Low USB 48MHz 48MHz DOT96 Normal Normal DOT96# Normal Normal REF 14.318MHz 14.318MHz
PD is an asynchronous active high input used to shut off all clocks cleanly prior to clock power. When PD is asserted high all clocks will be driven low before turning off the VCO. In PD de-assertion all clocks will start without glitches.
PD, POWER DOWN
PD 0 1
CPU Normal IREF * 2 or float
CPU# Normal Float
SRC Normal IREF * 2 or float
SRC# Normal Float
PCIF/PCI 33MHz Low
USB 48MHz Low
DOT96 Normal IREF * 2 or float
DOT96# Normal Float
REF 14.318MHz Low
PD ASSERTION
PD
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
IDT CONFIDENTIAL
14
IDTCV110L PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PD DE-ASSERTION
The time from the de-assertion of PD or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD tristate is programmed to `1' the stopped differential pair must first be driven high to a minimum of 200mV in less than 300s of PD deassertion.
tSTAB <1.8mS PD
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818 tDRIVE_PD <300S, <200mV
IDT CONFIDENTIAL
15
IDTCV110L PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
XXX IDTCV Device Type XX Package X Grade Blank Commercial Temperature Range (0C to +70C) Small Shrink Outline Package SSOP - Green Programmable FlexPCTM Clock for P4 Processor
PV PVG 110L
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
IDT CONFIDENTIAL
16

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