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| ICS672-01/02 QuadraClockTM Quadrature Delay Buffer Description The ICS672-01 and ICS672-02 are zero delay buffers that generate four output clocks whose phases are spaced at 90 intervals. Based on ICS' proprietary low jitter Phase Locked Loop (PLL) techniques, each device provides five low skew outputs, with clock rates up to 84 MHz for the ICS672-01 and up to 135 MHz for the ICS672-02. By providing outputs delayed one quarter clock cycle, the device is useful for systems requiring early or late clocks. The ICS672-01/02 include multiplier selections of x0.5, x1, x2, x3, x4, x5, or x6. They also offer a mode to power down all internal circuitry and tri state the outputs. In normal operation, output clock FBCLK is tied to the FBIN pin. ICS manufactures the largest variety of clock generators and buffers, and is the largest clock supplier in the world. Features * Packaged in 16 pin narrow SOIC * Input clock range from 10 MHz to 150 MHz * Clock outputs from up to 84 MHz (ICS672-01) and up to 135 MHz (ICS672-02) * Zero input-output delay * Integrated x0.5, x1, x2, x3, x4, x5, or x6 selections * Four accurate (<250 ps) outputs with 0, 90, 180, and 270 phase shift from ICLK, and one FBCLK (0) * Separate supply for output clocks from 2.5V to 5V * Full CMOS outputs (TTL compatible) * Tri state mode for board-level testing * Includes Power Down for power savings * Advanced, low power, sub-micron CMOS process * 3.3 V to 5 V operating voltage * Industrial temperature version available Block Diagram VDD 2 GND 3 VDDIO CLK0 IN FBIN PLL Multiplier and Quadrature Generation CLK90 CLK180 CLK270 CLKFB 3 Control Logic S2:S0 Power Down + Tri-State External Feedback 1 Revision 112200 Integrated Circuit Systems, Inc.* 525 Race Street * San Jose *CA*95126* (408) 295-9800 tel * www.icst.com MDS 672-01/02 C ICS672-01/02 QuadraClockTM Quadrature Delay Buffer Pin Assignment ICS672-01/02 ICLK CLK90 CLK180 CLK270 VDDIO GND GND S0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FBIN FBCLK CLK0 VDD GND VDD S2 S1 Output Clock Mode Select Table S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Output Clocks Power Down + Tri State x1 x2 x3 x4 x5 x6 x0.5 16 pin narrow (150 mil) SOIC Pin Descriptions Number 1 2 3 4 5 6, 7, 12 8 9 10 11, 13 14 15 16 Name ICLK CLK90 CLK180 CLK270 VDDIO GND S0 S1 S2 VDD CLK0 FBCLK FBIN Type I O O O P P I I I P O O I Description Clock Input. Clock Output (90 delayed from CLK0). Clock Output (180 delayed from CLK0). Clock Output (270 delayed from CLK0). Supply voltage for input and output clocks. Must not exceed VDD. Connect to ground. Select input 0. See table above. Select input 1. See table above. Select input 2. See table above. Connect to +3.3 V or +5.0 V. Clock Output phase aligned to ICLK. Feedback Clock Output (0 phase shift from CLK0). Feedback Clock Input. In normal operation, connect to FBCLK Key: I = Input; O = output; P = power supply connection. External Components The ICS672-01/01 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.01F should be connected between VDD and GND on pins 11 and 12, VDD and GND on pins 13 and 12, and VDDIO and GND on pins 5 and 6, as close to the device as possible. A series termination resistor of 33 may be used close to each clock output pin to reduce reflections. 2 Revision 112200 Integrated Circuit Systems, Inc.* 525 Race Street * San Jose *CA*95126* (408) 295-9800 tel * www.icst.com MDS 672-01/02 C ICS672-01/02 QuadraClockTM Quadrature Delay Buffer Operation and Applications The ICS672-01/02 each provide a total of five output clocks with multiple phase shifts relative to the input clock (ICLK). Phase shifts of 0 (CLK0), 90 (CLK90), 180 (CLK180), and 270 (CLK270) are provided, plus one feedback clock (FBCLK). All output clocks will be a multiple of the input clock, as determined by the table on page 2. Refer to the illustrations in Figure 1 and Figure 2. FBCLK is connected to the feedback input (FBIN) to provide a zero delay through the ICS672-01/02. FBCLK has a 0 phase shift from ICLK. ICLK CLK0, FBCLK CLK90 CLK180 CLK270 Figure 1. Phase alignment of input and output clocks. (x1 multiplier) ICLK CLK0, FBCLK CLK90 CLK180 CLK270 Figure 2. Phase alignment of input and output clocks. (x2 multiplier) 3 Revision 112200 Integrated Circuit Systems, Inc.* 525 Race Street * San Jose *CA*95126* (408) 295-9800 tel * www.icst.com MDS 672-01/02 C ICS672-01/02 QuadraClockTM Quadrature Delay Buffer Electrical Specifications Parameter Supply voltage, VDD & VDDIO Inputs and Clock Outputs Electrostatic Discharge Ambient Operating Temperature Ambient Operating Temperature, Industrial Soldering Temperature Junction temperature Storage temperature Operating Voltage, VDD Operating Voltage, VDDIO Input High Voltage, VIH, ICLK only Input Low Voltage, VIL, ICLK only Input High Voltage, VIH Input Low Voltage, VIL Output High Voltage, VOH Output Low Voltage, VOL Output High Voltage, VOH, CMOS level Operating Supply Current, IDD (Note 2) Operating Supply Current, IDD (Note 3) Short Circuit Current Input Capacitance Input Clock Frequency Output Clock Frequency Output Clock Frequency Output Clock Rise Time, CL = 15 pF Output Clock Fall Time, CL = 15 pF Output Clock Duty Cycle, VDDIO=3.3V Phased Outputs Accuracy (Note 4) Input to Output Skew, ICLK to CLK0 (Note 5) Maximum Absolute Jitter Cycle to Cycle Jitter, 15 pF loads Notes: Conditions Referenced to GND Referenced to GND MIL-STD-883 Available on -02 only Max of 10 seconds Minimum -0.5 -0.5 2000 0 -40 Typical Maximum 7 VDD+0.5 70 85 260 150 150 5.50 VDD VDD/2-1 2 0.8 IOH=-12 mA 2.4 IOL=12 mA IOH=-8mA VDDIO-0.4 No Load, S1=1, S0=0, S2=0 No Load, S1=1, S0=0, S2=0 Each output 0.4 11 22 50 7 150 84 135 1.5 1.5 55 250 300 Units V V V C C C C C V V V V V V V V V mA mA mA pF MHz MHz MHz ns ns % ps ps ps ps ABSOLUTE MAXIMUM RATINGS (note 1) -65 3.13 2.375 VDD/2+1 DC CHARACTERISTICS (VDD =VDDIO = 3.3 V unless specified otherwise) AC CHARACTERISTICS (VDD = VDDIO = 3.3 V unless specified otherwise) ICS672-01 ICS672-02 0.8 to 2.0V 2.0 to 0.8V At VDDIO/2 rising edges at VDDIO/2 15 15 15 45 -250 -300 50 75 150 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. 2. With ICLK = 20 MHz, FBCLK to FBIN, all outputs at 40 MHz. 3. With ICLK = 66.5 MHz, FBCLK to FBIN, all outputs at 133 MHz. 4. With CLK0:CLK270 equally loaded, and output frequency > 60 MHz. 5. Rising edge of ICLK compared with rising edge of CLK0, with FBCLK connected to FBIN, 15 pF load on CLK0, and CLK0 > 60 MHz. 4 Revision 112200 Integrated Circuit Systems, Inc.* 525 Race Street * San Jose *CA*95126* (408) 295-9800 tel * www.icst.com MDS 672-01/02 C ICS672-01/02 QuadraClockTM Quadrature Delay Buffer Package Outline and Package Dimensions (For current dimensional specifications, see JEDEC Publication No. 95.) 16 pin SOIC narrow Symbol A A1 E INDEX AREA H B C 1 2 D A1 e Ordering Information Part/Order Number ICS672M-01 ICS672M-01T ICS672M-02 ICS672M-02T ICS672M-02I ICS672M-02IT h x 45 A L D E e H h L Inches Min Max 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.3859 0.3937 0.1497 0.1574 .050 BSC 0.2284 0.2440 0.0099 0.0195 0.0160 0.0500 Millimeters Min Max 1.35 1.75 0.10 0.24 0.33 0.51 0.19 0.24 9.80 10.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.41 1.27 B C Marking ICS672M-01 ICS672M-01 ICS672M-02 ICS672M-02 ICS672M-02I ICS672M-02I Shipping packaging tubes tape and reel tubes tape and reel tubes tape and reel Package 16 pin SOIC 16 pin SOIC 16 pin SOIC 16 pin SOIC 16 pin SOIC 16 pin SOIC Temperature 0 to 70 C 0 to 70 C 0 to 70 C 0 to 70 C -40 to 85 C -40 to 85 C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 5 Revision 112200 Integrated Circuit Systems, Inc.* 525 Race Street * San Jose *CA*95126* (408) 295-9800 tel * www.icst.com MDS 672-01/02 C |
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