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ISL59483
Data Sheet December 22, 2006 FN6394.1
Dual, 500MHz Triple, Multiplexing Amplifiers
The ISL59483 contains a gain of 1 triple 4:1 MUX amplifier (MUX1), and a second gain of 2 triple 4:1 MUX amplifier (MUX2). Each feature high slew rate and excellent bandwidth for RGB video switching. They contain separate binary coded, channel select logic inputs (S0, S1), and separate logic inputs for High Impedance output (HIZ) and power-down (EN) modes. The HIZ state presents a high impedance at the output so that both RGB MUX outputs can be wired together to form an 8:1 RGB MUX amplifier or they can be used in R-R, G-G, and B-B pairs to form a 4:1 differential input/output MUX. Separate power-down mode controls (EN1, EN2) are included to turn off unneeded circuitry in power sensitive applications. With both EN pins pulled high, the ISL59483 enters a standby power mode, consuming just 36mW.
Features
* Separate gain of 1 and gain of 2, triple 4:1 multiplexers for RGB * Externally configurable for various video MUX circuits including - 8:1 RGB MUX with selectable gains of 1 or 2 - Two separate 4:1 RGB MUX with gains of 1 and 2 * High impedance outputs (HIZ) * Power-down mode (EN) * 5V operation * 870V/s slew rate (G = 1), 1600V/s slew rate (G = 2) * 500MHz bandwidth * Supply current 16mA/CH * Pb-free plus anneal (RoHS compliant)
Ordering Information
PART NUMBER (Note) ISL59483IRZ PART MARKING ISL59483 IRZ TAPE & REEL 13" PACKAGE (Pb-free) PKG. DWG. #
Applications
* HDTV/DTV analog inputs * Video projectors * Computer monitors * Set-top boxes * Security video * Broadcast video equipment
48 Ld Exposed L48.7x7B Pad 7x7 QFN 48 Ld Exposed L48.7x7B Pad 7x7 QFN
ISL59483IRZ-T13 ISL59483 IRZ
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
TABLE 1. CHANNEL SELECT LOGIC TABLE ISL59483 S1-1, 2 0 0 1 1 X X S0-1, 2 0 1 0 1 X X EN1, EN2 0 0 0 0 1 0 HIZ1, 2 0 0 0 0 X 1 OUTPUT1, 2 IN0 (A, B, C) IN1 (A, B, C) IN2 (A, B, C) IN3 (A, B, C) Power-down High Z
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL59483 Pinout
ISL59483 (48 LD QFN) TOP VIEW
46 IN3C1 45 IN3B1 44 IN3A1 37 IN1B1 36 IN2A2
0
42 IN2C1
41 IN2B1
40 IN2A1
OUTC1 1 OUTB1 2
+1
38 INIC1
43 GND
39 GND
48 S0-1
47 S1-1
35 GND +1
0
V1- 3 OUTA1 4 V1+ 5 EN1 6 HIZ1 7 IN0C1 8 IN0B1 9 IN0A1 10 GND 11 IN1A1B 12 +1
34 IN1C2 33 IN1B2
0
32 IN1A2 THERMAL PAD 31 GND 30 IN0A2 29 IN0B2 28 IN0C2 27 HIZ2
0 0 0
26 EN2 25 V2+
+2
+2
+2
S1-2 19
S0-2 20
OUTC2 21
OUTB2 22
V2- 23
THERMAL PAD INTERNALLY CONNECTED TO VPAD MUST BE TIED TO V-
Functional Diagram ISL59483
EN0-1 S0-1 EN1-1 S1-1 DECODE1 EN2-1 IN0(A1, B1, C1) IN1(A1, B1, C1) IN2(A1, B1, C1) IN3(A1, B1, C1) EN3-1 AMPLIFIER1 BIAS HIZ1 EN1 EN0-2 S0-2 EN1-2 S1-2 DECODE2 EN2-2 IN0(A2, B2, C2) IN1(A2, B2, C2) IN2(A2, B2, C2) IN3(A2, B2, C2) EN3-2 AMPLIFIER2 BIAS HIZ2 EN2 OUT(A2, B2, C2) x2 x1 OUT(A1, B1, C1)
2
OUTA2 24
IN2B2 13
IN2C2 14
GND 15
IN3A2 16
IN3B2 17
IN3C2 18
FN6394.1 December 22, 2006
ISL59483
Absolute Maximum Ratings (TA = +25C)
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/s Digital and Analog Input Current (Note 1) . . . . . . . . . . . . . . . . 50mA Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Information
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . .-40C to +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values. 2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER GENERAL
V1+ = V2+ = +5V, V1- = V2- = -5V, GND = 0V, TA = +25C, Input Video = 1VP-P and RL = 500 to GND, CL = 5pF unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT
+IS Enabled -IS Enabled
+IS Disabled -IS Disabled VOUT
Enabled Supply Current Enabled Supply Curren Disabled Supply Current Disabled Supply Current
No load, VIN = 0V, EN1, EN2 Low No load, VIN = 0V, EN1, EN2 Low No load, VIN = 0V, EN1, EN2 High No load, VIN = 0V, EN1, EN2 High
75 -96 4 -200 3.1 3.8 80 -10 -60 -10
92 -87 6.5 -10 3.4 4.0 125 2 -25 -2 1.2
100 -68 8
mA mA A A |V|
MUX1: Positive and Negative Output Swing VIN = 3.5V, RL = 500 MUX2: Positive and Negative Output Swing VIN = 2.5V; RL = 500
4.2
|V| |mA|
IOUT VOS
Output Current MUX1: Output Offset Voltage MUX2: Output Offset Voltage
RL = 10 to GND VIN = 0V VIN = 0V VIN = 0V HIZ = Logic High HIZ = Logic High HIZ = Logic Low VIN = 3.5V VIN = 1.5V, RL= 500 VIN = 1.5V, RL= 500 VOUT = 0V
14 20 +10
mV mV A M
Ib ROUT
Input Bias Current MUX1: HIZ Output Resistance MUX2: HIZ Output Resistance
700
1000 0.1 10
1300
M
ROUT RIN ACL or AV
Enabled Output Resistance Input Resistance MUX1: Voltage Gain MUX2: Voltage Gain
0.98 1.94
0.99 1.99 -9
1.02 2.04
V/V V/V A
IHIZ LOGIC VIH VIL IIH IIL
MUX1: Output Current in High Impedance State
Input High Voltage (Logic Inputs) Input Low Voltage (Logic Inputs) Input High Current (Logic Inputs) Input Low Current (Logic Inputs) VH = 5V VL = 0V
2 0.8 200 -10 270 -1 320 +10
V V A A
3
FN6394.1 December 22, 2006
ISL59483
Electrical Specifications
PARAMETER AC GENERAL PSRR MUX1: Power Supply Rejection Ratio MUX2: Power Supply Rejection Ratio ISO dG Channel Isolation MUX1: Differential Gain Error MUX2: Differential Gain Error dP MUX1: Differential Phase Error MUX2: Differential Phase Error BW FBW Small Signal -3dB Bandwidth MUX1: 0.1dB Bandwidth DC, PSRR V+ and V- combined DC, PSRR V+ and V- combined f = 10MHz, Ch-Ch X-Talk and Off Isolation, CL = 1.5pF NTC-7, RL = 150, CL = 1.5pF NTC-7, RL = 150, CL = 1.2pF NTC-7, RL = 150, CL = 1.5pF NTC-7, RL = 150, CL = 1.2pF VOUT = 0.2VP-P; CL = 1.5pF RL =500 CL = 1.5pF RL = 500 CL = 4.7pF RL = 500 FBW MUX2: 0.1dB Bandwidth CL = 1.1pF RL = 500 CL = 1.1pF RL = 150 SR MUX1: Slew Rate MUX2: Slew Rate SWITCHING CHARACTERISTICS VGLITCH MUX1: Channel-to-Channel Switching Glitch EN Switching Glitch HIZ Switching Glitch VGLITCH MUX2: Channel-to-Channel Switching Glitch EN Switching Glitch HIZ Switching Glitch tSW-L-H tSW-H-L tr, tf Channel Switching Time Low to High Channel Switching Time High to Low Rise and Fall Time VIN = 0V CL = 1.2pF VIN = 0V CL = 1.2pF VIN = 0V CL = 1.2pF VIN = 0V, RL = 150; CL = 2.1pF VIN = 0V, RL = 150; CL = 2.1pF VIN = 0V, RL = 150; CL = 2.1pF 1.2V logic threshold to 10% movement of analog output 1.2V logic threshold to 10% movement of analog output 10% to 90%; VIN = 1V RL =500 CL = 1.2pF 10% to 90%; VIN = 0.1V RL=500 CL=1.2pF ts tpd 0.1% Settling Time Propagation Delay VIN = 1V RL = 500 CL = 1.2pF 10% to 10% 40 300 200 15 1800 340 22 25 1.2 0.7 22 0.73 mVP-P mVP-P mVP-P mVP-P mVP-P mVP-P ns ns ns ns ns ns 25% to 75%, RL = 150, Input Enabled, CL = 1.5pF 25% to 75%, RL = 150, Input Enabled, CL = 1.5pF 52 45 56 53 75 0.02 0.008 0.02 0.01 500 60 120 160 50 870 1600 dB dB dB % % MHz MHz MHz MHz MHz V/s V/s V1+ = V2+ = +5V, V1- = V2- = -5V, GND = 0V, TA = +25C, Input Video = 1VP-P and RL = 500 to GND, CL = 5pF unless otherwise specified. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT
4
FN6394.1 December 22, 2006
ISL59483 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = +25C, unless otherwise specified.
10 8 6 NORMALIZED GAIN (dB) 4 2 0 -2 -4 -6 -8 -10 CL INCLUDES 1.5pF BOARD CAPACITANCE 1M 10M CL=4.7pF CL=2.2pF CL=1.5pF SOURCE POWER=-20dBm CL=16.5pF NORMALIZED GAIN (dB) CL=11.5pF CL=7.3pF CL=6.2pF 5 4 3 2 1 0 -1 -2 -3 -4 -5 100M 1G 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) RL=100 RL=150 RL=500 RL=1k SOURCE POWER=-20dBm
FIGURE 1. MUX1: GAIN vs FREQUENCY vs CL
FIGURE 2. MUX1: GAIN vs FREQUENCY vs RL
10 8 NORMALIZED GAIN (dB) 6 4 2 0 -2 -4 -6 -8 -10 1M 10M 100M 1G FREQUENCY (Hz) CL INCLUDES 0.6pF BOARD CAPACITANCE CL = 3.3pF CL = 2.1pF CL = 1.1pF CL = 0.6pF VOUT = 0.2VP-P CL = 8.8pF NORMALIZED GAIN (dB) CL = 7.4pF CL = 6.2pF CL = 4.5pF
10 8 6 4 2 0 -2 -4 -6 -8 -10 1M 10M 100M 1G FREQUENCY (Hz) CL INCLUDES 0.6pF BOARD CAPACITANCE CL = 4.5pF CL = 3.3pF CL = 2.1pF CL = 0.6pF VOUT = 0.2VP-P CL = 12.6pF CL = 10.6pF CL = 8.8pF CL = 6.2pF
FIGURE 3. MUX2: SMALL SIGNAL GAIN vs FREQUENCY vs CL INTO 500 LOAD
FIGURE 4. MUX2: SMALL SIGNAL GAIN vs FREQUENCY vs CL INTO 150 LOAD
0.2 SOURCE 0.1 POWER=-20dBm 0.0 NORMALIZED GAIN (dB) -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 1M 10M 100M 1G CL=1.5pF CL=4.7pF OUTPUT RESISTANCE ()
100
10
1
0.1 0.1k
1M
10M FREQUENCY (Hz)
100M
1G
FREQUENCY (Hz)
FIGURE 5. MUX1: 0.1dB GAIN vs FREQUENCY
FIGURE 6. MUX1: ROUT vs FREQUENCY
5
FN6394.1 December 22, 2006
ISL59483 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = +25C, unless otherwise specified.
10 8 6 NORMALIZED GAIN (dB) 4 2 0 -2 -4 -6 -8 -10 1M CL INCLUDES 0.6pF BOARD CAPACITANCE 10M CL = 0.6pF 100M 1G CL = 2.1pF CL = 5.3pF NORMALIZED GAIN (dB) VOUT = 2VP-P CL = 8.8pF 10 8 6 4 2 0 -2 -4 -6 -8 -10 1M CL INCLUDES 0.6pF BOARD CAPACITANCE 10M 100M 1G CL = 2.1pF CL = 0.6pF CL = 5.3pF VOUT = 2VP-P CL = 12.6pF
(Continued)
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 7. MUX2: LARGE SIGNAL GAIN vs FREQUENCY vs CL INTO 500 LOAD
FIGURE 8. MUX2: LARGE SIGNAL GAIN vs FREQUENCY vs CL INTO 150 LOAD
2 1 NORMALIZED GAIN (dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 1M 10M VOUT = 0.2VP-P CL = 1.1pF
RL = 1k RL = 500 NORMALIZED GAIN (dB)
0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 RL = 500 CL = 1.1pF VOUT = 0.2VP-P RL = 150 CL = 2.1pF
RL = 250 RL = 150
100M
1G
-0.7 1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. MUX2: GAIN vs FREQUENCY vs RL
FIGURE 10. MUX2: 0.1dB GAIN FLATNESS
100 VSOURCE = 2VP-P OUTPUT IMPEDANCE () OUTPUT IMPEDANCE ()
10k VSOURCE = 2VP-P
10
1k
1
100
0.1 0.1M
1M
10M FREQUENCY (Hz)
100M
1G
10 0.1M
1M
10M FREQUENCY (Hz)
100M
1G
FIGURE 11. MUX2: ZOUT vs FREQUENCY - ENABLED
FIGURE 12. MUX2: ZOUT vs FREQUENCY - HIZ
6
FN6394.1 December 22, 2006
ISL59483 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = +25C, unless otherwise specified.
0 -10 -20 -30 -40 (dB) -50 -60 -70 -80 -90 -100 0.1M 1M 10M FREQUENCY (Hz) 100M 1G OFF ISOLATION INPUT X TO OUTPUT X (dB) INPUT X TO OUTPUT Y CROSSTALK 0 -10 VIN = 1VP-P
(Continued)
-20 CROSSTALK RL = 500 -30 INPUT X TO OUTPUT Y RL = 150 -40 OFF ISOLATION RL = 500 -50 INPUT X TO OUTPUT X RL = 150 -60 -70 -80 -90 -100 0.1M 1M 10M FREQUENCY (Hz) 100M 1G
FIGURE 13. MUX1: CROSSTALK AND OFF ISOLATION
FIGURE 14. MUX 2: CROSSTALK AND OFF ISOLATION
60 50 40 30 20 10 0 100
60 VOLTAGE NOISE (nV/Hz) 1k 10k 100k 50 40 30 20 10 0 100
VOLTAGE NOISE (nV/Hz)
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 15. MUX1: INPUT NOISE vs FREQUENCY
FIGURE 16. MUX2: INPUT NOISE vs FREQUENCY
20 10 PSRR (V+) 0 -10 PSRR (dB) -20 -30 -40 -50 -60 -70 -80 0.3M 1M 10M FREQUENCY (Hz) 100M 1G PSRR (V-) PSRR (dB)
10 VSOURCE = 0.5VP-P 0 -10 -20 -30 -40 -50 -60 0.3M PSRR (V-) PSRR (V-)
1M
10M FREQUENCY (Hz)
100M
1G
FIGURE 17. MUX 1: PSRR vs FREQUENCY
FIGURE 18. MUX 2: PSRR vs FREQUENCY
7
FN6394.1 December 22, 2006
ISL59483 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = +25C, unless otherwise specified.
0.002 0.000 -0.002 -0.004 -0.006 -0.008 -0.010 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 -4 -3 -2 -1 1 0 VOUT DC (V) 2 3 4 NORMALIZED PHASE () NORMALIZED GAIN (dB) NORMALIZED PHASE () NORMALIZED GAIN (dB) 0.010 0.008 0.006 0.004 0.002 0.000 -0.002 -0.004 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 -4 -3 -2 -1 1 0 VOUT DC (V) 2 3 4
(Continued)
FIGURE 19. MUX 2: DIFFERENTIAL GAIN AND PHASE; VOUT = 0.2VP-P, FO = 3.58MHz, RL = 500
FIGURE 20. MUX 2: DIFFERENTIAL GAIN AND PHASE; VOUT = 0.2VP-P, FO = 3.58MHz, RL = 150
0.8 0.6 0.4 0.2
VOUT (V)
RL=500 CL=1.5pF
VOUT = 0.2VP-P 0.2 RL = 500 CL = 1.1pF
0.0 -0.2 -0.4
VOUT (V)
0.1
0.0
-0.6 -0.8 TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 21. MUX 1: SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 22. MUX 2: SMALL SIGNAL TRANSIENT RESPONSE; RL = 500
VOUT = 0.2VP-P 0.2 RL = 150 CL = 2.1pF
VOUT (V)
0.1
0.0
TIME (5ns/DIV)
FIGURE 23. MUX 2: SMALL SIGNAL TRANSIENT RESPONSE; RL = 150
8
FN6394.1 December 22, 2006
ISL59483 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = +25C, unless otherwise specified.
VOUT = 2VP-P 2.0 RL = 500 CL = 1.1pF 2.0
(Continued)
VOUT = 2VP-P RL = 150 CL = 2.1pF
VOUT (V)
VOUT (V)
1.0
1.0
0.0
0.0
TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 24. MUX2 : LARGE SIGNAL TRANSIENT RESPONSE; RL = 500
FIGURE 25. MUX 2: LARGE SIGNAL TRANSIENT RESPONSE; RL = 150
50 INPUT RISE, FALL TIMES VOUT = 2VP-P <175ps VOUT = 1.4VP-P
50 INPUT RISE, FALL TIMES <175ps 40 VOUT = 1.4VP-P OVERSHOOT (%) VOUT = 2VP-P
40 OVERSHOOT (%)
30
30
20 VOUT = 1VP-P 10 VOUT = 0.2VP-P
20 VOUT = 1VP-P 10 VOUT = 0.2VP-P
0 2 4 CL (pF) 6 8 10
0
2
4
CL (pF)
6
8
10
FIGURE 26. MUX 2: PULSE OVERSHOOT vs VOUT, CL; RL=500
FIGURE 27. MUX 2: PULSE OVERSHOOT vs VOUT, CL; RL=150
S0, S1 50 TERM. 1V/DIV
VIN = 0V
S0, S1 50 TERM. 1V/DIV
VIN = 0V
0 20mV/DIV 20mV/DIV
0 VOUT A, B, C 0 20ns/DIV
0 VOUT A, B, C 20ns/DIV
FIGURE 28. MUX 1: CHANNEL TO CHANNEL SWITCHING GLITCH VIN = 0V
FIGURE 29. MUX 2: CHANNEL TO CHANNEL SWITCHING GLITCH VIN = 0V
FN6394.1 December 22, 2006
9
ISL59483 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = +25C, unless otherwise specified.
S0, S1 50 TERM. VIN = 1V S0, S1 50 TERM.
(Continued)
VIN = 1V
1V/DIV
0 0.5V/DIV
1V/DIV 0 1V/DIV VOUT A, B, C 20ns/DIV 0
0
VOUT A, B, C 20ns/DIV
FIGURE 30. MUX 1: CHANNEL TO CHANNEL TRANSIENT RESPONSE VIN = 1V
FIGURE 31. MUX 2: CHANNEL TO CHANNEL TRANSIENT RESPONSE VIN = 1V
ENABLE 50 TERM. 1V/DIV
VIN = 0V
ENABLE 50 TERM. 1V/DIV
VIN = 0V
0 100mV/DIV
0
0 20ns/DIV
1V/DIV
VOUT A, B, C
VOUT A, B, C 0 40ns/DIV
FIGURE 32. MUX 1: ENABLE SWITCHING GLITCH VIN = 0V
FIGURE 33. MUX 2: ENABLE SWITCHING GLITCH VIN = 0V
ENABLE 50 TERM. 1V/DIV
VIN = 1V
ENABLE 50 TERM. 1V/DIV
VIN = 1V
0
0
1V/DIV
0
VOUT A, B, C 20ns/DIV
2V/DIV
0
VOUT A, B, C 40ns/DIV
FIGURE 34. MUX 1: ENABLE TRANSIENT RESPONSE VIN = 1V
FIGURE 35. MUX 2: ENABLE TRANSIENT RESPONSE VIN = 1V
10
FN6394.1 December 22, 2006
ISL59483 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = +25C, unless otherwise specified.
HIZ 50 TERM. 1V/DIV 1V/DIV VIN = 0V HIZ 50 TERM.
(Continued)
VIN = 0V
0 200mv/DIV 200mv/DIV
0
0 VOUT A, B, C 10ns/DIV
0 VOUT A, B, C 20ns/DIV
FIGURE 36. MUX 1: HIZ SWITCHING GLITCH VIN = 0V
FIGURE 37. MUX 2: HIZ SWITCHING GLITCH VIN = 0V
HIZ 50 TERM. 1V/DIV
VIN=1V
HIZ 50 TERM. 1V/DIV
VIN = 1V
0
0
1V/DIV
2V/DIV
VOUT A, B, C 0 10ns/DIV
VOUT A, B, C 0 20ns/DIV
FIGURE 38. MUX 1: HIZ TRANSIENT RESPONSE VIN = 1V
FIGURE 39. MUX 2: HIZ TRANSIENT RESPONSE VIN = 1V
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 6 POWER DISSIPATION (W) POWER DISSIPATION (W) 5 4.34W 4 3 2 1 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) QFN48 JA =+23C/ 1.2 1.0
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5
870mW 0.8 0.6 0.4 0.2 0.0 0 25 50
QFN48 JA =+115C/
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 40. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 41. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
11
FN6394.1 December 22, 2006
ISL59483 Pin Description
ISL59483 (48 LD QFN) 1 2 3, 23 4 5, 25 6 26 7 27 8 9 10 11 12 13 14 15 16 17 18 19, 47 20, 48 21 22 24 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 PIN NAME OUTC1 OUTB1 V1-, V2OUTA1 V1+, V2+ EN1 EN2 HIZ1 HIZ2 IN0C1 IN0B1 IN0A1 GND IN1A1 IN2B2 IN2C2 GND IN3A2 IN3B2 IN3C2 S1-2, S1-1 S0-2, S0-1 OUTC2 OUTB2 OUTA2 IN0C2 IN0B2 IN0A2 GND IN1A2 IN1B2 IN1C2 GND IN2A2 IN1B1 IN1C1 GND IN2A1 IN2B1 IN2C1 GND IN3A1 IN3B1 IN3C1 Circuit 1 Circuit 1 Circuit 1 Circuit 4A Circuit 1 Circuit 1 Circuit 1 Circuit 4B Circuit 1 Circuit 1 Circuit 1 Circuit 2 Circuit 2 Circuit 2 Circuit 1 Circuit 1 Circuit 1 Circuit 1 Circuit 1 Circuit 4B Circuit 1 Circuit 1 Circuit 1 Circuit 4B Circuit 1 Circuit 1 Circuit 1 Circuit 4A Circuit 1 Circuit 1 Circuit 1 Circuit 4A Circuit 1 Circuit 1 Circuit 1 Circuit 2 EQUIVALENT CIRCUIT Circuit 3 Circuit 3 Circuit 4A Circuit 3 Circuit 4A Circuit 2 Output of amplifier C1 Output of amplifier B1 Negative power supply #1 and #2 Output of amplifier A1 Positive Power Supply #1 and #2 Device enable (active low) with internal pull-down resistor. A logic High puts device into power-down mode leaving the logic circuitry active. This state is not recommended for logic control where more than one MUX-amp share the same video output line. Output disable (active high) with internal pull-down resistor. A logic high puts the output in a high impedance state. Use this state when more than one MUX-amp share the same video output line. Channel 0 input for amplifier C1 Channel 0 input for amplifier B1 Channel 0 input for amplifier A1 Ground pin for amplifier A1 Channel 1 input for amplifier A1 Channel 2 input for amplifier B2 Channel 2 input for amplifier C2 Ground pin for amplifier C2 Channel 3 input for amplifier A2 Channel 3 input for amplifier B2 Channel 3 input for amplifier C2 Channel select pin MSB (binary logic code) for amplifiers A2, B2, C2 (S1-2) and A1, B1, C1 (S1-1) Channel select pin LSB (binary logic code) for amplifiers A2, B2, C2 (S0-2) and A1, B1, C1 (S0-1) Output of amplifier C2 Output of amplifier B2 Output of amplifier A2 Channel 0 input for amplifier A2 Channel 0 input for amplifier B2 Channel 0 input for amplifier C2 Ground pin for amplifier A2 Channel 1 input for amplifier A2 Channel 1 input for amplifier B2 Channel 1 input for amplifier C2 Ground pin for amplifier B2 Channel 2 input for amplifier A2 Channel 1 input for amplifier B1 Channel 1 input for amplifier C1 Ground pin for amplifier B1 Channel 2 input for amplifier A1 Channel 2 input for amplifier B1 Channel 2 input for amplifier C1 Ground pin for amplifier C1 Channel 3 input for amplifier A1 Channel 3 input for amplifier B1 Channel 3 input for amplifier C1 DESCRIPTION
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FN6394.1 December 22, 2006
ISL59483 Pin Equivalent Circuits
V+ IN LOGIC PIN 21k 33k V+ 1.2V V+ GND VCIRCUIT 2 V2+ GNDA2
CAPACITIVELY COUPLED ESD CLAMP CAPACITIVELY COUPLED ESD CLAMP
V+ OUT V-
CIRCUIT 1
V1+ GNDA1 GNDB1 GNDC1 V1CIRCUIT 4A
CIRCUIT 3
SUBSTRATE 1 V1~1M
SUBSTRATE 2 V2~1M
GNDB2 GNDC2 V2CIRCUIT 4B
THERMAL HEAT SINK PAD
AC Test Circuits
ISL59483 VIN 50 or 75 CL 5pF RL 500
Application Information
General
The ISL59483 is ideal as the matrix element of high performance switchers and routers. Key features include high impedance buffered analog inputs and excellent AC performance at output loads down to 150 for video cabledriving. The current feedback output amplifiers are stable operating into capacitive loads and bandwidth is optimized with a load of 5pF in parallel with a 500. Total output capacitance can be split between the PCB capacitance and an external load capacitor.
FIGURE 42A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
ISL59483 VIN 50 or 75 CL 5pF RS 475 50 or 75
TEST EQUIPMENT 50 or 75
Ground Connections
For the best isolation and crosstalk rejection, all GND pins must connect to the GND plane.
Power-up Considerations
FIGURE 42B. TEST CIRCUIT FOR MEASURING WITH 50 OR 75 INPUT TERMINATED EQUIPMENT
ISL59483 VIN 50 or 75 CL 5pF RS 50 or 75
TEST EQUIPMENT 50 or 75
The ESD protection circuits use internal diodes from all pins the V+ and V- supplies. In addition, a dV/dT-triggered clamp is connected between the V+ and V- pins, as shown in the Equivalent Circuits 1 through 4 section of the Pin Description table. The dV/dT triggered clamp imposes a maximum supply turn-on slew rate of 1V/s. Damaging currents can flow for power supply rates-of-rise in excess of 1V/s, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the rate of rise is not exceeded. Consideration must be given to the order in which power is applied to the V+ and V- pins, as well as analog and logic input pins. Schottky diodes (Motorola MBR0550T or equivalent) connected from V+ to ground and V- to ground (Figure 43) will shunt damaging currents away from the internal V+ and V- ESD diodes in the event that the V+ supply is applied to the device before the V- supply. One Schottky can be used to protect both V+ power supply pins, and a second for the protection of both V- pins.
FIGURE 42C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE APPLICATION. BANDWIDTH AND LINEARITY FOR RL LESS THAN 500 WILL BE DEGRADED. FIGURE 42. TEST CIRCUITS
Figure 42A illustrates the optimum output load for testing AC performance. Figure 42B illustrates the optimum output load when connecting to 50 input terminated equipment.
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FN6394.1 December 22, 2006
ISL59483
V+ SUPPLY SCHOTTKY PROTECTION LOGIC POWER GND SIGNAL DE-COUPLING CAPS V- SUPPLY S0 GND IN0 IN1 VVVV+ VVV+ V+ OUT V+ V+ LOGIC CONTROL EXTERNAL CIRCUITS
FIGURE 43. SCHOTTKY PROTECTION CIRCUIT
If positive voltages are applied to the logic or analog video input pins before V+ is applied, current will flow through the internal ESD diodes to the V+ pin. The presence of large decoupling capacitors and the loading effect of other circuits connected to V+ can result in damaging currents through the ESD diodes and other active circuits within the device. Therefore, adequate current limiting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than V+.
HIZ State
Each internal 4:1 triple MUX-amp has a high impedance output control pin (HIZ1 and HIZ2). Each has an internal pulldown resistor to set the output to the enabled state with no connection to the HIZ pin. The HIZ state is established within approximately 15ns by placing a logic high (>2V) on the HIZ pin. If the HIZ state is selected, the MUX 1 output is a high impedance 1.4M with approximately 1.5pF in parallel with a 10A bias current from the output. In the HIZ state the MUX 2 output impedance is ~900. The supply current during this state is the same as the active state.
resistors (ranging from 10 to 75) may be needed close to the output pin in order to buffer the amplifer output stage from the effects of capacitive loading. When paralleling the amplifier outputs, resistance in series with MUX 1 output will form a resistor divider with the 900 HIZ impedance of MUX 2 when MUX 1 is enabled and MUX 2 is in the HIZ state. However, resistance in series with MUX 2 does not result in a resistor divider with MUX 1 due to the 1.4M HIZ impedance. In all cases, series resistance will form a voltage divider with any downstream load resistance, therefore the effects of series resistance on throughput gain must be considered.
Limiting the Output Current
No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 50mA. Adequate thermal heat sinking of the parts is also required.
PC Board Layout
The AC performance of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. * The use of low inductance components such as chip resistors and chip capacitors is strongly recommended. * Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners. Use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. High frequency performance may be degraded for traces greater than one inch, unless controlled impedance (50 or 75) strip lines or microstrips are used. * Match channel to channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. * Maximize use of AC de-coupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines.
EN and Power-down States
The EN pin is active low. An internal pull-down resistor ensures the device will be active with no connection to the EN pin. The power-down state is established within approximately 80ns if a logic high (>2V) is placed on the EN pin. In the power-down state, supply current is reduced significantly by shutting the three amplifiers off. The output presents a high impedance to the output pin, however, there is a risk that the disabled amplifier output can be back-driven at signal voltage levels exceeding ~2VP-P. Under this condition, large incoming slew rates can cause fault currents of tens of mA. Therefore, the parallel connection of multiple outputs is not recommended unless the application can tolerate the limited power-down output impedance.
Output Capacitive Loading Considerations
High speed amplifiers may be sensitive to capacitance at the output. Excessive pulse overshoot may result from the combination of output slew rates approaching the amplifier maximum and the presence of parasitic capacitance. In applications where high slew rates are expected and PC board output pin capacitance exceeds ~5pF, series connected
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FN6394.1 December 22, 2006
ISL59483
* Use proper value and location of termination resistors. Termination resistors should be as close to the device as possible. * When testing, use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. * A minimum of 2 power supply decoupling capacitors are recommended (1000pF, 0.01F) as close to the devices as possible. Avoid vias between the cap and the device because vias adds unwanted inductance. Larger caps can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. * The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk. The thermal pad requirements are proportional to power dissipation and ambient temperature. A dedicated layer eliminates the need for individual thermal pad area. When a dedicated layer is not possible, an isolated thermal pad on another layer should be used. Pad area requirements should be evaluated on a case by case basis.
MUX Application Circuits
Each of the two 4:1 triple MUX amplifiers have their own binary-coded, TTL compatible channel select logic inputs (S0-1, 2, and S1-1, 2). All three amplifiers are switched simultaneously from their respective inputs with S0-1 S1-1 controlling MUX 1, and S0-2, S1-2 controlling MUX 2. The HIZ control inputs (HIZ1, HIZ2) and device enable control inputs (EN1 and EN2) control MUX 1 and MUX 2 in a similar fashion. The individual control for each 4:1 triple MUX enables external connections to configure the device for different MUX applications.
The QFN Package Requires Additional PCB Layout Rules for the Thermal Pad
The thermal pad is electrically connected to V- supply through the high resistance IC substrate. Its primary function is to provide heat sinking for the IC. However, because of the connection to the V1- and V2- supply pins through the substrate, the thermal pad must be tied to the V- supply to prevent unwanted current flow to the thermal pad. Do not tie this pin to GND as this could result in large back biased currents flowing between GND and the V- pins. Maximum AC performance is achieved if the thermal pad is attached to a dedicated decoupled layer in a multi-layered PC board. In cases where a dedicated layer is not possible, AC performance may be reduced at upper frequencies.
8:1 RGB Dual Gain Video MUX
The triple input RGB 8:1 MUX (Figure 44) connects the RGB amplifier output of MUX 1 to the parallel-connected RGB amplifier output of MUX 2 to produce a single RGB video output. Input channels CH0 to CH3 are assigned to MUX 1 and have a throughput gain of 1. Channels CH4 through CH7 are assigned to MUX 2 and have a throughput gain of 2. Channels CH0 through CH3 are selected by setting S2 low, which forces HIZ1 low and HIZ2 high (enables MUX 1 and three-states MUX 2). Setting S2 high reverses the logic inputs of HIZ1, HIZ2 and switches from MUX 1 to MUX 2, enabling the selection of channels CH4 through CH7. The channel select inputs are parallel connected (S0-1 to S0-2) and S1-1 to S1-2) to form two logic controls, S0 and S1. The logic control truth table is shown in Figure 44.
ISL59483 1/3 MUX-AMP1 CH0 CH1 CH2 CH3 CH0A - CH7A CHANNELS B & C NOT SHOWN CH4 CH5 CH6 CH7 S0 CHANNEL SELECT LOGIC INPUTS S1 S2 IN0A1 IN1A1 IN2A1 IN3A1 * ROUTA1 S0-1 S1-1 HIZ1 IN0A2 IN1A2 IN2A2 IN3A2 S0-2 S1-2 HIZ2 * OPTIONAL - DEPENDING ON PARASITIC CAPACITANCE CONTROL LOGIC +2 OUTA2 1/3 MUX-AMP2 * ROUTA2 CONTROL LOGIC +1 OUTA1 CHANNEL SELECT TRUTH TABLE 8:1 VIDEO MUX S2 0 OUTA 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 GAIN 1 1 1 1 2 2 2 2 OUTA, B, C CH0A, B, C CH1A, B, C CH2A, B, C CH3A, B, C CH4A, B, C CH5A, B ,C CH6A, B, C CH7A, B, C
FIGURE 44. APPLICATION CIRCUIT FOR A DUAL GAIN 8:1 RGB VIDEO MUX
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FN6394.1 December 22, 2006
ISL59483
4:1 RGB Dual Gain Video MUX
Connecting the MUX inputs and outputs in parallel allows the 8 channel ISL59483 to be used as a 4:1 RGB MUX with selectable gains of 1 or 2 (Figure 10). In this example, the high input impedance of the MUX enables each input video line to be shared by any number of MUX input pins. The gain select
ISL59483 1/3 MUX-AMP1 CH0 CH1 CH2 CH3 IN0A1 IN1A1 IN2A1 IN3A1 * ROUTA1 S0-1 CH0 - CH3 CHANNELS B & C NOT SHOWN S1-1 HIZ1 IN0A2 IN1A2 IN2A2 IN3A2 S0-2 S1-2 HIZ2 +2 OUTA2 1/3 MUX-AMP2 * ROUTA2 CONTROL LOGIC OUT 0 1 1 0 0 1 CONTROL LOGIC 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 1 1 2 2 2 2 CH1A, B, C CH2A, B, C CH3A, B, C CH0A, B, C CH1A, B, C CH2A, B, C CH3A, B, C S1 0 S1 0 +1 OUTA1 CHANNEL SELECT TRUTH TABLE DUAL GAIN 4:1 VIDEO MUX GAIN SELECT 0 GAIN 1 OUTA, B, C CH0A, B, C
logic function is created by providing complememtary logic to the HIZ1 and HIZ2 pins. Channels CH0 through CH3 are selected by connecting the MUX 1 and MUX 2 S0-1, 2 and S1-1, 2 channel select inputs together to form channel select (S0 and S1), as shown in the truth table in Figure 10.
CHANNEL SELECT AND GAIN SELECT LOGIC INPUTS
S0 S1 GAIN SELECT
* OPTIONAL - DEPENDING ON PARASITIC CAPACITANCE
FIGURE 45. APPLICATION CIRCUIT FOR DUAL GAIN 4:1 VIDEO MUX
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
FN6394.1 December 22, 2006
ISL59483
Package Outline Drawing
L48.7x7B
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 12/06
4X 5.5 7.00 A B 6 PIN 1 INDEX AREA 37 36 44X 0.50 48 1 6 PIN #1 INDEX AREA
7.00
3.70
25 (4X) 0.15 24 TOP VIEW 48X 0 . 40 13
12
0.10 M C A B 4 0.25
BOTTOM VIEW
SEE DETAIL "X" 0.10 C BASE PLANE C
( 6 . 80 TYP ) ( 3.70 )
0 . 85 0 . 1
SIDE VIEW ( 44X 0 . 5 )
SEATING PLANE 0.08 C
C ( 48X 0 . 25 ) ( 48X 0 . 60 ) TYPICAL RECOMMENDED LAND PATTERN
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX. DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
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FN6394.1 December 22, 2006

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