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Preliminary Technical Data
FEATURES
50KHz Max Excitation Output Impedance Range .1k - 20M Ohm, 12-Bit Resolution System Clock provided via MCLK pin DSP Real and Imaginary Calculation (FFT) 3V Power Supply, Programmable Sinewave Output Frequency Resolution 27 Bits (<0.1 Hz) Frequency Sweep Capability 12-Bit Sampling ADC ADC Sampling 250KSPS, INL 1LSB Max Serial I2C Loading Temperature Range -40 - 125C 16 SSOP
250KSPS 12 Bit Impedance Converter Network Analyzer AD5934
Magnitude = R 2 + I 2
Phase = Tan -1 (I R )
To determine the actual real impedance value Z(W), a frequency sweep is generally performed. The impedance can be calculated at each point, and a frequency vs. magnitude plot can be created. The system allows the user to program a 2 V PK-PK sinusoidal signal as excitation to an external load. Output ranges of 1 V, 500 mV, and 200 mV can also be programmed. The signal is provided on chips using DDS techniques. Frequency resolution of 27 bits (less than 0.1HZ) can be achieved. To perform the frequency sweep, the user must first program the conditions required for the sweep; start frequency, delta frequency, step frequency, etc. A Start Command is then required to begin the sweep. At each point on the sweep the, ADC takes 1024 samples and calculates a Discrete Fourier Transform to provide the real and imaginary data for the waveform. The real and imaginary data is available to the user through the 12C interface. To determine the impedance of the load at any one frequency point, Z(w), a measurement system comprised of a trans impedance amplifier, gain stage, and ADC are used to record data. The gain stage for the response stage is 1 or 5. The ADC is a low-noise, high-speed 250 KSPS sampling ADC that operates from a 3 V supply. Clocking for both the DDS and ADC signals is provided externally via the MCLK reference clock, which is provided externally from a crystal oscillator. The AD5934 is available in a 16 ld SSOP.
APPLICATIONS
Complex Impedance Measurement Impedance Spectrometry Biomedical and Automotive Sensors Proximity Sensors FFT Processing
GENERAL DESCRIPTION
The AD5934 is a high precision impedance converter system solution which combines an on-board frequency generator with a 12-bit 250KSPS ADC. The frequency generator allows an external complex impedance to be excited with a known frequency. The response signal from the impedance is sampled by the onboard ADC and FFT processed by an onboard DSP engine. The FFT algorithm returns a Real (R) and Imaginary (I) data word, allowing impedance to be conveniently calculated. The impedance magnitude and phase is easily calculated using the following equations:
Figure 1.
Rev. PrA
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AD5934 TABLE OF CONTENTS
Specifications..................................................................................... 3 Timing Characteristics..................................................................... 5 Pin Configuration and Function Descriptions............................. 6 General Description ......................................................................... 7 Output Stage.................................................................................. 7 Circuit Description....................................................................... 7 Sin Rom.......................................................................................... 8 Response Stage.............................................................................. 8 ADC Operation ............................................................................ 8 DFT Conversion ........................................................................... 9 Register Map.................................................................................... 10 Control Register.......................................................................... 11 Control Register Map................................................................. 11 Control Register Decode ........................................................... 12
Preliminary Technical Data
Reset ............................................................................................. 12 System Clock............................................................................... 12 Output Voltage............................................................................ 12 Post Gain ..................................................................................... 12 Serial Bus Interface..................................................................... 13 General I2C Timing ................................................................... 13 Writing/Reading to the AD5934 .......................................... 14 Write Byte/Command Byte....................................................... 14 Block Write.................................................................................. 15 Read Operations......................................................................... 15 P.E.C. ............................................................................................ 16 Checksum.................................................................................... 16 Outline Dimensions ....................................................................... 17 ESD Caution................................................................................ 17
REVISION HISTORY
12/04--Revision PrA - Preliminary Version
Rev. PrA | Page 2 of 20
Preliminary Technical Data SPECIFICATIONS
VDD = +3.0 V 10%. TMIN to TMAX unless otherwise noted. Table 1.
Parameter System Specs Impedance Range Total System Accuracy System ppm MCLK Update Rate Output Stage Frequency Specs Output Frequency Range Frequency Resoltuion MCLK Initial Frequency Accuracy Output Voltage Specs AC Voltage Range Output Voltage Error DC Bias DC Bias Error AC Voltage Range Output Voltage Error DC Bias DC Bias Error AC Voltage Range Output Voltage Error DC Bias DC Bias Error AC Voltage Range Output Voltage Error DC Bias DC Bias Error DC Output Impedance Short Circuit Current Short Circuit Current AC Characteristics Signal to Noise Ratio Total Harmonic Distortion Spurious free Dynamic Range Wideband Narrowband Clock Feedthrough Min .0001 1 TDB 16 B Version1 Typ Max 20 Unit M Ohm % ppm/C MSPS Test Conditions/Comments
AD5934
0 27
50KHz
Hz Bits
Uni-polar sinusoidal signal <0.1 Hz resolution External reference clock; typically 16.667 MHz Output excitation accuracy. 0 -50 KHz range
0.1
Hz
2.0 TBD Vdd/2 TBD 1.0 TBD Vdd/4 1 0.4 TBD Vdd/8 TBD 0.2 TBD Vdd/16 TBD 120 75 100 60 -66 60 80 TBD
Volts % Volts % Volts % Volts % Volts % Volts % Volts % Volts % Ohm mA mA db db db db db
Pk-Pk unipolar voltage on output Voltage error on Pk-Pk output DC bias of AC signal Tolerance of DC bias Pk-Pk unipolar voltage on output Voltage error on Pk-Pk output DC bias of AC signal Tolerance of DC bias Pk-Pk unipolar voltage on output Voltage error on Pk-Pk output DC bias of AC signal Tolerance of DC Bias Pk-Pk unipolar voltage on output Voltage error on Pk-Pk output DC bias of AC signal Tolerance of DC bias
At 3 volts At 5 volts
Rev. PrA | Page 3 of 20
AD5934
Parameter System Response Stage Analog Input VIN Input Leakage Current Input Capacitance Input Impedance ADC Accuracy Resolution Sampling Rate Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error TEMPERATURE SENSOR Accuracy Resolution Temperature Conversion Time LOGIC INPUTS Vih, Input High Voltage Vil, Input Low Voltage Input Current Input Capacitance POWER REQUIREMENTS Vdd IDD (Normal Mode) IDD (Powerdown Mode) Min B Version1 Typ Max Unit
Preliminary Technical Data
Test Conditions/Comments
1 0.5 100M
nA pF Ohm
To Pin VIN To Pin VIN To Pin VIN
12 1 1 1
MSPS LSB LSB
No missing codes
2 0.03125 TBD
C C S
TA = -40 - 125 degrees
2.2 0.8 1 3
VDD = 3v VDD = 3V A pF
3.0 15 TBD
Volts mA A
1 2
Temperature ranges are as follows: B Version: -40C to +125C, typical at 25C. Guaranteed by design and characterization, not production tested.
Rev. PrA | Page 4 of 20
Preliminary Technical Data TIMING CHARACTERISTICS
Table 2. I2C Serial Interface
Parameter FSCL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Limit at TMIN, TMAX 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 0 300 0 300 20 + 0.1 CB 400 Unit kHz max s min s min s min s min ns min s max s min s min s min s min ns max ns min ns max ns min ns max ns min pF max Description SCL clock frequency SCL cycle time tHIGH, SCL high time tLOW, SCL low time tHD, STA, start/repeated start condition hold time tSU, DAT, data setup time tHD, DAT, data hold time tHD, DAT, data hold time tSU, STA, setup time for repeated start tSU, STO, stop condition setup time tBUF, bus free time between a stop and a start condition tF, fall time of SDA when transmitting tR, rise time of SCL and SDA when receiving (CMOS compatible) tF, fall time of SDA when transmitting tF, fall time of SDA when receiving (CMOS compatible) tF, fall time of SCL and SDA when receiving tF, fall time of SCL and SDA when transmitting Capacitive load for each bus line
AD5934
CB
Figure 2. I2C Interface Timing Diagram
Rev. PrA | Page 5 of 20
AD5934 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Preliminary Technical Data
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 4 5 6 8 9 10 11 12 13 14 25 16 Mnemonic N/C RFB_PIN VOUT VIN MCLK DVDD AVDD1 AVDD2 DGND AGND1 AGND2 SDA SCL Function No Connect. External Feedback Resistor. This is used to set the gain of the input signal of the VIN node. Output AC Excitation signal. Programmble Frequnency range 0-50KHz. Input Signal to transimpedance amplifier. External Feedback resistor will control gain of transimpedance amplifier. Master Clock for the system. Used to provide output excitation signal and as sampling of ADC. Digital Supply Voltage. Analog Supply Voltage 1. Analog Supply Voltage 2. Digital Ground. Analog Gnd 1. Analog Gnd 2. I2C DATA INPUT. I2C CLOCK INPUT.
Rev. PrA | Page 6 of 20
Preliminary Technical Data GENERAL DESCRIPTION
The AD5934 is a high precision impedance converter system solution which combines an onboard frequency generator with a 12-bit 1MSPS ADC. The frequency generator allows an external complex impedance to be excited with a known frequency. The response signal from the impedance is sampled by the on board ADC and FFT processed by an onboard DSP engine. The FFT algorithm returns two Real (R) and Imaginary (I) data words. The impedance magnitude and phase is easily calculated using the following equations:
AD5934
Magnitude = R 2 + I 2
Phase = Tan -1 (I R )
Figure 5.
CIRCUIT DESCRIPTION
The AD5934 has a fully integrated Direct Digital Synthesis (DDS) core to generate required frequencies. The block requires a reference clock to provide digitally created sine waves up to 50KHz. This is provided through an external reference clock, MCLK. This clock is internally divided down by 4 to provide the reference clock or fMCLK to the DDS. The internal circuitry of the DDS consists of the following main sections: a Numerical Controlled Oscillator (NCO), a Frequency Modulator, SIN ROM, and a digital-to-analog converter.
To determine the actual real impedance value Z(W), a frequency sweep is generally performed. The impedance can be calculated at each point, and a frequency vs. magnitude plot can be created.
Numerical Controlled Oscillator and Phase Modulator
The main component of the NCO is a 27-bit phase accumulator, which assembles the phase component of the output signal.
Figure 4.
The system allows the user to program a 2V PK-PK sinusoidal signal as excitation to an external load. Output ranges of 1V, 500mV, 200mV can also be programmed. The signal is provided on chip using DDS techniques. Frequency resolution of 27 bits (less than 0.1HZ) can be achieved. The clock for the DDS can be generated from an external reference clock, an internal RC oscillator, or an internal PLL. The PLL has a gain stage of 520, and typically needs a reference clock of 32 KHz on the MCLK pin.
Figure 6.
OUTPUT STAGE
The output stage of the AD5934, shown in Figure 5, provides a constant output frequency or frequency sweep function which has a programmable output voltage of 2/1/0.5/0.2 V. The frequency sweep sequence is pre-programmed through the I2C interface. An I2C command is used to start the excitation sequence.
Continuous time signals have a phase range of 0 to 2 pi. Outside this range of numbers, the sinusoid functions repeat themselves in a periodic manner. The digital implementation is no different. The accumulator simply scales the range of phase numbers into a multi-bit digital word. The phase accumulator in the DDS is implemented with 28 bits. Therefore, 2p = 227. Likewise, the DPhase term is scaled into this range of numbers 0 < DPhase < 227 - 1. Making these substitutions into the equation above
f = DPhase x f MCLK 2 27
where 0 < DPhase < 227 - 1. (Note. fmclk = MCLK/4) The input to the phase accumulator (i.e., the phase step) is selected from the frequency register. NCOs inherently generate continuous phase signals, thus avoiding any output discontinuity when switching between frequencies.
Rev. PrA | Page 7 of 20
AD5934
SIN ROM
To make the output from the NCO useful, it must be converted from phase information into a sinusoidal value. Since phase information maps directly into amplitude, the SIN ROM uses the digital phase information as an address to a look-up table, and converts the phase information into amplitude. Although the NCO contains a 27-bit phase accumulator, the output of the NCO is truncated to 12 bits. Using the full resolution of the phase accumulator is impractical and unnecessary as this would require a look-up table of 227 entries. It is necessary only to have sufficient phase resolution such that the errors due to truncation are smaller than the resolution of the 10-bitDAC. This requires the SIN ROM to have two bits of phase resolution more than the 10-bit DAC. The DDS includes a high impedance current source 10-bit DAC.
Preliminary Technical Data
ADC OPERATION
The AD5934 has an integrated on board 12-bit ADC. The ADC contains an on-chip track and hold amplifier, a successive approximation A/D converter. Clocking for the A/D is provided using a divided down ratio of the reference clock. The A/D is a successive approximation analog to digital converter, based on a Capacitive Dac design Architecture. The figures below show simplified schematics of the ADC. The ADC is comprised of control logic, a SAR, and a capacitive DAC, all of which are used to add and subtract fixed amounts of charge from the Sampling capacitor to bring the comparator back into a balanced condition. The 1st figure shows the ADC during its acquisition phase. SW2 is closed and SW1 is in position A, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on VA1, for example.
RESPONSE STAGE
The diagram below shows the input stage to pin TF1. Current from the external sensor load flows through the TF1 pin and into a transimpedance amplifier which has an external resistor across its feedback. The user needs to choose a precision resistor in the feedback loop such that the dynamic range of the ADC is used. The positive node of the transimpedance amplifier is biased to VDD/2. The output of the Transimpedance amplifier can then be gained by either 1 or 5, and is fed directly into the input of the ADC.
Figure 8.
When the ADC starts a conversion, SW2 will open and SW1 will move to position B, as shown below, causing the comparator to become unbalanced. The control logic and the capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code.
Figure 7.
Figure 9.
The start conversion for the ADC is either user controlled via an external adc_trig pin or can be internally programmed as a delay from the start of the excitation signal. The data from the ADC is directly available on the I2C interface or can either be stored in a FIFO RAM until the entire frequency sweep is completed.
Rev. PrA | Page 8 of 20
Preliminary Technical Data
DFT CONVERSION
A Discrete Fourier Transform is calculated for each frequency point in the sweep. The return signal is converted by the ADC, windowed, and then multiplied with a test phasor value to give a real and imaginary output. This is repeated for 1024 sample points of the input signal and the results of each multiplication summed to give a final answer as a complex number. The resultant answer at each frequency is two 16-bit words, the real and imaginary data in complex form. The DFT algorithm is represented by
AD5934
X ( f ) = SUM x(n ) [Cos (n ) - jSine(n )]
Both the real and imaginary data register have 15 bits of data and one sign bit. The 15 bits of data are in 2's compliment format. The magnitude of the signal can be represented by
Magnitude = R 2 + I 2
This returned magnitude is a scaled valued of the actual complex impedance measured. The multiplication factor between the magnitude returned and the actual impedance is called the GAIN FACTOR. The user needs to then calculate this GAIN FACTOR value and use it for calibration in the system.
Figure 10.
Rev. PrA | Page 9 of 20
AD5934 REGISTER MAP
Preliminary Technical Data
The register map contains the registers where the frequency sweep data is loaded, and the resultant real and imaginary data is stored. Each row equals 8 bits of data. Table 4. Register Map
Register Name RAM Control Register Start Frequency (24 Bits) Reg Add. 80h 81h 82h 83h 84h 85h 86h 87h 88h Register Data [8 Bits] D15 - D8 D7 - D0 D23 - D16 D1 5 -D8 D7 - D0 D23 - D16 D15 - D8 D7 -D0 D15 - D8 Read/Write Register Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Register Type RAM RAM RAM RAM RAM RAM RAM RAM RAM
Frequency Increment Word
No of Increments (9 Bits) Bits D15-D9 = Don't care Bits D8-D0 = Number of frequency increments Settling time Cycles (16 Bits) D15 - D11= Don't Care D10 - D9 = 2 Bit Decode D8 - D0 = Number of Cycles D10 0 0 1 1 D9 0 1 0 1
8Ah
D15 - D8
Read/Write
RAM
Default Number of Cycles x 2 Reserved Number of Cycles x 4 8Bh 8Ch D7 - D0 D7 - D0 Read/Write Read/Write RAM RAM
Leakage Limit for Test A D7 - D4 = Don't care D3 - D0 = 4-Bit Limit Leakage Limit for Test B D7 - D4 = Don't Care D3 - D0 = 4 Bit-Limit Leakage Limit for Test C D7 - D4 = Don't Care D3 - D0 = 4 Bit-Limit Status Register Index Counter of Frequency (9 Bits) Bits D15 - D9 = Don't Care Bits D8 - D0 = Increments Register after a Frequency increment command. Set to Zero at Initial Frequency. Temperature Data Register Real Data Imaginary Data Checksum
8Dh
D7 - D0
Read/Write
RAM
8Eh
D7 - D0
Read/Write
RAM
8fh 90h
D7 - D0 D15 - D8
Read/Write Read Only
RAM RAM
91h 92h 93h 94h 95h 96h 97h 98h
D7 - D0 D15 - D8 D7 - D0 D15 - D8 D7 - D0 D15 - D8 D7 - D0 D7-D0
Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only
RAM RAM RAM RAM RAM RAM RAM
Rev. PrA | Page 10 of 20
Preliminary Technical Data
CONTROL REGISTER
AD5934
The AD5934 contains a 16-bit control register that set the AD5934 control modes. The five MSBs of the control register are decoded to provide control functions for frequency sweep, power down and various other control functions, defined in Table below. The other command functions of the control register are explained on the following pages. Note: For error checking on the control register it is advised to write one byte at a time with PEC enabled. This allows full error checking to be completed before the control register is updated and therefore ensures the control is not updated with incorrect data. The Control register will power-up in the following state xA000h (i.e. in Powerdown)
CONTROL REGISTER MAP
Table 5. Control Register Map
Bit D15 D14 D13 D12 D11 D15 0 0 0 0 0 0 0 0 0 D14 0 0 0 0 0 1 1 1 1 D13 0 0 0 0 1 0 0 0 0 D9 0 0 1 1 D12 0 0 1 1 0 0 0 1 1 D8 0 1 0 1 D11 0 1 0 1 0 0 1 0 1 FREQUENCY SWEEP No Operation/ Exit Fuse Blow Mode Initialize Sensor with Start Frequency Start Frequency Sweep Increment Frequency Repeat Frequency Reserved Reserved Power Down Standby Mode External Calibration Mode = "1" Output Voltage No Divide. (Normal Mode = 2.0V) Divide by 10 (200mv) Divide by 5 (400mv) Divide by 2 (1.0v) Post Gain "0" = Multiply X 5; "1" = Multiply X 1. Error Checking Enable = "1"; Disable="0" Reserved. Set to "0" RESET RESERVED RESERVED RESERVED RESERVED
D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0
Rev. PrA | Page 11 of 20
AD5934
CONTROL REGISTER DECODE
Initialize Sensor with Start Frequency
This command enables the DDS to output the start frequency for an indefinite time. It is used is to excite the sensor initially. When the output load (sensor) has settled after a time determined by the user, the user must initiate a "start frequency sweep" command to begin the frequency sweep
Preliminary Technical Data
Standby Mode
Powers the part up for general operation; all the amplifiers will be powered up but their outputs will be tied to GND. The internal oscillator will also be powered up and running.
Read Temperature
This initiates a temperature reading from the part. The part does not need to be in Power Up mode to perform a temperature reading. The block will power itself up, take the reading and then power down again.
Start Frequency Sweep
This command starts the frequency sweep routine. When the AD11/2043 receives this command, it starts counting a delay cycle that will gate the ADC conversion pulse. This delay cycle has already been pre-programmed as number of output cycles by the user.
Error Checking
Set bit in Control Register to enable this. Enable = "1"; Disable="0"
RESET
A Reset will Refresh all Memory, Reset ADC, Frequency reverts to the INITIAL start frequency
Increment Frequency
The "Increment Frequency" command is used to step to the next frequency point in the sweep. This usually happens after data from the previous step has been transferred and verified by the DSP.
SYSTEM CLOCK
Allows the user to configure either the internal oscillator or an external reference clock, or allows an internal PLL to provide a clock for the system. In PLL mode the user will have to provide a stable ~32kHz clock as reference to the PLL.
Repeat Frequency
Repeat frequency allows the user to repeat any given frequency if the data gets corrupted or the measurement sequence does not complete.
OUTPUT VOLTAGE
This allows the user to change the excitation voltage levels. There are for output ranges, 2v, 1v, 500mv, 200mv.
Power Down
Power Down powers down all the blocks in the chip except the interface. All amplifiers and the oscillator will be powered off. The default on power-up of the AD11/2043 is powerdown and the control register will contain the code 1010000000000000. In this mode both the output and input pins DDS_OUT and IN_ADC will be tied to GND.
POST GAIN
Allows the user to multiply pre-amp the response signal by a multiplication factor of 5 into the ADC, if required.
Rev. PrA | Page 12 of 20
Preliminary Technical Data
AD5934
Figure 11. Performing a Frequency Sweep - Flow Chart
SERIAL BUS INTERFACE
Control of the AD5934 is carried out via the 12C Serial Interface Protocol. The AD5934 is connected to this bus as a slave device, under the control of a master device. The AD5934 has a 7-bit serial bus slave address. When the device is powered up, it will do so with a default serial bus address; 0001101.
GENERAL I2C TIMING
The diagram below shows the timing diagram for general read and write operations using the I2C interface. The general I2C protocol operates as follows:
Figure 12.
*
The master initiates data transfer by establishing a START condition, defined as a high to low transition on the serial data line SDA while the serial clock line SCL remains high. This indicates that a data stream will follow. The slave responds to the START condition and shift in the next
8 bits, consisting of a 7-bit slave address (MSB first) plus an R/W bit, which determines the direction of the data transfer, i.e. whether data will be written to or read from the slave device (0 = write, 1 = read).
Rev. PrA | Page 13 of 20
AD5934
* The slave responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, then the master will write to the slave device. If the R/W bit is a 1, the master will read from the slave device. Data is sent over the serial bus in sequences of nine clock pulses, 8 bits of data followed by an acknowledge bit, which can be from the master or slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to high transition when the clock is high may be interpreted as a STOP signal. If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It may be an instruction telling the slave device to expect a block write, or it may simply be a register address that tells the slave where subsequent data is to be written. Since data can flow in only one direction as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before doing a read operation, it may first be necessary to do a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. When all data bytes have been read or written, stop conditions are established. In WRITE mode, the master will pull the data line high during the 10th clock pulse to assert a STOP condition. In READ mode, the master device will release the SDA line during the low period before the 9th clock pulse, but the slave device will not pull it low. This is known as No Acknowledge. The master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a STOP condition.
Preliminary Technical Data
WRITE BYTE/COMMAND BYTE
In this operation, the master device sends a byte of data to the slave device. The write byte can either be a data byte write to a RAM location or can be a command operation. To write data to a register the command sequence is as follows: 1. 2. 3. 4. 5. 6. 7. 8. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a register address. The slave asserts ACK on SDA. The master sends a data byte. The slave asserts ACK on SDA. The master asserts a STOP condition on SDA to end the transaction.
*
Table 6. Writing Register Data to Register Address
S SLAVE ADDRESS W A REGISTER ADDRESS A REGISTER MAP A P
*
In the AD5934, the write byte protocol is also used to set a pointer to a register location. This is used for a subsequent single byte read from the same address or block read or write starting at that address. This is done as follows: To set a register pointer the following sequence is applied: 1. 2. 3. 4. 5. 6. 7. 8. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a command code (pointer command 1011 0000). The slave asserts ACK on SDA. The master sends a data byte (register location pointer is to point to). The slave asserts ACK on SDA. The master asserts a STOP condition on SDA to end the transaction.
WRITING/READING TO THE AD5934
The interface specification defines several different protocols for different types of read and write operations. Those used in the AD5934 are discussed below. These abbreviations are used: S P R - Start - Stop - Read
W - Write A A - Acknowledge - No Acknowledge
Rev. PrA | Page 14 of 20
Preliminary Technical Data
Table 7. Setting Pointer to Register Address
S SLAVE ADDRESS W A Pointer Command 011 0000 A Register Location to Point to A P
AD5934
3. 4. 5. The addressed slave device asserts ACK on SDA. The master sends An 8-bit command code (10100000) that tells the slave device to expect a block write. The slave asserts ACK on SDA. The master sends a data byte that tells the slave device the number of data bytes will be sent to it. The slave asserts ACK on SDA. The master sends the data bytes. The slave asserts ACK on SDA after each data byte.
BLOCK WRITE
In this operation, the master device writes a block of data to a slave device. The start address for a block write must previously have been set. In the case of the AD5934 this is done by setting a pointer to set the RAM/OTP address. 1. 2. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low).
6. 7. 8. 9.
10. The master asserts a STOP condition on SDA to end the transaction
Table 8. Writing a Block Write
S SLAVE ADDRESS W A BLOCK WRITE A NUMBER BYTES WRITE A ABYTE0 A BYTE1 A BYTE2 A P
READ OPERATIONS
The AD5934 uses the following I2C read protocols: 1. 2. 3. 4. 5. 6. 7. 8. 9. The master device asserts a START condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a command code (10100001) that tells the slave device to expect a block read. The slave asserts ACK on SDA. The master sends a byte count data byte that tells the slave how many data bytes to expect. The master asserts ACK on SDA. The master asserts a repeat start condition on SDA. (This is required to set read bit high) The master sends the 7-bit slave address followed by the read bit (high).
Receive Byte
In this operation, the master device receives a single byte from a slave device as follows: 1. 2. 3. 4. 5. 6. The master device asserts a START condition on SDA. The master sends the 7-bit slave address followed by the read bit (high). The addressed slave device asserts ACK on SDA. The master receives a data byte. The master asserts NO ACK on SDA. (Slave needs to check that master has received Data) The master asserts a STOP condition on SDA and the transaction ends.
In the AD5934, the receive byte protocol is used to read a single byte of data from a RAM or OTP memory location whose address has previously been setting the address pointer. Table 9. Reading Register Data
SLAVE ADDRESS REGISTER DATA
10. The slave asserts ACK on SDA. 11. The master receives the data bytes. 12. The master asserts ACK on SDA after each data byte.
S
R
A
A
P
Block Read
In this operation, the master device reads a block of data from a slave device. The start address for a block read must previously have been set. This is again done by setting a pointer to set the RAM/OTP address.
13. A NACK is generated after the last byte to signal the end of the read. 14. The master asserts a STOP condition on SDA to end the transaction.
Rev. PrA | Page 15 of 20
AD5934
Table 10.
S SLAVE ADDRESS W A BLOCK READ A NUMBER BYTES READ A S
Preliminary Technical Data
CHECKSUM
A checksum register is available to allow the user to verify the correct contents of the frequency register, frequency increment register, and number of increments. The checksum register is based on an error checking algorithm from the above registers. TBD. The user reads this checksum register and verifies contents are correct.
Table 11.
SLAVE ADDRESS R A BYTE0 A BYTE1 A BYTE2 A P
User Command Codes
These command codes are used for reading/writing to the interface and the memory. They are further explained in the appropriate sections but are grouped here for ease of reference. Table 12. Command Code
1010 0000
Performing a Block Read Error Correction
Code Name
Block Write Block Read
Code Description.
This command is used when writing multiple bytes to the RAM. See block write section for further explanations. This command is used when reading multiple bytes from the RAM/Memory. See block write section for further explanations. This command enables the user to set the address pointer to any location in the memory. The data will contain the address register of the register the pointer should be pointing to.
P.E.C.
The AD5934 provides the option of issuing a PEC (Packet Error Correction) byte after all commands. This enables the user to verify that the data received by or sent from the AD5934 is correct. The PEC byte is an optional byte sent after that last data byte has been written to or read from the AD5934. The protocol is as follows:- 1. The AD5934 issues a PEC byte to the master. The master should check the PEC byte and issue another block read if the PEC byte is incorrect. A NACK is generated after the PEC byte to signal the end of the read. The PEC is generated per the following specifications.
1010 0001
1011 0000
Address Pointer
2. 3.
Note: The PEC byte is calculated using CRC-8. The Frame Check Sequence (FCS) conforms to CRC-8 by the polynomial:
C (x ) = x 8 + x 2 + x1 + 1
Rev. PrA | Page 16 of 20
Preliminary Technical Data OUTLINE DIMENSIONS
AD5934
Figure 13. 16-Lead Shrink Small Outline Package [SSOP] (RS-16)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA | Page 17 of 20
AD5934
Preliminary Technical Data
NOTES
Rev. PrA | Page 18 of 20
Preliminary Technical Data
AD5934
NOTES
Rev. PrA | Page 19 of 20
AD5934
Preliminary Technical Data
NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05325-0-12/04(PrA)
Rev. PrA | Page 20 of 20
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