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| 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PS4066/PS4066A Low-Cost, Quad, SPST, CMOS Analog Switches Features * * * * * * * * * * * Low On-Resistance On-Resistance Matching Between Channels, 0.2 typ On-Resistance Flatness, <2 typ Low Off-Channel Leakage, <100pA @ +25oC TTL/CMOS Logic Compatible GND-to-V+ Analog Signal Dynamic Range Low Power Consumption (<12W) Low Crosstalk: -86dB @ 1MHz Low Off-Isolation: -58dB @ 1 MHz Wide Bandwidth: > 100 MHz Small QSOP-16 Package Saves Board Area Description The PS4066/PS4066A are improved SPST CMOS analog switches ideal for low-distortion audio switching. These high precision, medium voltage switches were designed to operate with single-supplies from +3V to 16V. They are fully specified with +12V, +5V, and +3V supplies. The PS4066/PS4066A has four normally open (NO) switches. Each switch conducts current equally well in either direction when on. In the off state each switch blocks voltages up to the power-supply rails. With +12V power supply, the PS4066/PS4066A guarantee <45 on-resistance. On-resistance matching between channels is within 2 (PS4066). On-resistance flatness is less than 4 (PS4066A) over the specified range. The PS4066A guarantees low leakage currents (<100pA @ 25oC, <6nA @ +85oC) and fast switching speeds (tON < 175ns). ESD sensitivity rating is >2,000V per MIL-STD 883, Method 3015.7 Both devices are available in PDIP-14, narrow-body SOIC-14, and QSOP-16 packages. Available temperature ranges are: commercial (0oC to 70oC), and industrial (-40oC to +85oC). For operation below 5V, the PI5A101/PI5A391/PI5A392 are also recommended. Applications * * * * * * Instrumentation, ATE Sample-and-Holds Audio Switching and Routing Telecommunication Systems PBX, PABX Battery-Powered Systems Functional Diagrams, Pin Configurations, and Truth Table Logic 0 1 Switch O FF ON Top View PDIP/SO N.C. = No Internal Connection Switches shown for logic "0" input Top View QSOP 1 PS8184A 10/15/98 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PS4066/PS4066A Low-Cost, Quad, SPST, CMOS Analog Switches Absolute Maximum Ratings Voltages Referenced to GND V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +17V VIN, VCOM, VNC, VNO (Note 1) . . . . . . . . -2V to (V+) +2V or 30mA, whichever occurs first Current (any terminal) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current, COM, NO, NC (pulsed at 1ms, 10% duty cycle) . . . . . . . . . . . . . . . . 100mA ESD per Method 3015.7 . . . . . . . . . . . . . . . . . . . . . . >2000V Thermal Information Continuous Power Dissipation (TA= +70C) Plastic DIP (derate 10.5mW/ C above +70C) . . . . . . 800mW SO and QSOP (derate 8.7mW/ C above +70C) . . . . . 650mW Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . +300C Note Signals on NC, NO, COM, or IN exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to 30mA. Caution: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Electrical Specifications - Single +12V Supply (V+ = 12V 10%, GND = 0V, VINH = 4V, VINL = 0.8V) Parame te r Analog Switch Analog Signal Range(3) On Resistance Symbol Conditions Te mp. (C) M in(1) Typ(2) M ax(1) Units VANALOG RON V+ = 12V, ICOM = 2mA, VNO = 10V V+ = 12V, ICOM = 2mA VNO = 10V PS4066 PS4066A Full 25 Full 25 Full 0 12 V+ 45 55 0.5 0.5 4 2 6 2 4 6 V On- Resistance Match Between Channels(4) On- Resistance Flatness(5) NO or NC Off Leakage Current(6) COM Off Leakage Current(6) RON RFLAT(ON) INO(OFF) INC(OFF) ICOM(OFF) OR V+ = 12V, ICOM = 2mA, VNO = 10V, 5V, 1V V+ = 12V, VCOM = 0V, VNO = 10V V+ = 12V, VCOM = 0V, VNO = 10V PS4066 PS4066A PS4066 PS4066A 25 Full 25 Full 25 Full PS4066 PS4066A 25 Full -1 - 0.1 -6 -1 - 0.1 -6 -2 - 0.2 - 12 1 0.1 6 1 0.1 6 2 0.2 12 nA COM On Leakage Current(6) ICOM(ON) V+ = 12V, VCOM = 10V, VNO = 10V 2 PS8184A 10/15/98 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PS4066/PS4066A Low-Cost, Quad, SPST, CMOS Analog Switches Electrical Specifications - Single +12V Supply (continued) (V+ = 12V 10%, GND = 0V, VINH = 4V, VINL = 0.8V) Parame te r Logic Input Input Current with Input Voltage High Input Current with Input Voltage Low D ynamic Turn- O n Time Turn- O ff Time O n- Channel Bandwidth Charge Injection(3) O ff Isolation Crosstalk(8) NO Capacitance CO M O ff Capacitance CO M O n Capacitance Supply Positive Supply Current Total Harmonic Distortion Symbol Conditions Te mp (C) M in(1) Typ(2) M ax(1) Units IINH IINL IN =5V, all others = 0.8V Full IN = 0.8V, all others =5V - 0.5 - 0.5 0.005 0.005 0.5 0.5 A tON tOFF BW Q O IRR XTALK C(OFF) 25 VCOM = 10V, Figure 2 Full 25 Full Signal = 0dbm Figure 4, 50 in and out CL=1nF, VGEN = 0V, RGEN = 0, Figure 3 RL = 50, CL= 5pF, f = 1 MHz, Figure 4 RL = 50, CL= 5pF, f = 1 MHz, Figure 5 f =1 MHz, Figure 6 f =1 MHz, Figure 6 25 45 17 100 150 75 100 ns 100 2 - 58 - 86 9 9 22 10 MHz pC dB pF CCOM(ON) f =1MHz, Figure 7 I+ THD VIN = 0V or V+, all channels on or off -1 Full 0.001 0.03 1 A % Notes: 1. The algebraic convention, where the most negative value is a minimum and the most positive is a maximum, is used in this data sheet. 2. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing. 3. Guaranteed by design 4. R = R max - R min 5. Flatness is defined as the difference between the maximum and minimum value of on-resistance measured. 6. Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at +25C. 7. Off Isolation = 20log10 [ VCOM / (VNO or VNO) ], VCOM = 0utput, VNC /VNO = input to off switch 8. Between any two switches. 3 PS8184A 10/15/98 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PS4066/PS4066A Low-Cost, Quad, SPST, CMOS Analog Switches Electrical Specifications - Single +5V Supply (V+ = +5V 10%, GND = 0V, VINH = 2.4V, VINL = 0.8V) Parame te r Analog Switch Analog Signal Range(3) On- Resistance O n- Resistance MatchBetween Channels(4) O n- Resistance Flatness(3,5) NO O ff Leakage Current(9) CO M O ff Leakage Curren(9) CO M O n Leakage Current(6) D ynamic Turn- O n Time Turn- O ff Time On- Channel Bandwidth Charge Injection(3) Supply Positive Supply Current Symbol VANALOG RON RON RFLAT(ON) Conditions Te mp (C) Full M in(1) 0 Typ(2) M ax(1) V+ Units V V+ = 4.5V, ICOM = - 1mA, VNO = 3.5V V+ =5V, ICOM = - 1mA, VNO = 3V V+ = 5V, ICOM = - 1mA, VNO = 1V, 3V V+ = 5.5V, VCOM = 0V, VNO = 4.5V V+ = 5.5V, VCOM = 0V, VNO = 4.5V V+ = 5.5V, VCOM = 5V VNO = 4.5V PS4066 PS4066A PS4066 PS4066A PS4066 PS4066A 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full 25 -1 - 0.1 -6 -1 - 0.1 -6 -2 - 0.2 - 12 22 0.3 4 75 100 4 12 6 8 1 0.1 6 1 0.1 6 2 0.2 12 nA INO(OFF) ICOM(OFF) ICOM(ON) tON VNO= 3V tOFF BW Q Signal = 0dBm, 50 in and out Figure 4 CL = 1nF, VGEN = 0V, RGEN = 0V, Figure 3 65 30 125 175 75 125 ns Full 25 Full 25 25 100 1 MHz 10 pC I+ V+ = 5.5V, VIN = 0V or V+, all channels on or off Full -1 1 A 4 PS8184A 10/15/98 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PS4066/PS4066A Low-Cost, Quad, SPST, CMOS Analog Switches Electrical Specifications - Single +3V Supply (V+ = +2.7V to 3.3V, GND = 0V, VINH = 2.4V, VINL = 0.8V) Parame te r Analog Switch Analog Signal Range(3) Channel O n- Resistance D ynamic Turn- O n- Time(3) Turn- O ff- Time(3) Charge Injection(3) Supply Positive Supply Current Symbol Conditions Te mpC M in.(1) Typ(2) M ax.(1) Units VANALOG RON V+ = 3V, ICOM = - 1mA, VNO = 1.5V 25 Full 25 Full 25 Full 25 0 V+ 170 225 80 40 185 230 150 200 2 10 V tON t(OFF) Q V+ =3V, VNO = 1.5V V+ =3V, VNO = 1.5V CL = 1nF, VGEN = 0V, RGEN = 0V V+ = 3.3V, VIN = 0V or V+, all channels on or off ns pC I+ Full -1 0.001 1 A Notes: 1. The algebraic convention, where the most negative value is a minimum and the most positive is a maximum, is used in this data sheet. 2. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing. 3. Guaranteed by design 4. R = R max - R min 5. Flatness is defined as the difference between the maximum and minimum value of on-resistance measured. 6. Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at +25C. 7. Off Isolation = 20log10 [ VCOM / (VNO or VNO) ], VCOM = 0utput, VNC /VNO = input to off switch 8. Between any two switches. 5 PS8184A 10/15/98 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PS4066/PS4066A Low-Cost, Quad, SPST, CMOS Analog Switches Typical Operating Characteristics (TA = +25C, unless otherwise noted) RON vs. VCOM & Supply Voltages RON vs. VCOM & Temperature Charge Injection vs. Analog Voltage Leakage Currents vs. VCOM 6 PS8184A 10/15/98 Leakage Current VIN (V) VIN (V) Switching Times vs. Temperature TON,TOFF(ns) I+ (mA) Starting Times (ns) I + (mA) 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PS4066/PS4066A Low-Cost, Quad, SPST, CMOS Analog Switches Input Switching Threshold vs. Supply Voltage Typical Operating Characteristics (TA = +25C, unless otherwise noted) Leakage Current vs. Temperature Temperature (C) Supply Current vs. VIN V + (V) Switching Current vs. Switching Frequency V + (V) Supply Currents vs. Switching Frequency Temperature (C) Frequency (MHz) 7 PS8184A 10/15/98 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PS4066/PS4066A Low-Cost, Quad, SPST, CMOS Analog Switches Pin Description Applications Information Overvoltage Protection Proper power-supply sequencing is recommended for all CMOS devices. Do not exceed the absolute maximum ratings, because stresses beyond the listed ratings may cause permanent damage to the devices. Always sequence V+ on first, and then the logic inputs. If power-supply sequencing is not possible, add a small signal diode or current limiting resistor in series with the supply pin for overvoltage protection (Figure 1). Adding a diode reduces the analog signal range, but low switch resistance and low leakage characteristics are unaffected. Test Circuits/Timing Diagrams Figure 1. Overvoltage protection is accomplished using an external blocking diode or a current limiting resistor . Figure 2. Switching Times Figure 3. Charge Injection PS8184A 10/15/98 8 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PS4066/PS4066A Low-Cost, Quad, SPST, CMOS Analog Switches Test Circuits/Timing Diagrams (continued) Figure 4. Off Isolation, BW Figure 5. Crosstalk 10nF +12V V+ COM Capacitance Meter f = 1kHz NO GND IN 0V Figure 6. Channel-Off Capacitance Ordering Information Part Numbe r PS4066CPD PS4066CSD PS4066CEE PS4066EPD PS4066ESD PS4066ACPD PS4066ACSD PS4066ACEE PS4066AEPD PS4066AESD PS4066AEEE Te mpe rature - Range 0C to + 70C 0C to + 70C 0C to + 70C - 40C to + 85C - 40C to + 85C 0C to + 70C 0C to + 70C 0C to + 70C - 40C to + 85C - 40C to + 85C - 40C to + 85C Package 14 Plastic DIP 14 Narrow SO 16 Q SO P 14 Plastic DIP 14 Narrow SO 14 Plastic DIP 14 Narrow SO 16 Q SO P 14 Plastic DIP 14 Narrow SO 16 Q SOP Figure 7. Channel-On Capacitance Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com 9 PS8184A 10/15/98 |
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